AD5678_技术文档

4 × 12-Bit and 4 × 16-Bit Octal DAC with

On-Chip Reference in 14-Lead TSSOP

AD5678

FUNCTIONAL BLOCK DIAGRAM

FEATURES

V

/V

V

REFIN REFOUT

DD

Low power octal DAC with

Four 16-bit DACs

AD5678

1.25V/2.5V

REF

BUFFER

Four 12-bit DACs

14-lead/16-lead TSSOP

DAC

STRING

DAC A

INPUT

V

A

B

C

D

E

F

LDAC

OUT

REGISTER

INPUT

REGISTER

DAC

REGISTER

STRING

DAC B

On-chip 1.25 V/2.5 V, 5 ppm/°C reference

Power down to 400 nA @ 5 V, 200 nA @ 3 V

2.7 V to 5.5 V power supply

Guaranteed monotonic by design

Power-on reset to zero scale

3 power-down functions

Hardware LDAC and LDAC override function

CLR function to programmable code

Rail-to-rail operation

DAC

REGISTER

STRING

DAC C

INPUT

REGISTER

SCLK

SYNC

DIN

INTERFACE

LOGIC

INPUT

REGISTER

DAC

REGISTER

STRING

DAC D

DAC

REGISTER

STRING

DAC E

INPUT

REGISTER

INPUT

REGISTER

DAC

REGISTER

STRING

DAC F

DAC

REGISTER

STRING

DAC G

INPUT

REGISTER

G

H

INPUT

REGISTER

DAC

REGISTER

STRING

DAC H

POWER-DOWN

POWER-ON

RESET

LOGIC

GND

1

LDAC CLR

APPLICATIONS

1

RU-16 PACKAGE ONLY

Figure 1.

Process control

Data acquisition systems

Portable battery-powered instruments

Digital gain and offset adjustment

Programmable voltage current sources

Programmable attenuators

GENERAL DESCRIPTION

The AD5678 is a low power, octal, buffered voltage-output

DAC with four 12-bit DACs and four 16-bit DACs in a single

package. All devices operate from a single 2.7 V to 5.5 V supply

and are guaranteed monotonic by design.

The outputs of all DACs can be updated simultaneously using

the function, with the added functionality of user-

LDAC

selectable DAC channels to simultaneously update. There is

also an asynchronous that clears all DACs to a software-

CLR

selectable code—0 V, midscale, or full scale.

The AD5678 has an on-chip reference with an internal gain of 2.

The AD5678-1 has a 1.25 V 5 ppm/°C reference, giving a full-

scale output of 2.5 V; the AD5678-2 has a 2.5 V 5 ppm/°C

reference, giving a full-scale output of 5 V. The on-board

reference is off at power-up, allowing the use of an external

reference. The internal reference is enabled via a software write.

The AD5678 utilizes a versatile 3-wire serial interface that

operates at clock rates of up to 50 MHz and is compatible with

standard SPI®, QSPI™, MICROWIRE™, and DSP interface

standards. The on-chip precision output amplifier enables rail-

to-rail output swing.

The part incorporates a power-on reset circuit that ensures that

the DAC output powers up to 0 V and remains powered up at

this level until a valid write takes place. The part contains a

power-down feature that reduces the current consumption of

the device to 400 nA at 5 V and provides software-selectable

output loads while in power-down mode for any or all DAC

channels.

PRODUCT HIGHLIGHTS

1. Octal DAC (four 12-bit DACs and four 16-bit DACs).

2. On-chip 1.25 V/2.5 V, 5 ppm/°C reference.

3. Available in 14-lead/16-lead TSSOP.

4. Power-on reset to 0 V.

5. Power-down capability. When powered down, the DAC

typically consumes 200 nA at 3 V and 400 nA at 5 V.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD5678

TABLE OF CONTENTS

Features .............................................................................................. 1

D/A Section................................................................................. 20

Resistor String............................................................................. 20

Internal Reference ...................................................................... 20

Output Amplifier........................................................................ 21

Serial Interface............................................................................ 21

Input Shift Register .................................................................... 22

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Characteristics........................................................................ 7

Timing Characteristics ................................................................ 8

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 11

Terminology .................................................................................... 18

Theory of Operation ...................................................................... 20

Interrupt .......................................................................... 22

SYNC

Internal Reference Register....................................................... 23

Power-On Reset.......................................................................... 23

Power-Down Modes .................................................................. 23

Clear Code Register ................................................................... 23

Function .......................................................................... 25

LDAC

Power Supply Bypassing and Grounding................................ 25

Outline Dimensions....................................................................... 26

Ordering Guide .......................................................................... 26

REVISION HISTORY

11/05—Rev. 0 to Rev. A

Change to General Description...................................................... 1

Change to Specifications.................................................................. 3

Replaced Figure 48 ......................................................................... 22

Change to the Power-Down Modes Section............................... 23

10/05—Revision 0: Initial Version

Rev. A | Page 2 of 28

AD5678

SPECIFICATIONS

V_DD= 4.5 V to 5.5 V, R_L= 2 kΩ to GND, C_L= 200 pF to GND, V_REFIN= V_DD. All specifications T_MINto T_MAX, unless otherwise noted.

Table 1.

A Grade¹

Typ Max

B Grade¹

Typ Max

Parameter

Min

Unit

Conditions/Comments

STATIC PERFORMANCE²

AD5678 (DAC C, D, E, F)

Resolution

12

Bits

LSB

±±.25 LSB

Relative Accuracy

Differential Nonlinearity

±±.5 ±2

±±.25

±±.5 ±1

See Figure 11

Guaranteed monotonic by design

(see Figure 12)

AD5678 (DAC A, B, G, H)

Resolution

16

Bits

Relative Accuracy

Differential Nonlinearity

Zero-Code Error

Zero-Code Error Drift

Full-Scale Error

Gain Error

Gain Temperature

Coefficient

±8

±32

±1

9

±8

±16

±1

9

LSB

mV

μV/°C

% FSR

ppm

See Figure 5

Guaranteed monotonic by design (see Figure 6)

All ±s loaded to DAC register (see Figure 17)

1

±2

−±.2 −1

±1

±2.5

1

±2

−±.2 −1

±1

±2.5

All 1s loaded to DAC register (see Figure 18)

Of FSR/°C

Offset Error

DC Power Supply Rejection

Ratio

±1

–8±

±9

±1

–8±

±9

mV

dB

V_DD± 1±%

DC Crosstalk

(External Reference)

1±

μV

Due to full-scale output change,

R_L= 2 kΩ to GND or V_DD

5

1±

25

5

1±

25

μV/mA

μV

Due to load current change

Due to powering down (per channel)

Due to full-scale output change,

R_L= 2 kΩ to GND or V_DD

DC Crosstalk

(Internal Reference)

1±

μV/mA

Due to load current change

OUTPUT CHARACTERISTICS³

Output Voltage Range

±

V_DD

±

V_DD

V

Capacitive Load Stability

2

nF

Ω

mA

μs

R_L= ∞

R_L= 2 kΩ

1±

±.5

3±

4

1±

±.5

3±

4

DC Output Impedance

Short-Circuit Current

Power-Up Time

V_DD= 5 V

Coming out of power-down mode; V_DD= 5 V

REFERENCE INPUTS

Reference Input Voltage

Reference Current

Reference Input Range

Reference Input Impedance

REFERENCE OUTPUT

Output Voltage

AD5678-2

Reference TC³

Reference Output Impedance

LOGIC INPUTS³

V_DD

35

V_DD

35

V

μA

V

±1% for specified performance

V_REF= V_DD= 5.5 V (per DAC channel)

45

V_DD

45

V_DD

±

14.6

kΩ

Per DAC channel

At ambient

2.495

2.5±5 2.495

±1±

2.5±5

±1±

V

±5

7.5

±5

7.5

ppm/°C

kΩ

Input Current

±3

±.8

2

±3

±.8

μA

V

All digital inputs

V_DD= 5 V

Input Low Voltage, V_INL

Input High Voltage, V_INH

Pin Capacitance

2

3

pF

Rev. A | Page 3 of 28

AD5678

A Grade¹

Typ Max

B Grade¹

Typ Max

Parameter

Min

Unit

Conditions/Comments

POWER REQUIREMENTS

V_DD

4.5

5.5

4.5

5.5

V

All digital inputs at ± or V_DD,

DAC active, excludes load current

I_DD(Normal Mode)⁴

V_DD= 4.5 V to 5.5 V

I_DD(All Power-Down Modes)⁵

V_IH= V_DDand V_IL= GND

Internal reference off

Internal reference on

1.3

2

1.8

2.5

1.3

2

1.8

2.5

mA

V_DD= 4.5 V to 5.5 V

±.4

1

±.4

1

μA

V_IH= V_DDand V_IL= GND

¹Temperature range is −4±°C to +1±5°C, typical at 25°C.

²Linearity calculated using a reduced code range of AD5678 12-bit DACs (Code 32 to Code 4,±64) and AD5678 16-bit DACs (Code 512 to Code 65,±24). Output

unloaded.

³Guaranteed by design and characterization; not production tested.

⁴Interface inactive. All DACs active. DAC outputs unloaded.

⁵All eight DACs powered down.

Rev. A | Page 4 of 28

AD5678

V_DD= 2.7 V to 3.6 V, R_L= 2 kΩ to GND, C_L= 200 pF to GND, V_REFIN= V_DD. All specifications T_MINto T_MAX, unless otherwise noted.

Table 2.

A Grade¹

Typ Max

B Grade¹

Typ Max

Parameter

Min

Unit

Conditions/Comments

STATIC PERFORMANCE²

AD5678 (DAC C, D, E, F)

Resolution

12

Bits

LSB

Relative Accuracy

Differential Nonlinearity

±±.5 ±2

±1

±±.5 ±1

±1

See Figure 11

Guaranteed monotonic by design

(see Figure 12)

AD5678 (DAC A, B, G, H)

Resolution

16

Bits

Relative Accuracy

Differential Nonlinearity

Zero-Code Error

±32

±1

9

±16

±1

9

LSB

mV

See Figure 5

Guaranteed monotonic by design (See Figure 6)

All ±s loaded to DAC register (See Figure 17)

1

Zero-Code Error Drift

Full-Scale Error

Gain Error

Gain Temperature Coefficient

Offset Error

±2

−±.2 −1

±1

±2.5

±1

±2

−±.2 −1

±1

±2.5

±1

μV/°C

% FSR

ppm

mV

All 1s loaded to DAC register (See Figure 18)

Of FSR/°C

±9

Offset Temperature Coefficient

DC Power Supply Rejection

Ratio

1.7

–8±

1.7

–8±

μV/°C

dB

V_DD± 1±%

DC Crosstalk

(External Reference)

1±

μV

Due to full-scale output change,

R_L= 2 kΩ to GND or V_DD

4.5

1±

25

4.5

1±

25

μV/mA

μV

Due to load current change

Due to powering down (per channel)

Due to full-scale output change,

R_L= 2 kΩ to GND or V_DD

DC Crosstalk

(Internal Reference)

4.5

μV/mA

Due to load current change

OUTPUT CHARACTERISTICS³

Output Voltage Range

±

V_DD

±

V_DD

V

Capacitive Load Stability

2

nF

Ω

mA

μs

R_L= ∞

R_L= 2 kΩ

1±

±.5

3±

4

1±

±.5

3±

4

DC Output Impedance

Short-Circuit Current

Power-Up Time

V_DD= 3 V

Coming out of power-down mode; V_DD= 3 V

REFERENCE INPUTS

Reference Input Voltage

Reference Current

Reference Input Range

Reference Input Impedance

REFERENCE OUTPUT

Output Voltage

AD5678-1

Reference TC³

Reference Output Impedance

V_DD

2±

V_DD

2±

V

μA

V

±1% for specified performance

V_REF= V_DD= 3.6 V (per DAC channel)

2±

V_DD

2±

V_DD

±

14.6

kΩ

Per DAC channel

At ambient

1.247

1.253 1.247

±15

1.253

±15

V

±5

7.5

±5

7.5

ppm/°C

kΩ

Rev. A | Page 5 of 28

AD5678

A Grade¹

Typ Max

B Grade¹

Typ Max

Parameter

LOGIC INPUTS³

Min

Unit

Conditions/Comments

Input Current

±3

±.8

±3

±.8

μA

V

All digital inputs

V_DD= 3 V

Input Low Voltage, V_INL

Input High Voltage, V_INH

Pin Capacitance

POWER REQUIREMENTS

V_DD

2

3

pF

2.7

3.6

2.7

3.6

V

All digital inputs at ± or V_DD,

DAC active, excludes load current

I_DD(Normal Mode)⁴

V_DD= 2.7 V to 3.6 V

I_DD(All Power-Down Modes)⁵

V_IH= V_DDand V_IL= GND

Internal reference off

Internal reference on

1.2

1.7

1.5

2.25

1.2

1.7

1.5

2.25

mA

V_DD= 2.7 V to 3.6 V

±.2

1

±.2

1

μA

V_IH= V_DDand V_IL= GND

¹Temperature range is −4±°C to +1±5°C, typical at 25°C.

²Linearity calculated using a reduced code range of AD5678 12-bit DACs (Code 32 to Code 4,±64) and AD5678 16-bit DACs (Code 512 to Code 65,±24). Output

unloaded.

³Guaranteed by design and characterization; not production tested.

⁴Interface inactive. All DACs active. DAC outputs unloaded.

⁵All eight DACs powered down.

Rev. A | Page 6 of 28

AD5678

AC CHARACTERISTICS

V_DD= 2.7 V to 5.5 V, R_L= 2 kΩ to GND, C_L= 200 pF to GND, V_REFIN= V_DD. All specifications T_MINto T_MAX, unless otherwise noted.

Table 3.

Parameter^{1, 2}

Min Typ

Max

Unit

μs

V/μs

nV-s

dB

nV-s

kHz

Conditions/Comments³

Output Voltage Settling Time

Slew Rate

Digital-to-Analog Glitch Impulse

Digital Feedthrough

Reference Feedthrough

Digital Crosstalk

6

1.5

4

1±

¼ to ¾ scale settling to ±2 LSB

1 LSB change around major carry (see Figure 34)

V_REF= 2 V ± ±.1 V p-p, frequency = 1± Hz to 2± MHz

±.1

−9±

±.5

2.5

3

34±

−8±

12±

1±±

15

Analog Crosstalk

DAC-to-DAC Crosstalk

Multiplying Bandwidth

Total Harmonic Distortion

Output Noise Spectral Density

V_REF= 2 V ± ±.2 V p-p

dB

V_REF= 2 V ± ±.1 V p-p, frequency = 1± kHz

DAC code = ±x84±±, 1 kHz

DAC code = ±x84±±, 1± kHz

±.1 Hz to 1± Hz

nV/√Hz

ꢀV p-p

Output Noise

¹Guaranteed by design and characterization; not production tested.

²See the Terminology section.

³Temperature range is −4±°C to +1±5°C, typical at 25°C.

Rev. A | Page 7 of 28

AD5678

TIMING CHARACTERISTICS

All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2. See Figure 2.

V_DD= 2.7 V to 5.5 V. All specifications T_MINto T_MAX, unless otherwise noted.

Table 4.

Limit at T_MIN, T_MAX

Parameter

V_DD= 2.7 V to 5.5 V

Unit

Conditions/Comments

SCLK cycle time

SCLK high time

SCLK low time

SYNC to SCLK falling edge set-up time

Data set-up time

1

t₁

t₂

t₃

t₄

2±

8

13

4

ns min

ns typ

t₅

t₆

t₇

Data hold time

±

SCLK falling edge to SYNC rising edge

Minimum SYNC high time

SYNC rising edge to SCLK fall ignore

SCLK falling edge to SYNC fall ignore

LDAC pulse width low

t₈

15

13

±

t₉

t_1±

t₁₁

t₁₂

t₁₃

t₁₄

t₁₅

1±

15

5

SCLK falling edge to LDAC rising edge

CLR pulse width low

±

SCLK falling edge to LDAC falling edge

CLR pulse activation time

3±±

¹Maximum SCLK frequency is 5± MHz at V_DD= 2.7 V to 5.5 V. Guaranteed by design and characterization; not production tested.

t₁₀

t₁

t₉

SCLK

t₂

t₈

t₇

t₃

t₄

SYNC

DIN

t₆

t₅

DB31

DB0

t₁₄

t₁₁

1

LDAC

t₁₂

2

t₁₃

CLR

t₁₅

V

OUT

1

2

ASYNCHRONOUS LDAC UPDATE MODE.

SYNCHRONOUS LDAC UPDATE MODE.

Figure 2. Serial Write Operation

Rev. A | Page 8 of 28

AD5678

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Table 5.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

V_DDto GND

−±.3 V to +7 V

−±.3 V to V_DD+ ±.3 V

Digital Input Voltage to GND

V_REFIN/V_REFOUTto GND

Operating Temperature Range

Industrial (B Version)

Storage Temperature Range

−4±°C to +1±5°C

−65°C to +15±°C

+15±°C

Junction Temperature (T_{J MAX}

)

TSSOP Package

Power Dissipation

θ_JAThermal Impedance

(T_{J MAX}− T_A)/θ_JA

15±.4°C/W

Lead Temperature, Soldering

SnPb

Pb Free

24±°C

26±°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4±±± V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. A | Page 9 of 28

AD5678

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

LDAC

SYNC

SCLK

DIN

1

2

3

4

5

6

7

SYNC

14

13

12

11

10

9

SCLK

DIN

V

GND

DD

AD5678

TOP VIEW

(Not to Scale)

V

A

GND

V

A

V

B

OUT

AD5678

TOP VIEW

(Not to Scale)

V

C

E

V

B

V

C

E

D

F

OUT

V

D

F

V

OUT

G

H

OUT

8

V

/V

H

REFIN REFOUT

V

/V

REFIN REFOUT

CLR

Figure 3. 14-Lead TSSOP (RU-14)

Figure 4. 16-Lead TSSOP (RU-16)

Table 6. Pin Function Descriptions

Pin No.

14-Lead

TSSOP

16-Lead

TSSOP

Mnemonic

Description

–

1

LDAC

Pulsing this pin low allows any or all DAC registers to be updated if the input registers have

new data. This allows all DAC outputs to simultaneously update. Alternatively, this pin can be

tied permanently low.

1

2

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. When

SYNC goes low, it powers on the SCLK and DIN buffers and enables the input shift register.

Data is transferred in on the falling edges of the next 32 clocks. If SYNC is taken high before

the 32^ndfalling edge, the rising edge of SYNC acts as an interrupt and the write sequence is

ignored by the device.

2

3

V_DD

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should

be decoupled with a 1± μF capacitor in parallel with a ±.1 μF capacitor to GND.

3

11

4

1±

7

4

13

5

12

8

V_OUT

A

B

C

D

Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

The AD5678 has a common pin for reference input and reference output. When using the

internal reference, this is the reference output pin. When using an external reference, this is

the reference input pin. The default for this pin is as a reference input.

V_REFIN/V_REFOUT

–

9

CLR

Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is low, all LDAC

pulses are ignored. When CLR is activated, the input register and the DAC register are

updated with the data contained in the CLR code register—zero, midscale, or full scale.

Default setting clears the output to ± V.

5

9

6

8

12

13

6

11

7

1±

14

15

V_OUT

GND

DIN

E

F

G

H

Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.

Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.

Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.

Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.

Ground Reference Point for All Circuitry on the Part.

Serial Data Input. This device has a 32-bit shift register. Data is clocked into the register on

the falling edge of the serial clock input.

14

16

SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial

clock input. Data can be transferred at rates of up to 5± MHz.

Rev. A | Page 1± of 28

AD5678

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

0.6

0.4

0.2

10

V

= 5V

DD

V

T

= V

= 25°C

= 5V

DD

REF

= 2.5V

REFOUT

8

A

T_A= 25°C

6

4

2

0

–2

–4

–0.2

–0.4

–0.6

–6

–8

–0.8

–1.0

–10

0

5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k

CODE

Figure 5. INL—16-Bit DAC

Figure 8. DNL 16-Bit DAC, 2.5 V Internal Reference

10

V

= 3V

= 1.25V

= 25°C

DD

REFOUT

1.0

8

6

V

= V

= 5V

DD

REF

T

A

0.8

0.6

0.4

0.2

T = 25°C

A

4

2

0

–2

–4

–6

–0.2

–0.4

–0.6

–8

–0.8

–1.0

–10

0

10k

20k

30k

CODE

40k

50k

60k

CODE

Figure 6. DNL—16-Bit DAC

Figure 9. INL—16-Bit DAC, 1.25 V Internal Reference

10

8

V

= 5V

DD

V

= 2.5V

REFOUT

T_A= 25°C

6

4

2

0

–2

–4

–6

–8

–10

CODE

Figure 7. INL—16-Bit DAC, 2.5 V Internal Reference

Rev. A | Page 11 of 28

AD5678

1.0

V

T

= 3V

= 1.25V

= 25°C

V

T

= 5V

DD

REFOUT

DD

REFOUT

= 25°C

0.8

0.6

= 2.5V

0.8

0.6

0.4

0.2

A

0.4

0.2

0

–0.2

–0.4

–0.6

–0.2

–0.4

–0.6

–0.8

–1.0

–0.8

–1.0

0

500

1000

1500 2000 2500 3000

CODE

3500 4000

CODE

Figure 13. INL—12-Bit DAC, 2.5 V Internal Reference

Figure 10. DNL—16-Bit DAC, 1.25 V Internal Reference

0.20

0.15

0.10

0.05

1.0

0.8

V

= 5V

DD

V

T

= V

= 25°C

= 5V

DD

REF

= 2.5V

REFOUT

A

T_A= 25°C

0.6

0.4

0.2

0

–0.05

–0.2

–0.4

–0.6

–0.8

–1.0

–0.10

–0.15

–0.20

0

500

1000

1500 2000 2500 3000

CODE

3500 4000

0

500

1000

1500 2000

CODE

2500 3000 3500 4000

Figure 14. DNL 12-Bit DAC, 2.5 V Internal Reference

Figure 11. INL—12-Bit DAC

1.0

0.8

0.6

0.4

0.2

0

V

= 3V

DD

REFOUT

0.20

0.15

0.10

0.05

0

= 1.25V

V

= V

= 25°C

= 5V

DD

REF

T

= 25°C

A

T

A

–0.2

–0.4

–0.6

–0.05

–0.10

–0.15

–0.20

–0.8

–1.0

0

500

1000 1500

2000 2500

CODE

3000 3500 4000

0

500

1000 1500 2000 2500 3000 3500 4000

CODE

Figure 15. INL—12-Bit DAC, 1.25 V Internal Reference

Figure 12. DNL—12-Bit DAC

Rev. A | Page 12 of 28

AD5678

0.20

0.15

0.10

0.05

0

1.0

V

= 3V

DD

REFOUT

= 1.25V

T

= 25°C

A

0.5

0

GAIN ERROR

FULL-SCALE ERROR

–0.5

–1.0

–0.05

–0.10

–1.5

–2.0

–0.15

–0.20

2.7

3.2

3.7

4.2

(V)

4.7

5.2

0

500

1000 1500

2000 2500

CODE

3000 3500 4000

V

DD

Figure 16. DNL—12-Bit DAC, 1.25 V Internal Reference

Figure 19. Gain Error and Full-Scale Error vs. Supply Voltage

0

–0.02

–0.04

–0.06

–0.08

1.0

V

= 5V

T

= 25°C

DD

A

0.5

0

ZERO-SCALE ERROR

GAIN ERROR

–0.5

–1.0

–1.5

–0.10

–0.12

–0.14

–0.16

FULL-SCALE ERROR

–2.0

–2.5

OFFSET ERROR

–0.18

–0.20

–40

–20

0

20

40

60

80

100

2.7

3.2

3.7

4.2

(V)

4.7

5.2

TEMPERATURE (

°C)

V

DD

Figure 17. Gain Error and Full-Scale Error vs. Temperature

Figure 20. Zero-Scale Error and Offset Error vs. Supply Voltage

1.5

20

V

= 3.6V

= 5.5V

DD

18

16

14

12

10

8

1.0

ZERO-SCALE ERROR

0.5

0

–0.5

–1.0

–1.5

–2.0

–2.5

6

4

OFFSET ERROR

2

0

–40

–20

0

20

40

60

80

100

1.20 1.22 1.24 1.26 1.28 1.30 1.32 1.34 1.36 1.38 1.40 1.42

1.44

TEMPERATURE (

°C)

I

(mA)

DD

Figure 18. Zero-Scale Error and Offset Error vs. Temperature

Figure 21. I_DDHistogram with External Reference

Rev. A | Page 13 of 28

AD5678

14

12

10

8

4.00

3.00

2.00

1.00

V

= 3.6V

= 5.5V

DD

V

= 3V

DD

= 1.25V

REFOUT

= 25°C

T

A

FULL SCALE

V

= 1.25V

V

= 2.5V

REFOUT

3/4 SCALE

MIDSCALE

1/4 SCALE

6

4

0

ZERO SCALE

2

0

–1.00

2.02 2.04 2.06 2.08 2.10 2.12 2.14 2.16 2.18 2.20 2.22 2.24 2.26 2.28

(mA)

–30

–20

–10

0

10

20

30

I

DD

CURRENT (mA)

Figure 22. I_DDHistogram with Internal Reference

Figure 25. AD5678-1 Source and Sink Capability

0.50

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

T

= 25°C

V

= V

= 5V

DAC LOADED WITH

FULL-SCALE

SOURCING CURRENT

DAC LOADED WITH

ZERO-SCALE

SINKING CURRENT

A

DD

REF

0.40

0.30

0.20

0.10

0

V

= 3V

DD

REFOUT

V

= V

= 3V

= 1.25V

DD

REF

–0.10

–0.20

–0.30

V

= 5V

DD

= 2.5V

–2

REFOUT

–0.40

–0.50

–10

–8

–6

–4

0

2

4

6

8

10

512

10512

20512

30512

CODE

40512

50512

60512

CURRENT (mA)

Figure 23. Headroom at Rails vs. Source and Sink

Figure 26. Supply Current vs. Code

6.00

5.00

4.00

3.00

2.00

1.00

1.6

1.4

1.2

V

= V = 5.5V

REFIN

DD

V

= 5V

DD

FULL SCALE

= 2.5V

REFOUT

= 25°C

T

A

3/4 SCALE

V

= V = 3.6V

REFIN

DD

1.0

0.8

MIDSCALE

1/4 SCALE

0.6

0.4

0

ZERO SCALE

0.2

0

–1.00

–30

–20

–10

0

10

20

30

–40

–20

0

20

40

60

80

100

CURRENT (mA)

TEMPERATURE (°C)

Figure 24. AD5678-2 Source and Sink Capability

Figure 27. Supply Current vs. Temperature

Rev. A | Page 14 of 28

AD5678

1.6

1.4

T

= 25°C

A

V

= V = 5V

REF

DD

= 25°C

T

A

1.2

1.0

0.8

V

DD

0.6

0.4

1

2

MAX(C2)*

420.0mV

0.2

0

V

OUT

2.7

3.2

3.7

4.2

(V)

4.7

5.2

CH1 2.0V

CH2 500mV

M100μs 125MS/s

A CH1 1.28V

8.0ns/pt

V

DD

Figure 31. Power-On Reset to 0 V

Figure 28. Supply Current vs. Supply Voltage

8

7

6

T

= 25°C

A

V

= V

REF

= 5V

DD

= 25°C

T

A

5

4

V

DD

1

2

V

= 5V

DD

3

2

1

0

V

OUT

V

= 3V

DD

0

1

2

3

4

5

6

CH1 2.0V

CH2 1.0V

M100μs 125MS/s

A CH1 1.28V

8.0ns/pt

V

(V)

LOGIC

Figure 32. Power-On Reset to Midscale

Figure 29. Supply Current vs. Logic Input Voltage

SYNC

SLCK

1

3

V

= V = 5V

REF

DD

= 25°C

T

A

FULL-SCALE CODE CHANGE

0x0000 TO 0xFFFF

OUTPUT LOADED WITH 2kΩ

AND 200pF TO GND

V

OUT

V

= 909mV/DIV

OUT

V

= 5V

DD

2

1

CH1 5.0V

CH3 5.0V

CH2 500mV

M400ns

A CH1

1.4V

TIME BASE = 4μs/DIV

Figure 33. Exiting Power-Down to Midscale

Figure 30. Full-Scale Settling Time, 5 V

Rev. A | Page 15 of 28

AD5678

2.505

2.504

2.503

2.502

2.501

2.500

2.499

2.498

2.497

2.496

2.495

2.494

2.493

2.492

2.491

2.490

2.489

2.488

2.487

2.486

V

T

= 5V

DD

REFOUT

= 25°C

= 2.5V

V

= V = 5V

REF

A

DD

= 25°C

4ns/SAMPLE NUMBER

GLITCH IMPULSE = 3.55nV-s

1 LSB CHANGE AROUND

MIDSCALE (0x8000 TO 0x7FFF)

T

A

DAC LOADED WITH MIDSCALE

1

Y AXIS = 2μV/DIV

X AXIS = 4s/DIV

2.485

0

64

128

192

256

320

384

448

512

SAMPLE

Figure 37. 0.1 Hz to 10 Hz Output Noise Plot, External Reference

Figure 34. Digital-to-Analog Glitch Impulse (Negative)

2.5000

V

= 5V

DD

REFOUT

= 25°C

2.4995

2.4990

2.4985

2.4980

2.4975

2.4970

2.4965

2.4960

2.4955

2.4950

= 2.5V

T

A

DAC LOADED WITH MIDSCALE

1

V

= 5V

DD

REFOUT

= 25°C

= 2.5V

T

A

4ns/SAMPLE NUMBER

0

64

128

192

256

SAMPLE

320 384 448 512

5s/DIV

Figure 38. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference

Figure 35. Analog Crosstalk

2.4900

2.4895

2.4890

2.4885

2.4880

2.4875

2.4870

2.4865

2.4860

2.4855

V

= 3V

DD

REFOUT

= 25°C

= 1.25V

T

A

DAC LOADED WITH MIDSCALE

1

V

= 5V

DD

REFOUT

= 25°C

= 2.5V

T

A

4ns/SAMPLE NUMBER

0

64

128

192

256

SAMPLE

320 384 448

512

4s/DIV

Figure 39. 0.1 Hz to 10 Hz Output Noise Plot, Internal Reference

Figure 36. DAC-to-DAC Crosstalk

Rev. A | Page 16 of 28

AD5678

800

700

600

500

400

300

200

T

= 25°C

A

MIDSCALE LOADED

CLR

3

V

F

OUT

V

= 5V

DD

REFOUT

= 2.5V

V

B

OUT

4

2

100

0

V

= 3V

DD

REFOUT

= 1.25V

1000

100

10000

100000

1000000

CH2 1.0V

CH4 1.0V

M200ns A CH3

1.10V

CH3 5.0V

FREQUENCY (Hz)

CLR

Figure 40. Noise Spectral Density, Internal Reference

Figure 43. Hardware

–20

–30

–40

V

= 5V

= 25°C

DD

T

A

DAC LOADED WITH FULL SCALE

V = 2V ± 0.3V p-p

REF

5

0

V

A

= 5V

DD

= 25°C

T

–50

–60

–70

–5

–10

–15

–20

–25

–30

–35

–40

–80

–90

–100

2k

4k

6k

8k

10k

FREQUENCY (Hz)

Figure 41. Total Harmonic Distortion

10k

100k

1M

10M

FREQUENCY (Hz)

Figure 44. Multiplying Bandwidth

16

14

12

10

8

V

= V

DD

= 25°C

REF

T

A

V

= 3V

DD

V

= 5V

DD

6

4

0

1

2

3

4

5

6

7

8

9

10

CAPACITANCE (nF)

Figure 42. Settling Time vs. Capacitive Load

Rev. A | Page 17 of 28

AD5678

TERMINOLOGY

Relative Accuracy

Full-Scale Error

For the DAC, relative accuracy, or integral nonlinearity (INL), is

a measure of the maximum deviation in LSBs from a straight

line passing through the endpoints of the DAC transfer

function. Figure 5, Figure 7, and Figure 9 show plots of typical

INL vs. code.

Full-scale error is a measure of the output error when full-scale

code (0xFFFF) is loaded into the DAC register. Ideally, the

output should be V_DD− 1 LSB. Full-scale error is expressed as a

percentage of the full-scale range. Figure 17 shows a plot of

typical full-scale error vs. temperature.

Differential Nonlinearity

Digital-to-Analog Glitch Impulse

Differential nonlinearity (DNL) is the difference between the

measured change and the ideal 1 LSB change between any two

adjacent codes. A specified differential nonlinearity of 1 LSB

maximum ensures monotonicity. This DAC is guaranteed mono-

tonic by design. Figure 6, Figure 8, and Figure 10 show plots of

typical DNL vs. code.

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state. It is normally specified as the area of the glitch in nV-s

and is measured when the digital input code is changed by

1 LSB at the major carry transition (0x7FFF to 0x8000). See

Figure 34.

Offset Error

DC Power Supply Rejection Ratio (PSRR)

Offset error is a measure of the difference between the actual

PSRR indicates how the output of the DAC is affected by changes

in the supply voltage. PSRR is the ratio of the change in V_OUTto

a change in V_DDfor full-scale output of the DAC. It is measured

in decibels. V_REFis held at 2 V, and V_DDis varied 10%.

V_OUTand the ideal V_OUT, expressed in millivolts in the linear

region of the transfer function. Offset error is measured on the

AD5678 with Code 512 loaded into the DAC register. It can be

negative or positive and is expressed in millivolts.

DC Crosstalk

Zero-Code Error

DC crosstalk is the dc change in the output level of one DAC in

response to a change in the output of another DAC. It is measured

with a full-scale output change on one DAC (or soft power-down

and power-up) while monitoring another DAC. It is expressed

in microvolts.

Zero-code error is a measure of the output error when zero

code (0x0000) is loaded into the DAC register. Ideally, the

output should be 0 V. The zero-code error is always positive in

the AD5678, because the output of the DAC cannot go below 0 V.

It is due to a combination of the offset errors in the DAC and

output amplifier. Zero-code error is expressed in millivolts.

Figure 18 shows a plot of typical zero-code error vs.

temperature.

DC crosstalk due to load current change is a measure of the

impact that a change in load current on one DAC has to another

DAC kept at midscale. It is expressed in microvolts per milliamp.

Reference Feedthrough

Reference feedthrough is the ratio of the amplitude of the signal

at the DAC output to the reference input when the DAC output

is not being updated (that is,

decibels.

Gain Error

Gain error is a measure of the span error of the DAC. It is the

deviation in slope of the DAC transfer characteristic from the

ideal, expressed as a percentage of the full-scale range.

is high). It is expressed in

LDAC

Zero-Code Error Drift

Channel-to-Channel Isolation

Zero-code error drift is a measure of the change in zero-code

error with a change in temperature. It is expressed in μV/°C.

Channel-to-channel isolation is the ratio of the amplitude of the

signal at the output of one DAC to a sine wave on the reference

input of another DAC. It is measured in decibels.

Gain Error Drift

Digital Feedthrough

Gain error drift is a measure of the change in gain error with

changes in temperature. It is expressed in (ppm of full-scale

range)/°C.

Digital feedthrough is a measure of the impulse injected into

the analog output of a DAC from the digital input pins of the

device, but is measured when the DAC is not being written to

(

held high). It is specified in nV-s and measured with a

SYNC

full-scale change on the digital input pins, that is, from all 0s to

all 1s or vice versa.

Rev. A | Page 18 of 28

AD5678

Digital Crosstalk

Multiplying Bandwidth

Digital crosstalk is the glitch impulse transferred to the output

of one DAC at midscale in response to a full-scale code change

(all 0s to all 1s or vice versa) in the input register of another

DAC. It is measured in standalone mode and is expressed in

nV-s.

The amplifiers within the DAC have a finite bandwidth. The

multiplying bandwidth is a measure of this. A sine wave on the

reference (with full-scale code loaded to the DAC) appears on

the output. The multiplying bandwidth is the frequency at

which the output amplitude falls to 3 dB below the input.

Analog Crosstalk

Total Harmonic Distortion (THD)

Analog crosstalk is the glitch impulse transferred to the output

of one DAC due to a change in the output of another DAC. It is

measured by loading one of the input registers with a full-scale

Total harmonic distortion is the difference between an ideal

sine wave and its attenuated version using the DAC. The sine

wave is used as the reference for the DAC, and the THD is a

measure of the harmonics present on the DAC output. It is

measured in decibels.

code change (all 0s to all 1s or vice versa) while keeping

LDAC

high, and then pulsing

low and monitoring the output of

LDAC

the DAC whose digital code has not changed. The area of the

glitch is expressed in nV-s.

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse transferred to the

output of one DAC due to a digital code change and subsequent

output change of another DAC. This includes both digital and

analog crosstalk. It is measured by loading one of the DACs

with a full-scale code change (all 0s to all 1s or vice versa) with

low and monitoring the output of another DAC. The

LDAC

energy of the glitch is expressed in nV-s.

Rev. A | Page 19 of 28

AD5678

THEORY OF OPERATION

D/A SECTION

R

The AD5678 DAC is fabricated on a CMOS process. The archi-

tecture consists of a string of DACs followed by an output buffer

amplifier. The parts include an internal 1.25 V/2.5 V, 5 ppm/°C

reference with an internal gain of 2. Figure 45 shows a block

diagram of the DAC architecture.

TO OUTPUT

AMPLIFIER

V

DD

REF (+)

RESISTOR

STRING

V

DAC REGISTER

OUT

REF (–)

OUTPUT

AMPLIFIER

(GAIN = +2)

R

GND

Figure 45. DAC Architecture

Because the input coding to the DAC is straight binary, the ideal

output voltage when using an external reference is given by

Figure 46. Resistor String

INTERNAL REFERENCE

D

⎛

⎜

⎝

⎞

⎟

⎠

V_OUT=V_REFIN

×

2^N

The AD5678 has an on-chip reference with an internal gain of

2. The AD5678-1 has a 1.25 V 5 ppm/°C reference, giving a full-

scale output of 2.5 V. The AD5678-2 has a 2.5 V 5 ppm/°C

reference, giving a full-scale output of 5 V. The on-board

reference is off at power-up, allowing the use of an external

reference. The internal reference is enabled via a write to a

control register. See Table 7.

the ideal output voltage when using an internal reference is

given by

D

⎛

⎜

⎝

⎞

⎟

⎠

V_OUT= 2×V_REFOUT

×

2^N

where:

The internal reference associated with each part is available at

the V_REFOUTpin. A buffer is required if the reference output is

used to drive external loads. When using the internal reference,

it is recommended that a 100 nF capacitor be placed between

the reference output and GND for reference stability.

D = decimal equivalent of the binary code that is loaded to the

DAC register.

0 to 4,095 for AD5678 DAC C, D, E, F (12 bits).

0 to 65,535 for AD5678 DAC A, B, G, H (16 bits).

N = the DAC resolution.

Individual channel power-down is not supported while using

the internal reference.

RESISTOR STRING

The resistor string section is shown in Figure 46. It is simply a

string of resistors, each of value R. The code loaded into the

DAC register determines at which node on the string the

voltage is tapped off to be fed into the output amplifier. The

voltage is tapped off by closing one of the switches connecting

the string to the amplifier. Because it is a string of resistors, it is

guaranteed monotonic.

Rev. A | Page 2± of 28

AD5678

Table 7. Command Definitions

Command

OUTPUT AMPLIFIER

The output buffer amplifier can generate rail-to-rail voltages on

its output, which gives an output range of 0 V to V_DD. The

amplifier is capable of driving a load of 2 kΩ in parallel with

1,000 pF to GND. The source and sink capabilities of the output

amplifier can be seen in Figure 24 and Figure 25. The slew rate

is 1.5 V/ꢀs with a ¼ to ¾ scale settling time of 10 ꢀs.

C3 C2 C1 C0 Description

±

1

±

1

±

Write to Input Register n

Update DAC Register n

Write to Input Register n, update all

(software LDAC)

±

1

–

1

±

1

±

–

1

±

1

±

–

1

±

1

±

1

±

1

–

1

Write to and update DAC Channel n

Power down/power up DAC

Load clear code register

Load LDAC register

Reset (power-on reset)

Set up internal REF register

Reserved

SERIAL INTERFACE

The AD5678 has a 3-wire serial interface (

, SCLK, and

SYNC

DIN) that is compatible with SPI, QSPI, and MICROWIRE

interface standards as well as most DSPs. See Figure 2 for a

timing diagram of a typical write sequence.

Reserved

The write sequence begins by bringing the

line low. Data

SYNC

from the DIN line is clocked into the 32-bit shift register on the

falling edge of SCLK. The serial clock frequency can be as high

as 50 MHz, making the AD5678 compatible with high speed

DSPs. On the 32^ndfalling clock edge, the last data bit is clocked

in and the programmed function is executed, that is, a change

in DAC register contents and/or a change in the mode of

operation. At this stage, the

brought high. In either case, it must be brought high for a

minimum of 15 ns before the next write sequence so that a

Table 8. Address Commands

Address (n)

Selected DAC

Channel

A3

±

A2

±

A1

±

A0

±

1

±

1

±

1

±

1

DAC A (16 bits)

DAC B (16 bits)

DAC C (12 bits)

DAC D (12 bits)

DAC E (12 bits)

DAC F (12 bits)

DAC G (16 bits)

DAC H (16 bits)

All DACs

line can be kept low or be

SYNC

±

1

±

1

falling edge of

can initiate the next write sequence.

SYNC

±

1

±

Because the

buffer draws more current when V_IN= 2 V

SYNC

±

1

±

than it does when V_IN= 0.8 V,

should be idled low

SYNC

between write sequences for even lower power operation of the

part. As is mentioned previously, however, must be

±

1

±

1

SYNC

brought high again just before the next write sequence.

1

Rev. A | Page 21 of 28

AD5678

INTERRUPT

SYNC

INPUT SHIFT REGISTER

In a normal write sequence, the

line is kept low for

SYNC

32 falling edges of SCLK, and the DAC is updated on the 32^nd

falling edge and rising edge of . However, if is

The input shift register is 32 bits wide. The first four bits are

don’t cares. The next four bits are the command bits, C3 to C0

(see Table 7), followed by the 4-bit DAC address bits, A3 to A0

(see Table 8), and finally the 16-/12-bit data-word. The data-

word comprises the 16-/12-bit input code followed by four or

eight don’t care bits for the AD5678 DAC A, B, G, H and

AD5678 DAC C, D, E, F, respectively (See Figure 47 and Figure

48). These data bits are transferred to the DAC register on the

32^ndfalling edge of SCLK.

SYNC

brought high before the 32^ndfalling edge, this acts as an

interrupt to the write sequence. The shift register is reset, and

the write sequence is seen as invalid. Neither an update of the

DAC register contents nor a change in the operating mode

occurs—see Figure 49.

DB31 (MSB)

DB0 (LSB)

X

C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X

DATA BITS

COMMAND BITS

ADDRESS BITS

Figure 47. AD5678 Input Register Content for DAC A, B, G , H

DB31 (MSB)

DB0 (LSB)

X

C3 C2 C1 C0 A3 A2 A1 A0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X

DATA BITS

COMMAND BITS

ADDRESS BITS

Figure 48. AD5678 Input Register Content for DAC C, D, E, F

SCLK

SYNC

DIN

DB31

DB0

DB31

DB0

INVALID WRITE SEQUENCE:

SYNC HIGH BEFORE 32ND FALLING EDGE

VALID WRITE SEQUENCE, OUTPUT UPDATES

ON THE 32ND FALLING EDGE

SYNC

Figure 49.

Interrupt Facility

Rev. A | Page 22 of 28

AD5678

the part is in power-down mode. There are three different

INTERNAL REFERENCE REGISTER

options. The output is connected internally to GND through

either a 1 kΩ or a 100 kΩ resistor, or it is left open-circuited

(three-state). The output stage is illustrated in Figure 50.

The on-board reference is off at power-up by default. This

allows the use of an external reference if the application requires

it. The on-board reference can be turned on/off by a user-

programmable internal REF register by setting Bit DB0 high or

low (see Table 9). Command 1000 is reserved for this internal

REF set-up command (see Table 7). Table 11 shows the state of

the bits in the input shift register corresponds to the mode of

operation of the device.

The bias generator of the selected DAC(s), output amplifier,

resistor string, and other associated linear circuitry are shut

down when the power-down mode is activated. However, the

contents of the DAC register are unaffected when in power-

down. The time to exit power-down is typically 5 ꢀs for

V_DD= 5 V and for V_DD= 3 V, see Figure 33.

POWER-ON RESET

Any combination of DACs can be powered up by setting PD1

and PD0 to 0 (normal operation). The output powers up to the

The AD5678 contains a power-on reset circuit that controls the

output voltage during power-up. The AD5678 output powers up

to 0 V, and the output remains powered up at this level until a

valid write sequence is made to the DAC. This is useful in

applications where it is important to know the state of the

output of the DAC while it is in the process of powering up.

There is also a software executable reset function that resets the

DAC to the power-on reset code. Command 0111 is reserved

value in the input register (

low) or to the value in the

LDAC

DAC register before powering down (

high).

LDAC

CLEAR CODE REGISTER

The AD5678 has a hardware

pin that is an asynchronous

CLR

clear input. The

input is falling edge sensitive . Bringing

CLR

for this reset function—see Table 7. Any events on

or

LDAC

the

line low clears the contents of the input register and the

CLR

DAC registers to the data contained in the user-configurable

register and sets the analog outputs accordingly. This

during power-on reset are ignored.

CLR

POWER-DOWN MODES

function can be used in system calibration to load zero scale,

midscale, or full scale to all channels together. These clear code

values are user-programmable by setting two bits, Bit DB1 and Bit

The AD5678 contains four separate modes of operation.

Command 0100 is reserved for the power-down function. See

Table 7. These modes are software-programmable by setting

two bits, Bit DB9 and Bit DB8, in the control register.

DB0, in the

control register. See Table 13. The default

CLR

setting clears the outputs to 0 V. Command 0101 is reserved for

loading the clear code register, see Table 7.

Table 11 shows how the state of the bits corresponds to the

mode of operation of the device. Any or all DACs (DAC H to

DAC A) can be powered down to the selected mode by setting

the corresponding eight bits (DB7 to DB0) to 1. See Table 12 for

the contents of the input shift register during power-down/power-

up operation. When using the internal reference, only all channel

power-down to the selected modes is supported.

The part exits clear code mode on the 32^ndfalling edge of the

next write to the part. If

is activated during a write

CLR

sequence, the write is aborted.

The pulse activation time—the falling edge of

to when

CLR

the output starts to change—is typically 280 ns. However, if the

value is outside the linear region, it typically takes 520 ns after

When both bits are set to 0, the part works normally with its

normal power consumption of 1.3 mA at 5 V. However, for the

three power-down modes, the supply current falls to 400 nA at

5 V (200 nA at 3 V). Not only does the supply current fall, but

the output stage is also internally switched from the output of

the amplifier to a resistor network of known values. This has the

advantage that the output impedance of the part is known while

executing

for the output to start changing. See Figure 43.

CLR

See Table 14 for contents of the input shift register during the

loading clear code register operation.

Rev. A | Page 23 of 28

AD5678

Table 9. Internal Reference Register

Internal REF Register (DB0)

Action

±

1

Reference off (default)

Reference on

Table 10. 32-Bit Input Shift Register Contents for Reference Set-Up Function

MSB

LSB

DB0

1/±

DB31 to DB28

X

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19 to DB1

X

1

±

X

Don’t cares

Command bits (C3 to C±)

Address bits (A3 to A±)

Don’t cares

Internal REF

register

Table 11. Power-Down Modes of Operation

DB9

DB8

Operating Mode

Normal operation

Power-down modes

1 kΩ to GND

1±± kΩ to GND

Three-state

±

1

±

1

Table 12. 32-Bit Input Shift Register Contents for Power-Down/Power-Up Function

MSB

LSB

DB31

to

DB28

DB19

to

DB10

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

X

±

1

±

X

PD1

PD±

DAC

H

DAC

G

DAC

F

DAC

E

DAC

D

DAC

C

DAC

B

DAC

A

Don’t

cares

Command bits (C3 to C±)

Address bits (A3 to A±)—

don’t cares

Don’t

cares

Power-

down mode

Power-down/power-up channel selection—set bit to 1 to select

V

FB

AMPLIFIER

V

OUT

RESISTOR

STRING DAC

POWER-DOWN

CIRCUITRY

RESISTOR

NETWORK

Figure 50. Output Stage During Power-Down

Table 13. Clear Code Register

Clear Code Register

DB1

CR1

±

DB0

CR0

±

Clears to Code

±x±±±±

±

1

±x8±±±

1

±

±xFFFF

1

No operation

Table 14. 32-Bit Input Shift Register Contents for Clear Code Function

MSB

LSB

DB0

CR±

DB31 to DB28

X

DB27

DB26

DB25

DB24

DB23

DB22

DB21

DB20

DB19 to DB2

X

DB1

±

1

±

1

X

CR1

Don’t cares

Command bits (C3 to C±)

Address bits (A3 to A±)—don’t cares

Don’t cares

Clear code register

Rev. A | Page 24 of 28

AD5678

pin. See Table 16 for the contents of the input shift register

during the load register mode of operation.

FUNCTION

LDAC

The outputs of all DACs can be updated simultaneously using

the hardware

pin.

LDAC

POWER SUPPLY BYPASSING AND GROUNDING

When accuracy is important in a circuit, it is helpful to carefully

consider the power supply and ground return layout on the

board. The printed circuit board containing the AD5678 should

have separate analog and digital sections. If the AD5678 is in a

system where other devices require an AGND-to-DGND

connection, the connection should be made at one point only.

This ground point should be as close as possible to the AD5678.

Synchronous

: After new data is read, the DAC registers

LDAC

are updated on the falling edge of the 32^ndSCLK pulse.

can be permanently low or pulsed as in Figure 2.

LDAC

Asynchronous

time that the input registers are written to. When

low, the DAC registers are updated with the contents of the

input register.

: The outputs are not updated at the same

LDAC

goes

LDAC

The power supply to the AD5678 should be bypassed with 10 ꢀF

and 0.1 ꢀF capacitors. The capacitors should physically be as

close as possible to the device, with the 0.1 ꢀF capacitor ideally

right up against the device. The 10 ꢀF capacitors are the tantalum

bead type. It is important that the 0.1 ꢀF capacitor has low effective

series resistance (ESR) and low effective series inductance (ESI),

such as is typical of common ceramic types of capacitors. This

0.1 ꢀF capacitor provides a low impedance path to ground for

high frequencies caused by transient currents due to internal

logic switching.

Alternatively, the outputs of all DACs can be updated simulta-

neously using the software

function by writing to Input

LDAC

Register n and updating all DAC registers. Command 0011 is

reserved for this software function.

LDAC

register gives the user extra flexibility and control

An

LDAC

over the hardware

pin. This register allows the user to

LDAC

select which combination of channels to simultaneously update

when the hardware pin is executed. Setting the bit

LDAC

register to 0 for a DAC channel means that this channel’s update

is controlled by the pin. If this bit is set to 1, this channel

LDAC

The power supply line should have as large a trace as possible to

provide a low impedance path and reduce glitch effects on the

supply line. Clocks and other fast switching digital signals should

be shielded from other parts of the board by digital ground. Avoid

crossover of digital and analog signals if possible. When traces

cross on opposite sides of the board, ensure that they run at right

angles to each other to reduce feedthrough effects through the

board. The best board layout technique is the microstrip technique,

where the component side of the board is dedicated to the ground

plane only and the signal traces are placed on the solder side.

However, this is not always possible with a 2-layer board.

LDAC

updates synchronously; that is, the DAC register is updated

after new data is read, regardless of the state of the pin. It

LDAC

pin as being tied low. (See Table 15

effectively sees the

LDAC

for the

register mode of operation.) This flexibility is

LDAC

useful in applications where the user wants to simultaneously

update select channels while the rest of the channels are

synchronously updating.

Writing to the DAC using command 0110 loads the 8-bit

LDAC

register (DB7 to DB0). The default for each channel is 0; that is,

the pin works normally. Setting the bits to 1 means the

LDAC

DAC channel is updated regardless of the state of the

LDAC

Table 15.

Register

LDAC

Load DAC Register

LDAC Bits (DB7 to DB0)

LDAC Pin

1/±

LDAC Operation

±

1

Determined by LDAC pin

X—don’t care

DAC channels update, overriding the LDAC pin. DAC channels see LDAC as ±.

Table 16. 32-Bit Input Shift Register Contents for

Overwrite Function

LDAC

MSB

LSB

DB31

to

DB19

to

DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

X

±

1

±

X

DAC

H

DAC

G

DAC

F

DAC

E

DAC

D

DAC

C

DAC

B

DAC

A

Don’t

cares

Command bits (C3 to C±)

Address bits (A3 to A±)—

don’t cares

Don’t

cares

LDAC

Setting

bit to 1 overrides

Rev. A | Page 25 of 28

AD5678

OUTLINE DIMENSIONS

5.10

5.00

4.90

14

8

7

4.50

4.40

4.30

6.40

BSC

1

PIN 1

0.65

BSC

1.05

1.00

0.80

0.20

0.09

1.20

MAX

0.75

0.60

0.45

8°

0°

0.15

0.05

0.30

0.19

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

Figure 51. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

5.10

5.00

4.90

16

9

8

4.50

4.40

4.30

6.40

BSC

1

PIN 1

1.20

MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

0.65

BSC

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 52. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

ORDERING GUIDE

Package

Option

Power-On

Reset to Code

Internal

Reference

Model

Temperature Range

−4±°C to +1±5°C

Package Description

14-Lead TSSOP

16-Lead TSSOP

Accuracy

AD5678BRUZ-1¹

AD5678BRUZ-1REEL7¹

AD5678BRUZ-2¹

AD5678BRUZ-2REEL7¹

AD5678ARUZ-2¹

AD5678ARUZ-2REEL7¹

RU-14

RU-16

Zero

±16 LSB INL

±32 LSB INL

1.25 V

2.5 V

¹Z = Pb-free part.

Rev. A | Page 26 of 28

AD5678

NOTES

Rev. A | Page 27 of 28

AD5678

NOTES

©

registered trademarks are the property of their respective owners.

D05299–0–11/05(A)

Rev. A | Page 28 of 28


型号：	AD5678
厂家：	ADI
描述：	4 】 12-Bit and 4 】 16-Bit Octal DAC with On-Chip Reference in 14-Lead TSSOP 4 】 12位和4 】 16位八通道DAC，具有片内基准14引脚TSSOP
文件：	总28页 (文件大小：890K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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