AD5684R_技术文档

Quad 16-/14-/12-Bit nanoDAC+

with 2 ppm/°C Reference, I²C Interface

Data Sheet

AD5696R/AD5695R/AD5694R

FEATURES

FUNCTIONAL BLOCK DIAGRAM

High relative accuracy (INL): 2 LSB maximum @ 16 bits

Low drift 2.5 V reference: 2 ppm/°C typical

V

GND

V

REF

DD

Tiny package: 3 mm × 3 mm, 16-lead LFCSP

2.5V

REFERENCE

AD5696R/AD5695R/AD5694R

Total unadjusted error (TUE): 0.1% of FSR maximum

Offset error: 1.5 mV maximum

V

LOGIC

SCL

STRING

DAC A

INPUT

DAC

V

A

B

C

D

OUT

REGISTER

BUFFER

Gain error: 0.1% of FSR maximum

High drive capability: 20 mA, 0.5 V from supply rails

User selectable gain of 1 or 2 (GAIN pin)

Reset to zero scale or midscale (RSTSEL pin)

1.8 V logic compatibility

STRING

DAC B

INPUT

REGISTER

DAC

REGISTER

SDA

A1

STRING

DAC C

INPUT

REGISTER

DAC

REGISTER

A0

Low glitch: 0.5 nV-sec

STRING

DAC D

INPUT

REGISTER

DAC

REGISTER

400 kHz I²C-compatible serial interface

Robust 3.5 kV HBM and 1.5 kV FICDM ESD rating

Low power: 3.3 mW at 3 V

POWER-ON

RESET

GAIN =

×1/×2

POWER-

DOWN

LOGIC

2.7 V to 5.5 V power supply

−40°C to +105°C temperature range

LDAC RESET

RSTSEL

GAIN

Figure 1.

APPLICATIONS

Optical transceivers

Base-station power amplifiers

Process control (PLC I/O cards)

Industrial automation

Data acquisition systems

Table 1. Quad nanoDAC+ Devices

Interface Reference 16-Bit

GENERAL DESCRIPTION

14-Bit

12-Bit

The AD5696R/AD5695R/AD5694R family, are low power,

quad, 16-/14-/12-bit buffered voltage output DACs. The devices

include a 2.5 V, 2 ppm/°C internal reference (enabled by

default) and a gain select pin giving a full-scale output of 2.5 V

(gain = 1) or 5 V (gain = 2). All devices operate from a single

2.7 V to 5.5 V supply, are guaranteed monotonic by design, and

exhibit less than 0.1% FSR gain error and 1.5 mV offset error

performance. The devices are available in a 3 mm × 3 mm

LFCSP and a TSSOP package.

SPI

I²C

Internal

AD5686R

AD5696R

AD5685R AD5684R

AD5695R AD5694R

PRODUCT HIGHLIGHTS

1. High Relative Accuracy (INL).

AD5696R (16-bit): 2 LSB maximum

AD5695R (14-bit): 1 LSB maximum

AD5694R (12-bit): 1 LSB maximum

2. Low Drift 2.5 V On-Chip Reference.

2 ppm/°C typical temperature coefficient

5 ppm/°C maximum temperature coefficient

3. Two Package Options.

The AD5696R/AD5695R/AD5694R also incorporate a power-

on reset circuit and a RSTSEL pin that ensures that the DAC

outputs power up to zero scale or midscale and remain there

until a valid write takes place. Each part contains a per-channel

power-down feature that reduces the current consumption of

the device to 4 µA at 3 V while in power-down mode.

3 mm × 3 mm, 16-lead LFCSP

The AD5696R/AD5695R/AD5694R use a versatile 2-wire serial

interface that operates at clock rates up to 400 kHz, and

includes a V_LOGICpin intended for 1.8 V/3 V/5 V logic.

16-lead TSSOP

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD5696R/AD5695R/AD5694R

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Serial Operation ......................................................................... 21

Write Operation.......................................................................... 21

Read Operation........................................................................... 22

Multiple DAC Readback Sequence.......................................... 22

Power-Down Operation............................................................ 23

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Characteristics........................................................................ 5

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

Terminology .................................................................................... 16

Theory of Operation ...................................................................... 18

Digital-to-Analog Converter .................................................... 18

Transfer Function....................................................................... 18

DAC Architecture....................................................................... 18

Serial Interface ............................................................................ 19

Write and Update Commands.................................................. 20

LDAC

Load DAC (Hardware

Pin)........................................... 24

Mask Register ................................................................. 24

Hardware Reset ( ) .......................................................... 25

LDAC

RESET

Reset Select Pin (RSTSEL) ........................................................ 25

Internal Reference Setup ........................................................... 25

Solder Heat Reflow..................................................................... 25

Long-Term Temperature Drift ................................................. 25

Thermal Hysteresis .................................................................... 26

Applications Information.............................................................. 27

Microprocessor Interfacing....................................................... 27

AD5696R/AD5695R/AD5694R to ADSP-BF531 Interface.. 27

Layout Guidelines....................................................................... 27

Galvanically Isolated Interface ................................................. 27

Outline Dimensions....................................................................... 28

Ordering Guide .......................................................................... 29

REVISION HISTORY

4/12—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

Data Sheet

AD5696R/AD5695R/AD5694R

SPECIFICATIONS

V_DD= 2.7 V to 5.5 V; 1.8 V ≤ V_LOGIC≤ 5.5 V; all specifications T_MINto T_MAX, unless otherwise noted. R_L= 2 kΩ; C_L= 200 pF.

Table 2.

B Grade¹

Typ

A Grade¹

Typ

Parameter

STATIC PERFORMANCE²

Min

Max

Min

Max

Unit

Test Conditions/Comments

AD5696R

Resolution

Relative Accuracy

16

Bits

LSB

2

8

1

2

3

1

Gain = 2

Gain = 1

Differential Nonlinearity

AD5695R

LSB

Guaranteed monotonic by design

Resolution

14

12

14

12

Bits

LSB

Relative Accuracy

Differential Nonlinearity

AD5694R

0.5

4

1

0.5

1

Guaranteed monotonic by design

Resolution

Bits

LSB

mV

Relative Accuracy

Differential Nonlinearity

Zero-Code Error

Offset Error

0.12

2

1

0.12

1

1.5

0.1

Guaranteed monotonic by design

All zeros loaded to DAC register

0.4

+0.1

+0.01

4

0.4

+0.1

+0.01

4

0.2

Full-Scale Error

% of

FSR

All ones loaded to DAC register

Gain Error

0.02

0.01

0.2

0.02

0.01

0.1

0.2

% of

FSR

% of

FSR

% of

FSR

Total Unadjusted Error

0.25

External reference; gain = 2; TSSOP

Internal reference; gain = 1; TSSOP

Offset Error Drift³

Gain Temperature

Coefficient³

1

µV/°C

ppm

Of FSR/°C

DC Power Supply Rejection

Ratio³

0.15

mV/V

DAC code = midscale; V_DD= 5 V 10%

DC Crosstalk³

2

µV

Due to single channel, full-scale

output change

3

2

3

2

µV/mA

µV

Due to load current change

Due to powering down (per channel)

OUTPUT CHARACTERISTICS³

Output Voltage Range

0

V_REF

2 × V_REF

0

V_REF

2 × V_REF

V

nF

Gain = 1

Gain = 2, see Figure 31

R_L= ∞

Capacitive Load Stability

2

10

nF

kΩ

µV/mA

R_L= 1 kΩ

Resistive Load⁴

Load Regulation

1

80

5 V 10%, DAC code = midscale;

−30 mA ≤ I_OUT≤ 30 mA

3 V 10%, DAC code = midscale;

−20 mA ≤ I_OUT≤ 20 mA

µV/mA

Short-Circuit Current⁵

Load Impedance at Rails⁶

Power-Up Time

40

25

2.5

40

25

2.5

mA

Ω

µs

See Figure 31

Coming out of power-down mode;

V_DD= 5 V

Rev. 0 | Page 3 of 32

AD5696R/AD5695R/AD5694R

Data Sheet

B Grade¹

Typ

A Grade¹

Typ

Parameter

Min

Max

Min

Max

Unit

Test Conditions/Comments

REFERENCE OUTPUT

Output Voltage⁷

Reference TC^{8, 9}

Output Impedance³

Output Voltage Noise³

Output Voltage Noise

Density³

2.4975

2.5025

20

2.4975

2.5025

5

V

At ambient

5

0.04

12

2

0.04

12

ppm/°C See the Terminology section

Ω

0.1 Hz to 10 Hz

µV p-p

nV/√Hz

240

At ambient; f = 10 kHz, C_L= 10 nF

Load Regulation Sourcing³

At ambient

V_DD≥ 3 V

20

40

±5

20

40

±5

µV/mA

mA

Load Regulation Sinking³

Output Current Load

Capability³

Line Regulation³

Long-Term Stability/Drift³

Thermal Hysteresis³

100

12

100

12

µV/V

ppm

At ambient

After 1000 hours at 125°C

First cycle

125

25

125

25

Additional cycles

LOGIC INPUTS³

Input Current

2

µA

V

Per pin

V_INL, Input Low Voltage

V_INH, Input High Voltage

Pin Capacitance

0.3 × V_LOGIC

0.7 × V_LOGIC

2

4

2

4

pF

LOGIC OUTPUTS (SDA)³

Output Low Voltage, V_OL

Floating State Output

Capacitance

0.4

V

pF

I_SINK= 3 mA

POWER REQUIREMENTS

V_LOGIC

I_LOGIC

1.8

5.5

3

1.8

5.5

3

V

µA

V

V_DD

2.7

V_REF+ 1.5

5.5

2.7

V_REF+ 1.5

5.5

Gain = 1

Gain = 2

I_DD

V_IH= V_DD, V_IL= GND, V_DD= 2.7 V to 5.5 V

Internal reference off

Internal reference on, at full scale

−40°C to +85°C

Normal Mode¹⁰

0.59

1.1

1

0.7

1.3

4

0.59

1.1

1

0.7

1.3

4

mA

µA

All Power-Down

Modes¹¹

6

µA

−40°C to +105°C

¹Temperature range: A and B grade: −40°C to +105°C.

²DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when V_REF= V_DDwith gain = 1 or when V_REF/2 =

V_DDwith gain = 2. Linearity calculated using a reduced code range of 256 to 65,280 (AD5696R), 64 to 16,320 (AD5695R), and 12 to 4080 (AD5694R).

³Guaranteed by design and characterization; not production tested.

⁴Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to

30 mA up to a junction temperature of 110°C.

⁵V_DD= 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded

during current limit. Operation above the specified maximum operation junction temperature may impair device reliability.

⁶When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output

devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 31).

⁷Initial accuracy presolder reflow is 750 µV; output voltage includes the effects of preconditioning drift. See the Internal Reference Setup section.

⁸Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C.

⁹Reference temperature coefficient calculated as per the box method. See the Terminology section for further information.

¹⁰Interface inactive. All DACs active. DAC outputs unloaded.

¹¹All DACs powered down.

Rev. 0 | Page 4 of 32

Data Sheet

AD5696R/AD5695R/AD5694R

AC CHARACTERISTICS

V_DD= 2.7 V to 5.5 V; R_L= 2 kΩ to GND; C_L= 200 pF to GND; 1.8 V ≤ V_LOGIC≤ 5.5 V; all specifications T_MINto T_MAX, unless otherwise

noted.¹

Table 3.

Parameter²

Min

Typ

Max

Unit

Test Conditions/Comments³

Output Voltage Settling Time

AD5696R

AD5695R

5

8

7

µs

¼ to ¾ scale settling to 2 LSB

AD5694R

Slew Rate

0.8

0.5

0.13

0.1

0.2

0.3

−80

300

6

V/µs

nV-sec

dB

nV/√Hz

µV p-p

dB

Digital-to-Analog Glitch Impulse

Digital Feedthrough

Digital Crosstalk

Analog Crosstalk

DAC-to-DAC Crosstalk

Total Harmonic Distortion⁴

Output Noise Spectral Density

Output Noise

1 LSB change around major carry

At ambient, BW = 20 kHz, V_DD= 5 V, f_OUT= 1 kHz

DAC code = midscale, 10 kHz; gain = 2

0.1 Hz to 10 Hz

At ambient, BW = 20 kHz, V_DD= 5 V, f_OUT= 1 kHz

SNR

SFDR

SINAD

90

83

80

dB

¹Guaranteed by design and characterization; not production tested.

²See the Terminology section.

³Temperature range is −40°C to +105°C, typical @ 25°C.

⁴Digitally generated sine wave @ 1 kHz.

Rev. 0 | Page 5 of 32

AD5696R/AD5695R/AD5694R

Data Sheet

TIMING CHARACTERISTICS

V_DD= 2.5 V to 5.5 V; 1.8 V ≤ V_LOGIC≤ 5.5 V; all specifications T_MINto T_MAX, unless otherwise noted. ¹

Table 4.

Parameter²

Unit

µs

ns

µs

ns

pF

Conditions/Comments

SCL cycle time

t_HIGH, SCL high time

t_LOW, SCL low time

t_HD,STA, start/repeated start condition hold time

t_SU,DAT, data setup time

t_HD,DAT, data hold time

t_SU,STA, setup time for repeated start

t_SU,STO, stop condition setup time

t_BUF, bus free time between a stop and a start condition

t_R, rise time of SCL and SDA when receiving

t_F, fall time of SDA and SCL when transmitting/ receiving

LDAC pulse width

Min

2.5

0.6

1.3

0.6

100

0

0.6

1.3

Max

t₁

t₂

t₃

t₄

t₅

3

t₆

0.9

t₇

t₈

t₉

t₁₀

t₁₁

t₁₂

t₁₃

0

300

4

20 + 0.1C_B

20

400

SCL rising edge to LDAC rising edge

Capacitive load for each bus line

4

C_B

400

¹See Figure 2.

²Guaranteed by design and characterization; not production tested.

³A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHmin of the SCL signal) to bridge the undefined region of SCL’s

falling edge.

⁴C_Bis the total capacitance of one bus line in pF. t_Rand t_Fmeasured between 0.3 V_DDand 0.7 V_DD

.

START

CONDITION

REPEATED START

CONDITION

STOP

CONDITION

SDA

SCL

t₉

t₁₀

t₁₁

t₄

t₃

t₄

t₂

t₁

t₆

t₅

t₇

t₈

t₁₂

1

2

t₁₃

LDAC

t₁₂

NOTES

1

ASYNCHRONOUS LDAC UPDATE MODE.

SYNCHRONOUS LDAC UPDATE MODE.

2

Figure 2. 2-Wire Serial Interface Timing Diagram

Rev. 0 | Page 6 of 32

Data Sheet

AD5696R/AD5695R/AD5694R

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Table 5.

Parameter

Rating

V_DDto GND

−0.3 V to +7 V

V_LOGICto GND

−0.3 V to +7 V

V_OUTto GND

V_REFto GND

−0.3 V to V_DD+ 0.3 V

−0.3 V to V_LOGIC+ 0.3 V

−0.3 V to +7 V

−40°C to +105°C

−65°C to +150°C

125°C

Digital Input Voltage to GND¹

SDA and SCL to GND

Operating Temperature Range

Storage Temperature Range

Junction Temperature

ESD CAUTION

16-Lead TSSOP, θ_JAThermal

112.6°C/W

Impedance, 0 Airflow (4-Layer Board)

16-Lead LFCSP, θ_JAThermal

Impedance, 0 Airflow (4-Layer Board)

Reflow Soldering Peak

70°C/W

260°C

Temperature, Pb Free (J-STD-020)

ESD²

FICDM

3.5 kV

1.5 kV

¹Excluding SDA and SCL.

²Human body model (HBM) classification.

Rev. 0 | Page 7 of 32

AD5696R/AD5695R/AD5694R

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

AD5696R/AD5695R/AD5694R

V

A 1

12 A1

11 SCL

10 A0

OUT

GND 2

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

V

RSTSEL

RESET

A1

REF

V

3

DD

V

B

A

OUT

9

V

C 4

AD5696R/

AD5695R/

AD5694R

TOP VIEW

(Not to Scale)

OUT

LOGIC

GND

SCL

V

A0

DD

V

C

D

V

LOGIC

OUT

TOP VIEW

(Not to Scale)

GAIN

LDAC

SDA

NOTES

1. THE EXPOSED PAD MUST BE TIED TO GND.

Figure 3. 16-Lead LFCSP Pin Configuration

Figure 4. 16-Lead TSSOP Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

TSSOP

LFCSP

Mnemonic Description

1

2

3

4

5

V_OUT

GND

V_DD

A

Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

Ground Reference Point for All Circuitry on the Part.

Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be

decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

4

5

6

7

8

V_OUT

SDA

C

D

Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the

24-bit input shift register. SDA is a bidirectional, open-drain data line that should be pulled to the

supply with an external pull-up resistor.

7

8

9

LDAC

GAIN

LDAC can be operated in two modes, asynchronously and synchronously. Pulsing this pin low allows

any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs

to simultaneously update. This pin can also be tied permanently low.

10

Span Set Pin. When this pin is tied to GND, all four DAC outputs have a span from 0 V to V_REF. If this

pin is tied to V_DD, all four DACs output a span of 0 V to 2 × V_REF

Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V.

Address Input. Sets the first LSB of the 7-bit slave address.

Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 24-bit

input register.

.

9

10

11

12

13

V_LOGIC

A0

SCL

12

13

14

15

A1

RESET

Address Input. Sets the second LSB of the 7-bit slave address.

Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC

pulses are ignored. When RESET is activated, the input register and the DAC register are updated

with zero scale or midscale, depending on the state of the RSTSEL pin.

Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to

V_DDpowers up all four DACs to midscale.

Reference Voltage. The AD5696R/AD5695R/AD5694R have a common reference pin. When using

the internal reference, this is the reference output pin. When using an external reference, this is the

reference input pin. The default for this pin is as a reference output.

14

15

16

1

RSTSEL

V_REF

16

17

2

N/A

V_OUT

EPAD

B

Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

Exposed Pad. The exposed pad must be tied to GND.

Rev. 0 | Page 8 of 32

Data Sheet

AD5696R/AD5695R/AD5694R

TYPICAL PERFORMANCE CHARACTERISTICS

2.5020

V

= 5.5V

0 HOUR

DD

DEVICE 1

DEVICE 2

DEVICE 3

DEVICE 4

DEVICE 5

V

= 5V

DD

168 HOURS

500 HOURS

1000 HOURS

60

50

40

30

20

10

0

2.5015

2.5010

2.5005

2.5000

2.4995

2.4990

2.4985

2.4980

2.498

2.499

2.500

(V)

2.501

2.502

–40

–20

0

20

40

60

80

100

120

V

TEMPERATURE (°C)

REF

Figure 5. Internal Reference Voltage vs. Temperature (Grade B)

Figure 8. Reference Long-Term Stability/Drift

2.5020

1600

1400

1200

1000

800

600

400

200

0

V

= 5V

= 25°C

DD

DEVICE 1

DEVICE 2

DEVICE 3

DEVICE 4

T

A

2.5015

DEVICE 5

2.5010

2.5005

2.5000

2.4995

2.4990

2.4985

2.4980

V

= 5V

120

DD

–40

–20

0

20

40

60

80

100

10

100

1k

10k

100k

1M

TEMPERATURE (°C)

FREQUENCY (MHz)

Figure 6. Internal Reference Voltage vs. Temperature (Grade A)

Figure 9. Internal Reference Noise Spectral Density vs. Frequency

90

V

= 5V

DD

V

= 5V

= 25°C

T

DD

80

70

60

50

40

30

20

10

0

T

A

1

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

CH1 10µV

M1.0s

A CH1

160mV

TEMPERATURE DRIFT (ppm/°C)

Figure 10. Internal Reference Noise, 0.1 Hz to 10 Hz

Figure 7. Reference Output Temperature Drift Histogram

Rev. 0 | Page 9 of 32

AD5696R/AD5695R/AD5694R

Data Sheet

2.5000

10

8

V

= 5V

= 25°C

DD

T

A

2.4999

2.4998

2.4997

2.4996

2.4995

2.4994

2.4993

6

4

2

0

–2

–4

–6

–8

–10

V

= 5V

= 25°C

DD

T

A

INTERNAL REFERENCE = 2.5V

2500 5000 7500

CODE

–0.005

–0.003

–0.001

0.001

(A)

0.003

0.005

0

10000

12500

15000 16348

I

LOAD

Figure 11. Internal Reference Voltage vs. Load Current

Figure 14. AD5695R INL

2.5002

10

8

T

= 25°C

A

D1

D3

2.5000

2.4998

2.4996

2.4994

2.4992

2.4990

6

4

2

0

–2

–4

–6

–8

–10

D2

(V)

V

= 5V

DD

T

= 25°C

A

INTERNAL REFERENCE = 2.5V

2.5

3.0

3.5

4.0

4.5

5.0

5.5

0

625

1250

1875

CODE

2500

3125

3750 4096

V

DD

Figure 12. Internal Reference Voltage vs. Supply Voltage

Figure 15. AD5694R INL

10

1.0

0.8

8

6

0.6

4

0.4

2

0.2

0

–2

–4

–6

–8

–10

–0.2

–0.4

–0.6

–0.8

–1.0

V

= 5V

= 25°C

V

= 5V

DD

T

T = 25°C

A

INTERNAL REFERENCE = 2.5V

10000 20000 30000

CODE

INTERNAL REFERENCE = 2.5V

10000 20000 30000

CODE

0

40000

50000

60000

0

40000

50000

60000

Figure 13. AD5696R INL

Figure 16. AD5696R DNL

Rev. 0 | Page 10 of 32

Data Sheet

AD5696R/AD5695R/AD5694R

10

8

1.0

0.8

6

0.6

4

0.4

2

0.2

INL

0

DNL

–2

–4

–6

–8

–10

–0.2

–0.4

–0.6

V

= 5V

= 25°C

DD

V

= 5V

= 25°C

DD

–0.8

–1.0

T

A

T

A

INTERNAL REFERENCE = 2.5V

2500 5000 7500

CODE

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

0

10000

12500

15000 16383

V

(V)

REF

Figure 17. AD5695R DNL

Figure 20. INL Error and DNL Error vs. V_REF

1.0

0.8

10

8

0.6

6

0.4

4

0.2

2

INL

0

DNL

–0.2

–0.4

–0.6

–0.8

–1.0

–2

–4

–6

–8

–10

V

T

= 5V

= 25°C

V

T

= 5V

= 25°C

DD

A

INTERNAL REFERENCE = 2.5V

2.7 3.2 3.7

SUPPLY VOLTAGE (V)

INTERNAL REFERENCE = 2.5V

0

625

1250

1875

CODE

2500

3125

3750 4096

4.2

4.7

5.2

Figure 18. AD5694R DNL

Figure 21. INL Error and DNL Error vs. Supply Voltage

10

8

0.10

0.08

0.06

0.04

0.02

0

6

4

FULL-SCALE ERROR

GAIN ERROR

2

INL

0

DNL

–2

–4

–6

–8

–10

–0.02

–0.04

–0.06

–0.08

–0.10

V

T

= 5V

= 25°C

V

T

= 5V

= 25°C

DD

A

INTERNAL REFERENCE = 2.5V

–40 –20 20 40

TEMPERATURE (°C)

INTERNAL REFERENCE = 2.5V

–40 10

60

110

0

60

80

100

120

TEMPERATURE (°C)

Figure 19. INL Error and DNL Error vs. Temperature

Figure 22. Gain Error and Full-Scale Error vs. Temperature

Rev. 0 | Page 11 of 32

AD5696R/AD5695R/AD5694R

Data Sheet

0.10

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

V

T

= 5V

= 25°C

V

T

= 5V

= 25°C

DD

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

A

INTERNAL REFERENCE = 2.5V

ZERO-CODE ERROR

OFFSET ERROR

–40

–20

0

20

40

60

80

100

120

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 23. Zero-Code Error and Offset Error vs. Temperature

Figure 26. TUE vs. Temperature

0.10

0.08

0.06

0.04

0.02

0

0.10

0.08

0.06

0.04

0.02

0

GAIN ERROR

FULL-SCALE ERROR

–0.02

–0.04

–0.06

–0.08

–0.10

–0.02

–0.04

–0.06

–0.08

–0.10

V

= 5V

= 25°C

V

= 5V

DD

T

T = 25°C

A

INTERNAL REFERENCE = 2.5V

2.7 3.2 3.7

SUPPLY VOLTAGE (V)

INTERNAL REFERENCE = 2.5V

2.7 3.2 3.7

SUPPLY VOLTAGE (V)

4.2

4.7

5.2

4.2

4.7

5.2

Figure 24. Gain Error and Full-Scale Error vs. Supply

Figure 27. TUE vs. Supply, Gain = 1

0

–0.01

–0.02

–0.03

–0.04

–0.05

–0.06

–0.07

–0.08

–0.09

–0.10

1.5

1.0

0.5

ZERO-CODE ERROR

OFFSET ERROR

0

–0.5

–1.0

–1.5

V

T

= 5V

= 25°C

V

T

= 5V

= 25°C

DD

A

INTERNAL REFERENCE = 2.5V

10000 20000 30000

CODE

2.7

3.2

3.7

4.2

4.7

5.2

0

40000

50000

60000 65535

SUPPLY VOLTAGE (V)

Figure 25. Zero-Code Error and Offset Error vs. Supply

Figure 28. TUE vs. Code

Rev. 0 | Page 12 of 32

Data Sheet

AD5696R/AD5695R/AD5694R

7

6

V

= 5V

= 25°C

DD

V

= 5V

= 25°C

DD

25

20

15

10

5

T

A

T

A

EXTERNAL

REFERENCE = 2.5V

GAIN = 2

INTERNAL

REFERENCE = 2.5V

0xFFFF

5

4

0xC000

0x8000

0x4000

0x0000

3

2

1

0

–1

0

–2

–0.06

540

560

580

600

620

640

–0.04

–0.02

0

0.02

0.04

0.06

I

(V)

DD

LOAD CURRENT (A)

Figure 29. I_DDHistogram with External Reference, 5 V

Figure 32. Source and Sink Capability at 5 V

5

4

V

= 5V

= 25°C

DD

V

= 5V

DD

30

25

20

15

10

5

T

A

T = 25°C

A

INTERNAL

REFERENCE = 2.5V

EXTERNAL REFERENCE = 2.5V

GAIN = 1

0xFFFF

3

0xC000

0x8000

2

1

0x4000

0x0000

0

–1

–2

0

1000

1020

1040

1060

1080

1100

1120

1140

–0.06

–0.04

–0.02

0

0.02

0.04

0.06

I

FULLSCALE (V)

DD

LOAD CURRENT (A)

Figure 30. I_DDHistogram with Internal Reference, V_REFOUT= 2.5 V, Gain = 2

Figure 33. Source and Sink Capability at 3 V

1.0

0.8

0.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

FULL-SCALE

ZERO CODE

0.4

SINKING 2.7V

0.2

SINKING 5V

0

EXTERNAL REFERENCE, FULL-SCALE

–0.2

SOURCING 5V

–0.4

–0.6

–0.8

–1.0

SOURCING 2.7V

15

0

5

10

20

25

30

–40

10

60

110

LOAD CURRENT (mA)

TEMPERATURE (°C)

Figure 31. Headroom/Footroom vs. Load Current

Figure 34. Supply Current vs. Temperature

Rev. 0 | Page 13 of 32

AD5696R/AD5695R/AD5694R

Data Sheet

2.5008

2.5003

2.4998

2.4993

2.4988

4.0

DAC A

DAC B

DAC C

3.5

DAC D

3.0

2.5

2.0

1.5

1.0

CHANNEL B

= 25°C

T

A

V

T

= 5V

= 25°C

V

= 5.25V

DD

INTERNAL REFERENCE

CODE = 7FFF TO 8000

ENERGY = 0.227206nV-sec

0.5

0

A

INTERNAL REFERENCE = 2.5V

¼ TO ¾ SCALE

10

20

40

80

160

320

0

2

4

6

8

10

12

TIME (µs)

Figure 35. Settling Time, 5.25 V

Figure 38. Digital-to-Analog Glitch Impulse

0.06

0.05

0.04

0.03

0.02

0.01

0

6

0.003

0.002

0.001

0

CH A

CH B

CH C

CH D

CH B

CH C

CH D

5

V

DD

4

3

2

1

–0.001

–0.002

0

T

= 25°C

A

INTERNAL REFERENCE = 2.5V

–0.01

–1

15

–10

–5

0

5

10

0

5

10

15

20

25

TIME (µs)

Figure 36. Power-On Reset to 0 V

Figure 39. Analog Crosstalk, Channel A

3

CH A

CH B

CH C

CH D

T

GAIN = 2

SYNC

2

1

0

GAIN = 1

1

V

= 5V

= 25°C

DD

V

= 5V

= 25°C

DD

T

A

T

A

INTERNAL REFERENCE = 2.5V

EXTERNAL REFERENCE = 2.5V

–5

0

5

10

TIME (µs)

CH1 10µV M1.0s

A CH1

802mV

Figure 37. Exiting Power-Down to Midscale

Figure 40. 0.1 Hz to 10 Hz Output Noise Plot, External Reference

Rev. 0 | Page 14 of 32

Data Sheet

AD5696R/AD5695R/AD5694R

4.0

3.9

3.8

3.7

3.6

3.5

3.4

3.3

3.2

3.1

3.0

0nF

V

= 5V

= 25°C

DD

0.1nF

10nF

0.22nF

4.7nF

T

A

T

INTERNAL REFERENCE = 2.5V

1

V

= 5V

= 25°C

DD

T

A

INTERNAL REFERENCE = 2.5V

1.590 1.595 1.600 1.605 1.610 1.615 1.620 1.625 1.630

TIME (ms)

CH1 10µV M1.0s

A CH1

802mV

Figure 44. Settling Time vs. Capacitive Load

Figure 41. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference

0

1600

V

= 5V

= 25°C

DD

FULL-SCALE

MIDSCALE

ZERO-SCALE

T

A

1400

1200

1000

800

600

400

200

0

–10

INTERNAL REFERENCE = 2.5V

–20

–30

–40

–50

–60

V

= 5V

DD

T

= 25°C

A

EXTERNAL REFERENCE = 2.5V, ±0.1V p-p

10k 100k 1M

FREQUENCY (Hz)

10M

10

100

1k

10k

100k

1M

FREQUENCY (Hz)

Figure 45. Multiplying Bandwidth, External Reference = 2.5 V, 0.1 V p-p,

10 kHz to 10 MHz

Figure 42. Noise Spectral Density

20

0

V

= 5V

= 25°C

DD

T

A

INTERNAL REFERENCE = 2.5V

–20

–40

–60

–80

–100

–120

–140

–160

–180

0

2000 4000 6000 8000 10000 12000 14000 16000 18000 20000

FREQUENCY (Hz)

Figure 43. Total Harmonic Distortion @ 1 kHz

Rev. 0 | Page 15 of 32

AD5696R/AD5695R/AD5694R

Data Sheet

TERMINOLOGY

Relative Accuracy or Integral Nonlinearity (INL)

For the DAC, relative accuracy or integral nonlinearity is a

measurement of the maximum deviation, in LSBs, from a

straight line passing through the endpoints of the DAC transfer

function. A typical INL vs. code plot is shown in Figure 13.

Output Voltage Settling Time

This is the amount of time it takes for the output of a DAC to

settle to a specified level for a ¼ to ¾ full-scale input change.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state. It is normally specified as the area of the glitch in nV-sec,

and is measured when the digital input code is changed by

1 LSB at the major carry transition (0x7FFF to 0x8000) (see

Figure 38).

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured

change and the ideal 1 LSB change between any two adjacent

codes. A specified differential nonlinearity of 1 LSB maximum

ensures monotonicity. This DAC is guaranteed monotonic by

design. A typical DNL vs. code plot can be seen in Figure 16.

Digital Feedthrough

Zero-Code Error

Digital feedthrough is a measure of the impulse injected into the

analog output of the DAC from the digital inputs of the DAC,

but is measured when the DAC output is not updated. It is

specified in nV-sec, and measured with a full-scale code change

on the data bus, that is, from all 0s to all 1s and vice versa.

Zero-code error is a measurement of the output error when

zero code (0x0000) is loaded to the DAC register. Ideally, the

output should be 0 V. The zero-code error is always positive in

the AD5696R because the output of the DAC cannot go below

0 V due to a combination of the offset errors in the DAC and

the output amplifier. Zero-code error is expressed in mV. A plot

of zero-code error vs. temperature can be seen in Figure 23.

Reference Feedthrough

Reference feedthrough is the ratio of the amplitude of the signal

at the DAC output to the reference input when the DAC output

is not being updated. It is expressed in dB.

Full-Scale Error

Full-scale error is a measurement of the output error when full-

scale code (0xFFFF) is loaded to the DAC register. Ideally, the

output should be V_DD− 1 LSB. Full-scale error is expressed in

percent of full-scale range (% of FSR). A plot of full-scale error

vs. temperature can be seen in Figure 22.

Noise Spectral Density

This is a measurement of the internally generated random

noise. Random noise is characterized as a spectral density

(nV/√Hz). It is measured by loading the DAC to midscale and

measuring noise at the output. It is measured in nV/√Hz. A plot

of noise spectral density is shown in Figure 42.

Gain Error

This is a measure of the span error of the DAC. It is the deviation

in slope of the DAC transfer characteristic from the ideal

expressed as % of FSR.

DC Crosstalk

DC crosstalk is the dc change in the output level of one DAC in

response to a change in the output of another DAC. It is

measured with a full-scale output change on one DAC (or soft

power-down and power-up) while monitoring another DAC kept

at midscale. It is expressed in μV.

Offset Error Drift

This is a measurement of the change in offset error with a

change in temperature. It is expressed in µV/°C.

Gain Temperature Coefficient

This is a measurement of the change in gain error with changes

in temperature. It is expressed in ppm of FSR/°C.

DC crosstalk due to load current change is a measure of the

impact that a change in load current on one DAC has to

another DAC kept at midscale. It is expressed in μV/mA.

Offset Error

Digital Crosstalk

Offset error is a measure of the difference between V_OUT(actual)

and V_OUT(ideal) expressed in mV in the linear region of the

transfer function. Offset error is measured on the AD5696R

with Code 512 loaded in the DAC register. It can be negative

or positive.

This is the glitch impulse transferred to the output of one DAC

at midscale in response to a full-scale code change (all 0s to all

1s and vice versa) in the input register of another DAC. It is

measured in standalone mode and is expressed in nV-sec.

DC Power Supply Rejection Ratio (PSRR)

This indicates how the output of the DAC is affected by changes

in the supply voltage. PSRR is the ratio of the change in V_OUTto

a change in V_DDfor full-scale output of the DAC. It is measured

in mV/V. V_REFis held at 2 V, and V_DDis varied by 10%.

Rev. 0 | Page 16 of 32

Data Sheet

AD5696R/AD5695R/AD5694R

Analog Crosstalk

Total Harmonic Distortion (THD)

This is the glitch impulse transferred to the output of one DAC

due to a change in the output of another DAC. It is measured by

loading one of the input registers with a full-scale code change

(all 0s to all 1s and vice versa). Then execute a software LDAC

and monitor the output of the DAC whose digital code was not

changed. The area of the glitch is expressed in nV-sec.

This is the difference between an ideal sine wave and its

attenuated version using the DAC. The sine wave is used as the

reference for the DAC, and the THD is a measurement of the

harmonics present on the DAC output. It is measured in dB.

Voltage Reference TC

Voltage reference TC is a measure of the change in the reference

output voltage with a change in temperature. The reference TC

is calculated using the box method, which defines the TC as the

maximum change in the reference output over a given tempera-

ture range expressed in ppm/°C as follows;

DAC-to-DAC Crosstalk

This is the glitch impulse transferred to the output of one DAC

due to a digital code change and subsequent analog output

change of another DAC. It is measured by loading the attack

channel with a full-scale code change (all 0s to all 1s and vice

versa), using the write to and update commands while monitor-

ing the output of the victim channel that is at midscale. The

energy of the glitch is expressed in nV-sec.









V

_REFmax−V_REFmin

TC =

×10⁶

V

×TempRange









REFnom

where:

_REFmaxis the maximum reference output measured over the

total temperature range.

_REFminis the minimum reference output measured over the total

temperature range.

_REFnomis the nominal reference output voltage, 2.5 V.

Multiplying Bandwidth

V

The amplifiers within the DAC have a finite bandwidth. The

multiplying bandwidth is a measure of this. A sine wave on the

reference (with full-scale code loaded to the DAC) appears on

the output. The multiplying bandwidth is the frequency at

which the output amplitude falls to 3 dB below the input.

V

TempRange is the specified temperature range of −40°C to

+105°C.

Rev. 0 | Page 17 of 32

AD5696R/AD5695R/AD5694R

Data Sheet

THEORY OF OPERATION

The resistor string structure is shown in Figure 47. It is a string

of resistors, each of Value R. The code loaded to the DAC register

determines the node on the string where the voltage is to be

tapped off and fed into the output amplifier. The voltage is

tapped off by closing one of the switches connecting the

string to the amplifier. Because it is a string of resistors, it is

guaranteed monotonic.

DIGITAL-TO-ANALOG CONVERTER

The AD5696R/AD5695R/AD5694R are quad 16-/14-/12-bit,

serial input, voltage output DACs with an internal reference.

The parts operate from supply voltages of 2.7 V to 5.5 V. Data is

written to the AD5696R/AD5695R/AD5694R in a 24-bit word

format via a 2-wire serial interface. The AD5696R/AD5695R/

AD5694R incorporate a power-on reset circuit to ensure that the

DAC output powers up to a known output state. The devices also

have a software power-down mode that reduces the typical

current consumption to typically 4 µA.

V

REF

R

TRANSFER FUNCTION

R

The internal reference is on by default. To use an external

reference, only a nonreference option is available. Because the

input coding to the DAC is straight binary, the ideal output

voltage when using an external reference is given by

TO OUTPUT

AMPLIFIER

D

2





V_OUT=V_REF×Gain

N









R

where:

D is the decimal equivalent of the binary code that is loaded to

the DAC register as follows:

0 to 4,095 for the 12-bit device.

0 to 16,383 for the 14-bit device.

0 to 65,535 for the 16-bit device.

Figure 47. Resistor String Structure

N is the DAC resolution.

Internal Reference

Gain is the gain of the output amplifier and is set to 1 by default.

This can be set to ×1 or ×2 using the gain select pin. When this

pin is tied to GND, all four DAC outputs have a span from 0 V

to V_REF. If this pin is tied to V_DD, all four DACs output a span of

The AD5696R/AD5695R/AD5694R on-chip reference is on at

power-up but can be disabled via a write to a control register.

See the Internal Reference Setup section for details.

The AD5696R/AD5695R/AD5694R have a 2.5 V, 2 ppm/°C

reference, giving a full-scale output of 2.5 V or 5 V depending

on the state of the GAIN pin. The internal reference associated

with the device is available at the V_REFpin. This buffered

reference is capable of driving external loads of up to 10 mA.

0 V to 2 × V_REF

.

DAC ARCHITECTURE

The DAC architecture consists of a string DAC followed by an

output amplifier. Figure 46 shows a block diagram of the DAC

architecture.

Output Amplifiers

V

REF

The output buffer amplifier can generate rail-to-rail voltages on

its output, which gives an output range of 0 V to V_DD. The actual

range depends on the value of V_REF, the GAIN pin, offset error,

and gain error. The GAIN pin selects the gain of the output.

2.5V

REF

REF (+)

INPUT

REGISTER

DAC

REGISTER

RESISTOR

STRING

V

X

OUT

REF (–)

•

If this pin is tied to GND, all four outputs have a gain of 1

and the output range is 0 V to V_REF

If this pin is tied to V_LOGIC, all four outputs have a gain of 2

and the output range is 0 V to 2 × V_REF

GAIN

.

(GAIN = 1 OR 2)

GND

•

Figure 46. Single DAC Channel Architecture Block Diagram

.

These amplifiers are capable of driving a load of 1 kΩ in parallel

with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼ to ¾ scale

settling time of 5 µs.

Rev. 0 | Page 18 of 32

Data Sheet

AD5696R/AD5695R/AD5694R

Table 7. Command Definitions

SERIAL INTERFACE

The AD5696R/AD5695R/AD5694R have 2-wire I²C-

Command

C3

0

C2 C1 C0 Description

compatible serial interfaces (refer to I²C-Bus Specification, Version

2.1, January 2000, available from Philips Semiconductor). See

Figure 2 for a timing diagram of a typical write sequence. The

AD5696R/AD5695R/AD5694R can be connected to an I²C bus as

a slave device, under the control of a master device. The

AD5696R/AD5695R/AD5694R support standard (100 kHz)

and fast (400 kHz) data transfer modes. Support is not provided

for 10-bit addressing and general call addressing.

0

1

0

1

0

No operation

LDAC

)

Write to Input Register n (dependent on

0

Update DAC Register n with contents of Input

Register n

0

1

0

1

0

Write to and update DAC Channel n

Power down/power up DAC

0

1

0

1

LDAC

Hardware mask register

0

1

0

1

0

1

0

Software reset (power-on reset)

Internal reference setup register

Reserved

Input Shift Register

The input shift register of the AD5696R/AD5695R/AD5694R is

24 bits wide. Data is loaded into the device as a 24-bit word

under the control of a serial clock input, SCL. The first eight

MSBs make up the command byte. The first four bits are the

command bits (C3, C2, C1, C0) that control the mode of

operation of the device (see Table 7). The last 4 bits of first byte

are the address bits (DAC A, DAC B, DAC C, DAC D) (see

Table 8).

…

1

…

1

…

1

…

1

Reserved

Table 8. Address Commands

Address (n)

DAC D DAC C

DAC B DAC A

Selected DAC Channel¹

DAC A

DAC B

DAC C

DAC D

DAC A and DAC B¹

All DACs

0

1

0

1

0

1

0

1

0

1

0

1

0

1

The data-word comprises 16-bit, 14-bit, or 12-bit input code,

followed by four, two, or zero don’t care bits for the AD5696R,

AD5695R, and AD5694R, respectively (see Figure 48, Figure 49,

and Figure 50). These data bits are transferred to the input

register on the 24 falling edges of SCL.

¹Any combination of DAC channels can be selected using the address bits.

Commands can be executed on individual DAC channels,

combined DAC channels, or on all DACs, depending on the

address bits selected.

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C3

C2

C1

C0 DAC D DAC C DAC B DAC A D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

X

COMMAND

DAC ADDRESS

DAC DATA

COMMAND BYTE

DATA HIGH BYTE

DATA LOW BYTE

Figure 48. AD5696R Input Shift Register Content

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C3

C2

C1

C0 DAC D DAC C DAC B DAC A D13

DAC ADDRESS

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

X

COMMAND

DAC DATA

COMMAND BYTE

DATA HIGH BYTE

DATA LOW BYTE

Figure 49. AD5695R Input Shift Register Content

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

C3

C2

C1

C0 DAC D DAC C DAC B DAC A D15

DAC ADDRESS

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

COMMAND

DAC DATA

COMMAND BYTE

DATA HIGH BYTE

DATA LOW BYTE

Figure 50. AD5694R Input Shift Register Content

Rev. 0 | Page 19 of 32

AD5696R/AD5695R/AD5694R

Data Sheet

Update DAC Register n with Contents of Input Register n

WRITE AND UPDATE COMMANDS

Command 0010 loads the DAC registers/outputs with the

contents of the input registers selected and updates the DAC

outputs directly.

Write to Input Register n (Dependent on

)

LDAC

Command 0001 allows the user to write to each DAC’s

LDAC

dedicated input register individually. When

the input register is transparent (if not controlled by the

mask register).

is low,

LDAC

Write to and Update DAC Channel n (Independent of

)

LDAC

Command 0011 allows the user to write to the DAC registers

and update the DAC outputs directly.

Rev. 0 | Page 20 of 32

Data Sheet

AD5696R/AD5695R/AD5694R

2. Data is transmitted over the serial bus in sequences of nine

clock pulses (eight data bits followed by an acknowledge

bit). The transitions on the SDA line must occur during

the low period of SCL and remain stable during the high

period of SCL.

3. When all data bits have been read or written, a stop

condition is established. In write mode, the master pulls

the SDA line high during the 10^thclock pulse to establish

a stop condition. In read mode, the master issues a no

acknowledge for the 9^thclock pulse (that is, the SDA line

remains high). The master then brings the SDA line low

before the 10^thclock pulse, and then high during the 10^th

clock pulse to establish a stop condition.

SERIAL OPERATION

The AD5696R/AD5695R/AD5694R each have a 7-bit slave

address. The five MSBs are 00011 and the two LSBs (A1, A0)

are set by the state of the A0 and A1 address pins. The ability

to make hardwired changes to A0 and A1 allows the user to

incorporate up to four of these devices on one bus, as outlined

in Table 9.

Table 9. Device Address Selection

A0 Pin Connection

A1 Pin Connection

A0

0

1

A1

0

GND

V_LOGIC

GND

V_LOGIC

0

1

V_LOGIC

1

WRITE OPERATION

The 2-wire serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a start

When writing to the AD5696R/AD5695R/AD5694R, the user

must begin with a start command followed by an address byte

W

(R/ = 0), after which the DAC acknowledges that it is

condition when a high-to-low transition on the SDA line

occurs while SCL is high. The following byte is the address

byte, which consists of the 7-bit slave address. The slave

address corresponding to the transmitted address responds

by pulling SDA low during the 9^thclock pulse (this is

termed the acknowledge bit). At this stage, all other devices

on the bus remain idle while the selected device waits for

data to be written to, or read from, its shift register.

prepared to receive data by pulling SDA low. The AD5696R/

AD5695R/AD5694R require two bytes of data for the DAC

and a command byte that controls various DAC functions.

Three bytes of data must, therefore, be written to the DAC with

the command byte followed by the most significant data byte

and the least significant data byte, as shown in Figure 51. All

these data bytes are acknowledged by the AD5696R/AD5695R/

AD5694R. A stop condition follows.

1

9

1

9

SCL

SDA

0

1

A1

A0

R/W

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16

ACK. BY

AD56x6

START BY

MASTER

AD56x6

FRAME 1

SLAVE ADDRESS

FRAME 2

COMMAND BYTE

1

9

1

9

SCL

(CONTINUED)

SDA

(CONTINUED)

DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB7

DB6 DB5 DB4

DB3

DB2

DB1

DB0

DB8

STOP BY

MASTER

ACK. BY

AD56x6

ACK. BY

AD56x6

FRAME 3

MOST SIGNIFICANT

DATA BYTE

FRAME 4

LEAST SIGNIFICANT

DATA BYTE

Figure 51. I²C Write Operation

Rev. 0 | Page 21 of 32

AD5696R/AD5695R/AD5694R

Data Sheet

MULTIPLE DAC READBACK SEQUENCE

READ OPERATION

W

The user begins with an address byte (R/ = 0), after which the

When reading data back from the AD5696R DACs, the user

DAC acknowledges that it is prepared to receive data by pulling

SDA low. This address byte must be followed by the control

byte, which is also acknowledged by the DAC. The user

configures which channel to start the readback using the

control byte. Following this, there is a repeated start condition

W

begins with an address byte (R/ = 0), after which the DAC

acknowledges that it is prepared to receive data by pulling SDA

low. This address byte must be followed by the control byte that

determines both the read command that is to follow and the

pointer address to read from, which is also acknowledged by

the DAC. The user configures which channel to read back and

sets the readback command to active using the control byte.

Following this, there is a repeated start condition by the master

W

by the master and the address is resent with R/ = 1. This is

acknowledged by the DAC, indicating that it is prepared to

transmit data. The first two bytes of data are then read from the

DAC Input Register n selected using the control byte, most

significant byte first as shown in Figure 52. The next two bytes

read back are the contents of DAC Input Register n + 1, the next

bytes read back are the contents of DAC Input Register n + 2.

Data continues to be read from the DAC input registers in this

auto-incremental fashion, until a NACK followed by a stop

condition follows. If the contents of DAC Input Register D are

read out, the next two bytes of data that are read are from the

contents of DAC Input Register A.

W

and the address is resent with R/ = 1. This is acknowledged

by the DAC, indicating that it is prepared to transmit data.

Two bytes of data are then read from the DAC, as shown in

Figure 52. A NACK condition from the master, followed by a

STOP condition, completes the read sequence. Default readback

is Channel A if more than one DAC is selected.

1

9

1

9

SCL

SDA

0

1

A1

A0

R/W

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16

ACK. BY

AD5696R

START BY

MASTER

AD5696R

FRAME 1

SLAVE ADDRESS

FRAME 2

COMMAND BYTE

1

9

1

9

SCL

SDA

0

1

A1

A0

R/W

DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

REPEATED START BY

MASTER

ACK. BY

AD5696R

ACK. BY

AD5696R

FRAME 3

SLAVE ADDRESS

FRAME 4

MOST SIGNIFICANT

DATA BYTE n

1

9

1

9

SCL

(CONTINUED)

SDA

(CONTINUED)

DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7 DB6

DB5 DB4

DB3 DB2

DB1

DB0

ACK. BY

MASTER

NACK. BY STOP BY

AD5696R MASTER

FRAME 3

FRAME 4

MOST SIGNIFICANT

DATA BYTE n – 1

SLAVE ADDRESS

SIGNIFICANT DATA BYTE n

Figure 52. I²C Read Operation

Rev. 0 | Page 22 of 32

Data Sheet

AD5696R/AD5695R/AD5694R

output stage is also internally switched from the output of the

amplifier to a resistor network of known values. This has the

advantage that the output impedance of the part is known while

the part is in power-down mode. There are three different

power-down options. The output is connected internally to

GND through either a 1 kΩ or a 100 kΩ resistor, or it is left

open-circuited (three-state). The output stage is illustrated in

Figure 53.

POWER-DOWN OPERATION

The AD5696R/AD5695R/AD5694R contain three separate

power-down modes. Command 0100 is designated for the power-

down function (see Table 7). These power-down modes are

software-programmable by setting eight bits, Bit DB7 to Bit DB0,

in the shift register. There are two bits associated with each DAC

channel. Table 10 shows how the state of the two bits corresponds

to the mode of operation of the device.

Table 10. Modes of Operation

AMPLIFIER

V

X

DAC

OUT

Operating Mode

Normal Operation

Power-Down Modes

1 kΩ to GND

100 kΩ to GND

Three-State

PDx1

PDx0

0

1

0

1

POWER-DOWN

CIRCUITRY

RESISTOR

NETWORK

Figure 53. Output Stage During Power-Down

Any or all DACs (DAC A to DAC D) can be powered down

to the selected mode by setting the corresponding bits. See

Table 11 for the contents of the input shift register during

the power-down/power-up operation.

The bias generator, output amplifier, resistor string, and other

associated linear circuitry are shut down when the power-down

mode is activated. However, the contents of the DAC register

are unaffected when in power-down. The DAC register can be

updated while the device is in power-down mode. The time

required to exit power-down is typically 4.5 µs for V_DD= 5 V.

When both Bit PDx1 and Bit PDx0 (where x is the channel

selected) in the input shift register are set to 0, the parts work

normally with its normal power consumption of 4 mA at 5 V.

However, for the three power-down modes, the supply current

falls to 4 μA at 5 V. Not only does the supply current fall, but the

To reduce the current consumption further, the on-chip reference

can be powered off. See the Internal Reference Setup section.

Table 11. 24-Bit Input Shift Register Contents of Power-Down/Power-Up Operation¹

DB15

to

DB8

DB0

(LSB)

DB23 DB22

DB21

DB20

DB19 to DB16

DB7

DB6

DB5

DB4

DB3

DB2

DB1

0

1

0

X

PDD1

PDD0

PDC1

PDC0

PDB1

PDB0 PDA1

PDA0

Command bits (C3 to C0)

Address bits

Don’t care

Power-Down

Select DAC D

Power-Down

Select DAC C

Power-Down

Select DAC B

Power-Down

Select DAC A

¹X = don’t care.

Rev. 0 | Page 23 of 32

AD5696R/AD5695R/AD5694R

Data Sheet

LOAD DAC (HARDWARE LDAC PIN)

LDAC MASK REGISTER

The AD5696R/AD5695R/AD5694R DACs have double

buffered interfaces consisting of two banks of registers:

input registers and DAC registers. The user can write to

any combination of the input registers. Updates to the DAC

LDAC

function.

Command 0101 is reserved for this software

Address bits are ignored. Writing to the DAC, using Command

LDAC

0101, loads the 4-bit

for each channel is 0; that is, the

Setting the bits to 1 forces this DAC channel to ignore transitions

LDAC LDAC

register (DB3 to DB0). The default

LDAC

pin works normally.

LDAC

register are controlled by the

pin.

OUTPUT

AMPLIFIER

on the

pin. This flexibility is useful in applications where the user

LDAC

pin, regardless of the state of the hardware

12-/14-/16-BIT

REFIN

LDAC

V

OUT

DAC

wishes to select which channels respond to the

LDAC

pin.

Table 12.

Load LDAC Register

LDAC Bits

Overwrite Definition

DAC

REGISTER

LDAC Pin LDAC Operation

(DB3 to DB0)

INPUT

REGISTER

0

1

1 or 0

X¹

Determined by the LDAC pin.

DAC channels update and

override the LDAC pin. DAC

channels see LDAC as 1.

SCL

SDO

INPUT SHIFT

REGISTER

¹X = don’t care.

Figure 54. Simplified Diagram of Input Loading Circuitry for a Single DAC

LDAC

The

over the hardware

bits (DB0 to DB3) to 0 for a DAC channel means that this

LDAC

register gives the user extra flexibility and control

LDAC

Instantaneous DAC Updating (

Held Low)

LDAC LDAC

pin (see Table 12). Setting the

LDAC

is held low while data is clocked into the input register

using Command 0001. Both the addressed input register and

the DAC register are updated on the 24^thclock and the output

begins to change (see Table 13).

channel’s update is controlled by the hardware

pin.

LDAC

Deferred DAC Updating (

is Pulsed Low)

LDAC

is held high while data is clocked into the input register

using Command 0001. All DAC outputs are asynchronously

th

LDAC

updated by taking

low after the 24 clock. The update

LDAC

now occurs on the falling edge of

Table 13. Write Commands and

Commands Description

.

1

LDAC

Pin Truth Table

Hardware LDAC

Pin State

Input Register

Contents

DAC Register Contents

No change (no update)

Data update

0001

Write to Input Register n (dependent on LDAC)

V_LOGIC

GND²

Data update

No change

0010

Update DAC Register n with contents of Input

Register n

V_LOGIC

Updated with input register

contents

GND

No change

Updated with input register

contents

0011

Write to and update DAC Channel n

V_LOGIC

GND

Data update

1

LDAC

A high to low hardware

pin transition always updates the contents of the contents of the DAC register with the contents of the input register on channels that

LDAC

are not masked (blocked) by the

mask register.

²When LDAC is permanently tied low, the LDAC mask bits are ignored.

Rev. 0 | Page 24 of 32

Data Sheet

AD5696R/AD5695R/AD5694R

HARDWARE RESET (

)

RESET

SOLDER HEAT REFLOW

RESET

is an active low reset that allows the outputs to be

cleared to either zero scale or midscale. The clear code value is

RESET

As with all IC reference voltage circuits, the reference value

experiences a shift induced by the soldering process. Analog

Devices, Inc., performs a reliability test called precondition to

mimic the effect of soldering a device to a board. The output

voltage specification quoted previously includes the effect of

this reliability test.

user selectable via the

RESET

operation (see Figure 2). When the

high, the output remains at the cleared value until a new value is

programmed. The outputs cannot be updated with a new value

select pin. It is necessary to keep

low for a minimum amount of time to complete the

RESET

signal is returned

Figure 55 shows the effect of solder heat reflow (SHR) as

measured through the reliability test (precondition).

RESET

while the

pin is low. There is also a software executable

reset function that resets the DAC to the power-on reset code.

Command 0110 is designated for this software reset function

POSTSOLDER

HEAT REFLOW

60

50

40

30

20

10

0

LDAC RESET

(see Table 7). Any events on

reset are ignored.

or

during power-on

PRESOLDER

HEAT REFLOW

RESET SELECT PIN (RSTSEL)

The AD5696R/AD5695R/AD5694R contain a power-on reset

circuit that controls the output voltage during power-up. By

connecting the RSTSEL pin low, the output powers up to zero

scale. Note that this is outside the linear region of the DAC; by

connecting the RSTSEL pin high, V_OUTpowers up to midscale.

The output remains powered up at this level until a valid write

sequence is made to the DAC.

2.498

2.499

2.500

(V)

2.501

2.502

V

REF

INTERNAL REFERENCE SETUP

Figure 55. SHR Reference Voltage Shift

The on-chip reference is on at power-up by default. To reduce

the supply current, this reference can be turned off by setting

software programmable bit, DB0, in the control register.

Table 14 shows how the state of the bit corresponds to the

mode of operation. Command 0111 is reserved for setting up

the internal reference (see Figure 6). Table 14 shows how the

state of the bits in the input shift register corresponds to the

mode of operation of the device during internal reference setup.

LONG-TERM TEMPERATURE DRIFT

Figure 56 shows the change in V_REFvalue after 1000 hours in life

test at 150°C.

0 HOUR

168 HOURS

500 HOURS

1000 HOURS

60

50

40

30

20

10

0

Table 14. Reference Setup Register

Internal Reference

Setup Register (DB0) Action

0

1

Reference on (default)

Reference off

2.498

2.499

2.500

(V)

2.501

2.502

V

REF

Figure 56. Reference Drift Through to 1000 Hours

Rev. 0 | Page 25 of 32

AD5696R/AD5695R/AD5694R

Data Sheet

9

8

7

6

5

4

3

2

1

THERMAL HYSTERESIS

FIRST TEMPERATURE SWEEP

SUBSEQUENT TEMPERATURE SWEEPS

Thermal hysteresis is the voltage difference induced on the

reference voltage by sweeping the temperature from ambient

to cold, to hot and then back to ambient.

Thermal hysteresis data is shown in Figure 57. It is measured by

sweeping temperature from ambient to −40°C, then to +105°C,

and returning to ambient. The V_REFdelta is then measured

between the two ambient measurements and shown in blue

in Figure 57. The same temperature sweep and measurements

were immediately repeated and the results are shown in red in

Figure 57.

0

–200

–150

–100

–50

0

50

DISTORTION (ppm)

Figure 57. Thermal Hysteresis

Table 15. 24-Bit Input Shift Register Contents for Internal Reference Setup Command¹

DB23

(MSB)

DB22 DB21

DB20

DB19

DB18

DB17

DB16

DB15 to DB1

X

DB0 (LSB)

0

1

X

1/0

Command bits (C3 to C0)

Address bits (A2 to A0)

Don’t care

Reference setup register

¹X = don’t care.

Rev. 0 | Page 26 of 32

Data Sheet

AD5696R/AD5695R/AD5694R

APPLICATIONS INFORMATION

special considerations to design the motherboard and to mount

the package. For enhanced thermal, electrical, and board level

performance, solder the exposed paddle on the bottom of the

package to the corresponding thermal land paddle on the PCB.

Design thermal vias into the PCB land paddle area to further

improve heat dissipation.

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5696R/AD5695R/

AD5694R is via a serial bus that uses a standard protocol that

is compatible with DSP processors and microcontrollers. The

communications channel requires a 2-wire interface consisting of

a clock signal and a data signal.

The GND plane on the device can be increased (as shown in

Figure 59) to provide a natural heat sinking effect.

AD5696R/AD5695R/AD5694R TO ADSP-BF531

INTERFACE

AD5696R/

AD5695R/

AD5694R

The I²C interface of the AD5696R/AD5695R/AD5694R is

designed to be easily connected to industry-standard DSPs and

microcontrollers. Figure 58 shows the AD5696R/AD5695R/

AD5694R connected to the Analog Devices Blackfin® DSP. The

Blackfin has an integrated I²C port that can be connected

directly to the I²C pins of the AD5696R/AD5695R/AD5694R.

GND

PLANE

AD5696R/

AD5695R/

AD5694R

BOARD

ADSP-BF531

Figure 59. Paddle Connection to Board

GPIO1

GPIO2

SCL

SDA

GALVANICALLY ISOLATED INTERFACE

In many process control applications, it is necessary to

provide an isolation barrier between the controller and

the unit being controlled to protect and isolate the controlling

circuitry from any hazardous common-mode voltages that

may occur. iCoupler® products from Analog Devices provide

voltage isolation in excess of 2.5 kV. The serial loading struc-

ture of the AD5696R/AD5695R/AD5694R makes the part ideal

for isolated interfaces because the number of interface lines is

kept to a minimum. Figure 60 shows a 4-channel isolated

interface to the AD5696R/AD5695R/AD5694R using an

ADuM1400. For further information, visit

PF9

PF8

LDAC

RESET

Figure 58. ADSP-BF531 Interface

LAYOUT GUIDELINES

In any circuit where accuracy is important, careful consider-

ation of the power supply and ground return layout helps

to ensure the rated performance. The PCB on which the

AD5696R/AD5695R/AD5694R are mounted should be

designed so that the AD5696R/AD5695R/AD5694R lie

on the analog plane.

http://www.analog.com/icouplers.

The AD5696R/AD5695R/AD5694R should have ample supply

bypassing of 10 μF in parallel with 0.1 μF on each supply, located as

close to the package as possible, ideally right up against the

device. The 10 μF capacitors are the tantalum bead type. The

0.1 μF capacitor should have low effective series resistance

(ESR) and low effective series inductance (ESI) such as the

common ceramic types, which provide a low impedance path to

ground at high frequencies to handle transient currents due to

internal logic switching.

ADuM1400¹

CONTROLLER

V

IA

IB

IC

ID

OA

OB

OC

OD

TO

SERIAL

ENCODE

DECODE

SCL

CLOCK IN

TO

SDA

SERIAL

DATA OUT

TO

RESET

RESET OUT

In systems where there are many devices on one board, it is

often useful to provide some heat sinking capability to allow

the power to dissipate easily.

LOAD DAC

OUT

TO

LDAC

1

ADDITIONAL PINS OMITTED FOR CLARITY.

The AD5696R/AD5695R/AD5694R LFCSP models have an

exposed paddle beneath the device. Connect this paddle to the

GND supply for the part. For optimum performance, use

Figure 60. Isolated Interface

Rev. 0 | Page 27 of 32

AD5696R/AD5695R/AD5694R

OUTLINE DIMENSIONS

Data Sheet

3.10

3.00 SQ

2.90

0.30

0.23

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

13

16

0.50

BSC

1

4

12

EXPOSED

PAD

1.75

1.60 SQ

1.45

9

8

5

0.50

0.40

0.30

0.25 MIN

TOP VIEW

BOTTOM VIEW

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.80

0.75

0.70

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.

Figure 61. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

3 mm × 3 mm Body, Very Very Thin Quad

(CP-16-22)

Dimensions shown in millimeters

5.10

5.00

4.90

16

9

8

4.50

4.40

4.30

6.40

BSC

1

PIN 1

1.20

MAX

0.15

0.05

0.20

0.09

0.75

0.60

0.45

8°

0°

0.30

0.19

0.65

BSC

SEATING

PLANE

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-153-AB

Figure 62. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

Rev. 0 | Page 28 of 32

Data Sheet

AD5696R/AD5695R/AD5694R

ORDERING GUIDE

Reference

Tempco

(ppm/°C)

Temperature

Range

Package

Description

Package

Option

Model¹

Resolution

16 Bits

14 Bits

12 Bits

Accuracy

8 LSB INL

2 LSB INL

8 LSB INL

2 LSB INL

1 LSB INL

4 LSB INL

1 LSB INL

2 LSB INL

1 LSB INL

Branding

DJA

DJD

AD5696RACPZ-RL7

AD5696RBCPZ-RL7

AD5696RARUZ

AD5696RARUZ-RL7

AD5696RBRUZ

AD5696RBRUZ-RL7

AD5695RBCPZ-RL7

AD5695RARUZ

AD5695RARUZ-RL7

AD5695RBRUZ

AD5695RBRUZ-RL7

AD5694RBCPZ-RL7

AD5694RARUZ

AD5694RARUZ-RL7

AD5694RBRUZ

−40°C to +105°C

5 (typ)

5 (max)

5 (typ)

5 (max)

5 (typ)

5 (max)

5 (typ)

5 (max)

16-Lead LFCSP_WQ CP-16-22

16-Lead TSSOP

RU-16

16-Lead LFCSP_WQ CP-16-22

DJR

DJL

16-Lead TSSOP

RU-16

16-Lead LFCSP_WQ CP-16-22

16-Lead TSSOP

RU-16

AD5694RBRUZ-RL7

EVAL-AD5696RSDZ

AD5696R TSSOP

Evaluation Board

EVAL-AD5694RSDZ

AD5694R TSSOP

Evaluation Board

¹Z = RoHS Compliant Part.

Rev. 0 | Page 29 of 32

AD5696R/AD5695R/AD5694R

NOTES

Data Sheet

Rev. 0 | Page 30 of 32

Data Sheet

NOTES

AD5696R/AD5695R/AD5694R

Rev. 0 | Page 31 of 32

AD5696R/AD5695R/AD5694R

NOTES

Data Sheet

registered trademarks are the property of their respective owners.

D10486-0-4/12(0)

Rev. 0 | Page 32 of 32


型号：	AD5684R
厂家：	ADI
描述：	Quad 16-/14-/12-Bit nanoDAC 四通道16位/ 14位/ 12位属于nanoDAC
文件：	总32页 (文件大小：755K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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