AD5724RBREZ-REEL7 [ADI]
Complete, Quad, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar Voltage Output DACs; 完整的四通道， 12位/ 14位/ 16位，串行输入，单极性/双极性电压输出DAC
| 型号： | AD5724RBREZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | Complete, Quad, 12-/14-/16-Bit, Serial Input, Unipolar/Bipolar Voltage Output DACs |
| 文件： | 总32页 (文件大小：302K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Complete, Quad, 12-/14-/16-Bit, Serial Input,
Unipolar/Bipolar Voltage Output DACs
Preliminary Technical Data
AD5724R/AD5734R/AD5754R
FEATURES
GENERAL DESCRIPTION
Complete, quad, 12-/14-/16-bit D/A converter
Operates from single/dual supplies
Software programmable output range
+5 V, +10 V, +10.8 V, 5 V, 10 V, 10.8 V
The AD5724R/AD5734R/AD5754R are quad, 12-/14-/16-bit
serial input, voltage output, digital-to-analog converters. They
operate from single supply voltages of +4.5 V up to +16.5 V or
dual supply voltages from 4.5 V up to 16.5 V. Nominal full-
INL error: 16 LSB maximum, DNL error: 1 LSB maximum
Total unadjusted error (TUE): 0.1% FSR maximum
Settling time: 10 µs maximum
Integrated reference: 5 ppm/°C typ.
Integrated reference buffers
Output control during power-up/brownout
Simultaneous updating via LDAC
Asynchronous CLR to zero-/mid-scale
DSP/microcontroller-compatible serial interface
24-lead TSSOP
scale output range is software-selectable from the options of
+5 V, +10 V, +10.8 V, 5 V, 10 V, or 10.8 V. Integrated output
amplifiers, reference buffers, and proprietary power-up/power-
down control circuitry are also provided.
The parts offer guaranteed monotonicity, integral nonlinearity
(INL) of 16 LꢀB maximum, low noise, 10 µs maximum settling
time, and an on-chip +2.5 V reference.
The AD5724R/AD5734R/AD5754R use a serial interface that
operates at clock rates up to 30 MHz and are compatible with
DꢀP and microcontroller interface standards. Double buffering
allows the simultaneous updating of all DACs. The input coding
is user-selectable twos complement or offset binary for a bipolar
Operating temperature range: −40°C to +85°C
iCMOS™ process technology1
APPLICATIONS
2sComp
output (depending on the state of pin BIN/
), and
Industrial automation
straight binary for a unipolar output. The asynchronous clear
function clears all DAC registers to a user-selectable zero-scale
or mid-scale output. The parts are available in a 24-lead TꢀꢀOP
and offer guaranteed specifications over the −40°C to +85°C
industrial temperature range.
Closed-loop servo control, process control
Automotive test and measurement
Programmable logic controllers
Table 1. Pin Compatible Devices
Part Number
Description
AD5724/AD5734/AD5754
AD5724R/AD5734R/AD5754R
without internal reference.
AD5722/AD5732/AD5752
Complete, dual, 12-/14-/16-bit,
serial input, unipolar/bipolar,
voltage output DAC.
AD5722R/AD5732R/AD5752R AD5722/AD5732/AD5752 with
internal reference.
1 For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a technology
platform that enables the development of analog ICs capable of 30 V and operating at ±15 V supplies while allowing dramatic reductions in power consumption and
package size, and increased AC and DC performance.
Rev. PrC
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
AD5724R/AD5734R/AD5754R
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
CLR
)....................................................... 23
Asynchronous Clear (
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
ꢀpecifications..................................................................................... 4
Dual ꢀupply ꢀpecifications.......................................................... 4
ꢀingle ꢀupply ꢀpecifications........................................................ 6
AC Performance Characteristics................................................ 7
Timing Characteristics ................................................................ 8
Absolute Maximum Ratings.......................................................... 11
EꢀD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Typical Performance Characteristics ........................................... 13
Terminology .................................................................................... 19
Theory of Operation ...................................................................... 21
Architecture................................................................................. 21
ꢀerial Interface ............................................................................ 21
Configuring the AD5724R/AD5734R/AD5754R.................. 23
Transfer Function....................................................................... 23
Input Register.............................................................................. 27
Data Register............................................................................... 27
Output Range ꢀelect Register ................................................... 28
Control Register ......................................................................... 28
Power Control Register ............................................................. 29
Features............................................................................................ 30
Analog Output Control ............................................................. 30
Overcurrent Protection ............................................................. 30
Thermal ꢀhutdown .................................................................... 30
Internal Reference ...................................................................... 30
Applications Information.............................................................. 31
Layout Guidelines....................................................................... 31
Galvanically Isolated Interface ................................................. 31
Microprocessor Interfacing....................................................... 31
Outline Dimensions....................................................................... 32
Ordering Guide .......................................................................... 32
LDAC
Load DAC (
)..................................................................... 23
REVISION HISTORY
PrC – Preliminary Revision, November 16, 2007
Rev. PrC | Page 2 of 32
Preliminary Technical Data
FUNCTIONAL BLOCK DIAGRAM
AD5724R/AD5734R/AD5754R
AV
AV
DD
REFIN/REFOUT
SS
DV
CC
2.5V
REFERENCE
REFERENCE
BUFFERS
AD5754R
16
16
16
16
16
INPUT
REGISTER A
DAC
REGISTER A
DAC A
DAC B
DAC C
DAC D
SDIN
SCLK
SYNC
SDO
V
A
OUT
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
INPUT
REGISTER B
DAC
REGISTER B
V
V
V
B
C
D
OUT
OUT
OUT
INPUT
REGISTER C
DAC
REGISTER C
CLR
BIN/2sCOMP
INPUT
DAC
REGISTER D
REGISTER D
DAC_GND (2)
SIG_GND (2)
GND
LDAC
Figure 1.
Rev. PrC | Page 3 of 32
AD5724R/AD5734R/AD5754R
Preliminary Technical Data
SPECIFICATIONS
DUAL SUPPLY SPECIFICATIONS
AVDD = 4.5 V1 to 16.5 V, AVꢀꢀ = −4.5 V1 to −16.5 V, GND = 0 V, REFIN= +2.5 V external, DVCC = 2.7 V to 5.5 V,
R
LOAD = 2 kΩ, CLOAD = 200 pF; all specifications TMIN to TMAX
,
10 V range unless otherwise noted.
Table 2.
Parameter
ACCURACY
Bipolar Output
Resolution
AD5754R
Value
Unit
Test Conditions/Comments
Outputs unloaded
16
14
12
0.1
Bits
Bits
Bits
AD5734R
AD5724R
Total Unadjusted Error (TUE)
% FSR max
Over temperature, supplies, and time
Relative Accuracy (INL)
B Grade
±16
±1
±5
±±
±1
±±
±0.05
±±
LSB max
LSB max
mV max
ppm FSR/°C max
mV max
ppm FSR/°C max
% FSR max
ppm FSR/°C max
LSB max
@ 16-bit resolution
Guaranteed monotonic (@ 16-bit resolution)
@ 25°C, error at other temperatures obtained using Bipolar ZeroTC
Differential Nonlinearity (DNL)
Bipolar Zero Error
Bipolar Zero TC2
Zero-Scale Error
Zero-Scale TC2
@ 25°C, error at other temperatures obtained using Zero Scale TC
@ 25°C, error at other temperatures obtained using Gain TC
@ 16-bit resolution
Gain Error
Gain TC2
DC Crosstalk2
0.6
Unipolar Output
Resolution
AD5754R
AD5734R
AD5724R
Total Unadjusted Error (TUE)
Relative Accuracy (INL)
B Grade
Differential Nonlinearity (DNL)
Zero-Scale Error
Zero-Scale TC2
16
14
12
0.1
Bits
Bits
Bits
% FSR max
Over temperature, supplies, and time
±16
±1
+10
±4
±10
±0.05
±4
LSB max
LSB max
mV max
ppm FSR/°C max
mV max
% FSR max
ppm FSR/°C max
LSB max
@ 16-bit resolution
Guaranteed monotonic (@ 16 bit-resolution)
@ 25°C, error at other temperatures obtained using Zero-Scale TC
Offset Error
Gain Error
@ 25°C, error at other temperatures obtained using Gain TC
@ 16-bit resolution
Gain TC2
DC Crosstalk2
0.6
REFERENCE INPUT/OUTPUT
Reference Input2
Reference Input Voltage
DC Input Impedance
Input Current
Reference Range
Reference Output
Output Voltage
Reference TC
2.5
1
±10
2 to 3
V nom
MΩ min
µA max
V min to V max
±1% for specified performance
Typically 100 MΩ
Typically ±30 nA
2.49± to 2.502 V min to V max
±5
@ 25°C
ppm/°C typ
±10
ppm/°C max
µV p-p typ
nV/√Hz typ
ppm/500 hr typ
ppm/1000 hr typ
Output Noise (0.1 Hz to 10 Hz)2 1±
Noise Spectral Density2
75
±40
±50
@ 10 kHz
Output Voltage Drift vs. Time2
Rev. PrC | Page 4 of 32
Preliminary Technical Data
AD5724R/AD5734R/AD5754R
Parameter
Value
Unit
Test Conditions/Comments
OUTPUT CHARACTERISTICS2
Output Voltage Range
±10.±
±12
0.9
V min to V max
V min to V max
V max
AVDD/AVSS = ±11.7 V min , REFIN = +2.5 V
AVDD/AVSS = ±12.9 V min, REFIN = +3 V
Headroom
0.5
V typ
Output Voltage TC
±±
ppm FSR/°C max
Output Voltage Drift vs. Time
±12
ppm FSR/500 hr
typ
±15
ppm FSR/1000 hr
typ
Short-Circuit Current
Load
Capacitive Load Stability
DC Output Impedance
DIGITAL INPUTS2
20
2
4000
0.5
mA typ
kΩ min
pF max
Ω typ
For specified performance
DVCC = 2.7 V to 5.5 V, JEDEC compliant
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
2
V min
0.±
±1
5
V max
µA max
pF typ
Per pin
Per pin
Pin Capacitance
DIGITAL OUTPUTS (SDO) 2
VOL, Output Low Voltage
VOH, Output High Voltage
VOL, Output Low Voltage
VOH, Output High Voltage
High Impedance Leakage Current ±1
High Impedance Output
Capacitance
0.4
DVCC − 1
0.4
V max
V min
V max
V min
µA max
pF typ
DVCC = 5 V ± 10%, sinking 200 µA
DVCC = 5 V ± 10%, sourcing 200 µA
DVCC = 2.7 V to 3.6 V, sinking 200 µA
DVCC = 2.7 V to 3.6 V, sourcing 200 µA
DVCC − 0.5
5
POWER REQUIREMENTS
AVDD
AVSS
DVCC
4.5 to 16.5
-4.5 to -16.5
2.7 to 5.5
V min to V max
V min to V max
V min to V max
Power Supply Sensitivity2
∆VOUT/∆ΑVDD
AIDD
AISS
DICC
−75
2
1.5
1
dB typ
200mV sine wave superimposed on AVSS/AVDD @ 50/60 Hz
mA/channel max Outputs unloaded
mA/channel max Outputs unloaded
µA max
mW typ
VIH = DVCC, VIL = GND, 0.5 µA typ
±12 V operation, outputs unloaded
Power Dissipation
TBD
Power-Down Currents
All DAC channels and internal reference powered-down
AIDD
AISS
DICC
±0
TBD
TBD
µA typ
µA typ
µA typ
1 For specified performance minimum headroom requirement is 0.9V
2 Guaranteed by characterization. Not production tested.
Rev. PrC | Page 5 of 32
AD5724R/AD5734R/AD5754R
Preliminary Technical Data
SINGLE SUPPLY SPECIFICATIONS
AVDD = 4.5 V1 to 16.5 V, AVꢀꢀ = 0 V, GND = 0 V, REFIN= 2.5 V external, DVCC = 2.7 V to 5.5 V,
RLOAD = 2 kΩ, CLOAD = 200 pF; all specifications TMIN to TMAX, 10 V range unless otherwise noted.
Table 3.
Parameter
Value
Unit
Test Conditions/Comments
Outputs unloaded
ACCURACY
Resolution
AD5754R
AD5734R
AD5724R
Total Unadjusted Error (TUE)
Relative Accuracy (INL)
B Grade
Differential Nonlinearity (DNL)
Zero-Scale Error
16
14
12
0.1
Bits
Bits
Bits
% FSR max
Across temperature and supplies
±16
±1
+10
LSB max
LSB max
mV max
@ 16-bit resolution
Guaranteed monotonic (@ 16-bit resolution)
@ 25°C, error at other temperatures obtained using Zero-Scale
TC
Zero-Scale TC2
Offset Error
±4
ppm FSR/°C max
mV max
% FSR max
ppm FSR/°C max
LSB max
±10
±0.02
±±
Gain Error
@ 25°C, error at other temperatures obtained using Gain TC
@ 16-bit resolution
Gain TC2
DC Crosstalk2
0.6
REFERENCE INPUT/OUTPUT
Reference Input2
Reference Input Voltage
DC Input Impedance
Input Current
Reference Range
Reference Output
Output Voltage
2.5
1
±10
2 to 3
V nom
MΩ min
µA max
±1% for specified performance
Typically 100 MΩ
Typically ±30 nA
V min to max
2.49± to 2.502 V min to V max
@ 25°C
Reference TC
±5
1±
75
±40
±50
ppm/°C max
µV p-p typ
nV/√Hz typ
ppm/500 hr typ
ppm/1000 hr typ
Output Noise (0.1 Hz to 10 Hz)2
Noise Spectral Density2
Output Drift vs. Time2
@ 10 kHz
OUTPUT CHARACTERISTICS2
Output Voltage Range
10.±
12
V max
V max
AVDD = 11.7 V min, REFIN = 2.5 V
AVDD = 12.9 V min, REFIN = 3.75 V
Headroom
0.9
0.5
±±
±12
±15
20
V max
V typ
ppm FSR/°C max
ppm/500 hr typ
ppm/1000 hr typ
mA typ
Output Voltage TC
Output Voltage Drift vs. Time
Short Circuit Current
Load
2
KΩ min
For specified performance
Capacitive Load Stability
DC Output Impedance
DIGITAL INPUTS2
4000
0.5
pF max
Ω typ
DVCC = 2.7 V to 5.5 V, JEDEC compliant
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
2
V min
0.±
±1
5
V max
µA max
pF max
Per pin
Per pin
Pin Capacitance
DIGITAL OUTPUTS (SDO)2
VOL, Output Low Voltage
0.4
V max
DVCC = 5 V ± 10%, sinking 200 µA
Rev. PrC | Page 6 of 32
Preliminary Technical Data
AD5724R/AD5734R/AD5754R
Parameter
Value
Unit
Test Conditions/Comments
VOH, Output High Voltage
VOL, Output Low Voltage
VOH, Output High Voltage
High Impedance Leakage Current
High Impedance Output
Capacitance
DVCC − 1
0.4
DVCC − 0.5
±1
5
V min
V max
V min
µA max
pF typ
DVCC = 5 V ± 10%, sourcing 200 µA
DVCC = 2.7 V to 3.6 V, sinking 200 µA
DVCC = 2.7 V to 3.6 V, sourcing 200 µA
POWER REQUIREMENTS
AVDD
DVCC
4.5 to 16.5
2.7 to 5.5
V min to V max
V min to V max
Power Supply Sensitivity2
∆VOUT/∆ΑVDD
AIDD
DICC
−75
2.75
1
dB typ
200mV sine wave superimposed on AVDD @ 50/60 Hz
mA/channel max Outputs unloaded
µA max
mW typ
VIH = DVCC, VIL = GND, 0.5 µA typ
12 V operation, outputs unloaded
Power Dissipation
TBD
Power-down currents
All DAC channels and internal reference powered-down
AIDD
DICC
±0
TBD
µA typ
µA typ
1 For specified performance minimum headroom requirement is 0.9V
2 Guaranteed by characterization. Not production tested.
AC PERFORMANCE CHARACTERISTICS
AVDD = 4.51 V to 16.5 V, AVꢀꢀ = −4.51 V to −16.5 V / 0V, GND = 0 V, REFIN= 2.5 V external, DVCC = 2.7 V to 5.5 V,
R
LOAD = 2 kΩ, CLOAD = 200 pF; all specifications TMIN to TMAX
,
10 V range unless otherwise noted.
Table 4.
Parameter2
B Grade
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time
±
10
5
µs typ
µs max
µs typ
Full-scale step (20 V) to ±0.03 % FSR
512 LSB step settling (@ 16 bits)
Slew Rate
4.5
35
25
10
10
0.1
0.05
±0
1
V/µs typ
nV-sec typ
mV typ
nV-sec typ
nV-sec typ
nV-sec typ
LSB p-p typ
µV rms typ
kHz typ
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Digital Crosstalk
DAC-to-DAC Crosstalk
Digital Feedthrough
Output Noise (0.1 Hz to 10 Hz Bandwidth)
Output Noise (100 kHz Bandwidth)
1/f Corner Frequency
@ 16 bit resolution
Measured at 10 kHz
Output Noise Spectral Density
120
nV/√Hz typ
1 For specified performance headroom requirement is 0.9V
2 Guaranteed by design and characterization, not production tested.
Rev. PrC | Page 7 of 32
AD5724R/AD5734R/AD5754R
Preliminary Technical Data
TIMING CHARACTERISTICS
AVDD = 4.5 V to 16.5 V, AVꢀꢀ = −4.5 V to −16.5 V / 0V, GND = 0 V, REFIN = 2.5 V external, DVCC = 2.7 V to 5.5 V,
LOAD = 2 kΩ, CLOAD = 200 pF; all specifications TMIN to TMAX, unless otherwise noted.
R
Table 5.
Parameter1, 2, 3
Limit at TMIN, TMAX
Unit
Description
t1
t2
t3
t4
33
13
13
13
13
100
5
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
µs max
µs max
µs max
ns min
µs max
ns min
ns max
ns min
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time (write mode)
Data setup time
t5
t6
t7
t±
t9
0
Data hold time
20
20
20
1.5
10
1.5
20
2.5
13
40
200
LDAC falling edge to SYNC falling edge
SYNC rising edge to LDAC falling edge
LDAC pulse width low
t10
t11
t12
t13
t14
t15
t16
LDAC falling edge to DAC output response time
DAC output settling time
SYNC rising edge to output response time (LDAC = 0)
CLR pulse width low
CLR pulse activation time
4
t17
SYNC rising edge to SCLK falling edge
SCLK rising edge to SDO valid (CL SDO5 = 15 pF)
Minimum SYNC high time (readback/daisy-chain mode)
4
t1±
t19
1 Guaranteed by characterization. Not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, and Figure 4.
4 Daisy-chain and Readback mode.
5 CL SDO = Capacitive load on SDO output.
Rev. PrC | Page ± of 32
Preliminary Technical Data
AD5724R/AD5734R/AD5754R
t1
SCLK
1
2
24
t2
t3
t6
t5
t4
SYNC
SDIN
t8
t7
DB23
DB0
t11
t9
t10
LDAC
t13
t12
V
V
X
OUT
OUT
t13
t14
X
t15
CLR
t16
V
X
OUT
Figure 2. Serial Interface Timing Diagram
t1
SCLK
24
48
t3
t2
t5
t19
t17
t4
SYNC
SDIN
t8
t7
DB23
DB0
DB23
DB0
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N-1
t18
DB23
DB0
SDO
t10
UNDEFINED
INPUT WORD FOR DAC N
t11
LDAC
Figure 3. Daisy Chain Timing Diagram
Rev. PrC | Page 9 of 32
AD5724R/AD5734R/AD5754R
Preliminary Technical Data
SCLK
1
1
24
24
t19
SYNC
DB23
DB23
DB0
DB23
DB0
SDIN
SDO
INPUT WORD SPECIFIES
REGISTER TO BE READ
NOP CONDITION
DB0
DB23
DB0
UNDEFINED
SELECTED REGISTER DATA
CLOCKED OUT
Figure 4. Readback Timing Diagram
Rev. PrC | Page 10 of 32
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
AD5724R/AD5734R/AD5754R
TA = 25°C unless otherwise noted.
Transient currents of up to 100 mA do not cause ꢀCR latch-up.
Table 6.
Parameter
ꢀtresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
AVDD to GND
AVSS to GND
DVCC to GND
Digital Inputs to GND
−0.3 V to +17 V
+0.3 V to −17 V
−0.3 V to +7 V
−0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
Digital Outputs to GND
−0.3 V to DVCC + 0.3 V or 7V
(whichever is less)
−0.3 V to +17 V
AVSS to AVDD
-0.3V to +0.3V
ESD CAUTION
REFIN/REFOUT to GND
VOUTA, VOUTB, VOUTC, VOUTD to GND
DAC_GND to GND
SIG_GND to GND
-0.3V to +0.3V
Operating Temperature Range, TA
Industrial
−40°C to +±5°C
−65°C to +150°C
105°C
Storage Temperature Range
Junction Temperature, TJ max
24-Lead TSSOP Package
θJA Thermal Impedance
Power Dissipation
90°C/W
(TJ max – TA)/ θJA
JEDEC Industry Standard
J-STD-020
Lead Temperature
Soldering
Rev. PrC | Page 11 of 32
Preliminary Technical Data
AD5724R/AD5734R/AD5754R
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AV
AV
1
2
3
4
5
6
7
8
9
24
23
22
21
DD
SS
NC
A
V
V
C
OUT
AD5724R/
AD5734R/
AD5754R
D
V
V
OUT
OUT
B
SIG_GND
OUT
20 SIG_GND
BIN/2sCOMP
NC
TOP VIEW
(Not to Scale)
19
18
DAC_GND
DAC_GND
SYNC
17 REFIN/REFOUT
16 SDO
SCLK
SDIN
LDAC 10
15 GND
DV
11
14
13
CLR
CC
NC
12
NC
NC = NO CONNECT
Figure 5.Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
AVSS
Negative Analog Supply Pin. Voltage ranges from –4.5 V to –16.5 V. This pin can be connected to 0 V if output
ranges are unipolar.
2, 6, 12, 13 NC
Do not connect to these pins.
3
4
5
VOUT
VOUT
BIN/2sCOMP
A
B
Analog Output Voltage of DAC A. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
Analog Output Voltage of DAC B. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
Determines the DAC coding for a bipolar output range. This pin should be hardwired to either DVCC or GND.
When hardwired to DVCC, input coding is offset binary. When hardwired to GND, input coding is twos
complement. (For unipolar output ranges, coding is always straight binary).
7
±
SYNC
SCLK
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is
transferred on the falling edge of SCLK.
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock
speeds up to 30 MHz.
9
SDIN
Serial Data Input. Data must be valid on the falling edge of SCLK.
10
LDAC
Load DAC, Logic Input. This is used to update the DAC registers and consequently, the analog output. When
tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If LDAC is held high
during the write cycle, the DAC input register is updated, but the output update is held off until the falling
edge of LDAC. In this mode, all analog outputs can be updated simultaneously on the falling edge of LDAC.
The LDAC pin should not be left unconnected.
11
14
15
16
CLR1
DVCC
GND
SDO
Active Low Input. Asserting this pin sets the DAC registers to zero-scale code or mid-scale code (user-selectable).
Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.
Ground Reference Pin.
Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode. Data is
clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.
17
REFIN/REFOUT External Reference Voltage Input and Internal Reference Voltage Output. Reference input range is 2 V to 3 V.
REFIN = 2.5 V for specified performance. REFOUT = 2.5 V ± 2 mV @ 25°C.
1±, 19
20, 21
22
23
24
DAC_GND
SIG_GND
Ground reference pins for the four digital-to-analog converters.
Ground reference pins for the four output amplifiers.
VOUT
VOUT
D
C
Analog Output Voltage of DAC D. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
Analog Output Voltage of DAC C. The output amplifier is capable of directly driving a 2 kΩ, 4000 pF load.
Positive Analog Supply Pin. Voltage ranges from 4.5 V to 16.5 V.
Negative Analog Supply connection. Voltage ranges from –4.5 V to –16.5 V. This paddle can be connected to
0 V if output ranges are unipolar.
AVDD
AVSS
Exposed
Paddle
1 Internal pull-up device on this logic input. Therefore, it can be left floating and defaults to a logic high.
Rev. PrC | Page 12 of 32
Preliminary Technical Data
AD5724R/AD5734R/AD5754R
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 6. AD5754R Integral Nonlinearity Error vs. Code (Four Traces)
Figure 9. AD5754R Differential Nonlinearity Error vs. Code (Four Traces)
Figure 7. AD5734R Integral Nonlinearity Error vs. Code (Four Traces)
Figure 10. AD5734R Differential Nonlinearity Error vs. Code (Four Traces)
Figure 8. AD5724R Integral Nonlinearity Error vs. Code (Four Traces)
Figure 11. AD5724R Differential Nonlinearity Error vs. Code (Four Traces)
Rev. PrC | Page 13 of 32
AD5724R/AD5734R/AD5754R
Preliminary Technical Data
Figure 12. AD5754R Integral Nonlinearity Error vs. Temperature (Four Traces)
Figure 13. AD5754R Differential Nonlinearity Error vs. Temperature (Four Traces)
Figure 14. AD5754R Integral Nonlinearity Error vs. Supply Voltage (Four Traces)
Figure 15.AD5754R Differential Nonlinearity Error vs. Supply Voltage (Four Traces)
Figure 16. AD5754R Integral Nonlinearity Error vs. Reference Voltage (Four Traces)
Figure 17. AD5754R Differential Nonlinearity vs. Reference Voltage (Four Traces)
Rev. PrC | Page 14 of 32
Preliminary Technical Data
AD5724R/AD5734R/AD5754R
Figure 18. AD5754R Total Unadjusted Error vs. Reference Voltage (Four Traces)
Figure 19. AD5754R Total Unadjusted Error vs. Supply Voltage (Four Traces)
Figure 20. AIDD/AISS vs. AVDD/AVSS
Figure 21. AIDD vs. AVDD
Figure 22. Zero-Scale Error vs. Temperature (Four Traces)
Figure 23. Bipolar Zero Error vs. Temperature (Two Traces)
Rev. PrC | Page 15 of 32
AD5724R/AD5734R/AD5754R
Preliminary Technical Data
Figure 24. Gain Error vs. Temperature (Four Traces)
Figure 25. DICC vs. Logic Input Voltage Increasing and Decreasing
Figure 26. Output Amplifier Source and Sink Capability (Four Traces)
Figure 27. Full-Scale Settling Time, 10 V Range (Two Traces)+ve & -ve
Figure 28. Full-Scale Settling Time, 5 V Range (Two Traces)
Figure 29. Full-Scale Settling Time, +10 V Range (Two Traces)
Rev. PrC | Page 16 of 32
Preliminary Technical Data
AD5724R/AD5734R/AD5754R
Figure 30. Full-Scale Settling Time, +5 V Range (Two Traces)
Figure 33. Peak-to-Peak Noise, 100 kHz Bandwidth, (Four Traces)
Figure 34. VOUT vs. AVDD/AVSS on Power Up (Two Traces) (single and dual)
Figure 31. Digital-to-Analog Glitch Energy (Four Traces)
Figure 32. Peak-to-Peak Noise, 0.1 Hz to 10 Hz Bandwidth (Four Traces)
Figure 35. REFOUT Turn-On Transient
Rev. PrC | Page 17 of 32
AD5724R/AD5734R/AD5754R
Preliminary Technical Data
Figure 36. REFOUT Output Noise (100 kHz Bandwidth)
Figure 39. REFOUT Load Transient (Two Traces)
Figure 37. REFOUT Output Noise (0.1 Hz to 10 Hz Bandwidth)
Figure 40. REFOUT Histogram of Thermal Hysteresis
Figure 41. REFOUT Voltage vs. Load Current
Figure 38. REFOUT Line Transient (Two Traces)
Rev. PrC | Page 1± of 32
Preliminary Technical Data
TERMINOLOGY
AD5724R/AD5734R/AD5754R
Slew Rate
Relative Accuracy or Integral Nonlinearity (INL)
The slew rate of a device is a limitation in the rate of change of
the output voltage. The output slewing speed of a voltage output
D/A converter is usually limited by the slew rate of the amplifier
used at its output. ꢀlew rate is measured from 10% to 90% of the
output signal and is given in V/µs.
For the DAC, relative accuracy, or integral nonlinearity, is a
measure of the maximum deviation in LꢀBs from a straight line
passing through the endpoints of the DAC transfer function. A
typical INL vs. code plot can be seen in Figure 6.
Differential Nonlinearity (DNL)
Gain Error
Differential nonlinearity is the difference between the measured
change and the ideal 1 LꢀB change between any two adjacent
codes. A specified differential nonlinearity of 1 LꢀB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot can be seen in Figure 9.
This is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed in % FꢀR. A plot of gain error vs. temperature can be
seen in Figure 24.
Gain TC
Monotonicity
This is a measure of the change in gain error with changes in
temperature. Gain TC is expressed in ppm FꢀR/°C.
A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5724R/
AD5734R/AD5754R are monotonic over their full operating
temperature range.
Total Unadjusted Error (TUE)
Total unadjusted error is a measure of the output error taking
all the various errors into account, namely INL error, offset
error, gain error, and output drift over supplies, temperature,
and time. TUE is expressed in % FꢀR.
Bipolar Zero Error
Bipolar zero error is the deviation of the analog output from the
ideal half-scale output of 0 V when the DAC register is loaded
with 0x8000 (straight binary coding) or 0x0000 (twos complement
coding). A plot of bipolar zero error vs. temperature can be seen
in Figure 23.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state, but the output voltage remains constant. It is normally
specified as the area of the glitch in nV-sec and is measured
when the digital input code is changed by 1 LꢀB at the major
carry transition (0x7FFF to 0x8000). ꢀee Figure 31.
Bipolar Zero TC
Bipolar Zero TC is a measure of the change in the bipolar zero
error with a change in temperature. It is expressed in ppm
FꢀR/°C.
Glitch Impulse Peak Amplitude
Zero-Scale Error/Negative Full-Scale Error
Glitch impulse peak amplitude is the peak amplitude of the
impulse injected into the analog output when the input code in
the DAC register changes state. It is specified as the amplitude
of the glitch in mV and is measured when the digital input code
is changed by 1 LꢀB at the major carry transition (0x7FFF to
0x8000). ꢀee Figure 31.
Zero-scale error is the error in the DAC output voltage when
0x0000 (straight binary coding) or 0x8000 (twos complement
coding) is loaded to the DAC register. Ideally, the output voltage
should be negative full-scale− 1 LꢀB. A plot of zero-scale error
vs. temperature can be seen in Figure 22.
Zero-Scale TC
Digital Feedthrough
This is a measure of the change in zero-scale error with a change in
temperature. Zero-ꢀcale TC is expressed in ppm FꢀR/°C.
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-sec and measured with a full-scale code
change on the data bus.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output to settle to a specified level for a full-scale input
change. A plot of settling time can be seen in Figure 27.
Power Supply Sensitivity
Power supply sensitivity indicates how the output of the DAC is
affected by changes in the power supply voltage, it is measured
by superimposing a 50/60Hz, 200mVpk-pk sine wave on the
supply voltages and measuring the proportion of the sine wave
that transfers to the outputs.
Rev. PrC | Page 19 of 32
AD5724R/AD5734R/AD5754R
Preliminary Technical Data
DC Crosstalk
DAC-to-DAC Crosstalk
This is the dc change in the output level of one DAC in response
to a change in the output of another DAC. It is measured with a
full-scale output change on one DAC while monitoring another
DAC. It is expressed in LꢀBs.
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DAC. This includes both digital and
analog crosstalk. It is measured by loading one of the DACs
with a full-scale code change (all 0s to all 1s and vice versa) with
Digital Crosstalk
low and monitoring the output of another DAC. The
energy of the glitch is expressed in nV-sec.
LDAC
Digital crosstalk is a measure of the impulse injected into the
analog output of one DAC from the digital inputs of another
DAC, but is measured when the DAC output is not updated. It
is specified in nV-sec and measured with a full-scale code
change on the data bus.
Voltage Reference TC
Reference TC is a measure of the change in the reference output
voltage with a change in temperature. It is expressed in ppm/°C.
Rev. PrC | Page 20 of 32
AD5724R/AD5734R/AD5754R
Preliminary Technical Data
THEORY OF OPERATION
REFIN
The AD5724R/AD5734R/AD5754R are quad, 12-/14-/16-bit,
serial input, unipolar/bipolar, voltage output DACs. They
operate from single supply voltages of +4.5 V to +16.5 V or dual
supply voltages of 4.5 V to 16.5 V. In addition, the parts have
software-selectable output ranges of +5 V, +10 V, +10.8 V, 5 V,
10 V, and 10.8 V. Data is written to the
R
R
R
AD5724R/AD5734R/AD5754R in a 24-bit word format via a
3-wire serial interface. The devices also offer an ꢀDO pin to
facilitate daisy chaining or readback.
TO OUTPUT
AMPLIFIER
The AD5724R/AD5734R/AD5754R incorporate a power-on
reset circuit to ensure that the DAC registers power up loaded
with 0x0000. When powered on, the outputs are clamped to 0 V
via a low impedance path. The parts also feature on-chip
reference and reference buffers.
R
R
ARCHITECTURE
The DAC architecture consists of a string DAC followed by an
output amplifier. Figure 42 shows a block diagram of the DAC
architecture. The reference input is buffered before being
applied to the DAC.
Figure 43. Resistor String Structure
Output Amplifiers
REF
IN
The output amplifiers are capable of generating both unipolar
and bipolar output voltages. They are capable of driving a load
of 2 kΩ in parallel with 4000 pF to GND. The source and sink
capabilities of the output amplifiers can be seen in Figure 26.
The slew rate is 4.5 V/µs with a full-scale settling time of 10 µs.
REF (+)
RESISTOR
STRING
DAC REGISTER
V
X
OUT
CONFIGURABLE
OUTPUT
REF (–)
AMPLIFIER
Reference Buffers
GND
The AD5724R/AD5734R/AD5754R can operate with either an
external or internal reference. The reference input has an input
range of 2 V to 3 V with 2.5 V for specified performance. This
input voltage is then buffered before it is applied to the DAC cores.
OUTPUT
RANGE CONTROL
Figure 42. DAC Architecture Block Diagram
The resistor string structure is shown in Figure 43. It is a string
of resistors, each of value R. The code loaded to the DAC
register determines the node on the string where the voltage is
to be tapped off and fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
SERIAL INTERFACE
The AD5724R/AD5734R/AD5754R are controlled over a
versatile 3-wire serial interface that operates at clock rates up to
30 MHz. It is compatible with ꢀPI®, QꢀPI™, MICROWIRE™, and
DꢀP standards.
Input Shift Register
The input shift register is 24 bits wide. Data is loaded into the
device MꢀB first as a 24-bit word under the control of a serial
clock input, ꢀCLK. The input register consists of a read/write
bit, three register select bits, three DAC address bits, and 16 data
bits. The timing diagram for this operation is shown in Figure 2.
Rev. PrC | Page 21 of 32
AD5724R/AD5734R/AD5754R
Preliminary Technical Data
Standalone Operation
Daisy-Chain Operation
The serial interface works with both a continuous and noncon-
tinuous serial clock. A continuous ꢀCLK source can only be
For systems that contain several devices, the ꢀDO pin can be
used to daisy chain several devices together. Daisy-chain mode
can be useful in system diagnostics and in reducing the number
ꢀYNC
used if
In gated clock mode, a burst clock containing the exact number
ꢀYNC
is held low for the correct number of clock cycles.
ꢀYNC
of serial interface lines. The first falling edge of
write cycle. ꢀCLK is continuously applied to the input shift
ꢀYNC
starts the
of clock cycles must be used, and
must be taken high
register when
is low. If more than 24 clock pulses are
after the final clock to latch the data. The first falling edge of
ꢀYNC
applied, the data ripples out of the shift register and appears on
the ꢀDO line. This data is clocked out on the rising edge of
ꢀCLK and is valid on the falling edge. By connecting the ꢀDO
of the first device to the ꢀDIN input of the next device in the
chain, a multidevice interface is constructed. Each device in the
system requires 24 clock pulses. Therefore, the total number of
clock cycles must equal 24 × N, where N is the total number of
AD5724R/AD5734R/AD5754R devices in the chain. When the
starts the write cycle. Exactly 24 falling clock edges must
ꢀYNC
be applied to ꢀCLK before
ꢀYNC
is brought high again. If
th
is brought high before the 24 falling ꢀCLK edge, the
data written is invalid. If more than 24 falling ꢀCLK edges are
ꢀYNC
applied before
invalid. The input register addressed is updated on the rising
ꢀYNC ꢀYNC
is brought high, the input data is also
edge of
. For another serial transfer to take place,
must be brought low again. After the end of the serial data
transfer, data is automatically transferred from the input shift
register to the addressed register.
ꢀYNC
serial transfer to all devices is complete,
is taken high.
This latches the input data in each device in the daisy chain and
prevents any further data from being clocked into the input shift
register. The serial clock can be a continuous or a gated clock.
When the data has been transferred into the chosen register of
the addressed DAC, all DAC registers and outputs can be
updated by taking
ꢀYNC
A continuous ꢀCLK source can only be used if
is held
LDAC
ꢀYNC
low while
is high.
low for the correct number of clock cycles. In gated clock mode,
a burst clock containing the exact number of clock cycles must
AD5724R/
AD5734R/
AD5754R*
*
68HC11
ꢀYNC
be used, and
latch the data.
Readback Operation
must be taken high after the final clock to
SDIN
MOSI
SCK
PC7
PC6
SCLK
SYNC
LDAC
W
Readback mode is invoked by setting the R/ bit = 1 in the
serial input register write. (If the ꢀDO output is disabled via the
ꢀDO DIꢀABLE bit in the control register, it is automatically
enabled for the duration of the read operation after which it is
SDO
MISO
SDIN
W
disabled again) With R/ = 1, Bit A2 to Bit A0 in association
AD5724R/
AD5734R/
AD5754R*
with Bit REG2 to Bit REG0 select the register to be read. The
remaining data bits in the write sequence are don’t care bits.
During the next ꢀPI write, the data appearing on the ꢀDO
output contains the data from the previously addressed register.
For a read of a single register, the NOP command can be used
in clocking out the data from the selected register on ꢀDO. The
readback diagram in Figure 4 shows the readback sequence. For
example, to read back the data register of Channel A, the
following sequence should be implemented:
SCLK
SYNC
LDAC
SDO
SDIN
AD5724R/
AD5734R/
AD5754R*
1. Write 0x800000 to the AD5724R/AD5734R/AD5754R
input register. This configures the part for read mode with
the data register of Channel A selected. Note that all the
data bits, DB15 to DB0, are don’t care bits.
SCLK
SYNC
LDAC
SDO
2. Follow this with a second write, a NOP condition, 0x180000.
During this write, the data from the register is clocked out
on the ꢀDO line.
*
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 44. Daisy Chaining the AD5724R/AD5734R/AD5754R
Rev. PrC | Page 22 of 32
Preliminary Technical Data
AD5724R/AD5734R/AD5754R
LOAD DAC (LDAC)
CONFIGURING THE AD5724R/AD5734R/AD5754R
When the power supplies are applied to the AD5724R/
AD5734R/AD5754R, the power-on reset circuit ensures that all
registers default to 0. This places all channels and the internal
reference in power-down mode. The first communication to the
AD5724R/AD5734R/AD5754R should be to set the required
output range on all channels (default range is the 5 V unipolar
range) by writing to the range select register. The user should then
write to the power-control register to power-on the required
channels and the internal reference, if required. If an external
reference source is being used, the internal reference must
remain in power-down mode. To program an output value on a
channel, that channel must first be powered up; any writes to a
channel while it is in power down mode are ignored. The
AD5724R/AD5734R/AD5754R operate with a wide power supply
range. It is important that the power supply applied to the parts
provides adequate headroom to support the chosen output
ranges.
After data has been transferred into the input register of the
DACs, there are two ways to update the DAC registers and DAC
ꢀYNC
LDAC
outputs. Depending on the status of both
and
, one
of two update modes is selected, individual DAC updating or
simultaneous updating of all DACs.
OUTPUT
AMPLIFIER
V
12-/14-/16-BIT
DAC
REFIN
V
OUT
DAC
REGISTER
LDAC
INPUT
REGISTER
SCLK
SYNC
SDIN
INTERFACE
LOGIC
SDO
TRANSFER FUNCTION
Figure 45. Simplified Diagram of Input Loading Circuitry for One DAC
Table 9 to Table 17 show the relationships of the ideal input code
to output voltage for the AD5754R, AD5734R, and AD5724R,
respectively, for all output voltage ranges. For unipolar output
ranges, the data coding is straight binary. For bipolar output
Individual DAC Updating
LDAC
In this mode,
the input shift register. The addressed DAC output is updated
ꢀYNC
is held low while data is being clocked into
on the rising edge of
Simultaneous Updating of All DACs
LDAC
.
2sCOMP
ranges, the data coding is user-selectable via the BIN/
pin and can be either offset binary or twos complement.
In this mode,
into the input shift register. All DAC outputs are
LDAC
is held high while data is being clocked
For a unipolar output range, the output voltage expression is
given by
ꢀYNC
has
asynchronously updated by taking
been taken high. The update now occurs on the falling edge of
LDAC
low after
D
2
⎡
⎤
VOUT =VREFIN ×Gain
N
⎢
⎣
⎥
⎦
.
For a bipolar output range, the output voltage expression is given by
ASYNCHRONOUS CLEAR (CLR)
Gain ×VREFIN
D
2
⎡
⎤
VOUT =VREFIN ×Gain
−
CLR
is an active low clear that allows the outputs to be cleared
N
⎢
⎣
⎥
⎦
2
to either zero-scale code or mid-scale code. The clear code value
is user-selectable via the CLR ꢀELECT bit of the control register
where:
CLR
(see the Control Register section). It is necessary to maintain
low for a minimum amount of time to complete the operation
CLR
D is the decimal equivalent of the code loaded to the DAC.
N is the bit resolution of the DAC.
V
REFIN is the reference voltage applied at the REFIN pin.
(see Figure 2). When the
signal is returned high, the output
remains at the cleared value until a new value is programmed.
Gain is an internal gain the value of which depends on the
output range selected by the user as shown in Table 8.
CLR
The outputs cannot be updated with a new value while the
pin is low. A clear operation can also be performed via the clear
command in the control register.
Table 8.
Output Range (V)
Gain Value
+5
2
+10
+10.±
±5
4
4.32
4
±10
±10.±
±
±.64
Rev. PrC | Page 23 of 32
AD5724R/AD5734R/AD5754R
Preliminary Technical Data
Ideal Output Voltage to Input Code Relationship—AD5754R
Table 9. Bipolar Output, Offset Binary Coding
Digital Input
Analog Output
MSB
1111
1111
–
LSB
1111
1110
–
5 V Output Range
+2 REFIN(32767/3276±)
+2 REFIN(32766/3276±)
–
10 V Output Range
+4 REFIN(32767/3276±)
+4 REFIN(32766/3276±)
–
10.8 V Output Range
+4.32 REFIN(32767/3276±)
+4.32 REFIN(32766/3276±)
–
1111
1111
–
1111
1111
–
1000
1000
0111
–
0000
0000
1111
–
0000
0000
1111
–
0001
0000
1111
–
+2 REFIN(1/3276±)
0 V
−2 REFIN(1/3276±)
–
+4 REFIN(1/3276±)
0 V
−4 REFIN(1/3276±)
–
+4.32 REFIN(1/3276±)
0 V
−4.32 REFIN(32766/3276±)
–
0000
0000
0000
0000
0000
0000
0001
0000
−2 REFIN(32766/3276±)
−2 REFIN(32767/3276±
−4 REFIN(32766/3276±)
−4 REFIN(32767/3276±)
−4.32 REFIN(32766/3276±)
−4.32 REFIN(32767/3276±)
Table 10. Bipolar Output, Twos Complement Coding
Digital Input
Analog Output
10 V Output Range
+4 REFIN(32767/3276±)
+4 REFIN(32766/3276±)
–
MSB
0111
0111
–
LSB
1111
1110
–
5 V Output Range
+2 REFIN(32767/3276±)
+2 REFIN(32766/3276±)
–
10.8 V Output Range
+4.32 REFIN(32767/3276±)
+4.32 REFIN(32766/3276±)
–
1111
1111
–
1111
1111
–
0000
0000
1111
–
0000
0000
1111
–
0000
0000
1111
–
0001
0000
1111
–
+2 REFIN(1/3276±)
0 V
−2 REFIN(1/3276±)
–
+4 REFIN(1/3276±)
0 V
−4 REFIN(1/3276±)
–
+4.32 REFIN(1/3276±)
0 V
−4.32 REFIN(1/3276±)
–
1000
1000
0000
0000
0000
0000
0001
0000
−2 REFIN(32766/3276±)
−2 REFIN(32767/3276±)
−4 REFIN(32766/3276±)
−4 REFIN(32767/3276±)
−4.32 REFIN(32766/3276±)
−4.32 REFIN(32767/3276±)
Table 11. Unipolar Output, Straight Binary Coding
Digital Input
Analog Input
+10 V Output Range
+4 REFIN(65535/65536)
+4 REFIN(65534/65536)
–
MSB
1111
1111
–
LSB
1111
1110
–
+5 V Output Range
+2 REFIN(65535/65536)
+2 REFIN(65534/65536)
–
+10.8 V Output Range
+4.32 REFIN(65535/65536)
+4.32 REFIN(65534/65536)
–
1111
1111
–
1111
1111
–
1000
1000
0111
–
0000
0000
1111
–
0000
0000
1111
–
0001
0000
1111
–
+2 REFIN(32769/65536)
+2 REFIN(3276±/65536)
+2 REFIN(32767/65536)
–
+4 REFIN(32769/65536)
+4 REFIN(3276±/65536)
+4 REFIN(32767/65536)
–
+4.32 REFIN(32769/65536)
+4.32 REFIN(3276±/65536)
+4.32 REFIN(32767/65536)
–
0000
0000
0000
0000
0000
0000
0001
0000
+2 REFIN(1/65536)
0 V
+4 REFIN(1/65536)
0 V
+4.32 REFIN(1/65536)
0 V
Rev. PrC | Page 24 of 32
Preliminary Technical Data
AD5724R/AD5734R/AD5754R
Ideal Output Voltage to Input Code Relationship—AD5734R
Table 12. Bipolar Output, Offset Binary Coding
Digital Input
Analog Output
MSB
11
11
–
LSB
1111
1110
–
5 V Output Range
+2 REFIN(±191/±192)
+2 REFIN(±190/±192)
–
10 V Output Range
+4 REFIN(±191/±192)
+4 REFIN(±190/±192)
–
10.8 V Output Range
+4.32 REFIN(±191/±192)
+4.32 REFIN(±190/±192)
–
1111
1111
–
1111
1111
–
10
10
01
–
0000
0000
1111
–
0000
0000
1111
–
0001
0000
1111
–
+2 REFIN(1/±192)
0 V
−2 REFIN(1/±192)
–
+4 REFIN(1/±192)
0 V
−4 REFIN(1/±192)
–
+4 REFIN(1/±192)
0 V
−4.32 REFIN(1/±192)
–
00
00
0000
0000
0000
0000
0001
0000
−2 REFIN(±190/±192)
−2 REFIN(±191/±191)
−4 REFIN(±190/±192)
−4 REFIN(±191/±192)
−4.32 REFIN(±190/±192)
−4.32 REFIN(±191/±192)
Table 13. Bipolar Output, Twos Complement Coding
Digital Input
Analog Output
10 V Output Range
+4 REFIN(±191/±192)
+4 REFIN(±190/±192)
–
MSB
01
01
–
LSB
1111
1110
–
5 V Output Range
+2 REFIN(±191/±192)
+2 REFIN(±190/±192)
–
10.8 V Output Range
+4.32 REFIN(±191/±192)
+4.32 REFIN(±190/±192)
–
1111
1111
–
1111
1111
–
00
00
11
–
0000
0000
1111
–
0000
0000
1111
–
0001
0000
1111
–
+2 REFIN(1/±192)
0 V
−2 REFIN(1/±192)
–
+4 REFIN(1/±192)
0 V
−4 REFIN(1/±192)
–
+4 REFIN(1/±192)
0 V
−4.32 REFIN(1/±192)
–
10
10
0000
0000
0000
0000
0001
0000
−2 REFIN(±190/±192)
−2 REFIN(±191/±192)
−4 REFIN(±190/±192)
−4 REFIN(±191/±192)
−4.32 REFIN(±190/±192)
−4.32 REFIN(±191/±192)
Table 14. Unipolar Output, Straight Binary Coding
Digital Input
Analog Output
10 V Output Range
+4 REFIN(163±3/163±4)
+4 REFIN(163±2/163±4)
–
MSB
11
11
–
LSB
1111
1110
–
5 V Output Range
+2 REFIN(163±3/163±4)
+2 REFIN(163±2/163±4)
–
10.8 V Output Range
+4.32 REFIN(163±3/163±4)
+4.32 REFIN(163±2/163±4)
–
1111
1111
–
1111
1111
–
10
10
01
–
0000
0000
1111
–
0000
0000
1111
–
0001
0000
1111
–
+2 REFIN(±193/163±4)
+2 REFIN(±192/163±4)
+2 REFIN(±191/163±4)
–
+4 REFIN(±193/163±4)
+4 REFIN(±192/163±4)
+4 REFIN(±191/163±4)
–
+4.32 REFIN(±193/163±4)
+4.32 REFIN(±192/163±4)
+4.32 REFIN(±191/163±4)
–
00
00
0000
0000
0000
0000
0001
0000
+2 REFIN(1/163±4)
0 V
+4 REFIN(1/163±4)
0 V
+4.32 REFIN(1/163±4)
0 V
Rev. PrC | Page 25 of 32
AD5724R/AD5734R/AD5754R
Preliminary Technical Data
Ideal Output Voltage to Input Code Relationship—AD5724R
Table 15. Bipolar Output, Offset Binary Coding
Digital Input
Analog Output
10 V Output Range
MSB
1111
1111
–
LSB
1111
1110
–
5 V Output Range
+2 REFIN(2047/204±)
+2 REFIN(2046/204±)
–
10.8 V Output Range
+4.32 REFIN(2047/204±)
+4.32 REFIN(2046/204±)
–
1111
1111
–
+4 REFIN(2047/204±)
+4 REFIN(2046/204±)
–
1000
1000
0111
–
0000
0000
1111
–
0001
0000
1111
–
+2 REFIN(1/204±)
0 V
−2 REFIN(1/204±)
–
+4 REFIN(1/204±)
0 V
−4 REFIN(1/204±)
–
+4 REFIN(1/204±)
0 V
−4.32 REFIN(1/204±)
–
0000
0000
0000
0000
0001
0000
−2 REFIN(2046/204±)
−2 REFIN(2047/2047)
−4 REFIN(2046/204±)
−4 REFIN(2047/204±)
−4.32 REFIN(2046/204±)
−4.32 REFIN(2047/204±)
Table 16. Bipolar Output, Twos Complement Coding
Digital Output
Analog Output
MSB
0111
0111
–
LSB
1111
1110
–
5 V Output Range
+2 REFIN(2047/204±)
+2 REFIN(2046/204±)
–
10 V Output Range
+4 REFIN(2047/204±)
+4 REFIN(2046/204±)
–
10.8 V Output Range
+4.32 REFIN(2047/204±)
+4.32 REFIN(2046/204±)
–
1111
1111
–
0000
0000
1111
–
0000
0000
1111
–
0001
0000
1111
–
+2 REFIN(1/204±)
0 V
−2 REFIN(1/204±)
–
+4 REFIN(1/204±)
0 V
−4 REFIN(1/204±)
–
+4 REFIN(1/204±)
0 V
−4.32 REFIN(1/204±)
–
1000
1000
0000
0000
0001
0000
−2 REFIN(2046/204±)
−2 REFIN(2047/204±)
−4 REFIN(2046/204±)
−4 REFIN(2047/204±)
−4.32 REFIN(2046/204±)
−4.32 REFIN(2047/204±)
Table 17. Unipolar Output, Straight Binary Coding
Digital Input
Analog Output
MSB
1111
1111
–
LSB
1111
1110
–
+5 V Output Range
+2 REFIN(4095/4096)
+2 REFIN(4094/4096)
–
+10 V Output Range
+4 REFIN(4095/4096)
+4 REFIN(4094/4096)
–
+10.8 V Output Range
+4.32 REFIN(4095/4096)
+4.32 REFIN(4094/4096)
–
1111
1111
–
1000
1000
0111
–
0000
0000
1111
–
0001
0000
1111
–
+2 REFIN(2049/4096)
+2 REFIN(204±/4096)
+2 REFIN(2047/4096)
–
+4 REFIN(2049/4096)
+4 REFIN(204±/4096)
+4 REFIN(2047/4096)
–
+4.32 REFIN(2049/4096)
+4.32 REFIN(204±/4096)
+4.32 REFIN(2047/4096)
–
0000
0000
0000
0000
0001
0000
+2 REFIN(1/4096)
0 V
+4 REFIN(1/4096)
0 V
4.32 REFIN(1/4096)
0 V
Rev. PrC | Page 26 of 32
Preliminary Technical Data
AD5724R/AD5734R/AD5754R
INPUT REGISTER
The input register is 24 bits wide and consists of a read/write bit, a reserved bit, three register select bits, three DAC address bits, and 12-
/14-/16 data bits. The register data is clocked in MꢀB first on the ꢀDIN pin. Table 18 shows the register format while Table 19 describes
the function of each bit in the register. All registers are read/write registers.
Table 18. Input Register Format
MSB
LSB
DB23
DB22
DB21
DB20
DB19
DB18
DB17
DB16
DB15 to DB0
W
R/
0
REG2
REG1
REG0
A2
A1
A0
DATA
Table 19. Input Register Bit Functions
Bit Mnemonic
Description
R/W
Indicates a read from or a write to the addressed register.
REG2, REG1, REG0
Used in association with the address bits to determine if a write operation is to the data register, output range
select register, power control register or control register.
REG2
REG1
REG0
Function
0
0
0
0
0
0
1
1
0
1
0
1
Data Register
Output Range Select Register
Power Control Register
Control Register
A2, A1, A0
These bits are used to decode the DAC channels.
A2
A1
0
A0
0
Channel Address
DAC A
0
0
0
1
DAC B
0
1
0
DAC C
0
1
1
DAC D
1
0
0
All Four DACs
DB15 to DB0
Data bits.
DATA REGISTER
The data register is addressed by setting the three REG bits to 000. The DAC address bits select the DAC channel where the data transfer
is to take place (see Table 19). The data bits are in positions DB15 to DB0 for the AD5754R (see Table 20), DB15 to DB2 for the AD5734R
(see Table 21), and DB15 to DB4 for the AD5724R (see Table 22).
Table 20. Programming the AD5754R Data Register
MSB
REG2
0
LSB
DB15 to DB0
REG1
REG0
A2
A1
DAC Address
A0
0
0
16-Bit DAC Data
Table 21. Programming the AD5734R Data Register
MSB
LSB
REG2
REG1
REG0
A2
A1
A0
DB15 to DB2
DB1
DB0
0
0
0
DAC Address
14-Bit DAC Data
X
X
Table 22. Programming the AD5724R Data Register
MSB
LSB
REG2
REG1
REG0
A2
A1
DAC Address
A0
DB15 to DB4
DB3
DB2
DB1
DB0
0
0
0
12-Bit DAC Data
X
X
X
X
Rev. PrC | Page 27 of 32
AD5724R/AD5734R/AD5754R
Preliminary Technical Data
OUTPUT RANGE SELECT REGISTER
The output range select register is addressed by setting the three REG bits to 001. The DAC address bits select the DAC channel, while,
the range bits (R2, R1, R0) select the required output range (see Table 23 and Table 24).
Table 23. Programming the Required Output Range
MSB
REG2
0
LSB
REG1
REG0
A2
A1
A0
DB15 to DB3
DB2
DB1
DB0
0
1
DAC Address
Don’t Care
R2
R1
R0
Table 24. Output Range Options
R2
R1
R0
Output Range (V)
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
+5
+10
+10.±
±5
±10
±10.±
CONTROL REGISTER
The control register is addressed by setting the three REG bits to 011. The value written to the address and data bits determines the
control function selected. The control register options are shown in Table 25 and Table 26.
Table 25. Control Register Format
MSB
REG2
0
LSB
REG1
REG0
A2
A1
A0
DB15 to DB4
DB3
DB2
DB1
DB0
1
1
0
0
0
NOP, Data = Don’t Care
REG2
REG1
REG0
A2
A1
A0
DB15 to DB4
DB3
DB2
DB1
DB0
0
1
1
0
0
1
Don’t Care
TSD ENABLE
CLAMP ENABLE
CLR SELECT
SDO DISABLE
REG2
REG1
REG0
A2
A1
A0
DB15 to DB4
DB15 to DB4
DB3
DB3
DB2
DB1
DB0
DB0
0
1
1
1
0
0
CLEAR, Data = Don’t Care
REG2
REG1
REG0
A2
A1
A0
DB2
DB1
0
1
1
1
0
1
LOAD, Data = Don’t Care
Table 26. Control Register Functions
Option
Description
NOP
No operation instruction used in readback operations.
CLEAR
LOAD
SDO DISABLE
CLR SELECT
CLAMP ENABLE
Addressing this function sets the DAC registers to the clear code and updates the outputs.
Addressing this function updates the DAC registers and consequently, the DAC outputs.
Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).
See Table 27 for a description of the CLR SELECT operation.
Set by the user to enable the current limit clamp (default). The channel does not power down on detection of
overcurrent; the current is clamped at 20 mA.
Cleared by the user to disable the current-limit clamp. The channel powers down on detection of overcurrent.
TSD ENABLE
Set by the user to enable the thermal shutdown feature. Cleared by the user to disable the thermal shutdown
feature (default).
Table 27. CLR Select Options
CLR SELECT
Output CLR Value
Bipolar Output Range
Setting
Unipolar Output Range
0
1
0 V
Mid-Scale
0 V
Negative Full-Scale
Rev. PrC | Page 2± of 32
Preliminary Technical Data
AD5724R/AD5734R/AD5754R
POWER CONTROL REGISTER
The power control register is addressed by setting the three REG bits to 010. This register allows the user to control and determine the
power and thermal status of the AD5724R/AD5734R/AD5754R. The power control register options are shown in Table 28 and Table 29.
Table 28. Power Control Register Format
MSB
LSB
DB3 DB2 DB1 DB0
PUREF PUD PUC PUB PUA
REG2 REG1 REG0 A2 A1 A0 DB15 to DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
1
0
0
0
0
Don’t Care
OCD
OCC
OCB
OCA
0
TSD
Table 29. Power Control Register Functions
Option Description
PUA
PUB
PUC
PUD
PUREF
DAC A Power-Up. When set, this bit places DAC A in normal operating mode. When cleared, this bit places DAC A in power-down
mode (default). If the CLAMP ENABLE bit of the control register is cleared, DACA will power down automatically on detection of
an over-current, PUA will be cleared to reflect this.
DAC B Power-Up. When set, this bit places DAC B in normal operating mode. When cleared, this bit places DAC B in power-down
mode (default). If the CLAMP ENABLE bit of the control register is cleared, DACB will power down automatically on detection of
an over-current, PUB will be cleared to reflect this.
DAC C Power-Up. When set, this bit places DAC C in normal operating mode. When cleared, this bit places DAC C in power-down
mode (default). If the CLAMP ENABLE bit of the control register is cleared, DACC will power down automatically on detection of
an over-current, PUC will be cleared to reflect this.
DAC D Power-Up. When set, this bit places DAC D in normal operating mode. When cleared, this bit places DAC D in power-down
mode (default). If the CLAMP ENABLE bit of the control register is cleared, DACD will power down automatically on detection of
an over-current, PUD will be cleared to reflect this.
Reference Power-Up. When set, this bit places the internal reference in normal operating mode. When cleared, this bit places the
internal reference in power-down mode (default).
TSD
OCA
OCB
OCC
OCD
Thermal Shutdown Alert. Read-Only Bit. In the event of an over-temperature situation, this bit is set.
DAC A Overcurrent Alert. Read-Only Bit. In the event of an overcurrent situation on DAC A, this bit is set.
DAC B Overcurrent Alert. Read-Only Bit. In the event of an overcurrent situation on DAC B, this bit is set.
DAC C Overcurrent Alert. Read-Only Bit. In the event of an overcurrent situation on DAC C, this bit is set.
DAC D Overcurrent Alert. Read-Only Bit. In the event of an overcurrent situation on DAC D, this bit is set.
Rev. PrC | Page 29 of 32
AD5724R/AD5734R/AD5754R
Preliminary Technical Data
FEATURES
ANALOG OUTPUT CONTROL
Constant Current Clamp (CLAMP ENABLE = 1)
If a short circuit occurs, in this configuration the current is
clamped at 20 mA. This event is signaled to the user by the
setting of the appropriate overcurrent (OCX) bit in the power
control register. Upon removal of the short-circuit fault, the
OCX bit is cleared.
In many industrial process control applications, it is vital that
the output voltage be controlled during power-up. When the
supply voltages change during power-up, the VOUT pins are
clamped to 0 V via a low impedance path (approxiamately
4kΩ). To prevent the output amplifiers from being shorted to
0 V during this time, Transmission Gate G1 is also opened (see
Figure 46). These conditions are maintained until the power
supplies have stabilized and a valid word is written to a DAC
register. At this time, G2 opens and G1 closes.
Automatic Channel Power-Down (CLAMP ENABLE = 0)
If a short circuit occurs, in this configuration the shorted
channel powers down and its output is clamped to ground via a
resistance of approx. 4kΩ, also at this time the output of the
amplifier is disconnected from the output pin. The short-circuit
event is signaled to the user via the overcurrent (OCX) bits,
while the power-up (PUX ) bits indicate which channels have
powered down. After the fault is rectified, the channels can be
powered up again by setting the PUX bits.
VOLTAGE
MONITOR
AND
CONTROL
G1
V
A
OUT
G2
THERMAL SHUTDOWN
The AD5724R/AD5734R/AD5754R incorporate a thermal
shutdown feature that automatically shuts down the device if
the core temperature exceeds approximately 150°C. The thermal
shutdown feature is disabled by default and can be enabled via
the TꢀD ENABLE bit of the control register. In the event of a
thermal shutdown, the TꢀD bit of the power control register is set.
Figure 46. Analog Output Control Circuitry
POWER-DOWN MODE
Each DAC channel of the AD5724R/AD5734R/AD5754R can
be individually powered-down. By default all channels are in
power-down mode. The power status is controlled by the
POWER CONTROL register, see Table 28 and Table 29 for
details. When a channel is in power-down mode its output pin
is clamped to ground through a resistance of approx. 4kΩ and
the output of the amplifier is disconnected from the output pin.
INTERNAL REFERENCE
The on-chip voltage reference is powered down by default. If an
external voltage reference source is to be used, the internal
reference must remain powered down at all times. If the internal
reference is to be used as the reference source, it must be
powered up via the PUREF bit of the power control register. The
internal reference voltage is accessible at the REFIN/REFOUT pin
for use as a reference source for other devices within the system.
If the internal reference is to be used external to the
OVERCURRENT PROTECTION
Each DAC channel of the AD5724R/AD5734R/AD5754R
incorporates individual overcurrent protection. The user has
two options for the configuration of the overcurrent protection,
constant current clamp, or automatic channel power-down. The
configuration of the overcurrent protection is selected via the
CLAMP ENABLE bit in the control register.
AD5724R/AD5734R/AD5754R, it must first be buffered.
Rev. PrC | Page 30 of 32
Preliminary Technical Data
AD5724R/AD5734R/AD5754R
APPLICATIONS INFORMATION
+5V / 5V OPERATION
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. The
iCoupler® family of products from Analog Devices provides
voltage isolation in excess of 2.5 kV. The serial loading structure
of the AD5724R/AD5734R/AD5754R make them ideal for
isolated interfaces because the number of interface lines is kept
to a minimum. Figure 47 shows a 4-channel isolated interface to
the AD5724R/AD5734R/AD5754R using an ADuM1400. For
further information, visit http://www.analog.com/icouplers.
When operating from a single +5V supply or a dual 5V supply
an output range of +5V or 5V is not achievable as sufficient
headroom for the output amplifier is not available. In this
situation a reduced reference voltage can be used, for instance a
2V reference will produce an output range of +4V or 4V, the
1V of headroom is more than enough for full operation. A
standard value voltage reference of 2.048V can be used to
produce output ranges of +4.096V and 4.096V. Refer to the
Typical Performance Characteristics plots for performance data
at a range of voltage reference values.
LAYOUT GUIDELINES
MICROCONTROLLER
ADuM1400*
V
V
V
V
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5724R/AD5734R/AD5754R are mounted should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. If the
V
V
V
V
OA
OB
OC
OD
IA
IB
IC
ID
SERIAL CLOCK OUT
ENCODE
DECODE
DECODE
DECODE
DECODE
TO SCLK
TO SDIN
TO SYNC
TO LDAC
SERIAL DATA OUT
SYNC OUT
ENCODE
ENCODE
ENCODE
CONTROL OUT
*ADDITIONAL PINS OMITTED FOR CLARITY.
AD5724R/AD5734R/AD5754R are in a system where multiple
devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
Figure 47. Isolated Interface
MICROPROCESSOR INTERFACING
The AD5724R/AD5734R/AD5754R should have an ample
supply bypassing of a 10 µF capacitor in parallel with 0.1 µF
capacitor on each supply located as close to the package as
possible, ideally right up against the device. The 10 µF
capacitors are the tantalum bead type. The 0.1 µF capacitor
should have low effective series resistance (EꢀR) and low
effective series inductance (EꢀI) such as the common ceramic
types, which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
Microprocessor interfacing to the AD5724R/AD5734R/AD5754R
is via a serial bus that uses standard protocol compatible with
microcontrollers and DꢀP processors. The communications
channel is a 3-wire (minimum) interface consisting of a clock
signal, a data signal, and a synchronization signal. The
AD5724R/AD5734R/AD5754R require a 24-bit data-word
with data valid on the falling edge of ꢀCLK.
For all interfaces, the DAC output update can be initiated
automatically when all the data is clocked in, or it can be
LDAC
performed under the control of
. The contents of the
The power supply lines of the AD5724R/AD5734R/AD5754R
should use as large a trace as possible to provide low impedance
paths and reduce the effects of glitches on the power supply
line. Fast switching signals such as clocks should be shielded
with digital ground to avoid radiating noise to other parts of the
board and should never be run near the reference inputs. A
ground line routed between the ꢀDIN and ꢀCLK lines helps
reduce crosstalk between them (this is not required on a
multilayer board that has a separate ground plane, but
separating the lines does help). It is essential to minimize noise
on the REFIN line because it couples through to the DAC
output.
registers can be read using the readback function.
AD5724R/AD5734R/AD5754R to Blackfin® DSP interface
Figure 48 shows how the AD5724R/AD5734R/AD5754R can be
interfaced to Analog Devices Blackfin DꢀP. The Blackfin has an
integrated ꢀPI port that can be connected directly to the ꢀPI
pins of the AD5724R/AD5734R/AD5754R and the programmable
I/O pins that can be used to set the state of a digital input such
LDAC
as the
pin.
SPISELx
SYNC
SCK
SCLK
SDIN
MOSI
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feed through the board. A
microstrip technique is by far the best, but not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to ground plane, while signal
traces are placed on the solder side.
AD5724R/
AD5734R/
AD5754R
ADSP-BF531
PF10
LDAC
Figure 48. AD5724R/AD5734R/AD5754R to Blackfin Interface
Rev. PrC | Page 31 of 32
AD5724R/AD5734R/AD5754R
OUTLINE DIMENSIONS
Preliminary Technical Data
5.02
5.00
4.95
7.90
7.80
7.70
24
13
12
4.50
4.40
4.30
3.25
3.20
3.15
EXPOSED
PAD
(Pins Up)
6.40 BSC
1
BOTTOM VIEW
TOP VIEW
1.20 MAX
1.05
1.00
0.80
8°
0°
0.20
0.09
0.15
0.05
0.30
0.19
0.65
BSC
0.75
0.60
0.45
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-ADT
Figure 49. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP]
(RE-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Resolution
Temperature Range
−40°C to ±5°C
−40°C to ±5°C
−40°C to ±5°C
−40°C to ±5°C
−40°C to ±5°C
−40°C to ±5°C
INL
Package Description
24-Lead TSSOP_EP
24-Lead TSSOP_EP
24-Lead TSSOP_EP
24-Lead TSSOP_EP
24-Lead TSSOP_EP
24-Lead TSSOP_EP
Package Option
RE-24
RE-24
AD5724RBREZ1
12
12
14
14
16
16
±1 LSB
±1 LSB
±4 LSB
±4 LSB
±16 LSB
±16 LSB
AD5724RBREZ-REEL71
AD5734RBREZ1
AD5734RBREZ-REEL71
AD5754RBREZ1
AD5754RBREZ-REEL71
RE-24
RE-24
RE-24
RE-24
1 Z = Pb-free part.
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PR06465-0-11/07(PrC)
Rev. PrC | Page 32 of 32
相关型号：
AD5725BRSZ-1REEL
PARALLEL, WORD INPUT LOADING, 10us SETTLING TIME, 12-BIT DAC, PDSO28, ROHS COMPLIANT, MO-150AH, SSOP-28
ADI
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