AD5744BSU_技术文档

Complete, Quad, 14/16-Bit, High Accuracy,

Serial Input, Bipolar Voltage Output DAC

i

CMOS^TM

Preliminary Technical Data

AD5744/AD5764

FEATURES

GENERAꢀ DESCRIPTION

Complete quad 14/16-bit D/A converter

Programmable output range: 10 V, 10.25 V, or 10.5 V

1 ꢀSB max INꢀ error, 1 ꢀSB max DNꢀ error

ꢀow noise : 60 nV/√Hz

The AD5744/64 is a quad, 14/16-bit serial input, voltage output

digital-to analog converter that operates from supply voltages of

1ꢀ ꢁ up to 15 ꢁ. Nominal full-scale output range is 1ꢂ ꢁ,

provided are integrated output amplifiers, reference buffers,

internal reference, and proprietary power-up/power-down

control circuitry. It also features a digital I/O port that may be

programmed via the serial interface, and an analog temperature

sensor. The part incorporates digital offset and gain adjust

registers per channel.

Settling time: 10µs max

Integrated reference buffers

Internal reference, 10 ppm/°C

On-chip temp sensor, 5°C accuracy

Output control during power-up/brownout

Programmable short-circuit protection

Simultaneous updating via ꢀDAC

The AD5744/64 is a high performance converter that offers

guaranteed monotonicity, integral nonlinearity (INL) of 1 LSB,

low noise and 1ꢂ µs settling time and includes an on-chip 5 ꢁ

reference with a reference tempco of 1ꢂ ppm/°C max. During

power-up (when the supply voltages are changing), ꢁout is

clamped to ꢂꢁ via a low impedance path.

CꢀR

Asynchronous

to zero code

Digital offset and gain adjust

ꢀogic output control pins

DSP/microcontroller compatible serial interface

Temperature range:−40°C to +85°C

iCMOS™ Process Technology

The AD5744/64 uses a serial interface that operates at clock rates

of up to 3ꢂ MHz and is compatible with DSP and microcontroller

interface standards. Double buffering allows the simultaneous

updating of all DACs. The input coding is programmable to either

twos complement or Offset binary formats. The asynchronous

clear function clears all DAC registers to either bipolar zero or

zero-scale depending on the coding used. The AD5744/64 is ideal

for both closed-loop servo control and open-loop control

applications. The AD5744/64 is available in a 3ꢀ-lead TQFP

package, and offers guaranteed specifications over the −4ꢂ°C to

+85°C industrial temperature range. See functional block

diagram, Figure 1.

APPꢀICATIONS

Industrial automation

Open/Closed-loop servo control

Process control

Data acquisition systems

Automatic Test Equipment

Automotive test and measurement

High accuracy instrumentation

iCMOS™ Process Technology

For analog systems designers within industrial/instrumentation equipment OEMs who need high performance ICs at higher-voltage levels, iCMOS is a

technology platform that enables the development of analog ICs capable of 30V and operating at +/-15V supplies while allowing dramatic reductions in

power consumption and package size, and increased AC and DC performance.

Rev. PrA

15-Nov-04

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

Preliminary Technical Data

AD5744/AD5764

TABLE OF CONTENTS

Functional Block Diagram .............................................................. 3

Coarse gain register.................................................................... ꢀꢂ

Fine gain register ........................................................................ ꢀ1

offset register............................................................................... ꢀ1

AD5744/64 Features....................................................................... ꢀꢀ

Analog Output Control ............................................................. ꢀꢀ

Digital Offset and Gain Control............................................... ꢀꢀ

Programmable Short-Circuit protection................................. ꢀꢀ

Digital I/O Port........................................................................... ꢀꢀ

Temperature Sensor ................................................................... ꢀꢀ

Local ground offset adjust......................................................... ꢀꢀ

applications information ............................................................... ꢀ3

typical operating circuit............................................................. ꢀ3

layout guidelines......................................................................... ꢀ4

Isolated interface ........................................................................ ꢀ4

microprocessor interfacing ....................................................... ꢀ4

Evaluation board ........................................................................ ꢀ6

Outline Dimensions....................................................................... ꢀ7

Ordering Guide .......................................................................... ꢀ7

Specifications..................................................................................... 4

AC Performance Characteristics................................................ 6

Timing Characteristics ................................................................ 7

Absolute Maximum Ratings.......................................................... 1ꢂ

ESD Caution................................................................................ 1ꢂ

Pin Configuration and Function Descriptions........................... 11

Terminology .................................................................................... 13

typical performance characteristics ............................................. 15

General Description....................................................................... 16

dac architecture........................................................................... 16

Reference Buffers........................................................................ 16

Serial interface ............................................................................ 16

LDAC

Simultaneous Updating ꢁia

transfer function......................................................................... 18

CLR

.......................................... 17

Asynchronous Clear (

)....................................................... 18

Function Register ....................................................................... 19

DAta register ............................................................................... ꢀꢂ

REVISION HISTORY

Revision PrA 15-Nov-ꢂ4: Preliminary ꢁersion

Rev. PrA 15-Nov-04| Page 2 of 27

Preliminary Technical Data

AD5744/AD5764

FUNCTIONAL BLOCK DIAGRAM

REFGND

PGND AV

AV

SS

VREF AB

RSTOUT

RSTIN

REFOUT

DD

SS

DD

VOLTAGE

MONITOR

AND

DV

CC

+5V

REFERENCE

BUFFERS

DGND

CONTROL

ISCC

14/16

G1

14/16

INPUT

REG A

DAC

REG A

DAC A

DAC B

DAC C

DAC D

SDIN

SCLK

SYNC

SDO

VOUTA

AGNDA

INPUT SHIFT

REGISTER

AND

CONTROL

LOGIC

G2

GAIN REG A

OFFSET REG A

14/16

INPUT

REG B

DAC

REG B

VOUTB

AGNDB

G2

GAIN REG B

OFFSET REG B

D0

D1

INPUT

REG C

DAC

REG C

VOUTC

AGNDC

GAIN REG C

OFFSET REG C

BIN/2SCOMP

INPUT

REG D

DAC

REG D

VOUTD

AGNDD

GAIN REG D

CLR

OFFSET REG D

REFERENCE

BUFFERS

TEMP

SENSOR

LDAC

VREF CD

TEMP

Figure 1. Functional Block Diagram

Rev. PrA 15-Nov-04| Page 3 of 27

Preliminary Technical Data

AD5744/AD5764

SPECIFICATIONS

Aꢁ_DD= +11.4 ꢁ to +16.5 ꢁ, Aꢁ_SS= −11.4 ꢁ to −16.5 ꢁ, AGND = DGND = REFGND = PGND=ꢂ ꢁ; REFAB = REFCD= 5 ꢁ Ext;

Dꢁ_CC= ꢀ.7 ꢁ to 5.5 ꢁ, R_LOAD= 1ꢂ kΩ, C_L= ꢀꢂꢂ pF. All specifications T_MINto T_MAX, unless otherwise noted.

Table 1.

Parameter

ACCURACY

Resolution

A Grade¹

B Grade¹

C Grade¹

Unit

Test Conditions/Comments

16

14

4

1

16

14

2

1

16

14

1

Bits

AD5764

AD5744

Relative Accuracy (INL)

Differential Nonlinearity

Bipolar Zero Error

LSB max

mV max

Guaranteed monotonic

At 25°C. Error at other

temperatures

obtained using bipolar zero TC.

Bipolar Zero TC

Zero Code Error

2

1

2

1

2

1

ppm FSR/°C max

mV max

At 25°C. Error at other

temperatures

obtained using zero code TC.

Zero Code TC

Gain Error

2

0.02

2

0.02

2

0.02

ppm FSR/°C max

% FSR max

At 25°C. Error at other

temperatures

obtained using gain TC.

Gain TC

DC Crosstalk²

2

0.5

2

0.5

2

0.5

ppm FSR/°C max

LSB max

REFERENCE INPUT/OUTPUT

Reference Input²

Reference Input Voltage

DC Input Impedance

Input Current

Reference Range

Reference Output

Output Voltage

5

1

10

1/5

5

1

10

1/5

5

1

10

1/5

V nom

1% for specified performance

Typically 100 MΩ

Typically 30 nA

MΩ min

µA max

V min/max

4.999/5.001 4.999/5.001 4.999/5.001 V min/max

At 25°C

Reference TC

Output Noise(0.1 Hz to 10 Hz) TBD

Noise Spectral Density

10

TBD

10

TBD

ppm/°C max

µV p-p typ

TBD

Hz

nV/√ typ

OUTPUT CHARACTERISTICS²

Output Voltage Range³

10

13

2

10

13

2

10

13

2

V min/max

ppm FSR/°C max

AV_DD/AV_SS= 11.4 V

AV_DD/AV_SS= 16.5 V

Output Voltage TC

Output Voltage Drift V_STime

TBD

ppm FSR/1000 Hours

typ

Short Circuit Current

Load Current

10

1

10

1

10

1

mA max

RI_SCC= 6 KΩ , See Figure ???

For specified performance

Capacitive Load Stability

R_L= ∞

R_L= 10 kΩ

DC Output Impedance

DIGITAL INPUTS²

200

TBD

0.3

200

TBD

0.3

200

TBD

0.3

pF max

Ω max

DV_CC= 2.7 V to 5.5 V, JEDEC

compliant

V_IH, Input High Voltage

2

V min

¹Temperature range −40°C to +85°C; typical at +25°C. Device functionality is guaranteed to +105°C with degraded performance.

²Guaranteed by characterization. Not production tested.

³Output amplifier headroom requirement is 1.4 V min.

Rev. PrA 15-Nov-04| Page 4 of 27

Preliminary Technical Data

AD5744/AD5764

Parameter

A Grade¹

0.8

10

B Grade¹

C Grade¹

Unit

Test Conditions/Comments

V_IL, Input Low Voltage

Input Current

Pin Capacitance

0.8

10

0.8

10

V max

µA max

pF max

Total for All Pins. T_A= T_MINto T_MAX

.

10

DIGITAL OUTPUTS (D0,D1, SDO) ²

Output Low Voltage

Output High Voltage

0.4

DV_CC– 1

0.4

DV_CC– 1

0.4

DV_CC– 1

V max

V min

DV_CC= 5 V 10%, sinking 200 µA

DV_CC= 5 V 10%, Sourcing 200

µA

Output Low Voltage

Output High Voltage

0.4

V max

V min

DV_CC= 2.7 V to 3.6 V, Sinking 200

µA

DV_CC= 2.7 V to 3.6 V, Sourcing

200 µA

DV_CC– 0.5

High Impedance Leakage

Current

High Impedance Output

Capacitance

1

5

1

5

1

5

µA max

pF typ

SDO only

TEMP SENSOR

Accuracy

1

5

1.5

5

0/3.0

200

10

1

5

1.5

5

0/3.0

200

10

1

5

1.5

5

0/3.0

200

10

°C typ

°C max

V typ

mV/°C typ

V min/max

µA max

ms typ

At 25°C

−40°C < T <+85°C

Output Voltage @ 25°C

Output Voltage Scale Factor

Output Voltage Range

Output Load Current

Power On Time

POWER REQUIREMENTS

AV_DD/AV_SS

Current source only.

To within 5°C

11.4/16.5

2.7/5.5

11.4/16.5

2.7/5.5

11.4/16.5

2.7/5.5

V min/max

DV_CC

Power Supply Sensitivity⁴

∆V_OUT/∆ΑV_DD

AI_DD

AI_SS

DI_CC

−85

3.75

2.75

1

−85

3.75

2.75

1

−85

3.75

2.75

1

dB typ

mA/Channel max

mA max

Outputs unloaded

V_IH= DV_CC, V_IL= DGND. TBD mA

typ

Power Dissipation

244

mW typ

12 V operation output

unloaded

⁴Guaranteed by characterization. Not production tested.

Rev. PrA 15-Nov-04| Page 5 of 27

Preliminary Technical Data

AD5744/AD5764

AC PERFORMANCE CHARACTERISTICS

Aꢁ_DD= +11.4 ꢁ to +16.5 ꢁ, Aꢁ_SS= −11.4 ꢁ to −16.5 ꢁ, AGND = DGND = REFGND = PGND=ꢂ ꢁ; REFAB = REFCD= 5 ꢁ Ext;

Dꢁ_CC= ꢀ.7 ꢁ to 5.5 ꢁ, R_LOAD= 1ꢂ kΩ, C_L= ꢀꢂꢂ pF. All specifications T_MINto T_MAX, unless otherwise noted. Guaranteed by design and

characterization, not production tested.

Table 2.

Parameter

A Grade B Grade C Grade Unit

Test Conditions/Comments

Full-scale step

DYNAMIC PERFORMANCE

Output Voltage Settling Time

8

µs typ

10

1

5

10

1

5

100

5

10

1

5

100

5

µs max

V/µs typ

nV-s typ

mV max

dB typ

nV-s typ

512 LSB step settling @ 16 Bits

Slew Rate

Digital-to-Analog Glitch Energy

Glitch Impulse Peak Amplitude

Channel-to-Channel Isolation

DAC-to-DAC Crosstalk

Digital Crosstalk

100

5

Digital Feedthrough

1

Effect of input bus activity on DAC

output under test

Output Noise (0.1 Hz to 10 Hz)

Output Noise (0.1 kHz to 100 kHz)⁵

1/f Corner Frequency

0.1

45

1

0.1

45

1

LSB p-p typ

µV rms max

kHz typ

Output Noise Spectral Density

60

80

60

80

Hz

nV/√ typ

Hz

nV/√ typ

Measured at 10 kHz

Complete System Output Noise Spectral

Density⁶

⁵Guaranteed by design and characterization. Not production tested.

⁶Includes noise contributions from integrated reference buffers, 14/16-bit DAC and output amplifier.

Rev. PrA 15-Nov-04| Page 6 of 27

Preliminary Technical Data

AD5744/AD5764

TIMING CHARACTERISTICS

Aꢁ_DD= +11.4 ꢁ to +16.5 ꢁ, Aꢁ_SS= −11.4 ꢁ to −16.5 ꢁ, AGND = DGND = REFGND = PGND = ꢂ ꢁ; REFAB = REFCD= 5 ꢁ Ext;

Dꢁ_CC= ꢀ.7 ꢁ to 5.5 ꢁ, R_LOAD= 1ꢂ kΩ, C_L= ꢀꢂꢂ pF. All specifications T_MINto T_MAX, unless otherwise noted.

Table 3.

Parameter^7,8,9

ꢀimit at T_MIN, T_MAX

Unit

Description

t₁

t₂

t₃

t₄

33

13

40

5

ns min

µs max

ns min

µs max

ns max

ns min

SCLK cycle time

SCLK high time

SCLK low time

SYNC

falling edge to SCLK falling edge setup time

10

th

t₅

SYNC

rising edge

24 SCLK falling edge to

t₆

SYNC

high time

Minimum

t₇

t₈

t₉

Data setup time

Data hold time

0

20

5

SYNC

LDAC

falling edge

rising edge to

pulse width low

falling edge to DAC output response time

t₁₀

t₁₁

t₁₂

t₁₃

t₁₄

10

20

12

20

8

DAC output settling time

CLR

pulse width low

pulse activation time

11,12

t₁₅

t₁₆

SCLK rising edge to SDO valid

12

SCLK

SYNC

falling edge to SYNC rising edge

LDAC

12

t₁₇

20

rising edge to

falling edge

⁷Guaranteed by design and characterization. Not production tested.

⁸All input signals are specified with t_r= t_f= 5 ns (10% to 90% of DV_CC) and timed from a voltage level of 1.2 V.

⁹See Figure 2, Figure 3, and Figure 4.

¹⁰Stand-alone mode only.

¹¹Measured with the load circuit of Figure 5.

¹²Daisy-chain mode only.

Rev. PrA 15-Nov-04| Page 7 of 27

Preliminary Technical Data

AD5744/AD5764

t₁

SCLK

1

2

24

t₆

t₃

t₂

t₄

t₅

SYNC

t₈

t₇

SDIN

DB23

DB0

t₁₀

t₉

LDAC

t₁₂

t₁₁

V

OUT

LDAC = 0

t₁₂

t₁₁

V

OUT

t₁₃

CLR

t₁₄

V

OUT

Figure ꢀ. Serial Interface Timing Diagram

t₁

SCLK

24

48

t₃

t₂

t₅

t₆

t₁₆

t₄

SYNC

t₈

t₇

DB23

DB0

DB23

DB0

SDIN

INPUT WORD FOR DAC N

INPUT WORD FOR DAC N+1

INPUT WORD FOR DAC N

t₁₅

DB23

DB0

SDO

t₁₇

UNDEFINED

t₁₀

LDAC

Figure 3. Daisy Chain Timing Diagram

Rev. PrA 15-Nov-04| Page 8 of 27

Preliminary Technical Data

AD5744/AD5764

SCLK

24

48

SYNC

DB23

DB0

DB23

DB0

SDIN

SDO

INPUT WORD SPECIFIES

REGISTER TO BE READ

NOP CONDITION

DB23

UNDEFINED

SELECTED REGISTER DATA

CLOCKED OUT

Figure 4. Readback Timing Diagram

200µA

I

OL

V

(MIN) OR

(MAX)

TO OUTPUT

OH

OL

C

L

50pF

200µA

I

OH

Figure 5. Load Circuit for SDO Timing Diagram

Rev. PrA 15-Nov-04| Page 9 of 27

AD5744/AD5764

Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

T_A= ꢀ5°C unless otherwise noted.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational sections

of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Transient currents of up to 1ꢂꢂ mA will not cause SCR latch-up.

Table 4.

Parameter

Rating

AV_DDto AGND, DGND

AV_SSto AGND, DGND

DV_CCto DGND

Digital Inputs to DGND

Digital Outputs to DGND

REF IN to AGND, PWRGND

REF OUT to AGND

−0.3 V to +17 V

+0.3 V to −17 V

−0.3 V to +7 V

−0.3 V to DV_CC+ 0.3 V

−0.3 V to +17 V

AV_SSto AV_DD

V_OUTA,B,C,D to AGND

AGND to DGND

AV_SSto AV_DD

−0.3 V to +0.3 V

Operating Temperature Range

Industrial

−40°C to +85°C

−65°C to +150°C

150°C

Storage Temperature Range

Junction Temperature (T_Jmax)

32-Lead TQFP Package,

θ_JAThermal Impedance

Reflow Soldering

TBD°C/W

Peak Temperature

220°C

Time at Peak Temperature

10 sec to 40 sec

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. PrA 15-Nov-04| Page 10 of 27

Preliminary Technical Data

AD5744/AD5764

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

32

25

1

24

SYNC

SCLK

SDIN

SDO

CLR

LDAC

D0

AGNDA

VOUTA

VOUTB

AGNDB

AGNDC

VOUTC

VOUTD

AGNDD

PIN 1

INDICATOR

AD5744/64

TOP VIEW

(Not to Scale)

D1

8

17

9

16

Figure 6. 3ꢀ-Lead TQFP Pin Configuration Diagram

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Function

1

SYNC

Active Low Input. This is the frame synchronization signal for the serial interface.

SYNC

While

is low, data is transferred in on the falling edge of SCLK.

2

SCLK¹³

Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK.

This operates at clock speeds up to 30 MHz.

3

4

SDIN¹³

SDO

Serial Data Input. Data must be valid on the falling edge of SCLK.

Serial Data Output. Used to clock data from the serial register in daisy-chain or

readback mode.

5

6

CLR¹³

LDAC

Active Low Input. Asserting this pin sets the DAC registers to 0x0000.

Load DAC. Logic input. This is used to update the DAC registers and consequently

the analog output. When tied permanently low, the addressed DAC register is

th

LDAC

updated on the 24 clock of the serial register write. If

is held high during the

write cycle, the DAC input register is updated but the output is held off until the

LDAC

falling edge of

. In this mode, all analog outputs can be updated

LDAC

simultaneously on the falling edge of

.

7, 8

D0, D1

D0 and D1 form a digital I/O port. The user can configure these pins as inputs or

outputs that are configurable and readable over the serial interface. When

configured as inputs, these pins have weak internal pull-ups to DV_CC.

9

RSTOUT

RSTIN

Reset Logic Output. This is the output from the on-chip voltage monitor used in the

reset circuit. If desired, it may be used to control other system components.

Reset Logic Input. This input allows external access to the internal reset logic.

Applying a Logic 0 to this input resets the DAC output to 0 V. In normal operation,

10

RSTIN

should be tied to Logic 1.

11

12

DGND

DV_CC

Digital GND Pin.

Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V. When programmed as

outputs, D0 and D1 are referenced to DV_CC.

13, 31

14

15, 30

AV_DD

PGND

AV_SS

Positive Analog Supply Pins. Voltage ranges from 11.4 V to 16.5 V.

Ground Reference Point for Analog Circuitry.

Negative Analog Supply Pins. Voltage ranges from –11.4 V to –16.5 V.

¹³Internal pull-up device on this logic input. Therefore, it can be left floating and will default to a logic high condition.

Rev. PrA 15-Nov-04| Page 11 of 27

Preliminary Technical Data

Pin No.

Mnemonic

Function

16

ISCC

This pin us used in association with an external resistor to AGND to program the

short-circuit current of the output amplifiers.

17

18

AGNDD

VOUTD

Ground Reference Pin for DAC D Output amplifier.

Analog Output Voltage of DAC D. Buffered output with a nominal full-scale output

range of 10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF

load.

19

VOUTC

Analog Output Voltage of DAC C. Buffered output with a nominal full-scale output

range of 10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF

load.

20

21

22

AGNDC

AGNDB

VOUTB

Ground Reference Pin for DAC C Output Amplifier.

Ground Reference pin for DAC B Output Amplifier.

Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output

range of 10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF

load.

23

VOUTA

Analog Output Voltage of DAC A. Buffered output with a nominal full-scale output

range of 10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF

load.

24

25

AGNDA

REFAB

Ground Reference Pin for DAC A Output Amplifier.

External Reference Voltage Input for Channels A and B. Reference input range is 1 V

to 5 V; programs the full-scale output voltage. REFIN = 5 V for specified performance.

26

27

REFCD

External Reference Voltage Input for Channels C and D. Reference input range is 1 V

to 5 V; programs the full-scale output voltage. REFIN = 5 V for specified performance.

Reference Output. This is the buffered reference output from the internal voltage

reference. The internal reference is 5 V 1 mV, with a reference tempco of 10

ppm/°C.

REFOUT

28

29

REFGND

TEMP

Reference Ground Return for the Reference Generator and Buffers.

This pin provides an output voltage proportional to temperature. The output

voltage is 1.5 V typical at 25°C; variation with temperature is 5 mV/°C.

32

2sCOMP

BIN/

Determines the DAC Coding. When set to a logic high, input coding is offset binary.

When set to a logic low, input coding is twos complement. (See Table 6 and Table 7)

Rev. PrA 15-Nov-04| Page 12 of 27

Preliminary Technical Data

TERMINOLOGY

Relative Accuracy

9ꢂ% of the output signal and is given in ꢁ/µs.

For the DAC, relative accuracy or Integral Nonlinearity (INL) is

a measure of the maximum deviation, in LSBs, from a straight

line passing through the endpoints of the DAC transfer

function. A typical INL vs. code plot can be seen in Figure ?.

Gain Error

This is a measure of the span error of the DAC. It is the

deviation in slope of the DAC transfer characteristic from the

ideal, expressed as a percentage of the full-scale range.

Differential Nonlinearity

Total Unadjusted Error

Differential Nonlinearity (DNL) is the difference between the

measured change and the ideal 1 LSB change between any two

adjacent codes. A specified differential nonlinearity of 1 LSB

maximum ensures monotonicity. This DAC is guaranteed

monotonic by design. A typical DNL vs. code plot can be seen

in Figures ?.

Total Unadjusted Error (TUE) is a measure of the output error

taking all the various errors into account. A typical TUE vs.

code plot can be seen in Figure ?.

Zero-Code Error Drift

This is a measure of the change in zero-code error with a

change in temperature. It is expressed in µꢁ/°C.

Monotonicity

A DAC is monotonic, if the output either increases or remains

constant for increasing digital input code. The AD5744/64 is

monotonic over its full operating temperature range

Gain Error Drift

This is a measure of the change in gain error with changes in

temperature. It is expressed in (ppm of full-scale range)/°C.

Bipolar Zero Error

Digital-to-Analog Glitch Impulse

Bipolar zero error is the deviation of the analog output from the

ideal half-scale output of ꢂ ꢁ when the DAC register is loaded

with ꢂx8ꢂꢂꢂ (Offset Binary coding) or ꢂxꢂꢂꢂꢂ (ꢀsComplement

coding)

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

state. It is normally specified as the area of the glitch in nꢁ secs

and is measured when the digital input code is changed by

1 LSB at the major carry transition (7FFF Hex to 8ꢂꢂꢂ Hex). See

Figure ?.

Full-Scale Error

Full-scale error is a measure of the output error when full-scale

code is loaded to the DAC register. Ideally the output voltage

should be full scale value – 1 LSB. Full-scale error is expressed

in percentage of full-scale range. A plot of full-scale error vs.

temperature can be seen in Figure ?.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into

the analog output of the DAC from the digital inputs of the

DAC but is measured when the DAC output is not updated. It is

specified in nꢁ secs and measured with a full-scale code change

on the data bus, i.e., from all ꢂs to all 1s and vice versa.

Negative Full-Scale Error / Zero Scale Error

Negative full-scale error is the error in the DAC output voltage

when ꢂxꢂꢂꢂꢂ (Offset Binary coding) or ꢂx8ꢂꢂꢂ (ꢀsComplement

coding) is loaded to the DAC register. Ideally the output voltage

should be negative full scale value – 1 LSB.

Power Supply Sensitivity

Power supply sensitivity indicates how the output of the DAC is

affected by changes in the power supply voltage.

Output Voltage Settling Time

DC Crosstalk

Output voltage settling time is the amount of time it takes for

the output to settle to a specified level for a full-scale input

change.

This is the dc change in the output level of one DAC in response

to a change in the output of another DAC. It is measured with a

full-scale output change on one DAC while monitoring another

DAC. It is expressed in µꢁ.

Slew Rate

The slew rate of a device is a limatation in the rate of change of

the output voltage. The output slewing speed of a voltage-

output D/A converter is usually limited by the slew rate of the

amplifier used at its output. Slew rate is measured from 1ꢂ% to

DAC-to-DAC Crosstalk

This is the glitch impulse transferred to the output of one DAC

due to a digital code change and subsequent output change of

Rev. PrA 15-Nov-04| Page 13 of 27

Preliminary Technical Data

another DAC. This includes both digital and analog crosstalk. It

is measured by loading one of the DACs with a full-scale code

LDAC

change (all ꢂs to all 1s and vice versa) with

low and

monitoring the output of another DAC. The energy of the glitch

is expressed in nꢁ-s.

Channel-to-Channel Isolation

This is the ratio of the amplitude of the signal at the output of

one DAC to a sine wave on the reference input of another DAC.

It is measured in dB.

Rev. PrA 15-Nov-04| Page 14 of 27

Preliminary Technical Data

TYPICAL PERFORMANCE

CHARACTERISTICS

Rev. PrA 15-Nov-04| Page 15 of 27

Preliminary Technical Data

SERIAꢀ INTERFACE

GENERAL DESCRIPTION

The AD5744/64 is controlled over a versatile 3-wire serial

interface that operates at clock rates of up to 3ꢂ MHz and is

compatible with SPI, QSPI, MICROWIRE and DSP standards.

The AD5744/64 is a quad 14/16-bit, serial input, bipolar voltage

output DAC. It operates from supply voltages of 11.4 ꢁ to

16.5 ꢁ and has a buffered output voltage of up to 1ꢂ.5 ꢁ.

Data is written to the AD5744/64 in a ꢀ4-bit word format, via a

3-wire serial interface. The device also offers an SDO pin, which

is available for daisy chaining or readback.

Input Shift Register

The input shift register is ꢀ4 bits wide. Data is loaded into the

device MSB first as a ꢀ4-bit word under the control of a serial

clock input, SCLK. The input register consists of a read/write

bit, three register select bits, three DAC address bits and 14/16

data bits as shown in Table 8.The timing diagram for this

operation is shown in Figure ꢀ.

The AD5744/64 incorporates a power-on reset circuit, which

ensures that the DAC registers power up loaded with ꢂxꢂꢂꢂꢂ.

The AD5744/64 also features a digital I/O port that may be

programmed via the serial interface, an analog temperature

sensor, on-chip 1ꢂ ppm/°C voltage reference, on-chip reference

buffers and per channel digital gain and offset registers.

Upon power-up the DAC registers are loaded with zero code

(ꢂxꢂꢂꢂꢂ). The corresponding output voltage depends on the

ꢀsCOMP

state of the BIN/

pin. If the BIN/

pin is tied to

DAC ARCHITECTURE

DGND then the data coding is ꢀsComplement and the outputs

ꢀsCOMP

The DAC architecture of the AD5744/64 consists of a 14/16-bit

current-mode segmented R-ꢀR DAC. The simplified circuit

diagram for the DAC section is shown in Figure 13.

will power-up to ꢂꢁ. If the BIN/

pin is tied high then

the data coding is Offset binary and the outputs will power-up

to Negative Full-scale.

Standalone Operation

The four MSBs of the 14/16-bit data word are decoded to drive

15 switches, E1 to E15. Each of these switches connects one of

the 15 matched resistors to either AGND or IOUT. The

remaining 1ꢀ bits of the data word drive switches Sꢂ to S11 of

the 1ꢀ-bit R-ꢀR ladder network.

The serial interface works with both a continuous and noncon-

tinuous serial clock. A continuous SCLK source can only be

SYNC

used if

In gated clock mode, a burst clock containing the exact number

SYNC

is held low for the correct number of clock cycles.

of clock cycles must be used and

the final clock to latch the data. The first falling edge of

starts the write cycle. Exactly ꢀ4 falling clock edges must be

must be taken high after

R

V

ref

SYNC

2R

SYNC

applied to SCLK before

SYNC

is brought back high again; if

th

R/8

is brought high before the ꢀ4 falling SCLK edge, the

E15

E14

E1

S0

S11

S10

write is aborted. If more than ꢀ4 falling SCLK edges are applied

SYNC

before

The input register addressed is updated on the rising edge of

SYNC SYNC

is brought high, the input data will be corrupted.

V

OUT

AGND

. In order for another serial transfer to take place,

4 MSBs DECODED INTO

15 EQUAL SEGMENTS

12 BIT R-2R LADDER

must be brought low again. After the end of the serial data

transfer, data is automatically transferred from the input shift

register to the input register of the addressed DAC.

Figure 7. DAC Ladder Structure

When the data has been transferred into the input register of

the addressed DAC, all DAC registers and outputs can be

REFERENCE BUFFERS

LDAC

SYNC

The AD5744/64 can operate with either an external or internal

reference. The reference inputs (REFAB and REFCD) have an

input range up to 5 ꢁ. This input voltage is then used to provide

a buffered positive and negative reference for the DAC cores.

The positive reference is given by

updated by taking

low while

is high.

+ ꢁ_REF= ꢀ* ꢁ_REF

While the negative reference to the DAC cores is given by

-ꢁ_REF= -ꢀ*ꢁ_REF

These positive and negative reference voltages (along with the

gain register values) define the output ranges of the DACs.

Rev. PrA 15-Nov-04| Page 16 of 27

Preliminary Technical Data

containing the exact number of clock cycles must be used and

SYNC

68HC11*

AD5744/64*

must be taken high after the final clock to latch the data.

MOSI

SCK

PC7

PC6

SDIN

SCLK

SYNC

LDAC

Readback Operation

Readback mode is invoked by setting the R/ bit = 1 in the

W

serial input register write. With R/ = 1, Bits Aꢀ–Aꢂ, in

association with Bits REGꢀ , REG1, and REGꢂ, select the

register to be read. The remaining data bits in the write

sequence are don’t cares. During the next SPI write, the data

appearing on the SDO output will contain the data from the

previously addressed register. For a read of a single register, the

NOP command can be used in clocking out the data from the

selected register on SDO. The readback diagram in Figure 4

shows the readback sequence. For example, to read back the

fine gain register of Channel A on the AD5744/64, the following

sequence should be implemented. First, write ꢂxAꢂXXXX to

the AD5744/64 input register. This configures the AD5744/64

for read mode with the fine gain register of Channel A selected.

Note that all the data bits, DB15 to DBꢂ, are don’t cares. Follow

this with a second write, a NOP condition, ꢂxꢂꢂXXXX. During

this write, the data from the fine gain register is clocked out on

the SDO line, i.e., data clocked out will contain the data from

the fine gain register in Bits DB5 to DBꢂ.

MISO

SDO

SDIN

AD5744/64*

SCLK

SYNC

LDAC

SDO

R

SDIN

AD5744/64*

SCLK

SYNC

LDAC

SIMUꢀTANEOUS UPDATING VIA ꢀDAC

After data has been transferred into the input register of the

DACs, there are two ways in which the DAC registers and DAC

SDO

SYNC

outputs can be updated. Depending on the status of both

LDAC

*ADDITIONAL PINS OMITTED FOR CLARITY

and

.

Figure 8. Daisy chaining the AD5744/64

Individual DAC Updating

LDAC

Daisy-Chain Operation

In this mode,

is held low while data is being clocked into

the input shift register. The addressed DAC output is updated

SYNC

For systems that contain several devices, the SDO pin may be

used to daisy-chain several devices together. This daisy-chain

mode can be useful in system diagnostics and in reducing the

on the rising edge of

Simultaneous Updating of All DACs

LDAC

.

SYNC

number of serial interface lines. The first falling edge of

starts the write cycle. The SCLK is continuously applied to the

SYNC

In this mode,

into the input shift register. All DAC outputs are updated by

LDAC SYNC

is held high while data is being clocked

input shift register when

is low. If more than ꢀ4 clock

taking

low any time after

has been taken high.

LDAC

pulses are applied, the data ripples out of the shift register and

appears on the SDO line. This data is clocked out on the rising

edge of SCLK and is valid on the falling edge. By connecting the

SDO of the first device to the DIN input of the next device in

the chain, a multidevice interface is constructed. Each device in

the system requires ꢀ4 clock pulses. Therefore, the total number

of clock cycles must equal ꢀ4N, where N is the total number of

AD5744/64s in the chain. When the serial transfer to all devices

The update now occurs on the falling edge of

.

SYNC

is complete,

is taken high. This latches the input data in

each device in the daisy chain and prevents any further data

from being clocked into the input shift register. The serial clock

may be a continuous or a gated clock. A continuous SCLK

SYNC

source can only be used if

is held low for the correct

number of clock cycles. In gated clock mode, a burst clock

Rev. PrA 15-Nov-04| Page 17 of 27

Preliminary Technical Data

OUTPUT

I/V AMPLIFIER

Table 7. Ideal output voltage to input Code relationship for the

AD5744

16-BIT

DAC

V

REFIN

V

OUT

Digital Input

Analog Output

Offset Binary Data Coding

DAC

LDAC

MSB

11

ꢀSB V_OUT

REGISTER

+2 V_REFx (8192/8192)

+2 V_REFx (1/8192)

0 V

1111

0000

1111

0000

1111

0000

1111

0000

1111

0001

0000

1111

0000

10

01

00

INPUT

REGISTER

-2 V_REFx (1/8192)

-2 V_REFx (8192/8192)

SCLK

SYNC

SDIN

Twos Complement Data Coding

INTERFACE

LOGIC

SDO

V_OUT

MSB

01

ꢀSB

1111

+2 V_REFx (8192/8192)

+2 V_REFx (1/8192)

0 V

1111

0000

1111

0000

1111

0000

1111

0000

Figure 9. Simplified Serial Interface showing input loading

circuitry for one DAC Channel

00

11

10

0001

0000

1111

0000

-2 V_REFx (1/8192)

-2 V_REFx (8192/8192)

TRANSFER FUNCTION

Table 6 and Table 7 Show the ideal input code to output voltage

relationship for the AD5744/64 for both Offset binary and twos

complement data coding.

The output voltage expression for the AD5764 is given by:

Table 6. Ideal output voltage to input code relationship for the

AD5764

D

⎡

⎤

V_OUT= −2×V_REFIN+ 4×V_REFIN

⎢

⎣

⎥

⎦

Digital Input

Analog Output

65536

The output voltage expression for the AD5744 is given by:

Offset Binary Data Coding

MSB

1111

1000

0111

0000

ꢀSB V_OUT

D

⎡

⎤

+2 V_REFx (32767/32768)

+2 V_REFx (1/32768)

0 V

1111

0000

1111

0000

1111

0000

1111

0000

1111

0001

0000

1111

0000

V_OUT= −2×V_REFIN+ 4×V_REFIN

⎢

⎣

⎥

⎦

16384

where:

-2 V_REFx (1/32768)

-2 V_REFx (32767/32768)

D is the decimal equivalent of the code loaded to the DAC.

ꢁ_REFINis the reference voltage applied at the REFIN pin.

Twos Complement Data Coding

V_OUT

MSB

0111

0000

1111

1000

ꢀSB

1111

ASYNCHRONOUS CꢀEAR (CꢀR)

+2 V_REFx (32767/32768)

+2 V_REFx (1/32768)

0 V

1111

0000

1111

0000

1111

0000

1111

0000

CLR

is an active low, level sensitive clear that allows the outputs

0001

0000

1111

0000

to be cleared to either ꢂ ꢁ (Offset binary coding) or negative

full scale (twos complement coding). It is necessary to maintain

-2 V_REFx (1/32768)

-2 V_REFx (32767/32768)

CLR

low for a minimum amount of time (refer to Figure 3) for

CLR

the operation to complete. When the

signal is returned

high, the output remains at the cleared value until a new value is

CLR LDAC

programmed. The

SYNC

signal has priority over

. A clear can also be initiated through software by writing

the command ꢂxꢂ4XXXX to the AD5744/64.

and

Rev. PrA 15-Nov-04| Page 18 of 27

Preliminary Technical Data

Table 8. AD5744/64 Input Register Format

MSB

ꢀSB

DB23

DB22

DB21

DB20

DB19

DB18

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

W

R/

0

REG2

REG1

REG0

A2

A1

A0

DATA

Table 9. Input Register Bit Functions

Indicates a read from or a write to the addressed register.

W

R/

REG2, REG1, REG0

Used in association with the address bits to determine if a read or write operation is to the data register, offset

register, gain register, or function register.

REG2

REG1

REG0

Function

0

1

0

1

0

1

0

1

Function Register

Data Register

Coarse Gain Register

Fine Gain Register

Offset Register

A2, A1, A0

These bits are used to decode the DAC channels

A2

0

A1

0

A0

0

Channel Address

DAC A

0

1

DAC B

0

1

0

DAC C

0

1

DAC D

1

0

ALL DACs

D15 – D0

Data Bits

FUNCTION REGISTER

The Function Register is addressed by setting the three REG bits to ꢂꢂꢂ. The values written to the address bits and the data bits determine

the function addressed. The Functions available through the function register are shown in Table 1ꢂ and

Table 11.

Table 1ꢂ. Function Register Options

REG2 REG1 REG0 A2 A1 A0

DB15 .. DB6

DB5

DB4

NOP, Data = Don’t Care

D1

D1 Value D0

Direction

DB3

DB2

DB1

DB0

0

1

Don’t Care

Local-

Ground-

Offset Adjust

D0

Value

SDO

Disable

Direction

0

1

0

1

CLR, Data = Don’t Care

LOAD, Data = Don’t Care

Rev. PrA 15-Nov-04| Page 19 of 27

Preliminary Technical Data

Table 11. Explanation of Function Register Options

NOP

No operation instruction used in readback operations.

Local-Ground-

Offset Adjust

Set by the user to enable local-ground-offset adjust function.

Cleared by the user to disable local-ground-offset adjust function (default).

Set by the user to enable D0/D1 as outputs.

D0 / D1

Direction

Cleared by the user to enable D0/D1 as inputs (default). Have weak internal pull-ups.

D0 / D1 Value

I/O port status bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when

configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input. When

enabled as inputs, these bits are don’t cares during a write operation.

SDO Disable

Set by the user to disable the SDO output.

Cleared by the user to enable the SDO output (default).

CLR

Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary

mode.

LOAD

Addressing this function updates the DAC registers and consequently the analog outputs.

DATA REGISTER

The Data register is addressed by setting the three REG bits to ꢂ1ꢂ. The DAC address bits select with which DAC Channel the Data

transfer is to take place (Refer to Table 9). The data bits are in positions D15 to Dꢂ for the AD5764 as shown in Table 1ꢀ and D13 to Dꢂ

for the AD5744 as shown in Table 13.

Table 1ꢀ. Programming the AD5764 Data Register

REG2

REG1

REG0

A2

A1

A0

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

DAC Address

16 Bit DAC Data

Table 13. Programming the AD5744 Data Register

REG2

REG1

REG0

A2

A1

A0

DB15

DB14

DB10

DB9

DB8

DB7

DB1

DB0

0

1

0

DAC Address

14 Bit DAC Data

X

COARSE GAIN REGISTER

The Coarse Gain Register is addressed by setting the three REG bits to ꢂ11. The DAC address bits select with which DAC Channel the

Data transfer is to take place (Refer to Table 9). The Coarse Gain Register is a ꢀ-bit register and allows the user to select the output range

of each DAC as shown in Table 15.

Table 14. Programming the Coarse Gain Register

REG2 REG1 REG0 A2 A1 A0 DB15 …. DB2 DB1 DB0

0

1

DAC Address

Don’t Care

CG1 CG0

Table 15. Output Range Selection

Output Range

CG1

CG0

10 V

10.25 V

10.5 V

0

1

0

1

0

Rev. PrA 15-Nov-04| Page 20 of 27

Preliminary Technical Data

FINE GAIN REGISTER

The Fine Gain Register is addressed by setting the three REG bits to 1ꢂꢂ. The DAC address bits select with which DAC Channel the Data

transfer is to take place (Refer to Table 9). The Fine Gain Register is a 6-bit register and allows the user to adjust the gain of each DAC

channel by -3ꢀ LSBs to +31 LSBs in 1 LSB steps as shown in

Table 16 and

Table 17.

Table 16. Programming AD5764 Fine Gain Register

REG2 REG1 REG0 A2

A1

A0

DB15 …. DB6

DB5 DB4 DB3 DB2 DB1 DB0

1

0

DAC Address

Don’t Care

FG5 FG4 FG3 FG2 FG1 FG0

Table 17. Fine Gain Register Options

Gain Adjustment

+31 LSBs

+30 LSBs

FG5 FG4 FG3 FG2 FG1 FG0

0

-

1

-

1

-

1

-

1

-

1

0

-

No Adjustment

0

-

0

-

0

-

0

-

0

-

0

-

-31 LSBs

-32 LSBs

1

0

1

0

OFFSET REGISTER

The Offset Register is addressed by setting the three REG bits to 1ꢂ1. The DAC address bits select with which DAC Channel the Data

transfer is to take place (Refer to Table 9). The Offset Register is an 8-bit register and allows the user to adjust the offset of each channel

by – 15.875 LSBs to + 16 LSBs in steps of 1/8 LSB as shown in Table 18 and Table 19.

Table 18. Programming the Offset Register

REG2 REG1 REG0 A2 A1 A0 DB15 …. DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1

0

1

DAC Address

Don’t Care

OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0

Table 19. Offset Register options

Offset Adjustment

+15.875 LSBs

+16.5 LSBs

OF7 OF6 OF5 OF4 OF3 OF2 OF1 OF0

0

-

1

-

1

-

1

-

1

-

1

-

1

-

1

0

-

No Adjustment

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

-15.875 LSBs

-16 LSBs

1

0

1

0

Rev. PrA 15-Nov-04| Page 21 of 27

Preliminary Technical Data

AD5744/64 FEATURES

ANAꢀOG OUTPUT CONTROꢀ

The resistor value is calculated as follows;

In many industrial process control applications, it is vital that

the output voltage be controlled during power up and during

brownout conditions. When the supply voltages are changing,

the ꢁOUT pin is clamped to ꢂ ꢁ via a low impedance path. To

prevent the output amp being shorted to ꢂ ꢁ during this time,

transmission gate G1 is also opened. These conditions are

maintained until the power supplies stabilize and a valid word is

written to the DAC register. At this time, Gꢀ opens and G1

closes. Both transmission gates are also externally controllable

60

R =

Isc

If the ISCC pin is left unconnected the short circuit current

limit defaults to 5 mA. It should be noted that limiting the short

circuit current to a small value can affect the slew rate of the

output when driving into a capacitive load, therefore the value

of short-circuit current programmed should take into account

the size of the capacitive load being driven.

RSTIN

input is

via the Reset In (

) control input. For instance, if

RSTIN

is

driven from a battery supervisor chip, the

DIGITAꢀ I/O PORT

driven low to open G1 and close Gꢀ on power-off or during a

brownout. Conversely, the on-chip voltage detector output

The AD5744/64 contains a ꢀ-bit digital I/O port (D1 and Dꢂ);

these bits can be configured as inputs or outputs independently,

and can be driven or have their values read back via the serial

interface. The I/O port signals are referenced to Dꢁ_CCand

DGND. When configured as outputs, they can be used as con-

trol signals to multiplexers or can be used to control calibration

circuitry elsewhere in the system. When configured as inputs,

the logic signals from limit switches, for example can be applied

to Dꢂ and D1 and can be read back via the digital interface.

RSTOUT

(

) is also available to the user to control other parts of

the system. The basic transmission gate functionality is shown

in Figure 1ꢂ.

RSTOUT

RSTIN

VOLTAGE

MONITOR

AND

TEMPERATURE SENSOR

CONTROL

The on-chip temperature sensor provides a voltage output that

is linearly proportional to the Centigrade temperature scale.

The typical accuracy of the temperature sensor is 1°C at +ꢀ5°C

and 5°C over the −4ꢂ°C to +1ꢂ5°C range. Its nominal output

voltage is 1.5ꢁ at +ꢀ5°C, varying at 5 mꢁ/°C, giving a typical

output range of 1.175ꢁ to 1.9 ꢁ over the full temperature range.

Its low output impedance, low self heating, and linear output

simplify interfacing to temperature control circuitry and A/D

converters.

G1

VOUTA

AGNDA

G2

Figure 1ꢂ. Analog Output Control Circuitry

DIGITAꢀ OFFSET AND GAIN CONTROꢀ

ꢀOCAꢀ GROUND OFFSET ADJUST

The AD5744/64 incorporates a digital offset adjust function

The AD5744/64 incorporates a Local Ground Offset Adjust

feature which when enabled in the Function Register adjusts the

DAC outputs for voltage differences between The individual

DAC ground pins and the REFGND pin ensuring that the DAC

output voltages are always with respect to the local DAC ground

pin. For instance if pin AGNDA is at +5mꢁ with respect to the

REFGND pin and ꢁOUTA is measured with respect to

AGNDA then a +5mꢁ error will result, enabling the Local

Ground Offset Adjust feature will offset ꢁOUTA by +5mꢁ

eliminating the error.

with a 16 LSB adjust range and ꢂ.1ꢀ5 LSB resolution. The gain

register allows the user to adjust the AD5744/64’s full-scale

output range. The full-scale output can be programmed to

achieve full-scale ranges of 1ꢂ ꢁ, 1ꢂ.ꢀ5 ꢁ, and 1ꢂ.5 ꢁ. A fine

gain trim is also available, allowing a trim range of 16 LSB in 1

LSB steps.

PROGRAMMABꢀE SHORT-CIRCUIT PROTECTION

The short-circuit current of the output amplifiers can be pro-

grammed by inserting an external resistor between the ISCC

pin and AGND. The programmable range for the current is

5ꢂꢂ µA to 1ꢂ mA, corresponding to a resistor range of 1ꢀꢂ kΩ

to 6 kΩ.

Rev. PrA 15-Nov-04| Page 22 of 27

Preliminary Technical Data

in the voltage reference is reflected in the outputs of the device.

APPLICATIONS INFORMATION

There are four possible sources of error to consider when

choosing a voltage reference for high accuracy applications:

initial accuracy, temperature coefficient of the output voltage,

long term drift and output voltage noise.

TYPICAꢀ OPERATING CIRCUIT

Figure 11 shows the typical operating circuit for the

AD5744/64. The only external components needed for this

precision 14/16-bit DAC are decoupling capacitors on the

supply pins, R-C connection from REFOUT to REFAB and

REFCD and a short circuit current setting resistor. Because the

device incorporates a voltage reference, and reference buffers, it

eliminates the need for an external bipolar reference and

associated buffers. This leads to an overall saving in both cost

and board space.

Initial accuracy error on the output voltage of an external

reference could lead to a full-scale error in the DAC. Therefore,

to minimize these errors, a reference with low initial accuracy

error specification is preferred. Also, choosing a reference with

an output trim adjustment, such as the ADR4ꢀ5, allows a

system designer to trim system errors out by setting the

reference voltage to a voltage other than the nominal. The trim

adjustment can also be used at temperature to trim out any

error.

In the circuit below, ꢁDD and ꢁSS are both connected to 15 ꢁ,

but ꢁDD and ꢁSS can operate with supplies from 11.4 ꢁ to

16.5 ꢁ. In Figure 11, AGNDA is connected to REFGND, but

the option of Force/Sense is included on this device, if required

by the user.

Long term drift is a measure of how much the reference output

voltage drifts over time. A reference with a tight lon-term drift

specification ensures that the overall solution remains relatively

stable over its entire lifetime.

+15V -15V

10 µF

The temperature coefficient of a reference’s output voltage

affects INL, DNL and TUE. A reference with a tight

tempaerature coefficient specifiaction should be chosen to

reduce the dependence of the DAC output voltage on ambient

conditions.

100 nF

TEMP

+5V

BIN/2SCOMP

32 31 30 29 28 27 26 25

In high accuracy applications, which have a relatively low noise

budget, reference output voltage noise needs to be considered.

Choosing a reference waith as low an output noise voltage as

practical for the system resolution required is important.

Precision voltage references such as the ADR435 (XFET design)

produce low output noise in the ꢂ.1 Hx to 1ꢂ Hz region.

However, as the circuit bandwidth increases, filtering the output

of the reference may be required to minimise the output noise.

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

SYNC

SCLK

SDIN

SDO

SYNC

AGNDA

VOUTA

VOUTB

AGNDB

AGNDC

VOUTC

VOUTD

AGNDD

VOUTA

VOUTB

SCLK

SDIN

SDO

CLR

LDAC

D0

AD5744/64

VOUTC

VOUTD

LDAC

D0

D1

9

10 11 12 13 14 15 16

RSTOUT

RSTIN

6kΩ

Table ꢀꢂ. Partial List of Precision References Recommended for

use with the AD5744/64

10 µF

100 nF

10 µF

Initial

ꢀong-Term

Drift

Temp Drift

0.1 Hz to

Accuracy

(ppm/

10 Hz Noise

Part No.

ADR435

ADR425

ADR02

(mV max) (ppm typ)

°C max)

(µV p-p typ)

+15V

-15V

+5V

6

30

50

15

3

3.4

15

5

6

3

Figure 11. Typical operating circuit

5

3

ADR395

AD586

6

25

10

2.5

4

Precision Voltage Reference Selection

To achieve the optimum performance from the AD5744/64 over

it’s full operating temperature range an external voltage

reference must be used. Thought should be given to the

selection of a precision voltage reference. The AD5744/64 has

two reference inputs, REFAB and REFCD. The voltages applied

to the reference inputs are used tomprovide a buffered positiver

and negative reference for the DAC cores. Therefore, any error

Rev. PrA 15-Nov-04| Page 23 of 27

Preliminary Technical Data

DAC is not required, the LDAC pin may be tied permanently

low. The DAC can then be updated on the rising edge of SYNC.

ꢀAYOUT GUIDEꢀINES

In any circuit where accuracy is important, careful

consideration of the power supply and ground return layout

helps to ensure the rated performance. The printed circuit

board on which the AD5744/64 is mounted should be designed

so that the analog and digital sections are separated and

confined to certain areas of the board. If the AD5744/64 is in a

system where

multiple devices require an AGND-to-DGND connection, the

connection should be made at one point only. The star ground

point should be established as close as possible to the device.

DV

CC

µCONTROLLER

CONTROL OUT

TO LDAC

TO SYNC

TO SCLK

TO SDIN

SYNC OUT

The AD5744/64 should have ample supply bypassing of 1ꢂ µF

in

SERIAL CLOCK OUT

parallel with ꢂ.1 µF on each supply located as close to the

package as possible, ideally right up against the device. The 1ꢂ

µF capacitors are the tantalum bead type. The ꢂ.1 µF capacitor

should have low effective series resistance (ESR) and low

effective series inductance (ESI) such as the common ceramic

types, which provide a low impedance path to ground at high

frequencies to handle transient currents due to internal logic

switching.

SERIAL DATA OUT

OPTO-COUPLER

Figure 1ꢀ. Isolated Interface

The power supply lines of the AD5744/64 should use as large a

trace as possible to provide low impedance paths and reduce

the effects of glitches on the power supply line. Fast switching

signals such as clocks should be shielded with digital ground to

avoid radiating noise to other parts of the board, and should

never be run near the reference inputs. A ground line routed

between the SDIN and SCLK lines helps reduce crosstalk

between them (not required on a multilayer board, which has a

separate ground plane, but separating the lines helps). It is

essential to minimize noise on the reference inputs, because it

couples through to the DAC output.

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5744/64 is via a serial bus

that uses standard protocol compatible with microcontrollers

and DSP processors. The communications channel is a 3-wire

(minimum) interface consisting of a clock signal, a data signal,

and a synchronization signal. The AD5744/64 requires a ꢀ4-bit

data word with data valid on the falling edge of SCLK.

For all the interfaces, the DAC output update may be done

automatically when all the data is clocked in, or it may be done

under the control of LDAC. The contents of the DAC register

may be read using the readback function.

Avoid crossover of digital and analog signals. Traces on

opposite sides of the board should run at right angles to each

other. This reduces the effects of feed through the board. A

microstrip technique is by far the best, but not always possible

with a double-sided board. In this technique, the component

side of the board is dedicated to ground plane, while signal

traces are placed on the solder side.

AD5744/64 to MC68HC11 Interface

Figure 13 shows an example of a serial interface between the

AD5744/64 and the MC68HC11 microcontroller. The serial

peripheral interface (SPI) on the MC68HC11 is configured for

master mode (MSTR = 1), clock polarity bit (CPOL = ꢂ), and

the clock phase bit (CPHA = 1). The SPI is configured by

writing to the SPI control register (SPCR)----see the 68HC11

User Manual. SCK of the 68HC11 drives the SCLK of the

AD5744/64, the MOSI output drives the serial data line (DIN)

of

ISOꢀATED INTERFACE

In many process control applications, it is necessary to provide

an isolation barrier between the controller and the unit being

controlled. Opto-isolators can provide voltage isolation in

excess of 3 kꢁ. The serial loading structure of the AD5744/64

makes it ideal for opto-isolated interfaces, because the number

of interface lines is kept to a minimum. Figure 1ꢀ shows a 4-

channel isolated interface to the AD5744/64. To reduce the

number of opto-isolators, if the simultaneous updating of the

the AD5744/64, and the MISO input is driven from SDO. The

SYNC is driven from one of the port lines, in this case PC7.

When data is being transmitted to the AD5744/64, the SYNC

line

Rev. PrA 15-Nov-04| Page 24 of 27

Preliminary Technical Data

(PC7) is taken low and data is transmitted MSB first. Data

appearing on the MOSI output is valid on the falling edge of

SCK. Eight falling clock edges occur in the transmit cycle, so, in

order to load the required ꢀ4-bit word, PC7 is not brought high

until the third 8-bit word has been transferred to the DAC’s

input shift register.

through the SPORT control register and should be configured

as follows: internal clock operation, active low framing, and

ꢀ4-bit word length.

Transmission is initiated by writing a word to the Tx register

after the SPORT has been enabled. As the data is clocked out of

the DSP on the rising edge of SCLK, no glue logic is required to

interface the DSP to the DAC. In the interface shown, the DAC

output is updated using the LDAC pin via the DSP.

Alternatively, the LDAC input could be tied permanently low,

and then the update takes place automatically when TFS is

taken high.

MC68HC11*

AD5744/64*

MISO

MOSI

SCLK

PC7

SDO

SDIN

SCLK

ADSP2101/

ADSP2103*

AD5744/64*

SYNC

DR

DT

SDO

*ADDITIONAL PINS OMITTED FOR CLARITY

SDIN

SCLK

Figure 13. AD5744/64 to MC68HC11 Interface

SCLK

TFS

SYNC

LDAC

LDAC is controlled by the PC6 port output. The DAC can be

updated after each 3-byte transfer by bringing LDAC low. This

example does not show other serial lines for the DAC. If CLR

were used, it could be controlled by port output PC5, for

example.

RFS

FO

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 14. AD5744/64 to ADSPꢀ1ꢂ1/ADSPꢀ1ꢂ3 Interface

AD5744/64 to 8051 Interface

The AD5744/64 requires a clock synchronized to the serial

data. For this reason, the 8ꢂ51 must be operated in Mode ꢂ. In

this mode, serial data enters and exits through RxD, and a shift

clock is output on TxD.

P3.3 and P3.4 are bit programmable pins on the serial port and

are used to drive SYNC and LDAC, respectively.

The 8ꢂ51 provides the LSB of its SBUF register as the first bit in

the data stream. The user must ensure that the data in the SBUF

register is arranged correctly, because the DAC expects MSB

first. When data is to be transmitted to the DAC, P3.3 is taken

low. Data on RxD is clocked out of the microcontroller on the

rising edge of TxD and is valid on the falling edge. As a result,

no glue logic is required between this DAC and the

microcontroller interface.

AD5744/64 to PIC16C6x/7x Interface

The PIC16C6x/7x synchronous serial port (SSP) is configured

as an SPI master with the clock polarity bit set to ꢂ. This is done

by writing to the synchronous serial port control register

(SSPCON). See the PIC16/17 Microcontroller User Manual. In

this example, I/O port RA1 is being used to pulse SYNC and

enable the serial port of the AD5744/64. This microcontroller

transfers only eight bits of data during each serial transfer

operation; therefore, three consecutive write operations are

needed. Figure 15 shows the connection diagram.

PIC16C6x/7x*

AD5744/64*

SDI/RC4

SDO/RC5

SCLK/RC3

RA1

SDO

SDIN

SCLK

The 8ꢂ51 transmits data in 8-bit bytes with only eight falling

clock edges occurring in the transmit cycle. Because the DAC

expects a ꢀ4-bit word, SYNC (P3.3) must be left low after the

first eight bits are transferred. After the third byte has been

transferred, the P3.3 line is taken high. The DAC may be

updated using LDAC via P3.4 of the 8ꢂ51.

SYNC

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 15. AD5744/64 to PIC16C6x/7x Interface

AD5744/64 to ADSP2101/ADSP2103 Interface

An interface between the AD5744/64 and the ADSPꢀ1ꢂ1/

ADSPꢀ1ꢂ3 is shown in Figure 14. The ADSPꢀ1ꢂ1/ADSPꢀ1ꢂ3

should be set up to operate in the SPORT transmit alternate

framing mode. The ADSPꢀ1ꢂ1/ADSPꢀ1ꢂ3 are programmed

Rev. PrA 15-Nov-04| Page 25 of 27

Preliminary Technical Data

EVAꢀUATION BOARD

The AD5744/64 comes with a full evaluation board to aid

designers in evaluating the high performance of the part with a

minimum of effort. All that is required with the evaluation

board is a power supply, and a PC. The AD5744/64 evaluation

kit includes a populated, tested AD5744/64 printed circuit

board. The evaluation board interfaces to the USB interface of

the PC. Software is available with the evaluation board, which

allows the user to easily program the AD5744/64. The software

runs on any PC that has Microsoft Windows® 98/ꢀꢂꢂꢂ/NT/XP

installed.

An application note is available that gives full details on

operating the evaluation board.

Rev. PrA 15-Nov-04| Page 26 of 27

Preliminary Technical Data

OUTLINE DIMENSIONS

1.20

MAX

9.00 SQ

0.75

0.60

0.45

24

17

16

25

TOP VIEW

(PINS DOWN)

7.00

SQ

32

9

1

8

0.15

0.05

0.80

BSC

0.45

0.37

0.30

1.05

1.00

0.95

7°

0°

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-026ABA

Figure 16. 3ꢀ-Lead Thin Quad Flatpack [TQFP]

(SU-3ꢀ)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Function

INꢀ

1 LSB Max

Package Description

32-Lead TQFP

Package Option

SU-32

AD5764CSU

AD5764BSU

AD5764ASU

AD5744CSU

AD5744BSU

AD5744ASU

Quad 16-Bit DAC

Quad 14-Bit DAC

2 LSB Max

4 LSB Max

1 LSB Max

2 LSB Max

4 LSB Max

SU-32

©

registered trademarks are the property of their respective owners.

PR05303-0-11/04(PrA)

Rev. PrA 15-Nov-04| Page 27 of 27


型号：	AD5744BSU
厂家：	ADI
描述：	Complete, Quad, 14/16-Bit, High Accuracy, Serial Input, Bipolar Voltage Output DAC 完整的四通道14位/ 16位，高精度，串行输入，双极性电压输出DAC 转换器数模转换器
文件：	总27页 (文件大小：367K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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