AD5744CSUZ-REEL7 [ADI]
IC SERIAL INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP32, LEAD FREE, PLASTIC, MS-026ABA, TQFP-32, Digital to Analog Converter;
| 型号： | AD5744CSUZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | IC SERIAL INPUT LOADING, 8 us SETTLING TIME, 14-BIT DAC, PQFP32, LEAD FREE, PLASTIC, MS-026ABA, TQFP-32, Digital to Analog Converter 输入元件 转换器 |
| 文件： | 总32页 (文件大小：463K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Low Power CMOS Analog Front End
with DSP Microcomputer
Preliminary Technical Data
AD5744
FEATURES
GENERAꢀ DESCRIPTION
Complete quad, 14-bit digital-to-analog
converters (DACs)
Programmable output range: 10 V, 10.2564 V,
or 10.5263 V
1 ꢀSB max INꢀ error, 1 ꢀSB max DNꢀ error
ꢀow noise: 60 nV/√Hz
Settling time: 10 μs max
The AD5744 is a quad, 14-bit, serial input, bipolar voltage
output digital-to-analog converter that operates from supply
voltages of 11ꢀ4 V up to 1ꢁꢀ5 ꢀ Nominal full-scale output
range is 1ꢂ ꢀ The AD5744 provides integrated output
amplifiers, reference buffers and proprietary power-up/power-
down control circuitryꢀ The part also features a digital I/O port,
which is programmed via the serial interfaceꢀ The AD5744
incorporates digital gain adjust registers per channelꢀ
Integrated reference buffers
Output control during power-up/brownout
Programmable short-circuit protection
Simultaneous updating via ꢀDAC
Asynchronous CꢀR to zero code
Digital gain adjust
The AD5744 is a high performance converter that offers
guaranteed monotonicity, integral nonlinearity (INL) of 1 LꢃB,
low noise, and 1ꢂ μs settling timeꢀ During power-up (when the
supply voltages are changing), VOUT is clamped to ꢂ V via a
low impedance pathꢀ
ꢀogic output control pins
DSP-/microcontroller-compatible serial interface
Temperature range: −40°C to +85°C
iCMOS™ process technology1
The AD5744 uses a serial interface that operates at clock rates of
up to 3ꢂ MHz and is compatible with DꢃP and microcontroller
interface standardsꢀ Double buffering allows the simultaneous
updating of all DACsꢀ The input coding is programmable to
either twos complement or offset binary formatsꢀ The
asynchronous clear function clears all DAC registers to either
bipolar zero or zero scale depending on the coding usedꢀ The
AD5744 is ideal for both closed-loop servo control and open-
loop control applicationsꢀ The AD5744 is available in a 32-lead
TQFP, and offers guaranteed specifications over the −4ꢂ°C to
+85°C industrial temperature rangeꢀ ꢃee Figure 1, the functional
block diagramꢀ
APPꢀICATIONS
Industrial automation
Open-/closed-loop servo control
Process control
Data acquisition systems
Automatic test equipment
Automotive test and measurement
High accuracy instrumentation
Table 1. Related Devices
Part No.
Description
AD5744R
AD5744 with Internal voltage
reference
AD5764
Complete Quad, 16-Bit, High
Accuracy, Serial Input, Bipolar
Voltage Output DACs
AD5764R
AD5764 with internal voltage
reference
1 For analog systems designers within industrial/instrumentation equipment
OEMs who need high performance ICs at higher voltage levels, iCMOS is a
technology platform that enables the development of analog ICs capable of
30 V and operating at 15 V supplies while allowing dramatic reductions in
power consumption and package size, and increased AC and DC
performance.
Rev. PrE
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD5744
Preliminary Technical Data
TABLE OF CONTENTS
Features ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 1
Transfer Function ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 22
Applicationsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 1
General Descriptionꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 1
Revision History ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 2
Functional Block Diagram ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 3
ꢃpecificationsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 4
AC Performance Characteristicꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ ꢁ
Timing Characteristicsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 7
Absolute Maximum Ratingsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 1ꢂ
EꢃD Cautionꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 1ꢂ
Pin Configuration and Function Descriptionsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 11
Terminology ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 13
Typical Performance Characteristics ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 15
Theory of Operation ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 2ꢂ
DAC Architectureꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 2ꢂ
Reference Buffersꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 2ꢂ
ꢃerial Interface ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 2ꢂ
Asynchronous Clear (
)ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 22
CLR
Function Register ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 23
Data Registerꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 24
Coarse Gain Register ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 24
Fine Gain Registerꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 24
AD5744 Features ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 25
Analog Output Control ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 25
Programmable ꢃhort-Circuit Protection ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 25
Digital I/O Portꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 25
Local Ground Offset Adjustꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 25
Applications Informationꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 2ꢁ
Typical Operating Circuit ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 2ꢁ
Layout Guidelinesꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 27
Galvanically Isolated Interface ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 27
Microprocessor Interfacingꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 27
Outline Dimensionsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 3ꢂ
Ordering Guide ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 3ꢂ
ꢃimultaneous Updating via
ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 21
LDAC
REVISION HISTORY
3/06—Revision PrE
Removed AD5744R, AD57ꢁ4, and AD57ꢁ4RꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀUniversal
Changes to Ordering Guide ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 3ꢂ
Rev. PrE | Page 2 of 32
Preliminary Technical Data
FUNCTIONAL BLOCK DIAGRAM
AD5744
AV
AV
AV
AV
SS
RSTOUT
RSTIN
PGND
REFGND
REFAB
DD
SS
DD
VOLTAGE
MONITOR
AND
DV
CC
REFERENCE
BUFFERS
AD5744
CONTROL
DGND
ISCC
14
14
G1
G1
G1
G1
INPUT
REG A
DAC
REG A
DAC A
DAC B
DAC C
DAC D
SDIN
SCLK
SYNC
SDO
VOUTA
AGNDA
INPUT
SHIFT
G2
REGISTER
AND
GAIN REG A
CONTROL
LOGIC
OFFSET REG A
14
14
14
INPUT
REG B
DAC
REG B
VOUTB
AGNDB
G2
G2
G2
GAIN REG B
OFFSET REG B
D0
D1
INPUT
REG C
DAC
REG C
VOUTC
AGNDC
GAIN REG C
OFFSET REG C
BIN/2sCOMP
INPUT
REG D
DAC
REG D
VOUTD
AGNDD
GAIN REG D
CLR
OFFSET REG D
REFERENCE
BUFFERS
LDAC
REFCD
Figure 1. Functional Block Diagram
Rev. PrE | Page 3 of 32
AD5744
Preliminary Technical Data
SPECIFICATIONS
AVDD = 11ꢀ4 V to 1ꢁꢀ5 V, AVꢃꢃ = −11ꢀ4 V to −1ꢁꢀ5 V, AGND = DGND = REFGND = PGND = ꢂ V; REFAB = REFCD = 5 V;
DVCC = 2ꢀ7 V to 5ꢀ25 V, RLOAD = 1ꢂ kΩ, CL = 2ꢂꢂ pFꢀ All specifications TMIN to TMAX, unless otherwise notedꢀ
Table 2.
Parameter
B Grade2
C Grade2
Unit
Test Conditions/Comments
ACCURACY
Outputs unloaded
Resolution
14
2
1
14
1
1
Bits
Relative Accuracy (INL)
Differential Nonlinearity
Bipolar Zero Error
LSB max
LSB max
mV max
Guaranteed monotonic
2
2
At 25°C; error at other
temperatures obtained using
bipolar zero TC
Bipolar Zero TC3
Zero-Scale Error
2
2
2
2
ppm FSR/°C max
mV max
At 25°C; error at other
temperatures obtained using
zero scale TC
Zero-Scale TC3
Gain Error
2
0.02
2
0.02
ppm FSR/°C max
% FSR max
At 25°C; error at other
temperatures obtained using
gain TC
Gain TC3
DC Crosstalk3
2
2
ppm FSR/°C max
LSB max
0.125
0.125
REFERENCE INPUT3
Reference Input Voltage
DC Input Impedance
Input Current
5
1
10
1/7
5
1
10
1/7
V nominal
MΩ min
μA max
1% for specified performance
Typically 100 MΩ
Typically 30 nA
Reference Range
V min/V max
OUTPUT CHARACTERISTICS3
Output Voltage Range4
10.5263
14
10.5263
14
V min/V max
V min/V max
AVDD/AVSS = 11.4 V, REFIN = 5V
AVDD/AVSS = 16.5 V, REFIN = 7V
Output Voltage Drift vs. Time
13
13
ppm FSR/500 hours
typ
15
15
ppm FSR/1000 hours
typ
Short Circuit Current
Load Current
10
1
10
1
mA typ
mA max
RISCC = 6 kΩ, see Figure 31
For specified performance
Capacitive Load Stability
RL = ∞
RL = 10 kΩ
200
1000
0.3
200
1000
0.3
pF max
pF max
Ω max
DC Output Impedance
Rev. PrE | Page 4 of 32
Preliminary Technical Data
AD5744
Parameter
DIGITAL INPUTS3
B Grade2
C Grade2
Unit
Test Conditions/Comments
DVCC = 2.7 V to 5.25 V, JEDEC
compliant
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
2
0.8
1
2
0.8
1
V min
V max
μA max
pF max
Per pin
Per pin
Pin Capacitance
10
10
DIGITAL OUTPUTS (D0, D1, SDO)3
Output Low Voltage
Output High Voltage
Output Low Voltage
0.4
DVCC − 1
0.4
0.4
DVCC − 1
0.4
V max
V min
V max
DVCC = 5 V 5%, sinking 200 μA
DVCC = 5 V 5%, sourcing 200 μA
DVCC = 2.7 V to 3.6 V,
sinking 200 μA
Output High Voltage
DVCC − 0.5
DVCC − 0.5
V min
DVCC = 2.7 V to 3.6 V,
sourcing 200 μA
High Impedance Leakage
Current
High Impedance Output
Capacitance
1
5
1
5
μA max
pF typ
SDO only
SDO only
POWER REQUIREMENTS
AVDD/AVSS
DVCC
Power Supply Sensitivity3
11.4/16.5
2.7/5.25
11.4/16.5
2.7/5.25
V min/V max
V min/V max
∆VOUT/∆ΑVDD
AIDD
AISS
DICC
−85
3.5
2.75
1.2
−85
3.5
2.75
1.2
dB typ
mA/channel max
mA/channel max
mA max
Outputs unloaded
Outputs unloaded
VIH = DVCC, VIL = DGND, 750 μA typ
12 V operation output unloaded
Power Dissipation
275
275
mW typ
2 Temperature range: -40°C to +85°C; typical at +25°C. Device functionality is guaranteed to +105°C with degraded performance.
3 Guaranteed by design and characterization; not production tested.
4 Output amplifier headroom requirement is 1.4 V minimum.
Rev. PrE | Page 5 of 32
AD5744
Preliminary Technical Data
AC PERFORMANCE CHARACTERISTIC
AVDD = 11ꢀ4 V to 1ꢁꢀ5 V, AVꢃꢃ = −11ꢀ4 V to −1ꢁꢀ5 V, AGND = DGND = REFGND = PGND = ꢂ V; REFAB = REFCD = 5 V;
DVCC = 2ꢀ7 V to 5ꢀ25 V, RLOAD = 1ꢂ kΩ, CL = 2ꢂꢂ pFꢀ All specifications TMIN to TMAX, unless otherwise notedꢀ Guaranteed by design and
characterization, not production testedꢀ
Table 3.
Parameter
B Grade C Grade Unit
Test Conditions/Comments
Full-scale step to 1 LSB
512 LSB step settling
DYNAMIC PERFORMANCE1
Output Voltage Settling Time
8
8
μs typ
10
2
10
2
μs max
μs typ
Slew Rate
5
8
25
80
8
5
8
25
80
8
V/μs typ
nV-s typ
mV max
dB typ
nV-s typ
nV-s typ
nV-s typ
Digital-to-Analog Glitch Energy
Glitch Impulse Peak Amplitude
Channel-to-Channel Isolation
DAC-to-DAC Crosstalk
Digital Crosstalk
2
2
2
2
Digital Feedthrough
Effect of input bus activity on DAC
outputs
Output Noise (0.1 Hz to 10 Hz)
Output Noise (0.1 Hz to 100 kHz)
1/f Corner Frequency
0.025
45
1
0.025
45
1
LSB p-p typ
μV rms max
kHz typ
Output Noise Spectral Density
60
60
nV/√Hz typ
nV/√Hz typ
Measured at 10 kHz
Measured at 10 kHz
Complete System Output Noise Spectral
Density2
80
80
1 Guaranteed by design and characterization; not production tested.
2 Includes noise contributions from integrated reference buffers, 14-bit DAC and output amplifier.
Rev. PrE | Page 6 of 32
Preliminary Technical Data
TIMING CHARACTERISTICS
AD5744
AVDD = 11ꢀ4 V to 1ꢁꢀ5 V, AVꢃꢃ = −11ꢀ4 V to −1ꢁꢀ5 V, AGND = DGND = REFGND = PGND = ꢂ V; REFAB = REFCD = 5 V;
DVCC = 2ꢀ7 V to 5ꢀ25 V, RLOAD = 1ꢂ kΩ, CL = 2ꢂꢂ pFꢀ All specifications TMIN to TMAX, unless otherwise notedꢀ
Table 4.
Parameter1, 2, 3
ꢀimit at TMIN, TMAX
Unit
Description
t1
t2
t3
t4
33
13
13
13
13
40
2
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs min
ns min
ns min
ns max
μs max
ns min
μs max
ns max
ns min
μs min
ns min
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24th SCLK falling edge to SYNC rising edge
Minimum SYNC high time
Data setup time
4
t5
t6
t7
t8
t9
5
Data hold time
1.4
400
10
500
10
10
2
SYNC rising edge to LDAC falling edge (all DACs updated)
SYNC rising edge to LDAC falling edge (single DAC updated)
LDAC pulse width low
t10
t11
t12
t13
t14
LDAC falling edge to DAC output response time
DAC output settling time
CLR pulse width low
CLR pulse activation time
5, 6
t15
25
20
2
SCLK rising edge to SDO valid
t16
t17
t18
SYNC rising edge to SCLK rising edge
SYNC rising edge to DAC output response time (LDAC = 0)
LDAC falling edge to SYNC rising edge
170
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
3 See Figure 2, Figure 3, and Figure 4.
4 Standalone mode only.
5 Measured with the load circuit of Figure 5.
6 Daisy-chain mode only.
Rev. PrE | Page 7 of 32
AD5744
Preliminary Technical Data
t1
SCLK
SYNC
1
2
24
t3
t2
t6
t4
t5
t8
t7
DB23
SDIN
DB0
t10
t10
t9
LDAC
t18
t12
t11
VOUT
LDAC = 0
t12
t17
VOUT
CLR
t13
t14
VOUT
Figure 2. Serial Interface Timing Diagram
t1
SCLK
24
48
t3
t2
t6
t5
t16
t4
SYNC
SDIN
t8
t7
DB23
DB0
DB23
DB0
INPUT WORD FOR DAC N
INPUT WORD FOR DAC N–1
t15
DB23
DB0
SDO
t9
UNDEFINED
INPUT WORD FOR DAC N
t10
LDAC
Figure 3. Daisy Chain Timing Diagram
Rev. PrE | Page 8 of 32
Preliminary Technical Data
AD5744
SCLK
24
48
SYNC
DB23
DB0
DB23
DB0
SDIN
SDO
NOP CONDITION
INPUT WORD SPECIFIES
REGISTER TO BE READ
DB23
DB0
UNDEFINED
SELECTED REGISTER DATA
CLOCKED OUT
Figure 4. Readback Timing Diagram
200µA
I
OL
V
V
(MIN) OR
(MAX)
TO OUTPUT
PIN
OH
OL
C
L
50pF
200µA
I
OH
Figure 5. Load Circuit for SDO Timing Diagram
Rev. PrE | Page 9 of 32
AD5744
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise notedꢀ Transient currents of up to
1ꢂꢂ mA do not cause ꢃCR latch-upꢀ
ꢃtresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the deviceꢀ This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not impliedꢀ Exposure to absolute
maximum rating conditions for extended periods may affect
device reliabilityꢀ
Table 5.
Parameter
Rating
AVDD to AGND, DGND
AVSS to AGND, DGND
DVCC to DGND
−0.3 V to +17 V
+0.3 V to −17 V
−0.3 V to +7 V
Digital Inputs to DGND
−0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
Digital Outputs to DGND
REFIN to AGND, PGND
REFOUT to AGND
TEMP
−0.3 V to DVCC + 0.3 V
−0.3 V to AVDD + 0.3V
AVSS to AVDD
AVSS to AVDD
VOUTA, VOUTB, VOUTC, VOUTD to
AGND
AVSS to AVDD
AGND to DGND
−0.3 V to +0.3 V
Operating Temperature Range
Industrial
Storage Temperature Range
Junction Temperature (TJ max)
32-Lead TQFP
−40°C to +85°C
−65°C to +150°C
150°C
θJA Thermal Impedance
θJC Thermal Impedance
Reflow Soldering
65°C/W
12°C/W
Peak Temperature
220°C
Time at Peak Temperature
10 sec to 40 sec
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrE | Page 10 of 32
Preliminary Technical Data
AD5744
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
AGNDA
23 VOUTA
22
SYNC
PIN 1
SCLK
SDIN
SDO
VOUTB
AD5744
TOP VIEW
(Not to Scale)
21 AGNDB
20 AGNDC
19 VOUTC
18 VOUTD
CLR
LDAC
D0
AGNDD
17
D1
9
10 11 12 13 14 15 16
NC = NO CONNECT
Figure 6. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
SYNC
Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low,
data is transferred in on the falling edge of SCLK.
2
SCLK
Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at
clock speeds up to 30 MHz.
3
4
51
SDIN
SDO
CLR1
LDAC
Serial Data Input. Data must be valid on the falling edge of SCLK.
Serial Data Output. Used to clock data from the serial register in daisy-chain or readback mode.
Negative Edge Triggered Input. Asserting this pin sets the DAC registers to 0x0000.
6
Load DAC. Logic input. This is used to update the DAC registers and consequently the analog outputs.
When tied permanently low, the addressed DAC register is updated on the rising edge of SYNC. If
LDAC is held high during the write cycle, the DAC input register is updated but the output update is
held off until the falling edge of LDAC. In this mode, all analog outputs can be updated
simultaneously on the falling edge of LDAC. The LDAC pin must not be left unconnected.
7, 8
D0, D1
D0 and D1 form a digital I/O port. The user can set up these pins as inputs or outputs that are
configurable and readable over the serial interface. When configured as inputs, these pins have weak
internal pull-ups to DVCC. When programmed as outputs, D0 and D1 are referenced by DVCC and
DGND.
9
RSTOUT
RSTIN
Reset Logic Output. This is the output from the on-chip voltage monitor used in the reset circuit. If
desired, it can be used to control other system components.
Reset Logic Input. This input allows external access to the internal reset logic. Applying a Logic 0 to
this input clamps the DAC outputs to 0 V. In normal operation, RSTIN should be tied to Logic 1.
Register values remain unchanged.
10
11
12
13, 31
14
15, 30
16
DGND
DVCC
AVDD
PGND
AVSS
Digital Ground Pin.
Digital Supply Pin. Voltage ranges from 2.7 V to 5.25 V.
Positive Analog Supply Pins. Voltage ranges from 11.4 V to 16.5 V.
Ground Reference Point for Analog Circuitry.
Negative Analog Supply Pins. Voltage ranges from –11.4 V to –16.5 V.
This pin is used in association with an optional external resistor to AGND to program the short-circuit
current of the output amplifiers. Refer to the Features section for further details.
ISCC
17
18
AGNDD
VOUTD
Ground Reference Pin for DAC D Output Amplifier.
Analog Output Voltage of DAC D. Buffered output with a nominal full-scale output range of 10 V. The
output amplifier is capable of directly driving a 10 kΩ, 200 pF load.
19
20
VOUTC
AGNDC
Analog Output Voltage of DAC C. Buffered output with a nominal full-scale output range of 10 V. The
output amplifier is capable of directly driving a 10 kΩ, 200 pF load.
Ground Reference Pin for DAC C Output Amplifier.
Rev. PrE | Page 11 of 32
AD5744
Preliminary Technical Data
Pin No.
21
Mnemonic
AGNDB
Description
Ground Reference Pin for DAC B Output Amplifier.
22
VOUTB
Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output range of 10 V. The
output amplifier is capable of directly driving a 10 kΩ, 200 pF load.
23
VOUTA
Analog Output Voltage of DAC A. Buffered output with a nominal full-scale output range of 10 V. The
output amplifier is capable of directly driving a 10 kΩ, 200 pF load.
24
25
AGNDA
REFAB
Ground Reference Pin for DAC A Output Amplifier.
External Reference Voltage Input for Channel A and Channel B. Reference input range is 1 V to 7 V;
programs the full-scale output voltage. REFIN = 5 V for specified performance.
26
REFCD
External Reference Voltage Input for Channel C and Channel D. Reference input range is 1 V to 7 V;
programs the full-scale output voltage. REFIN = 5 V for specified performance.
27
28
29
32
NC
REFGND
NC
No Connect.
Reference Ground Return for the Reference Generator and Buffers.
No Connect.
Determines the DAC Coding. This pin should be hardwired to either DVCC or DGND. When hardwired to
DVCC, input coding is offset binary. When hardwired to DGND, input coding is twos complement (see
Table 7).
BIN/2sCOMP
1 Internal pull-up device on this logic input. Therefore, it can be left floating and defaults to a logic high condition.
Rev. PrE | Page 12 of 32
Preliminary Technical Data
TERMINOLOGY
AD5744
Relative Accuracy or Integral nonlinearity (INL)
Gain Error
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LꢃBs, from a straight
line passing through the endpoints of the DAC transfer
functionꢀ A typical INL vsꢀ code plot can be seen in Figure 7ꢀ
Gain error is a measure of the span error of the DACꢀ It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percentage of the full-scale rangeꢀ A plot of
gain error vsꢀ temperature can be seen in Figure 23ꢀ
Differential Nonlinearity (DNL)
Total Unadjusted Error
Differential nonlinearity is the difference between the measured
change and the ideal 1 LꢃB change between any two adjacent
codesꢀ A specified differential nonlinearity of 1 LꢃB maximum
ensures monotonicityꢀ This DAC is guaranteed monotonicꢀ A
typical DNL vsꢀ code plot can be seen in Figure 9ꢀ
Total unadjusted error (TUE) is a measure of the output error
considering all the various errorsꢀ A plot of total unadjusted
error vsꢀ reference can be seen in Figure 19ꢀ
Zero-Scale Error TC
Zero-scale error TC is a measure of the change in zero-scale
error with a change in temperatureꢀ Zero-scale error TC is
expressed in ppm FꢃR/°Cꢀ
Monotonicity
A DAC is monotonic if the output either increases or remains
constant for increasing digital input codeꢀ The AD5744 is
monotonic over its full operating temperature rangeꢀ
Gain Error TC
Gain error TC is a measure of the change in gain error with
changes in temperatureꢀ Gain Error TC is expressed in
(ppm of FꢃR)/°Cꢀ
Bipolar Zero Error
Bipolar zero error is the deviation of the analog output from the
ideal half-scale output of ꢂ V when the DAC register is loaded
with ꢂx8ꢂꢂꢂ (offset binary coding) or ꢂxꢂꢂꢂꢂ (twos
complement coding)ꢀ A plot of bipolar zero error vsꢀ
temperature can be seen in Figure 22ꢀ
Digital-to-Analog Glitch Energy
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
stateꢀ It is normally specified as the area of the glitch in nV secs
and is measured when the digital input code is changed by 1
LꢃB at the major carry transition (ꢂx7FFF to ꢂx8ꢂꢂꢂ) (see
Figure 28)ꢀ
Bipolar Zero TC
Bipolar zero TC is the measure of the change in the bipolar zero
error with a change in temperatureꢀ It is expressed in ppm
FꢃR/°Cꢀ
Digital Feedthrough
Full-Scale Error
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC but is measured when the DAC output is not updatedꢀ It is
specified in nV secs and measured with a full-scale code change
on the data bus, that is, from all ꢂs to all 1s and vice versaꢀ
Full-scale error is a measure of the output error when full-scale
code is loaded to the DAC registerꢀ Ideally the output voltage
should be 2 × VREF − 1 LꢃBꢀ Full-scale error is expressed in
percentage of full-scale rangeꢀ
Negative Full-Scale Error/Zero Scale Error
Power Supply Sensitivity
Negative full-scale error is the error in the DAC output voltage
when ꢂxꢂꢂꢂꢂ (offset binary coding) or ꢂx8ꢂꢂꢂ (twos
complement coding) is loaded to the DAC registerꢀ Ideally, the
output voltage should be −2 × VREFꢀ A plot of zero-scale error vsꢀ
temperature can be seen in Figure 21ꢀ
Power supply sensitivity indicates how the output of the DAC is
affected by changes in the power supply voltageꢀ
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DACꢀ It is
measured with a full-scale output change on one DAC while
monitoring another DAC, and is expressed in LꢃBsꢀ
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output to settle to a specified level for a full-scale input
changeꢀ
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
output change of another DACꢀ This includes both digital and
analog crosstalkꢀ It is measured by loading one of the DACs
with a full-scale code change (all ꢂs to all 1s and vice versa) with
Slew Rate
The slew rate of a device is a limitation in the rate of change of
the output voltageꢀ The output slewing speed of a voltage-output
D/A converter is usually limited by the slew rate of the amplifier
used at its outputꢀ ꢃlew rate is measured from 1ꢂ% to 9ꢂ% of the
output signal and is given in V/μsꢀ
low and monitoring the output of another DACꢀ The
LDAC
energy of the glitch is expressed in nV-sꢀ
Rev. PrE | Page 13 of 32
AD5744
Preliminary Technical Data
Channel-to-Channel Isolation
Digital Crosstalk
Channel-to-channel isolation is the ratio of the amplitude of the
signal at the output of one DAC to a sine wave on the reference
input of another DACꢀ It is measured in dBꢀ
Digital crosstalk is a measure of the impulse injected into the
analog output of one DAC from the digital inputs of another
DAC but is measured when the DAC output is not updatedꢀ It is
specified in nV secs and measured with a full-scale code change
on the data bus, that is, from all ꢂs to all 1s and vice versaꢀ
Rev. PrE | Page 14 of 32
Preliminary Technical Data
AD5744
TYPICAL PERFORMANCE CHARACTERISTICS
0.25
0.25
0.20
0.15
0.10
0.05
0
T
= 25°C
A
T
= 25°C
A
V
/V = ±15V
0.20
DD SS
V
/V = ±12V
DD SS
REFIN = 5V
REFIN = 5V
0.15
0.10
0.05
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.05
–0.10
–0.15
–0.20
–0.25
0
0
0
2000 4000 6000 8000 1000 12000 14000 16000
CODE
0
2000 4000 6000 8000 1000 12000 14000 16000
CODE
Figure 7. Integral Nonlinearity Error vs. Code,
Figure 10. Differential Nonlinearity Error vs. Code,
VDD/VSS
=
15 V
VDD/VSS
=
12 V
0.25
0.20
0.15
0.10
0.05
0
0.12
0.10
0.08
0.06
0.04
0.02
0
T
= 25°C
A
V
/V = ±12V
DD SS
REFIN = 5V
–0.05
–0.10
–0.15
–0.20
–0.25
–0.02
–0.04
2000 4000 6000 8000 1000 12000 14000 16000
CODE
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 8. Integral Nonlinearity Error vs. Code,
Figure 11. Integral Nonlinearity Error vs. Temperature,
V
DD/VSS = 12 V
VDD/VSS
=
15 V
0.25
0.20
0.15
0.10
0.05
0
0.12
0.10
0.08
0.06
0.04
0.02
0
T
= 25°C
A
V
/V = ±15V
DD SS
REFIN = 5V
–0.05
–0.10
–0.15
–0.20
–0.25
–0.02
–0.04
2000 4000 6000 8000 1000 12000 14000 16000
CODE
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 9. Differential Nonlinearity Error vs. Code,
Figure 12. Integral Nonlinearity Error vs. Temperature,
VDD/VSS 12 V
V
DD/VSS = 15 V
=
Rev. PrE | Page 15 of 32
AD5744
Preliminary Technical Data
0.04
0.03
0.02
0.03
0.02
0.01
0.01
0
0
–0.01
–0.02
–0.02
–0.04
–0.05
–0.06
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–40
–20
0
20
40
60
80
100
11.4
12.4
13.4
14.4
15.4
16.4
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
Figure 13. Differential Nonlinearity Error vs. Temperature,
Figure 16. Differential Nonlinearity Error vs. Supply Voltage
VDD/VSS
=
15 V
0.04
0.03
0.20
0.15
0.10
0.02
0.01
0.05
0
0
–0.01
–0.02
–0.03
–0.04
–0.05
–0.06
–0.05
–0.10
–0.15
–0.20
–0.25
–40
–20
0
20
40
60
80
100
1
2
3
4
5
6
7
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
Figure 14. Differential Nonlinearity Error vs. Temperature,
Figure 17. Integral Nonlinearity Error vs. Reference Voltage
VDD/VSS
= 12 V
0.12
–0.10
–0.08
–0.06
–0.04
–0.02
0
0.10
0.08
0.06
0.04
0.02
0
–0.02
–0.04
–0.06
–0.08
–0.10
–0.02
–0.04
11.4
12.4
13.4
14.4
15.4
16.4
1
2
3
4
5
6
7
SUPPLY VOLTAGE (V)
REFERENCE VOLTAGE (V)
Figure 15. Integral Nonlinearity Error vs. Supply Voltage
Figure 18. Differential Nonlinearity Error vs. Reference Voltage
Rev. PrE | Page 16 of 32
Preliminary Technical Data
AD5744
0.6
0.8
0.6
0.4
0.2
0
T
= 25°C
A
REFIN = 5V
0.4
0.2
V
/V = ±15V
DD SS
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
–1.4
–1.6
V
/V = ±12V
DD SS
–0.2
–0.4
1
2
3
4
5
6
7
–40
–20
0
20
40
60
80
100
REFERENCE VOLTAGE (V)
TEMPERATURE (°C)
Figure 19. Total Unadjusted Error vs. Reference Voltage,
Figure 22. Bipolar Zero Error vs. Temperature
VDD/VSS
= 16.5 V
14
13
12
11
10
9
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
T
= 25°C
REFIN = 5V
A
REFIN = 5V
|I
DD
|
V
/V = ±12V
DD SS
V
/V = ±15V
DD SS
|I
SS
|
8
11.4
–0.2
–40
12.4
13.4
V
14.4
/V (V)
15.4
16.4
–20
0
20
40
60
80
100
TEMPERATURE (°C)
DD SS
Figure 23. Gain Error vs. Temperature
Figure 20. IDD/ISS vs. VDD/VSS
0.0014
0.0013
0.0012
0.0011
0.0010
0.0009
0.0008
0.0007
0.0006
0.25
0.20
0.15
0.10
0.05
0
T
= 25°C
REFIN = 5V
A
V
/V = ±15V
DD SS
5V
V
/V = ±12V
DD SS
–0.05
–0.10
–0.15
–0.20
–0.25
3V
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
–40
–20
0
20
40
60
80
100
V
TEMPERATURE (°C)
LOGIC
Figure 21. Zero-Scale Error vs. Temperature
Figure 24. DICC vs. Logic Input Voltage
Rev. PrE | Page 17 of 32
AD5744
Preliminary Technical Data
7000
6000
5000
4000
3000
2000
1000
0
–4
–6
T
= 25°C
A
REFIN = 5V
V
/V = ±15V
DD SS
–8
–10
–12
–14
–16
–18
–20
–22
–24
–26
V
/V = ±12V
DD SS
V
/V = ±12V,
DD SS
REFIN = 5V,
= 25°C,
T
A
0x8000 TO 0x7FFF,
500ns/DIV
–1000
–10
–5
0
5
10
–2.0–1.5–1.0–0.5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
TIME (µs)
SOURCE/SINK CURRENT (mA)
Figure 25. Source and Sink Capability of Output Amplifier with Positive
Full Scale Loaded
Figure 28. Major Code Transition Glitch Energy, VDD/VSS = 12 V
10000
T
= 25°C
V
/V = ±15V
DD SS
A
REFIN = 5V
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
MIDSCALE LOADED
REFIN = 0V
15V SUPPLIES
12V SUPPLIES
4
50µV/DIV
CH4
–1000
–12
–7
–2
3
8
CH4 50.0µV
M1.00s
26µV
SOURCE/SINK CURRENT (mA)
Figure 26. Source and Sink Capability of Output Amplifier with Negative
Full Scale Loaded
Figure 29. Peak-to-Peak Noise (100 kHz Bandwidth)
V
/V = ±12V,
DD SS
T
V
/V = ±15V
= 25°C
DD SS
REFIN = 5V, T = 25°C,
RAMP TIME = 100µs,
LOAD = 200pF||10kΩ
A
T
A
REFIN = 5V
1
2
3
1
1µs/DIV
CH1 –120mV
B
CH1 10.0V
CH2 10.0V
M100µs A CH1
29.60%
7.80mV
CH1 3.00V
M1.00µs
W
B
CH3 10.0mV
T
W
Figure 30. VOUT vs. VDD/VSS on Power-Up
Figure 27. Full-Scale Settling Time
Rev. PrE | Page 18 of 32
Preliminary Technical Data
AD5744
10
9
8
7
6
5
4
3
2
1
0
V
/V = ±15V
= 25°C
DD SS
T
A
REFIN = 5V
0
20
40
60
(kΩ)
80
100
120
RI
SCC
Figure 31. Short-Circuit Current vs. RISCC
Rev. PrE | Page 19 of 32
AD5744
Preliminary Technical Data
THEORY OF OPERATION
The AD5744 is a quad, 14-bit, serial input, bipolar voltage output
DAC and operates from supply voltages of 11ꢀ4 V to 1ꢁꢀ5 V and
has a buffered output voltage of up to 1ꢂꢀ52ꢁ3 ꢀ Data is written to
the AD5744 in a 24-bit word format, via a 3-wire serial interfaceꢀ
The device also offers an ꢃDO pin, which is available for daisy
chaining or readbackꢀ
SERIAꢀ INTERFACE
The AD5744 is controlled over a versatile 3-wire serial interface
that operates at clock rates of up to 3ꢂ MHz and is compatible
with ꢃPI®, QꢃPI™, MICROWIRE™, and DꢃP standardsꢀ
Input Shift Register
The input shift register is 24 bits wideꢀ Data is loaded into the
device MꢃB first as a 24-bit word under the control of a serial
clock input, ꢃCLKꢀ The input register consists of a read/write
bit, three register select bits, three DAC address bits and 1ꢁ data
bits as shown in Table 8ꢀ The timing diagram for this operation
is shown in Figure 2ꢀ
The AD5744 incorporates a power-on reset circuit, which
ensures that the DAC registers power up loaded with ꢂxꢂꢂꢂꢂꢀ
The AD5744 features a digital I/O port that can be programmed
via the serial interface, on-chip reference buffers and per
channel digital gain registersꢀ
DAC ARCHITECTURE
Upon power-up, the DAC registers are loaded with zero code
(ꢂxꢂꢂꢂꢂ) and the outputs are clamped to ꢂ V via a low
impedance pathꢀ The outputs can be updated with the zero code
The DAC architecture of the AD5744 consists of a
14-bit current mode segmented R-2R DACꢀ The simplified
circuit diagram for the DAC section is shown in Figure 32ꢀ
value at this time by asserting either
or ꢀ The
LDAC CLR
corresponding output voltage depends on the state of the
BIN/ pinꢀ If the BIN/ pin is tied to DGND,
The four MꢃBs of the 14-bit data word are decoded to drive 15
switches, E1 to E15ꢀ Each of these switches connects one of the
15 matched resistors to either AGND or IOUTꢀ The remaining
1ꢂ bits of the data word drive switches ꢃꢂ to ꢃ9 of the 1ꢂ-bit R-
2R ladder networkꢀ
2sCOMP
then the data coding is twos complement and the outputs
update to ꢂ ꢀ If the BIN/ pin is tied to DVCC, then the
2sCOMP
2sCOMP
data coding is offset binary and the outputs update to negative
full scaleꢀ To have the outputs power-up with zero code loaded
R
R
R
V
REF
to the outputs, the
pin should be held low during power-
CLR
upꢀ
2R
2R
2R
2R
2R
2R
2R
Standalone Operation
R/8
E15
E14
E1
S0
S9
S8
The serial interface works with both a continuous and noncon-
tinuous serial clockꢀ A continuous ꢃCLK source can only be
I
OUT
used if
is held low for the correct number of clock cyclesꢀ
ꢃYNC
In gated clock mode, a burst clock containing the exact number
of clock cycles must be used and must be taken high after
V
OUT
AGND
4 MSBs DECODED INTO
15 EQUAL SEGMENTS
10-BIT, R-2R LADDER
ꢃYNC
the final clock to latch the dataꢀ The first falling edge of
Figure 32. DAC Ladder Structure
ꢃYNC
starts the write cycleꢀ Exactly 24 falling clock edges must be
applied to ꢃCLK before is brought back high againꢀ If
REFERENCE BUFFERS
ꢃYNC
is brought high before the 24th falling ꢃCLK edge, then
The AD5744 operates with an external referenceꢀ The reference
inputs (REFAB and REFCD) have an input range up to 7 ꢀ This
input voltage is then used to provide a buffered positive and
negative reference for the DAC coresꢀ The positive reference is
given by
ꢃYNC
the data written is invalidꢀ If more than 24 falling ꢃCLK edges
are applied before is brought high, then the input data is
ꢃYNC
also invalidꢀ The register addressed is updated on the rising
edge of
ꢃYNC
ꢀ In order for another serial transfer to take place,
must be brought low againꢀ After the end of the serial
ꢃYNC
+ VREF = 2 × VREF
While the negative reference to the DAC cores is given by
−VREF = −2 × VREF
data transfer, data is automatically transferred from the input
shift register to the addressed registerꢀ
When the data has been transferred into the chosen register of
the addressed DAC, all DAC registers and outputs can be
These positive and negative reference voltages (along with the
gain register values) define the output ranges of the DACsꢀ
updated by taking
lowꢀ
LDAC
Rev. PrE | Page 20 of 32
Preliminary Technical Data
AD5744
1
AD57441
68HC11
A continuous ꢃCLK source can only be used if
is held
ꢃYNC
MOSI
SCK
PC7
low for the correct number of clock cyclesꢀ In gated clock mode,
a burst clock containing the exact number of clock cycles must
SDIN
SCLK
SYNC
LDAC
be used and
must be taken high after the final clock to
ꢃYNC
latch the dataꢀ
PC6
MISO
SDO
Readback Operation
Before a readback operation is initiated, the ꢃDO pin must be
enabled by writing to the function register and clearing the
ꢃDO DIꢃABLE bit; this bit is cleared by defaultꢀ Readback mode
SDIN
AD57441
SCLK
is invoked by setting the R/ bit = 1 in the serial input register
W
SYNC
LDAC
writeꢀWith R/ = 1, Bit A2 to Bit Aꢂ, in association with Bit
W
REG2, Bit REG1, and Bit REGꢂ, select the register to be readꢀ
The remaining data bits in the write sequence are don’t careꢀ
During the next ꢃPI write, the data appearing on the ꢃDO
output contain the data from the previously addressed registerꢀ
For a read of a single register, the NOP command can be used in
clocking out the data from the selected register on ꢃDOꢀ The
readback diagram in Figure 4 shows the readback sequenceꢀ For
example, to read back the fine gain register of Channel A on the
AD5744, the following sequence should be implemented:
SDO
SDIN
AD57441
SCLK
SYNC
LDAC
SDO
1ꢀ Write ꢂxAꢂXXXX to the AD5744 input registerꢀ This
configures the AD5744 for read mode with the fine gain
register of Channel A selectedꢀ Note that all the data bits,
DB15 to DBꢂ, are don’t careꢀ
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 33. Daisy Chaining the AD5744
Daisy-Chain Operation
2ꢀ Follow this with a second write, a NOP condition,
ꢂxꢂꢂXXXXꢀ During this write, the data from the fine gain
register is clocked out on the ꢃDO line, that is, data clocked
out contains the data from the fine gain register in Bit DB5 to
Bit DBꢂꢀ
For systems that contain several devices, the ꢃDO pin can be
used to daisy chain several devices togetherꢀ This daisy-chain
mode can be useful in system diagnostics and in reducing the
number of serial interface linesꢀ The first falling edge of
ꢃYNC
starts the write cycleꢀ The ꢃCLK is continuously applied to the
input shift register when is lowꢀ If more than 24 clock
SIMUꢀTANEOUS UPDATING VIA
ꢀDAC
ꢃYNC
pulses are applied, the data ripples out of the shift register and
appears on the ꢃDO lineꢀ This data is clocked out on the rising
edge of ꢃCLK and is valid on the falling edgeꢀ By connecting the
ꢃDO of the first device to the ꢃDIN input of the next device in
the chain, a multidevice interface is constructedꢀ Each device in
the system requires 24 clock pulsesꢀ Therefore, the total number
of clock cycles must equal 24N, where N is the total number of
AD5744 devices in the chainꢀ When the serial transfer to all
Depending on the status of both
and
, and after
LDAC
ꢃYNC
data has been transferred into the input register of the DACs,
there are two ways in which the DAC registers and DAC
outputs can be updatedꢀ
Individual DAC Updating
In this mode,
is held low while data is being clocked into
LDAC
the input shift registerꢀ The addressed DAC output is updated
on the rising edge of
devices is complete,
is taken highꢀ This latches the input
ꢃYNC
ꢀ
ꢃYNC
Simultaneous Updating of All DACs
In this mode, is held high while data is being clocked
data in each device in the daisy chain and prevents any further
data from being clocked into the input shift registerꢀ The serial
clock can be a continuous or a gated clockꢀ
LDAC
into the input shift registerꢀ All DAC outputs are updated by
taking low any time after has been taken highꢀ
LDAC
ꢃYNC
The update now occurs on the falling edge of
ꢀ
LDAC
Rev. PrE | Page 21 of 32
AD5744
Preliminary Technical Data
OUTPUT
I/V AMPLIFIER
The output voltage expression for the AD5744 is given by
14-BIT
DAC
V
REFIN
V
OUT
D
⎡
⎤
VOUT = −2×VREFIN + 4×VREFIN
⎢
⎣
⎥
⎦
16384
DAC
REGISTER
LDAC
where:
D is the decimal equivalent of the code loaded to the DACꢀ
REFIN is the reference voltage applied at the REFAB/REFCD
INPUT
REGISTER
V
pinsꢀ
SCLK
SYNC
SDIN
INTERFACE
LOGIC
SDO
ASYNCHRONOUS CꢀEAR (
)
CꢀR
is a negative edge triggered clear that allows the outputs to
be cleared to either ꢂ V (twos complement coding) or negative
CLR
Figure 34. Simplified Serial Interface of Input Loading Circuitry
for One DAC Channel
full scale (offset binary coding)ꢀ It is necessary to maintain
low for a minimum amount of time (see Figure 3) for the
CLR
TRANSFER FUNCTION
Table 7 shows the ideal input code to output voltage
relationship for the AD5744 for both offset binary and twos
complement data codingꢀ
operation to completeꢀ When the
signal is returned high,
CLR
the output remains at the cleared value until a new value is
programmedꢀ If at power-on is at ꢂ V, then all DAC outputs
CLR
Table 7. Ideal Output Voltage to Input Code Relationship for
the AD5744
Digital Input
are updated with the clear valueꢀ A clear can also be initiated
through software by writing the command ꢂxꢂ4XXXX to the
AD5744ꢀ
Analog Output
Offset Binary Data Coding
MSB
ꢀSB VOUT
11
10
10
01
00
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
1111
0001
0000
1111
0000
+2 VREF × (8191/8192)
+2 VREF × (1/8192)
0 V
−2 VREF × (1/8192)
−2 VREF × (8191/8192)
Twos Complement Data Coding
MSB
ꢀSB VOUT
01
00
00
11
10
1111
0000
0000
1111
0000
1111
0000
0000
1111
0000
1111
0001
0000
1111
0000
+2 VREF × (8191/8192)
+2 VREF × (1/8192)
0 V
−2 VREF × (1/8192)
−2 VREF × (8191/8192)
Rev. PrE | Page 22 of 32
Preliminary Technical Data
AD5744
Table 8. AD5744 Input Register Format
MSB
LSB
DB23
DB22
0
DB21
REG2
DB20
REG1
DB19
REG0
DB18
A2
DB17
A1
DB16
A0
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
W
R/
DATA
Table 9. Input Register Bit Functions
Register
Function
R/W
Indicates a read from or a write to the addressed register.
REG2, REG1, REG0
Used in association with the address bits to determine if a read or write operation is to the data register, offset
register, gain register, or function register.
REG2
REG1
REG0
Function
0
0
0
1
0
1
1
0
0
0
1
0
Function Register
Data Register
Coarse Gain Register
Fine Gain Register
A2, A1, A0
These bits are used to decode the DAC channels.
A2
A1
0
A0
0
Channel Address
DAC A
0
0
0
1
DAC B
0
1
0
DAC C
0
1
1
DAC D
1
0
0
ALL DACs
D15:D0
Data Bits.
FUNCTION REGISTER
The function register is addressed by setting the three REG bits to ꢂꢂꢂꢀ The values written to the address bits and the data bits determine
the function addressedꢀ The functions available via the function register are outlined in Table 1ꢂ and Table 11ꢀ
Table 10. Function Register Options
REG2 REG1 REG0 A2 A1 A0
DB15:DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
0
0
0
0
0
0
0
0
0
0
1
NOP, Data = Don’t Care
Don’t Care
Local-
Ground-
Offset Adjust
D1 Direction D1
Value
D0
Direction
D0
Value
SDO
Disable
0
0
0
0
0
0
1
1
0
0
0
1
CLR, Data = Don’t Care
LOAD, Data = Don’t Care
Table 11. Explanation of Function Register Options
Option
Description
NOP
No operation instruction used in readback operations.
Local-Ground-
Offset Adjust
Set by the user to enable local-ground-offset adjust function. Cleared by the user to disable local-ground-offset adjust
function (default). Refer to Features section for further details.
D0/D1
Direction
Set by the user to enable D0/D1 as outputs. Cleared by the user to enable D0/D1 as inputs (default). Refer to the Features
section for further details.
D0/D1 Value
I/O Port Status Bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when
configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input. When
enabled as inputs, these bits are don’t cares during a write operation.
SDO Disable
CLR
LOAD
Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).
Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary mode.
Addressing this function updates the DAC registers and consequently the analog outputs.
Rev. PrE | Page 23 of 32
AD5744
Preliminary Technical Data
DATA REGISTER
The data register is addressed by setting the three REG bits to ꢂ1ꢂꢀ The DAC address bits select with which DAC channel the data transfer
is to take place (see Table 9)ꢀ The data bits are in positions DB15 to DB2 as shown in Table 12ꢀ
Table 12. Programming the AD5744 Data Register
REG2
REG1
REG0
A2
A1
A0
DB15
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
0
1
0
DAC Address
14-Bit DAC Data
X
X
COARSE GAIN REGISTER
The coarse gain register is addressed by setting the three REG bits to ꢂ11ꢀ The DAC address bits select with which DAC channel the data
transfer is to take place (see Table 9)ꢀ The coarse gain register is a 2-bit register and allows the user to select the output range of each DAC
as shown in Table 13 and Table 14ꢀ
Table 13. Programming the AD5744 Coarse Gain Register
REG2
REG1
REG0
A2
A1
A0
DB15 …. DB2
DB1
DB0
0
1
1
DAC Address
Don’t Care
CG1
CG0
Table 14. Output Range Selection
Output Range CG1 CG0
10 V (default)
10.2564 V
10.5263 V
0
0
1
0
1
0
FINE GAIN REGISTER
The fine gain register is addressed by setting the three REG bits to 1ꢂꢂꢀ The DAC address bits select with which DAC channel the data
transfer is to take place (see Table 9)ꢀ The fine gain register is a ꢁ-bit register and allows the user to adjust the gain of each DAC channel
by −8 LꢃBs to +7ꢀ75 LꢃBs in ꢂꢀ25 LꢃB steps as shown in Table 15 and Table 1ꢁꢀ The adjustment is made to both the positive full-scale
points and the negative full-scale points simultaneously, each point being adjusted by ½ of one stepꢀ The fine gain register coding is twos
complementꢀ
Table 15. Programming AD5744 Fine Gain Register
REG2
REG1
REG0
A2
A1
A0
DB15:DB6
DB5
DB4
DB3
DB2
DB1
DB0
1
0
0
DAC Address
Don’t Care
FG5
FG4
FG3
FG2
FG1
FG0
Table 16. AD5744 Fine Gain Register Options
Gain Adjustment
FG5
FG4
FG3
FG2
FG1
FG0
+7.75 LSBs
+7.5 LSBs
0
0
-
1
1
-
1
1
-
1
1
-
1
1
-
1
0
-
No Adjustment (default)
0
-
0
-
0
-
0
-
0
-
0
-
−7.75 LSBs
−8 LSBs
1
1
0
0
0
0
0
0
0
0
1
0
Rev. PrE | Page 24 of 32
Preliminary Technical Data
AD5744
AD5744 FEATURES
ANAꢀOG OUTPUT CONTROꢀ
If the IꢃCC pin is left unconnected, the short circuit current
limit defaults to 5 mAꢀ It should be noted that limiting the short
circuit current to a small value can affect the slew rate of the
output when driving into a capacitive load, therefore, the value
of short-circuit current programmed should take into account
the size of the capacitive load being drivenꢀ
In many industrial process control applications, it is vital that
the output voltage be controlled during power-up and during
brownout conditionsꢀWhen the supply voltages are changing,
the VOUT pins are clamped to ꢂ V via a low impedance pathꢀ
To prevent the output amp being shorted to ꢂ V during this
time, transmission gate G1 is also opened (see Figure 35)ꢀ These
conditions are maintained until the power supplies stabilize and
a valid word is written to the DAC registerꢀ At this time, G2
opens and G1 closesꢀ Both transmission gates are also externally
DIGITAꢀ I/O PORT
The AD5744 contains a 2-bit digital I/O port (D1 and Dꢂ),
these bits can be configured as inputs or outputs independently,
and can be driven or have their values read back via the serial
interfaceꢀ The I/O port signals are referenced to DVCC and
DGNDꢀWhen configured as outputs, they can be used as
control signals to multiplexers or can be used to control
calibration circuitry elsewhere in the systemꢀ When configured
as inputs, the logic signals from limit switches, for example can
be applied to Dꢂ and D1 and can be read back via the digital
interfaceꢀ
controllable via the Reset In (
) control inputꢀ For
RꢃTIN
instance, if
is driven from a battery supervisor chip, the
RꢃTIN
input is driven low to open G1 and close G2 on power-
RꢃTIN
off or during a brownoutꢀ Conversely, the on-chip voltage
detector output ( ) is also available to the user to
RꢃTOUT
control other parts of the systemꢀ The basic transmission gate
functionality is shown in Figure 35ꢀ
RSTOUT
RSTIN
ꢀOCAꢀ GROUND OFFSET ADJUST
The AD5744 incorporates a local-ground-offset adjust feature
which when enabled in the function register adjusts the DAC
outputs for voltage differences between the individual DAC
ground pins and the REFGND pin ensuring that the DAC
output voltages are always with respect to the local DAC ground
pinꢀ For instance, if pin AGNDA is at +5 mV with respect to the
REFGND pin and VOUTA is measured with respect to AGNDA
then a −5mV error results, enabling the local-ground-offset
adjust feature adjusts VOUTA by +5 mV, eliminating the errorꢀ
VOLTAGE
MONITOR
AND
CONTROL
G1
VOUTA
AGNDA
G2
Figure 35. Analog Output Control Circuitry
PROGRAMMABꢀE SHORT-CIRCUIT PROTECTION
The short-circuit current of the output amplifiers can be pro-
grammed by inserting an external resistor between the IꢃCC
pin and PGNDꢀ The programmable range for the current is
5ꢂꢂ μA to 1ꢂ mA, corresponding to a resistor range of 12ꢂ kΩ
to ꢁ kΩ ꢀ The resistor value is calculated as follows:
60
R =
Isc
Rev. PrE | Page 25 of 32
AD5744
Preliminary Technical Data
APPLICATIONS INFORMATION
TYPICAꢀ OPERATING CIRCUIT
Precision Voltage Reference Selection
To achieve the optimum performance from the AD5744 over its
full operating temperature range, a precision voltage reference
must be usedꢀ Thought should be given to the selection of a
precision voltage referenceꢀ The AD5744 has two reference
inputs, REFAB and REFCDꢀ The voltages applied to the
reference inputs are used to provide a buffered positive and
negative reference for the DAC coresꢀ Therefore, any error in the
voltage reference is reflected in the outputs of the deviceꢀ
Figure 3ꢁ shows the typical operating circuit for the AD5744ꢀ
The only external components needed for this precision 14-bit
DAC are a reference voltage source, decoupling capacitors on
the supply pins and reference inputs, and an optional short-
circuit current setting resistorꢀ Because the device incorporates
reference buffers, it eliminates the need for an external bipolar
reference and associated buffersꢀ This leads to an overall savings
in both cost and board spaceꢀ
There are four possible sources of error to consider when
choosing a voltage reference for high accuracy applications:
initial accuracy, temperature coefficient of the output voltage,
long term drift, and output voltage noiseꢀ
In Figure 3ꢁ, VDD and Vꢃꢃ are both connected to 15 V, but VDD
and Vꢃꢃ can operate with supplies from 11ꢀ4 V to 1ꢁꢀ5 ꢀ In
Figure 3ꢁ, AGNDA is connected to REFGNDꢀ
+15V
ADR02
2
6
VIN
VOUT
Initial accuracy error on the output voltage of an external refer-
ence could lead to a full-scale error in the DACꢀ Therefore, to
minimize these errors, a reference with low initial accuracy
error specification is preferredꢀ Choosing a reference with an
output trim adjustment, such as the ADR425, allows a system
designer to trim system errors out by setting the reference
voltage to a voltage other than the nominalꢀ The trim ad-
justment can also be used at temperature to trim out any errorꢀ
GND
4
+15V –15V
10µF
10µF
100nF
100nF
100nF
BIN/2sCOMP
32 31 30 29 28 27 26 25
+5V
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
SYNC
SCLK
SDIN
SDO
SYNC
AGNDA
VOUTA
VOUTB
AGNDB
AGNDC
VOUTC
VOUTD
AGNDD
Long term drift is a measure of how much the reference output
voltage drifts over timeꢀ A reference with a tight long-term drift
specification ensures that the overall solution remains relatively
stable over its entire lifetimeꢀ
SCLK
SDIN
SDO
CLR
LDAC
D0
VOUTA
VOUTB
AD5744
LDAC
D0
VOUTC
VOUTD
The temperature coefficient of a reference’s output voltage
affects INL, DNL, and TUEꢀ A reference with a tight
temperature coefficient specification should be chosen to
reduce the dependence of the DAC output voltage on ambient
conditionsꢀ
D1
D1
9
10 11 12 13 14 15 16
RSTOUT
RSTIN
10µF
100nF
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise needs to be consideredꢀ
Choosing a reference with as low an output noise voltage as
practical for the system resolution required is importantꢀ
Precision voltage references such as the ADR435 (XFET design)
produce low output noise in the ꢂꢀ1 Hz to 1ꢂ Hz regionꢀ
However, as the circuit bandwidth increases, filtering the output
of the reference may be required to minimize the output noiseꢀ
NC = NO CONNECT
10µF
+5V
+15V –15V
Figure 36. Typical Operating Circuit
Table 17. Some Precision References Recommended for Use with the AD5744
Part No. Initial Accuracy(mV Max) ꢀong-Term Drift (ppm Typ) Temp Drift (ppm/°C Max) 0.1 Hz to 10 Hz Noise (μV p-p Typ)
ADR435
ADR425
ADR02
ADR395
AD586
6
6
5
6
30
50
50
50
15
3
3
3
25
10
3.4
3.4
15
5
2.5
4
Rev. PrE | Page 26 of 32
Preliminary Technical Data
LAYOUT GUIDELINES
AD5744
1
ADuM1400
µCONTROLLER
In any circuit where accuracy is important, careful consider-
ation of the power supply and ground return layout helps to
ensure the rated performanceꢀ The printed circuit board on
which the AD5744 is mounted should be designed so that the
analog and digital sections are separated and confined to
certain areas of the boardꢀ If the AD5744 is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point onlyꢀ The star ground
point should be established as close as possible to the deviceꢀ
The AD5744 should have ample supply bypassing of 1ꢂ μF in
parallel with ꢂꢀ1 μF on each supply located as close to the
package as possible, ideally right up against the deviceꢀ The 1ꢂ
μF capacitors are the tantalum bead typeꢀ The ꢂꢀ1 μF capacitor
should have low effective series resistance (EꢃR) and low
effective series inductance (EꢃI) such as the common ceramic
types, which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switchingꢀ
V
V
V
V
V
V
V
V
IA
IB
IC
ID
OA
ENCODE
ENCODE
ENCODE
ENCODE
DECODE
DECODE
DECODE
DECODE
SERIAL CLOCK OUT
TO SCLK
OB
SERIAL DATA OUT
SYNC OUT
TO SDIN
OC
TO SYNC
OD
CONTROL OUT
TO LDAC
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 37. Isolated Interface
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5744 is via a serial bus
that uses standard protocol compatible with microcontrollers
and DꢃP processorsꢀ The communications channel is a 3-wire
(minimum) interface consisting of a clock signal, a data signal,
and a synchronization signalꢀ The AD5744 requires a 24-bit
data-word with data valid on the falling edge of ꢃCLKꢀ
The power supply lines of the AD5744 should use as large a
trace as possible to provide low impedance paths and reduce
the effects of glitches on the power supply lineꢀ Fast switching
signals, such as clocks, should be shielded with digital ground
to avoid radiating noise to other parts of the board, and should
never be run near the reference inputsꢀ A ground line routed
between the ꢃDIN and ꢃCLK lines helps reduce cross-talk
between them (not required on a multilayer board, which has a
separate ground plane, however, it is helpful to separate the
lines)ꢀ It is essential to minimize noise on the reference inputs,
because it couples through to the DAC outputꢀ Avoid crossover
of digital and analog signalsꢀ Traces on opposite sides of the
board should run at right angles to each otherꢀ This reduces the
effects of feed through on the boardꢀ A microstrip technique is
recommended, but not always possible with a double-sided
boardꢀ In this technique, the component side of the board is
dedicated to ground plane, while signal traces are placed on the
solder sideꢀ
For all the interfaces, the DAC output update can be done
automatically when all the data is clocked in, or it can be done
under the control of LDACꢀ The contents of the DAC register
can be read using the readback functionꢀ
AD5744 to MC68HC11 Interface
Figure 38 shows an example of a serial interface between the
AD5744 and the MCꢁ8HC11 microcontrollerꢀ The serial peripheral
interface (ꢃPI) on the MCꢁ8HC11 is configured for master mode
(MꢃTR = 1), clock polarity bit (CPOL = ꢂ), and the clock phase bit
(CPHA = 1)ꢀ The ꢃPI is configured by writing to the ꢃPI control
register (ꢃPCR) (see the 68HC11User Manual)ꢀ ꢃCK of the
MCꢁ8HC11 drives the ꢃCLK of theAD5744, the MOꢃI output
drives the serial data line (DIN) of the AD5744/ AD5744, and the
MIꢃO input is driven from ꢃDOꢀ The ꢃYNC is driven from one of
the port lines, in this case PC7ꢀ
GAꢀVANICAꢀꢀY ISOꢀATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that might occurꢀ
Isocouplers provide voltage isolation in excess of 2ꢀ5 kVꢀ The
serial loading structure of the AD5744 makes it ideal for
isolated interfaces, because the number of interface lines is kept
to a minimumꢀ Figure 37 shows a 4-channel isolated interface
to the AD5744 using an ADuM14ꢂꢂꢀ For more information, go
to wwwꢀanalogꢀcomꢀ
Rev. PrE | Page 27 of 32
AD5744
Preliminary Technical Data
When data is being transmitted to the AD5744, the ꢃYNC line
(PC7) is taken low and data is transmitted MꢃB firstꢀ Data
appearing on the MOꢃI output is valid on the falling edge of
ꢃCKꢀ Eight falling clock edges occur in the transmit cycle, so, in
order to load the required 24-bit word, PC7 is not brought high
until the third 8-bit word has been transferred to the DACs
input shift registerꢀ
The 8XC51 transmits data in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycleꢀ Because the DAC
expects a 24-bit word, ꢃYNC (P3ꢀ3) must be left low after the
first eight bits are transferredꢀ After the third byte has been
transferred, the P3ꢀ3 line is taken highꢀ The DAC can be
LDAC
updated using
via P3ꢀ4 of the 8XC51ꢀ
AD5744 to ADSP2101/ADSP2103 Interface
1
MC68HC111
AD5744
An interface between the AD5744 and the ADꢃP21ꢂ1/
ADꢃP21ꢂ3 is shown in Figure 4ꢂꢀ The ADꢃP21ꢂ1/ ADꢃP21ꢂ3
should be set up to operate in the ꢃPORT transmit alternate
framing modeꢀ The ADꢃP21ꢂ1/ADꢃP21ꢂ3 are programmed
through the ꢃPORT control register and should be configured
as follows: internal clock operation, active low framing, and 24-
bit word lengthꢀ
MISO
MOSI
SCK
PC7
SDO
SDIN
SCLK
SYNC
Transmission is initiated by writing a word to the TX register
after the ꢃPORT has been enabledꢀ As the data is clocked out of
the DꢃP on the rising edge of ꢃCLK, no glue logic is required to
interface the DꢃP to the DACꢀ In the interface shown, the DAC
output is updated using the LDAC pin via the Dꢃ ꢀ Alterna-
tively, the LDAC input could be tied permanently low, and then
the update takes place automatically when TFꢃ is taken highꢀ
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 38. AD5744 to MC68HC11 Interface
LDAC is controlled by the PCꢁ port outputꢀ The DAC can be
updated after each 3-byte transfer by bringing LDAC lowꢀ This
example does not show other serial lines for the DACꢀ For
example, if CLR were used, it could be controlled by port
output PC5ꢀ
AD57441
ADSP2101/
ADSP21031
AD5744 to 8XC51 Interface
DR
DT
SDO
The AD5744 requires a clock synchronized to the serial dataꢀ
For this reason, the 8XC51 must be operated in Mode ꢂꢀ In this
mode, serial data enters and exits through RXD, and a shift
clock is output on TXDꢀ
SDIN
SCLK
SCLK
TFS
SYNC
LDAC
RFS
FO
P3ꢀ3 and P3ꢀ4 are bit programmable pins on the serial port and
ꢃYNC
LDAC
are used to drive
and
, respectivelyꢀ The 8CX51
1
ADDITIONAL PINS OMITTED FOR CLARITY
provides the LꢃB of its ꢃBUF register as the first bit in the data
streamꢀ The user must ensure that the data in the ꢃBUF register
is arranged correctly, because the DAC expects MꢃB firstꢀWhen
data is to be transmitted to the DAC, P3ꢀ3 is taken lowꢀ Data on
RXD is clocked out of the microcontroller on the rising edge of
TXD and is valid on the falling edgeꢀ As a result, no glue logic is
required between this DAC and the microcontroller interfaceꢀ
Figure 40. AD5744 to ADSP2101/ADSP2103 Interface
AD5744 to PIC16C6x/7x Interface
The PIC1ꢁCꢁx/7x synchronous serial port (ꢃꢃP) is configured
as an ꢃPI master with the clock polarity bit set to ꢂꢀ This is done
by writing to the synchronous serial port control register
(ꢃꢃPCON)ꢀ ꢃee the PIC16/17 Microcontroller User Manualꢀ In
ꢃYNC
AD57441
8XC511
this example, I/O port RA1 is being used to pulse
and
enable the serial port of the AD5744ꢀ This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, three consecutive write operations are
neededꢀ Figure 41 shows the connection diagramꢀ
RxD
TxD
SDIN
SCLK
P3.3
P3.4
SYNC
LDAC
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 39. AD5744 to 8XC51 Interface
Rev. PrE | Page 28 of 32
Preliminary Technical Data
AD5744
AD57441
PIC16C6x/7x1
SDI/RC4
SDO/RC5
SCLK/RC3
RA1
SDO
SDIN
SCLK
SYNC
1
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 41. AD5744 to PIC16C6x/7x Interface
Rev. PrE | Page 29 of 32
AD5744
Preliminary Technical Data
OUTLINE DIMENSIONS
1.20
MAX
0.75
0.60
0.45
9.00 BSC SQ
25
32
1
24
PIN 1
7.00
BSC SQ
TOP VIEW
(PINS DOWN)
0° MIN
1.05
1.00
0.95
0.20
0.09
7°
8
17
3.5°
0°
0.15
0.05
9
16
SEATING
PLANE
0.08 MAX
COPLANARITY
VIEW A
0.80
0.45
0.37
0.30
BSC
LEAD PITCH
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026ABA
Figure 42. 32-Lead Thin Plastic Quad Flat Package [TQFP]
(SU-32-2)
Dimensions shown in millimeters
ORDERING GUIDE1
Package Option
Model
Function
INꢀ
2 LSB max
2 LSB max
1 LSB max
1 LSB max
Temperature
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
32-lead TQFP
32-lead TQFP
32-lead TQFP
32-lead TQFP
AD5744BSUZ2
AD5744BSUZ-REEL72
AD5744CSUZ2
AD5744CSUZ-REEL72
Quad 14-bit DAC
Quad 14-bit DAC
Quad 14-bit DAC
Quad 14-bit DAC
SU-32-2
SU-32-2
SU-32-2
SU-32-2
1 Analog Devices reserves the right to ship higher grade devices in place of lower grade.
2 Z = Pb-free part.
Rev. PrE | Page 30 of 32
Preliminary Technical Data
NOTES
AD5744
Rev. PrE | Page 31 of 32
AD5744
NOTES
Preliminary Technical Data
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06063-0-3/06(PrE)
Rev. PrE | Page 32 of 32
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