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AD5748 [ADI]

Industrial Current/Voltage Output Driver with Programmable Ranges; 用可编程范围工业电流/电压输出驱动器
AD5748
型号： AD5748
厂家： ADI    ADI
描述：

Industrial Current/Voltage Output Driver with Programmable Ranges
用可编程范围工业电流/电压输出驱动器

驱动器
文件： 总32页 (文件大小：812K)
中文：  中文翻译
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Industrial Current/Voltage Output Driver  
with Programmable Ranges  
AD5748  
The output current range is programmable across two current  
ranges: 4 mA to 21 mA and 0 mA to 21 mA.  
FEATURES  
Current output ranges: 4 mA to 21 mA, 0 mA to 21 mA  
0.15% FSR total unadjusted error (TUE)  
5 ppm/°C FSR typical output drift  
Voltage output ranges: 0 V to 5 V, 0 V to 10.5 V, 10.5 V  
0.05% FSR total unadjusted error (TUE)  
3 ppm/°C FSR output drift  
Voltage output is provided from a separate pin that can be  
configured to provide 0 V to 5 V, 0 V to 10.5 V, or 10.5 V  
output range.  
Analog outputs are short-circuit and open-circuit protected and  
can drive capacitive loads of 2 μF and inductive loads of 0.1 H.  
Flexible serial digital interface  
On-chip output fault detection  
PEC error checking  
The device is specified to operate with a power supply range from  
12 V to 24 V. Output loop compliance is 0 V to AVDD − 2.75 V.  
Asynchronous CLEAR function  
Flexible power-up condition to 0 V or tristate  
Power supply range  
AVDD: +12 V ( 10%) to +24 V ( 10%)  
AVSS: −12 V ( 10%) to −24 V ( 10%)  
Output loop compliance to AVDD − 2.75 V  
Temperature range: −40°C to +105°C  
32-lead, 5 mm × 5 mm LFCSP package  
The flexible serial interface is SPI- and MICROWIRE-compatible  
and can be operated in 3-wire mode to minimize the digital  
isolation required in isolated applications. The interface also  
features an optional PEC error checking feature using CRC-8  
error checking, useful in industrial environments where data  
communication corruption can occur.  
The device also includes a power-on-reset function, ensuring  
that the device powers up in a known state (0 V or tristate),  
and a asynchronous CLEAR pin that sets the outputs to zero  
scale/midscale voltage output or the low end of the selected  
current range.  
APPLICATIONS  
Process control  
Actuator control  
PLCs  
An HW SELECT pin is used to configure the part for hardware  
or software mode on power-up.  
GENERAL DESCRIPTION  
Note that the plots in the Typical Performance Characteristics  
section of this data sheet contain information on the standard  
ranges, as released in the AD5750/AD5750-1 data sheet. Although  
the overranges have been tested, new plots were not generated  
and substitution data was used for plotting purposes.  
The AD5748 is a single-channel, low cost, precision, voltage/  
current output driver with hardware or software programmable  
output ranges. The software ranges are configured via an SPI-/  
MICROWIRE™-compatible serial interface. The AD5748 targets  
applications in PLC and industrial process control. The analog  
input to the AD5748 is provided from a low voltage, single-supply,  
digital-to-analog converter (DAC) and is internally conditioned  
to provide the desired output current/voltage range. The analog  
input range is 0 V to 4.096 V.  
Table 1. Related Device  
Part Number Description  
AD5422  
Single-channel, 16-bit, serial input current  
source and voltage output DAC  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2010 Analog Devices, Inc. All rights reserved.  
 
AD5748  
TABLE OF CONTENTS  
Features .............................................................................................. 1  
Reset Function............................................................................ 25  
OUTEN........................................................................................ 25  
Software Control ........................................................................ 25  
Hardware Control ...................................................................... 27  
Transfer Function....................................................................... 27  
Detailed Description of Features.................................................. 28  
Output Fault Alert—Software Mode ....................................... 28  
Output Fault Alert—Hardware Mode ..................................... 28  
Voltage Output Short-Circuit Protection................................ 28  
Asynchronous Clear (CLEAR)................................................. 28  
Current Setting Resistor ............................................................ 29  
Packet Error Checking............................................................... 29  
Applications Information.............................................................. 30  
Transient Voltage Protection .................................................... 30  
Thermal Considerations............................................................ 30  
Layout Guidelines....................................................................... 30  
Galvanically Isolated Interface ................................................. 31  
Microprocessor Interfacing....................................................... 31  
Outline Dimensions....................................................................... 32  
Ordering Guide .......................................................................... 32  
Applications....................................................................................... 1  
General Description......................................................................... 1  
Revision History ............................................................................... 2  
Functional Block Diagram .............................................................. 3  
Specifications..................................................................................... 4  
Timing Characteristics ................................................................ 7  
Absolute Maximum Ratings............................................................ 9  
ESD Caution.................................................................................. 9  
Pin Configuration and Function Descriptions........................... 10  
Typical Performance Characteristics ........................................... 12  
Voltage Output............................................................................ 12  
Current Output........................................................................... 16  
Terminology .................................................................................... 21  
Theory of Operation ...................................................................... 22  
Software Mode............................................................................ 22  
Current Output Architecture.................................................... 24  
Driving Inductive Loads............................................................ 24  
Power-On State of the AD5748 ................................................ 24  
Default Registers at Power-On ................................................. 25  
REVISION HISTORY  
5/10—Rev. 0 to Rev. A  
Changes to Table 2, Power Requirements ..................................... 6  
3/10—Revision 0: Initial Version  
Rev. A | Page 2 of 32  
 
AD5748  
FUNCTIONAL BLOCK DIAGRAM  
DVCC GND  
AVDD GND COMP1 COMP2  
CLEAR  
AD5748  
CLRSEL  
VSENSE+  
VOUT  
SCLK/OUTEN*  
SDIN/R0*  
INPUT SHIFT  
REGISTER  
AND  
CONTROL  
LOGIC  
VOUT RANGE  
SCALING  
SYNC/RSET*  
SDO/VFAULT*  
VOUT  
SHORT FAULT  
STATUS  
REGISTER  
HW SELECT  
VSENSE–  
AVDD  
VIN  
R2  
R3  
VREF  
REXT1  
REXT2  
IOUT  
RESET  
IOUT RANGE  
SCALING  
R
SET  
OVERTEMP  
FAULT/TEMP*  
NC/IFAULT*  
VOUT SHORT FAULT  
IOUT OPEN FAULT  
PEC ERROR  
IOUT  
OPEN FAULT  
POWER-  
ON RESET  
AD2/R1*  
AD1/R2*  
AD0/R3*  
AVSS  
*DENOTES SHARED PIN. SOFTWARE MODE DENOTED BY REGULAR TEXT, HARDWARE MODE  
DENOTED BY ITALIC TEXT. FOR EXAMPLE, FOR FAULT/TEMP PIN, IN SOFTWARE MODE, THIS  
PIN TAKES ON FAULT FUNCTION. IN HARDWARE MODE, THIS PIN TAKES ON TEMP FUNCTION.  
Figure 1.  
Rev. A | Page 3 of 32  
 
 
AD5748  
SPECIFICATIONS  
AVDD/AVSS  
= 12 V ( 10ꢀ) to 24 V ( 10ꢀ), DVCC = 2.7 V to 5.5 V, GND = 0 V. IOUT: RLOAD = 300 Ω. All specifications TMIN to TMAX,  
unless otherwise noted.  
Table 2.  
Parameter1  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
INPUT VOLTAGE RANGE  
VIN  
Output unloaded  
0 to 4.096  
V
Input Leakage Current  
REFERENCE INPUT  
Reference Input Voltage  
−1  
+1  
μA  
4.096  
V
External reference needs to be exactly as  
stated; otherwise, accuracy errors show  
up as error in output  
Input Leakage Current  
VOLTAGE OUTPUT, VOUT  
Output Voltage Ranges  
−1  
+1  
μA  
0
0
5
10.5  
V
V
AVDD must have minimum 1.3 V  
headroom  
−10.5  
+10.5  
V
AVDD/AVSS must have minimum 1.3 V  
headroom  
Accuracy  
Total Unadjusted Error (TUE)2  
−0.3  
−0.1  
−0.02  
−10  
+0.3  
+0.1  
+0.02  
+10  
% FSR  
% FSR  
% FSR  
mV  
0.05  
0.005  
TA = 25°C  
Relative Accuracy (INL)  
Bipolar Zero Error (Offset at  
Midscale)  
10.5 V range  
−8  
0.5  
1.5  
+8  
mV  
ppm FSR/°C  
mV  
mV  
ppm FSR/°C  
mV  
TA = 25°C, 10.5 V range  
10.5 V range  
10.5 V range  
TA = 25°C, 10.5 V range  
10.5 V range  
Bipolar Zero Error TC 3  
Zero-Scale Error  
−10  
−8  
+10  
+8  
0.5  
1
Zero-Scale Error TC3  
Zero-Scale/Offset Error  
−5  
−4  
−3  
+5  
+4  
+3  
0 V to 10.5 V range  
TA = 25°C, 0 V to 10.5 V range  
0 V to 5 V range  
0.5  
mV  
mV  
−2.2  
0.3  
2
+2.2  
mV  
ppm FSR/°C  
% FSR  
% FSR  
ppm FSR/°C  
% FSR  
TA = 25°C, 0 V to 5 V range  
Offset Error TC3  
Gain Error  
−0.05  
−0.04  
+0.05  
+0.04  
All ranges  
TA = 25°C  
0.015  
0.5  
Gain Error TC3  
Full-Scale Error  
−0.05  
−0.04  
+0.05  
+0.04  
All ranges  
TA = 25°C  
0.015  
1.5  
% FSR  
ppm FSR/°C  
Full-Scale Error TC3  
VOLTAGE OUTPUT CHARACTERISTICS3  
Headroom  
Short-Circuit Current  
Load  
1.3  
V
mA  
kΩ  
Output unloaded  
TA = 25°C  
15  
1
Capacitive Load Stability  
RLOAD = ∞  
1
1
2
nF  
nF  
μF  
RLOAD = 2 kΩ  
RLOAD = ∞  
External compensation capacitor required;  
see the Driving Inductive Loads section  
DC Output Impedance  
0 V to 5 V range, ¼ to ¾ Step  
0 V to 5 V range, 40 mV Input Step  
Slew Rate  
0.12  
7
4.5  
2
2.5  
45.5  
Ω
μs  
μs  
V/μs  
μV rms  
μV rms  
Specified with 2 kΩ || 220 pF, 0.05%  
Specified with 2 kΩ || 220 pF, 0.05%  
Specified with 2 kΩ || 220 pF  
0.1 Hz to 10 Hz bandwidth  
Output Noise  
100 kHz bandwidth  
Rev. A | Page 4 of 32  
 
 
 
 
AD5748  
Parameter1  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
Output Noise Spectral Density  
165  
nV/√Hz  
Measured at 10 kHz; specified with  
2 kΩ || 220 pF  
AC PSRR  
−65  
10  
dB  
200 mV, 50 Hz/60 Hz sine wave  
superimposed on power supply voltage  
Outputs unloaded  
DC PSRR  
μV/V  
CURRENT OUTPUT, IOUT  
Output Current Ranges  
0
4
21  
21  
mA  
mA  
4
Accuracy, Internal RSET  
Total Unadjusted Error (TUE)2  
−0.5  
−0.3  
−0.02  
−16  
+0.5  
+0.3  
+0.02  
+16  
% FSR  
0.15  
0.01  
% FSR  
% FSR  
μA  
TA = 25°C  
Relative Accuracy (INL)  
Offset Error  
4 mA to 21 mA, 0 mA to 21 mA  
4 mA to 21 mA, 0 mA to 21 mA  
TA = 25°C  
4 mA to 21 mA, 0 mA to 21 mA  
4 mA to 21 mA, 0 mA to 21 mA  
TA = 25°C  
4 mA to 21 mA, 0 mA to 21 mA  
4 mA to 21 mA, 0 mA to 21 mA  
TA = 25°C  
−10  
+5  
3
+10  
μA  
Offset Error TC3  
Gain Error  
ppm FSR/°C  
% FSR  
% FSR  
ppm FSR/°C  
% FSR  
% FSR  
−0.2  
−0.03  
+0.2  
+0.03  
0.006  
8
Gain TC3  
Full-Scale Error  
−0.2  
−0.125  
+0.2  
+0.125  
0.02  
4
Full-Scale TC3  
ppm FSR/°C  
4 mA to 21 mA, 0 mA to 21 mA  
4
Accuracy, External RSET  
Total Unadjusted Error (TUE)2  
−0.3  
−0.1  
−0.02  
−14  
+0.3  
+0.1  
+0.02  
+14  
% FSR  
0.02  
0.01  
% FSR  
% FSR  
μA  
μA  
TA = 25°C  
Relative Accuracy (INL)  
Offset Error  
4 mA to 21 mA, 0 mA to 21 mA  
4 mA to 21 mA, 0 mA to 21 mA  
TA = 25°C  
−11  
+5  
+11  
Offset Error TC3  
Gain Error  
2
ppm FSR/°C  
% FSR  
% FSR  
ppm FSR/°C  
% FSR  
% FSR  
4 mA to 21 mA, 0 mA to 21 mA  
4 mA to 21 mA, 0 mA to 21 mA  
TA = 25°C  
4 mA to 21 mA, 0 mA to 21 mA  
4 mA to 21 mA, 0 mA to 21 mA  
TA = 25°C  
−0.08  
−0.07  
+0.08  
+0.07  
0.02  
1
Gain TC  
Full-Scale Error  
−0.1  
−0.07  
+0.1  
+0.07  
0.02  
2
Full-Scale TC3  
ppm FSR/°C  
4 mA to 21 mA, 0 mA to 21 mA  
CURRENT OUTPUT CHARACTERISTICS3  
Current Loop Compliance Voltage  
Resistive Load  
0
AVDD − 2.75  
V
See comments  
See comments  
Chosen so that compliance is not  
exceeded  
Needs appropriate capacitor at higher  
inductance values; see the Driving  
Inductive Loads section  
Inductive Load  
Settling Time  
4 mA to 21 mA, Full-Scale Step  
120 μA Step, 4 mA to 21 mA Range  
DC PSRR  
8.5  
1.2  
μs  
μs  
μA/V  
MΩ  
250 Ω load  
250 Ω load  
1
Output Impedance  
130  
DIGITAL INPUT  
JEDEC compliant  
Input High Voltage, VIH  
Input Low Voltage, VIL  
Input Current  
2
V
V
μA  
pF  
0.8  
+1  
−1  
Per pin  
Per pin  
Pin Capacitance  
5
DIGITAL OUTPUTS3  
FAULT, IFAULT, TEMP, VFAULT  
Output Low Voltage, VOL  
Output Low Voltage, VOL  
Output High Voltage, VOH  
0.4  
V
V
V
10 kΩ pull-up resistor to DVCC  
At 2.5 mA  
10 kΩ pull-up resistor to DVCC  
0.6  
3.6  
Rev. A | Page 5 of 32  
 
 
 
AD5748  
Parameter1  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
SDO  
Output Low Voltage, VOL  
Output High Voltage, VOH  
High Impedance Output  
Capacitance  
0.5  
DVCC − 0.5  
0.5  
DVCC − 0.5  
3
V
V
pF  
Sinking 200 μA  
Sourcing 200 μA  
High Impedance Leakage Current  
POWER REQUIREMENTS  
−1  
+1  
μA  
Positive Analog Supply, AVDD  
Negative Analog Supply, AVSS  
Digital Power Supply, DVCC  
Input Voltage  
12  
−12  
24  
−24  
V
V
10%  
10%  
2.7  
5.5  
5.6  
V
mA  
AIDD  
4.4  
Output unloaded, output disabled,  
R3, R2, R1, R0 = 0, 1, 0, 1  
5.2  
5.2  
2.0  
6.2  
6.2  
2.5  
mA  
mA  
mA  
Current output enabled  
Voltage output enabled  
Output unloaded, output disabled,  
R3, R2, R1, R0 = 0, 1, 0, 1  
AISS  
2.5  
2.5  
0.3  
108  
3
3
1
mA  
mA  
mA  
mW  
Current output enabled  
Voltage output enabled  
VIH = DVCC, VIL = GND  
AVDD/AVSS = 24 V, outputs unloaded  
DICC  
Power Dissipation  
1 Temperature range: −40°C to +105°C; typical at +25°C.  
2 Specification includes gain and offset errors over temperature, and drift after 1000 hours, TA = 125°C.  
3 Guaranteed by characterization, but not production tested.  
4 See the Current Setting Resistor section.  
Rev. A | Page 6 of 32  
 
 
 
 
AD5748  
TIMING CHARACTERISTICS  
AVDD/AVSS  
= 12 V ( 10ꢀ) to 24 V ( 10ꢀ), DVCC = 2.7 V to 5.5 V, GND = 0 V. VOUT: RLOAD = 2 kΩ, CL = 200 pF, IOUT: RLOAD =  
300 Ω. All specifications TMIN to TMAX, unless otherwise noted.  
Table 3.  
Parameter 1,  
2
Limit at TMIN, TMAX  
Unit  
Description  
t1  
t2  
t3  
t4  
20  
8
8
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
μs max  
ns min  
ns max  
ns min  
SCLK cycle time  
SCLK high time  
SCLK low time  
5
SYNC falling edge to SCLK falling edge setup time  
16th SCLK falling edge to SYNC rising edge (on 24th SCLK falling edge if using PEC)  
Minimum SYNC high time (write mode)  
Data setup time  
t5  
10  
5
t6  
t7  
t8  
t9, t10  
t11  
t12  
t13  
5
5
1.5  
5
Data hold time  
CLEAR pulse low/high activation time  
Minimum SYNC high time (read mode)  
SCLK rising edge to SDO valid (SDO CL = 15 pF)  
RESET pulse low time  
40  
10  
1 Guaranteed by characterization, but not production tested.  
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.  
Rev. A | Page 7 of 32  
 
 
AD5748  
Timing Diagrams  
t1  
SCLK  
1
2
16  
t3  
t2  
t6  
t4  
t5  
SYNC  
t8  
t7  
D15  
SDIN  
CLEAR  
VOUT  
D0  
t10  
t9  
RESET  
t13  
Figure 2. Write Mode Timing Diagram  
1
2
16  
SCLK  
SYNC  
t11  
A2  
A1  
A0  
t12  
R = 1  
0
X
X
X
X
X
X
X
X
X
X
X
SDIN  
SDO  
PEC  
OVER  
IOUT  
VOUT  
X
X
X
X
X
R3  
R2  
R1  
R0 CLRSEL OUTEN RSET  
ERROR TEMP FAULT FAULT  
Figure 3. Readback Mode Timing Diagram  
Rev. A | Page 8 of 32  
 
AD5748  
ABSOLUTE MAXIMUM RATINGS  
TA = 25°C unless otherwise noted.  
Transient currents of up to 100 mA do not cause SCR latch-up.  
Table 4.  
Parameter  
AVDD to GND  
AVSS to GND  
AVDD to AVSS  
DVCC to GND  
VSENSE+ to GND  
VSENSE− to GND  
Digital Inputs to GND  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Rating  
−0.3 V to +30 V  
+0.3 V to −28 V  
−0.3 V to +58 V  
−0.3 V to +7 V  
AVSS to AVDD  
5.0 V  
ESD CAUTION  
−0.3 V to DVCC + 0.3 V or 7 V  
(whichever is less)  
Digital Outputs to GND  
−0.3 V to DVCC + 0.3 V or 7 V  
(whichever is less)  
VREF to GND  
VIN to GND  
VOUT, IOUT to GND  
Operating Temperature Range,  
Industrial  
−0.3 V to +7 V  
−0.3 V to +7 V  
AVSS to AVDD  
−40°C to +105°C  
Storage Temperature Range  
Junction Temperature (TJ max)  
32-Lead LFCSP Package  
θJA Thermal Impedance  
Lead Temperature  
−65°C to +150°C  
125°C  
28°C/W  
JEDEC industry standard  
Soldering  
ESD (Human Body Model)  
J-STD-020  
3 kV  
Rev. A | Page 9 of 32  
 
AD5748  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
PIN 1  
INDICATOR  
SDO/VFAULT  
CLRSEL  
CLEAR  
DVCC  
GND  
SYNC/RSET  
SCLK/OUTEN  
SDIN/R0  
1
2
3
4
5
6
7
8
24 VSENSE+  
23 VOUT  
22 VSENSE–  
21 AVSS  
20 COMP1  
19 COMP2  
18 IOUT  
AD5748  
TOP VIEW  
(Not to Scale)  
17 AVDD  
NOTES  
1. NC = NO CONNECT.  
2. THE EXPOSED PADDLE IS TIED TO AVSS.  
Figure 4. Pin Configuration  
Table 4. Pin Function Descriptions  
Pin No.  
Mnemonic  
Description  
1
SDO/VFAULT  
Serial Data Output (SDO). In software mode, this pin is used to clock data from the input shift register in  
readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.  
This pin is a CMOS output.  
Short-Circuit Fault Alert (VFAULT). In hardware mode, this pin acts as a short-circuit fault alert pin and is  
asserted low when a short-circuit error is detected. This pin is an open-drain output and must be connected  
to a pull-up resistor.  
2
3
CLRSEL  
CLEAR  
In hardware or software mode, this pin selects the clear value, either zero-scale or midscale code. In software  
mode, this pin is implemented as a logic OR with the internal CLRSEL bit.  
Active High Input. Asserting this pin sets the output current/voltage to zero-scale code or midscale code of the  
range selected (user-selectable). CLEAR is a logic OR with the internal clear bit.  
In software mode, during power-up, the CLEAR pin level determines the power-on condition of the voltage  
channel, which can be active 0 V or tristate. See the Asynchronous Clear (CLEAR) section for more details.  
4
5
6
DVCC  
GND  
SYNC/RSET  
Digital Power Supply.  
Ground Connection.  
Positive Edge-Sensitive Latch (SYNC). In software mode, a rising edge parallel loads the input shift register data  
into the AD5748, also updating the output.  
Resistor Select (RSET). In hardware mode, this pin chooses whether the internal or the external current sense  
resistor is used.  
If RSET = 0, the external sense resistor is chosen.  
If RSET = 1, the internal sense resistor is chosen.  
7
8
9
SCLK/OUTEN Serial Clock Input (SCLK). In software mode, data is clocked into the input shift register on the falling edge of  
SCLK. This pin operates at clock speeds of up to 50 MHz.  
Output Enable (OUTEN). In hardware mode, this pin acts as an output enable pin.  
SDIN/R0  
AD2/R1  
Serial Data Input (SDIN). In software mode, data must be valid on the falling edge of SCLK.  
Range Decode Bit (R0). In hardware mode, this pin, in conjunction with R1, R2, and R3, selects the output  
current/voltage range setting on the part.  
Device Addressing Bit (AD2). In software mode, this pin, in conjunction with AD1 and AD0, allows up to eight  
devices to be addressed on one bus.  
Range Decode Bit (R1). In hardware mode, this pin, in conjunction with R0, R2, and R3, selects the output  
current/voltage range setting on the part.  
10  
AD1/R2  
Device Addressing Bit (AD1). In software mode, this pin, in conjunction with AD2 and AD0 allows up to eight  
devices to be addressed on one bus.  
Range Decode Bit (R2). In hardware mode, this pin, in conjunction with R0, R1, and R3, selects the output  
current/voltage range setting on the part.  
Rev. A | Page 10 of 32  
 
AD5748  
Pin No.  
Mnemonic  
Description  
11  
AD0/R3  
Device Addressing Bit (AD0). In software mode, this pin, in conjunction with AD1 and AD2, allows up to eight  
devices to be addressed on one bus.  
Range Decode Bit (R3). In hardware mode, this pin, in conjunction with, R0, R1, and R2, selects the output  
current/voltage range setting on the part.  
12, 13  
REXT2, REXT1 A 15 kΩ external current setting resistor can be connected between the REXT1 and REXT2 pins to improve the  
IOUT temperature drift performance.  
14  
15  
16  
17  
VREF  
VIN  
GND  
AVDD  
IOUT  
Buffered Reference Input.  
Buffered Analog Input (0 V to 4.096 V).  
Ground Connection.  
Positive Analog Supply Pin.  
Current Output Pin.  
18  
19, 20  
COMP2,  
COMP1  
Optional Compensation Capacitor Connections for the Voltage Output Buffer. These are used to drive higher  
capacitive loads on the output. These pins also reduce overshoot on the output. Care should be taken when  
choosing the value of the capacitor connected between the COMP1 and COMP2 pins because it has a direct  
influence on the settling time of the output. See the Driving Large Capacitive Loads section for further details.  
21  
22  
AVSS  
VSENSE−  
Negative Analog Supply Pin.  
Sense Connection for the Negative Voltage Output Load Connection. This pin must stay within 3.0 V of  
ground for correct operation.  
23  
24  
25, 26,  
27, 28  
VOUT  
VSENSE+  
NC  
Buffered Analog Output Voltage.  
Sense Connection for the Positive Voltage Output Load Connection.  
No Connect. Can be tied to GND.  
29  
HW SELECT  
This pin is used to configure the part to hardware or software mode.  
HW SELECT = 0 selects software control.  
HW SELECT = 1 selects hardware control.  
30  
31  
RESET  
Resets the part to its power-on state.  
FAULT/TEMP  
Fault Alert (FAULT). In software mode, this pin acts as a general fault alert pin. It is asserted low when an open  
circuit, short circuit, overtemperature error, or PEC interface error is detected. This pin is an open-drain output  
and must be connected to a pull-up resistor.  
Overtemperature Fault (TEMP). In hardware mode, this pin acts as an overtemperature fault pin. It is asserted  
low when an overtemperature error is detected. This pin is an open-drain output and must be connected to a  
pull-up resistor.  
32  
NC/IFAULT  
No Connect (NC). In software mode, this pin is a no connect. Instead, tie this pin to GND.  
Open-Circuit Fault Alert (IFAULT). In hardware mode, this pin acts as an open-circuit fault alert pin. It is asserted  
low when an open-circuit error is detected. This pin is an open-drain output and must be connected to a pull-  
up resistor.  
33 (EPAD) Exposed  
paddle  
The exposed paddle is tied to AVSS.  
Rev. A | Page 11 of 32  
AD5748  
TYPICAL PERFORMANCE CHARACTERISTICS  
VOLTAGE OUTPUT  
0.0020  
0.10  
0.08  
0.06  
0.04  
0.02  
0
AV  
= +24V  
DD  
AV = –24V  
SS  
0.0015  
0.0010  
0.0005  
0
–0.0005  
–0.0010  
–0.0015  
–0.0020  
–0.0025  
–0.0030  
–0.02  
–0.04  
–0.06  
–0.08  
–0.10  
+5V POSITIVE TUE, NO LOAD  
+10V POSITIVE TUE, NO LOAD  
±10V POSITIVE TUE, NO LOAD  
+5V NEGATIVE TUE, NO LOAD  
+10V NEGATIVE TUE, NO LOAD  
±10V NEGATIVE TUE, NO LOAD  
+5V  
+10V  
±10V  
0
0.585  
1.170  
1.755  
2.341  
(V)  
2.926  
3.511  
4.096  
–40  
25  
105  
V
TEMPERATURE (°C)  
IN  
Figure 8. Total Unadjusted Error vs. Temperature  
Figure 5. Integral Nonlinearity Error vs. VIN  
0.03  
0.02  
0.01  
0
0.005  
0.004  
0.003  
0.002  
0.001  
0
+5V LINEARITY, NO LOAD  
+10V LINEARITY, NO LOAD  
±10V LINEARITY, NO LOAD  
AV  
= +24V  
DD  
AV = –24V  
SS  
–0.01  
–0.02  
–0.03  
–0.04  
–0.001  
–0.002  
–0.003  
–0.004  
–0.005  
+5V RANGE, FULL-SCALE ERROR  
+10V RANGE, FULL-SCALE ERROR  
±10V RANGE, FULL-SCALE ERROR  
–40  
25  
105  
–40  
25  
TEMPERATURE (°C)  
105  
TEMPERATURE (°C)  
Figure 9. Full-Scale Error vs. Temperature  
Figure 6. Integral Nonlinearity Error vs. Temperature  
2.5  
2.0  
0.006  
0.004  
0.002  
0
AV  
= +24V  
DD  
AV  
= +24V  
DD  
AV = –24V  
SS  
AV = –24V  
SS  
1.5  
1.0  
±10V ZERO ERROR  
0.5  
0
–0.002  
–0.004  
–0.006  
–0.008  
–0.010  
–0.5  
–1.0  
–1.5  
–2.0  
–2.5  
+5V  
+10V  
±10V  
–40  
25  
TEMPERATURE (°C)  
105  
0
0.585  
1.170  
1.755  
2.341  
(V)  
2.926  
3.511  
4.096  
V
IN  
Figure 10. Bipolar Zero Error vs. Temperature  
Figure 7. Total Unadjusted Error vs. VIN  
Rev. A | Page 12 of 32  
 
 
 
 
AD5748  
0.020  
0.015  
0.010  
0.005  
0
0.10  
0.08  
0.06  
0.04  
0.02  
0
AV  
= +24V  
+5V POSITIVE TUE, NO LOAD  
+10V POSITIVE TUE, NO LOAD  
±10V POSITIVE TUE, NO LOAD  
+5V NEGATIVE TUE, NO LOAD  
+10V NEGATIVE TUE, NO LOAD  
±10V NEGATIVE TUE, NO LOAD  
DD  
AV = –24V  
SS  
–0.005  
–0.010  
–0.015  
–0.020  
–0.025  
–0.02  
–0.04  
–0.06  
–0.08  
–0.10  
+5V GAIN, NO LOAD  
+10V GAIN, NO LOAD  
±10V GAIN, NO LOAD  
+11.2/–10.8  
±15.0  
±24.0  
±26.4  
–40  
25  
105  
TEMPERATURE (°C)  
SUPPLY VOLTAGES (AV /AV  
)
SS  
DD  
Figure 11. Gain Error vs. Temperature  
Figure 14. Total Unadjusted Error vs. Supply Voltages  
2.5  
2.0  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
AV  
= +24V  
DD  
AV = –24V  
OUTPUT UNLOADED  
SS  
1.5  
1.0  
0.5  
±10V AV  
HEADROOM, LOAD OFF  
DD  
0
–0.5  
–1.0  
–1.5  
–2.0  
–2.5  
–3.0  
+5V RANGE  
+10V RANGE  
±10V RANGE  
–40  
25  
105  
–40  
25  
TEMPERATURE (°C)  
105  
TEMPERATURE (°C)  
Figure 12. Zero-Scale Error (Offset Error) vs. Temperature  
Figure 15. AVDD Headroom, 10 V Range, Output Set to 10 V, Load Off  
0.003  
0.05  
+5V LINEARITY, NO LOAD  
+10V LINEARITY, NO LOAD  
±10V LINEARITY, NO LOAD  
+5V RANGE  
±10V RANGE  
0.04  
0.03  
0.002  
0.001  
0
0.02  
0.01  
0
–0.01  
–0.02  
–0.03  
–0.04  
–0.05  
–0.001  
–0.002  
–0.003  
+11.2/–10.8  
±15.0  
±24.0  
±26.4  
–15 –13 –11 –9 –7 –5 –3 –1  
1
3
5
7
9
11 13 15  
SUPPLY VOLTAGES (AV /AV  
)
SS  
DD  
SOURCE/SINK CURRENT (mA)  
Figure 13. Integral Nonlinearity Error vs. Supply Voltage  
Figure 16. Source and Sink Capability of Output Amplifier  
Rev. A | Page 13 of 32  
 
 
AD5748  
12  
10  
8
1
6
4
2
2
0
–8  
B
CH1 5.00V CH2 20.0mV  
M1.0µs  
A CH1  
3.00V  
W
–3  
2
7
12  
17  
22  
27  
TIME (µs)  
Figure 17. Full-Scale Positive Step  
Figure 20. VOUT Enable Glitch, Load = 2 kΩ || 1 nF  
12  
10  
8
6
4
2
5µV/DIV  
1s/DIV  
0
–8  
–3  
2
7
12  
17  
22  
27  
TIME (µs)  
Figure 18. Full-Scale Negative Step  
Figure 21. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth)  
40  
35  
30  
25  
20  
15  
10  
5
0
100µV/DIV  
1s/DIV  
–5  
–1.0  
–0.5  
0
0.5  
1.0  
1.5  
2.0  
2.5  
TIME (ms)  
Figure 22. Peak-to-Peak Noise (100 kHz Bandwidth)  
Figure 19. VOUT vs. Time on Power-Up, Load = 2 kΩ || 200 pF  
Rev. A | Page 14 of 32  
AD5748  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
1.0  
0.8  
0.6  
0.4  
0.2  
0
AV  
DD  
V
OUT  
–0.2  
–1.5  
–1.0  
–0.5  
0
0.5  
1.0  
1.5  
2.0  
TIME (ms)  
Figure 23. AVDD and VOUT vs. Time on Power-Up  
Rev. A | Page 15 of 32  
AD5748  
CURRENT OUTPUT  
0.004  
0.010  
0.008  
0.006  
0.004  
0.002  
0
+4mA TO +20mA  
0mA TO +20mA  
+4mA TO +20mA INTERNAL R  
0mA TO +20mA INTERNAL R  
LINEARITY  
SET  
LINEARITY  
SET  
0.002  
0
–0.002  
–0.004  
–0.006  
–0.008  
–0.002  
–0.004  
–0.006  
–0.008  
–0.010  
AV  
= +24V  
DD  
AV = –24V  
SS  
–0.010  
+11.2/–10.8  
±15.0  
±24.0  
±26.4  
0
0.585  
1.170  
1.755  
2.341  
(V)  
2.926  
3.511  
4.096  
V
SUPPLY VOLTAGES (AV /AV  
DD  
)
IN  
SS  
Figure 24. Integral Nonlinearity Error vs. VIN, External RSET Resistor  
Figure 27. Integral Nonlinearity Error Current Mode,  
Internal RSET Sense Resistor  
0.010  
0.008  
0.006  
0.004  
0.002  
0
0.004  
+4mA TO +20mA  
0mA TO +20mA  
AV  
= +24V  
DD  
AV = –24V  
SS  
0.002  
0
–0.002  
–0.004  
–0.006  
–0.008  
–0.010  
–0.012  
–0.002  
–0.004  
–0.006  
–0.008  
AV  
= +24V  
DD  
+4mA TO +20mA  
0mA TO +20mA  
AV = –24V  
SS  
0
0.585  
1.170  
1.755  
2.341  
(V)  
2.926  
3.511  
4.096  
0
0.585  
1.170  
1.755  
2.341  
(V)  
2.926  
3.511  
4.096  
V
V
IN  
IN  
Figure 28. Total Unadjusted Error vs. VIN, External RSET Resistor  
Figure 25. Integral Nonlinearity Error vs. VIN, Internal RSET Resistor  
0.015  
0.010  
+4mA TO +20mA  
0mA TO +20mA  
+4mA TO +20mA EXTERNAL R  
0mA TO +20mA EXTERNAL R  
LINEARITY  
AV  
= +24V  
SET  
LINEARITY  
DD  
AV = –24V  
SS  
0.008  
0.006  
0.004  
0.002  
0
SET  
0.010  
0.005  
0
–0.002  
–0.004  
–0.006  
–0.008  
–0.010  
–0.005  
–0.010  
–0.015  
+11.2/–10.8  
±15.0  
±24.0  
±26.4  
0
0.585  
1.170  
1.755  
2.341  
(V)  
2.926  
3.511  
4.096  
V
SUPPLY VOLTAGES (AV /AV  
DD  
)
IN  
SS  
Figure 29. Total Unadjusted Error vs. VIN, Internal RSET Resistor  
Figure 26. Integral Nonlinearity Error, Current Mode,  
External RSET Sense Resistor  
Rev. A | Page 16 of 32  
 
AD5748  
0.10  
0.08  
0.06  
0.04  
0.02  
0
0.010  
0.008  
0.006  
0.004  
0.002  
0
+4mA TO +20mA EXTERNAL R  
0mA TO +20mA EXTERNAL R  
+4mA TO +20mA EXTERNAL R  
POSITIVE TUE  
+4mA TO +20mA EXTERNAL R  
0mA TO +20mA EXTERNAL R  
LINEARITY  
SET  
POSITIVE TUE  
SET  
LINEARITY  
SET  
SET  
NEGATIVE TUE  
SET  
NEGATIVE TUE  
0mA TO +20mA EXTERNAL R  
SET  
–0.02  
–0.04  
–0.06  
–0.08  
–0.10  
–0.002  
–0.004  
–0.006  
–0.008  
–0.010  
AV  
= +24V  
DD  
AV = –24V  
SS  
+11.2/–10.8  
±15.0  
±24.0  
±26.4  
–40  
25  
TEMPERATURE (°C)  
105  
SUPPLY VOLTAGES (AV /AV  
)
SS  
DD  
Figure 30. Total Unadjusted Error Current Mode, External RSET Sense Resistor  
Figure 33. INL vs. Temperature, External RSET Sense Resistor  
0.10  
0.10  
0.08  
0.06  
0.04  
0.02  
0
+4mA TO +20mA INTERNAL R  
POSITIVE TUE  
SET  
POSITIVE TUE  
+4mA TO +20mA INTERNAL R  
POSITIVE TUE  
SET  
POSITIVE TUE  
0mA TO +20mA INTERNAL R  
SET  
+4mA TO +20mA INTERNAL R  
0.08  
0.06  
0mA TO +20mA INTERNAL R  
SET  
+4mA TO +20mA INTERNAL R  
NEGATIVE TUE  
SET  
NEGATIVE TUE  
NEGATIVE TUE  
SET  
NEGATIVE TUE  
0mA TO +20mA INTERNAL R  
SET  
0mA TO +20mA INTERNAL R  
SET  
0.04  
0.02  
0
–0.02  
–0.04  
–0.06  
–0.08  
–0.10  
–0.02  
–0.04  
–0.06  
–0.08  
–0.10  
+11.2/–10.8  
±15.0  
±24.0  
±26.4  
–40  
25  
TEMPERATURE (°C)  
105  
SUPPLY VOLTAGES (AV /AV  
)
SS  
DD  
Figure 31. Total Unadjusted Error Current Mode, Internal RSET Sense Resistor  
Figure 34. Total Unadjusted Error vs. Temperature, Internal RSET Sense Resistor  
0.10  
0.010  
+4mA TO +20mA EXTERNAL R  
0mA TO +20mA EXTERNAL R  
+4mA TO +20mA EXTERNAL R  
POSITIVE TUE  
+4mA TO +20mA INTERNAL R  
0mA TO +20mA INTERNAL R  
LINEARITY  
SET  
POSITIVE TUE  
SET  
LINEARITY  
SET  
SET  
0.08  
0.06  
0.008  
0.006  
0.004  
0.002  
0
NEGATIVE TUE  
SET  
NEGATIVE TUE  
0mA TO +20mA EXTERNAL R  
SET  
0.04  
0.02  
0
–0.02  
–0.04  
–0.06  
–0.08  
–0.10  
–0.002  
–0.004  
–0.006  
–0.008  
–0.010  
AV  
= +24V  
DD  
AV = –24V  
SS  
–40  
25  
TEMPERATURE (°C)  
105  
–40  
25  
TEMPERATURE (°C)  
105  
Figure 35. Total Unadjusted Error vs. Temperature, External RSET Sense Resistor  
Figure 32. INL vs. Temperature, Internal RSET Sense Resistor  
Rev. A | Page 17 of 32  
AD5748  
6
0.04  
0.03  
+4mA TO +20mA EXTERNAL R  
0mA TO +20mA EXTERNAL R  
+4mA TO +20mA INTERNAL R  
0mA TO +20mA INTERNAL R  
SET  
SET  
SET  
SET  
4
0.02  
0.01  
2
0
0
–0.01  
–0.02  
–0.03  
–0.04  
–0.05  
–0.06  
–2  
–4  
AV  
= +24V  
AV  
= +24V  
DD  
DD  
AV = –24V  
AV = –24V  
SS  
SS  
–6  
–40  
25  
105  
–40  
25  
TEMPERATURE (°C)  
105  
TEMPERATURE (°C)  
Figure 36. Zero-Scale Error vs. Temperature, External RSET Sense Resistor  
Figure 39. Full-Scale Error vs. Temperature, Internal RSET Sense Resistor  
25  
0.020  
+4mA TO +20mA EXTERNAL R  
SET  
0mA TO +20mA EXTERNAL R  
SET  
+4mA TO +20mA INTERNAL R  
SET  
0mA TO +20mA INTERNAL R  
SET  
20  
15  
0.015  
0.010  
0.005  
0
AV  
= +24V  
DD  
AV = –24V  
10  
5
SS  
0
–5  
–0.005  
–0.010  
–10  
–15  
–20  
±20mA INTERNAL R  
±24mA INTERNAL R  
AV  
= +24V  
DD  
SET  
SET  
AV = –24V  
SS  
–0.015  
–40  
25  
105  
–40  
25  
105  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 37. Zero-Scale Error vs. Temperature, Internal RSET Sense Resistor  
Figure 40. Gain Error vs. Temperature, External RSET Sense Resistor  
0.08  
0.04  
+4mA TO +20mA INTERNAL R  
SET  
+4mA TO +20mA EXTERNAL R  
SET  
0mA TO +20mA INTERNAL R  
0mA TO +20mA EXTERNAL R  
SET  
SET  
0.06  
0.04  
0.02  
0
0.03  
0.02  
0.01  
0
–0.02  
–0.04  
–0.06  
–0.08  
–0.01  
–0.02  
–0.03  
AV  
= +24V  
DD  
AV  
= +24V  
DD  
AV = –24V  
SS  
AV = –24V  
SS  
–0.10  
–0.04  
–40  
25  
105  
–40  
25  
105  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 41. Gain Error vs. Temperature, Internal RSET Sense Resistor  
Figure 38. Full-Scale Error vs. Temperature, External RSET Sense Resistor  
Rev. A | Page 18 of 32  
AD5748  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0
0.025  
0.020  
0.015  
0.010  
0.005  
0
AV  
COMPLIANCE  
DD  
–40  
25  
TEMPERATURE (°C)  
105  
–12 –6  
1
8
14 21 28 34 41 48 54 61 68  
TIME (µs)  
Figure 42. Output Compliance vs. Temperature  
Tested When IOUT = 10.8 mA  
Figure 45. 4 mA to 20 mA Output Current Step  
12  
10  
8
0.000010  
0.000008  
0.000006  
0.000004  
0.000002  
0
3000  
2500  
2000  
1500  
1000  
500  
6
DV  
= 5V  
CC  
I
OUT  
4
–0.000002  
–0.000004  
–0.000006  
–0.000008  
–0.000010  
2
0
V
DD  
DV  
= 3V  
CC  
–2  
0
–10  
–8  
–6  
–4  
–2  
0
2
4
6
8
10  
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
LOGIC LEVEL (V)  
TIME (ms)  
Figure 46. DICC vs. Logic Input Voltage  
Figure 43. Output Current vs. Time on Power-Up  
0
–2  
–4  
–6  
–8  
–10  
–12  
–14  
–16  
–18  
–2  
–1  
0
1
2
3
4
5
6
7
8
TIME (µs)  
Figure 44. Output Current vs. Time on Output Enable  
Rev. A | Page 19 of 32  
AD5748  
6
6
5
5
AI  
AI  
DD  
DD  
4
4
3
3
2
2
1
1
0
0
–1  
–2  
–3  
–1  
–2  
–3  
AI  
AI  
SS  
SS  
±10.8  
±15.0  
±24.0  
±26.4  
±10.8  
±15.0  
±24.0  
±26.4  
AV /AV (V)  
AV /AV (V)  
DD SS  
DD SS  
Figure 47. AIDD/AISS vs. AVDD/AVSS, VOUT = 0 V  
Figure 48. AIDD/AISS vs. AVDD/AVSS, IOUT = 0 mA  
Rev. A | Page 20 of 32  
AD5748  
TERMINOLOGY  
Total Unadjusted Error (TUE)  
Zero-Scale Error  
TUE is a measure of the output error taking all the various  
errors into account: INL error, offset error, gain error, and  
output drift over supplies, temperature, and time. TUE is  
expressed as a percentage of full-scale range (ꢀ FSR).  
Zero-scale error is the deviation of the actual zero-scale analog  
output from the ideal zero-scale output. Zero-scale error is  
expressed in millivolts (mV).  
Zero-Scale TC  
Relative Accuracy or Integral Nonlinearity (INL)  
INL is a measure of the maximum deviation, in ꢀ FSR, from a  
straight line passing through the endpoints of the output driver  
transfer function. A typical INL vs. input voltage plot can be  
seen in Figure 5.  
Zero-scale TC is a measure of the change in zero-scale error  
with a change in temperature. Zero-scale error TC is expressed  
in ppm FSR/°C.  
Offset Error  
Offset error is a measurement of the difference between VOUT  
(actual) and VOUT (ideal) expressed in millivolts (mV) in the  
linear region of the transfer function. It can be negative or  
positive.  
Bipolar Zero Error  
Bipolar zero error is the deviation of the actual vs. ideal half-  
scale output of 0 V/0 mA with a bipolar range selected. A plot  
of bipolar zero error vs. temperature can be seen in Figure 10.  
Output Voltage Settling Time  
Bipolar Zero TC  
Output voltage settling time is the amount of time it takes for  
the output to settle to a specified level for a half-scale input change.  
Bipolar zero TC is a measure of the change in the bipolar  
zero error with a change in temperature. It is expressed in  
ppm FSR/°C.  
Slew Rate  
The slew rate of a device is a limitation in the rate of change  
of the output voltage. The output slewing speed is usually  
limited by the slew rate of the amplifier used at its output.  
Slew rate is measured from 10ꢀ to 90ꢀ of the output signal  
and is expressed in V/ꢁs.  
Full-Scale Error  
Full-scale error is the deviation of the actual full-scale analog  
output from the ideal full-scale output. Full-scale error is  
expressed as a percentage of full-scale range (ꢀ FSR).  
Full-Scale TC  
Current Loop Voltage Compliance  
Full-scale TC is a measure of the change in the full-scale error  
with a change in temperature. It is expressed in ppm FSR/°C.  
Current loop voltage compliance is the maximum voltage at  
the IOUT pin for which the output current is equal to the  
programmed value.  
Gain Error  
Gain error is a measure of the span error of the output. It is the  
deviation in slope of the output transfer characteristic from the  
ideal expressed in ꢀ FSR. A plot of gain error vs. temperature  
can be seen in Figure 11.  
Power-On Glitch Energy  
Power-on glitch energy is the impulse injected into the analog  
output when the AD5748 is powered on. It is specified as the  
area of the glitch in nV-sec.  
Gain Error TC  
Power Supply Rejection Ratio (PSRR)  
PSRR indicates how the output is affected by changes in the  
power supply voltage.  
Gain error TC is a measure of the change in gain error  
with changes in temperature. Gain error TC is expressed  
in ppm FSR/°C.  
Rev. A | Page 21 of 32  
 
AD5748  
THEORY OF OPERATION  
The AD5748 is a single-channel, precision, voltage/current  
output driver with hardware or software programmable  
output ranges. The software ranges are configured via an SPI-/  
MICROWIRE-compatible serial interface. The analog input  
to the AD5748 is provided from a low voltage, single-supply,  
digital-to-analog converter and is internally conditioned to  
provide the desired output current/voltage range. The analog  
input range is 0 V to 4.096 V.  
Figure 49 and Figure 50 show a typical configuration of the  
AD5748 in software mode and in hardware mode, respectively,  
in an output module system. The HW SELECT pin selects  
whether the part is configured in software or hardware mode.  
The analog input to the AD5748 is provided from a low voltage,  
single-supply, digital-to-analog converter (DAC) such as the  
AD506x or AD566x, which provides an output range of 0 V  
to 4.096 V. The supply and reference for the DAC, as well as  
the reference for the AD5748, can be supplied from a reference  
such as the ADR392. The AD5748 can operate from supplies  
up to 26.4 V.  
The output current range is programmable across two current  
ranges: 4 mA to 21 mA and 0 mA to 21 mA.  
The voltage output is provided from a separate pin that can  
be configured to provide 0 V to 5 V, 0 V to 10.5 V, or 10.5 V  
output ranges. The current and voltage outputs are available on  
separate pins. Only one output can be enabled at one time. The  
output range is selected by programming the R3 to R0 bits in  
the control register (see Table 6 and Table 7).  
SOFTWARE MODE  
In current mode, software-selectable output ranges include 0 mA  
to 21 mA, and 4 mA to 21 mA.  
In voltage mode, software-selectable output ranges include 0 V  
to 5 V, 0 V to 10.5 V, and 10.5 V.  
VDD AGND VSS  
ADP1720  
ADR392  
AVDD GND AVSS  
AD5748  
VSENSE+  
VSENSE–  
VREF  
VDD REFIN  
SCLK  
VOUT  
RANGE  
SCALE  
VOUT  
0V TO +5V,  
0V TO +10.5V,  
±10.5V  
SDI/DIN  
VIN  
AD506x  
MCU  
SDO  
AD566x  
IOUT  
RANGE  
SCALE  
SYNC1  
IOUT  
4mA TO 21mA,  
0mA TO 21mA  
SCLK  
SDIN  
SDO  
VOUT SHORT FAULT  
IOUT OPEN FAULT  
OVERTEMP FAULT  
PEC ERROR  
SERIAL  
INTERFACE  
SYNC  
STATUS REGISTER  
HW SELECT  
FAULT  
Figure 49. Typical System Configuration in Software Mode (Pull-Up Resistors Not Shown for Open-Drain Outputs)  
Rev. A | Page 22 of 32  
 
 
AD5748  
VDD AGND VSS  
AVDD GND AVSS  
ADP1720  
ADR3192  
AD5748  
VSENSE+  
VSENSE–  
VREF  
REFIN  
VDD  
VOUT  
RANGE  
SCALE  
SCLK  
SDI/DIN  
SDO  
VOUT  
0V TO +5V,  
0V TO +10.5V,  
±10.5V  
VIN  
AD506x  
AD566x  
MCU  
SYNC1  
IOUT  
RANGE  
SCALE  
IOUT  
4mA TO +21mA,  
0mA TO +21mA  
DVCC  
HW SELECT  
OUTEN  
R3  
R2  
R1  
OUTPUT RANGE  
SELECT PINS  
TEMP  
VFAULT  
IFAULT  
R0  
Figure 50. Typical System Configuration in Hardware Mode Using Internal DAC Reference (Pull-Up Resistors Not Shown for Open-Drain Outputs)  
Table 5. Suggested Parts for Use with AD5748  
DAC  
Reference  
Internal  
Internal  
Internal  
ADR434  
ADR434  
ADR3922  
ADR3922  
Power  
ADP17201  
N/A  
Accuracy  
12-bit INL  
N/A  
N/A  
16-bit INL  
N/A  
Description  
AD5660  
AD5664R  
AD5668  
AD5060  
AD5064  
AD5662  
AD5664  
Mid end system, single channel, internal reference  
Mid end system, quad channel, internal reference  
Mid end system, octal channel, internal reference  
High end system, single channel, external reference  
High end system, quad channel, external reference  
Mid end system, single channel, external reference  
Mid end system, quad channel, external reference  
N/A  
ADP1720  
N/A  
ADR3922  
12-bit INL  
N/A  
N/A  
1 ADP1720 input range up to 28 V.  
2 ADR392 input range up to 15 V.  
Rev. A | Page 23 of 32  
 
 
 
AD5748  
Driving Large Capacitive Loads  
CURRENT OUTPUT ARCHITECTURE  
The voltage input from the analog input VIN pin (0 V to 4.096 V)  
is either converted to a current (see Figure 51), which is then  
mirrored to the supply rail so that the application simply sees  
a current source output with respect to an internal reference  
voltage, or buffered and scaled to output a software-selectable  
unipolar or bipolar voltage range (see Figure 52). The reference  
is used to provide internal offsets for range and gain scaling.  
The selectable output range is programmable through the  
digital interface.  
The voltage output amplifier is capable of driving capacitive loads  
of up to 1 μF with the addition of a nonpolarized compensation  
capacitor between the COMP1 and COMP2 pins.  
Without the compensation capacitor, up to 20 nF capacitive loads  
can be driven. Care should be taken to choose an appropriate  
value for the CCOMP capacitor. This capacitor, while allowing the  
AD5748 to drive higher capacitive loads and reduce overshoot,  
increases the settling time of the part and, therefore, affects the  
bandwidth of the system. Considered values of this capacitor  
should be in the range 100 pF to 4 nF depending on the trade-  
off required between settling time, overshoot, and bandwidth.  
AVDD  
RANGEDECODE  
FROM INTERFACE  
R2  
R3  
POWER-ON STATE OF THE AD5748  
T2  
A2  
On power-up, the AD5748 senses whether hardware or  
software mode is loaded and sets the power-up conditions  
accordingly.  
T1  
VIN  
IOUT  
RANGE  
SCALING  
A1  
IOUT  
VREF  
RSET  
In software SPI mode, the power-up state of the output is depen-  
dent on the state of the CLEAR pin. If the CLEAR pin is pulled  
high, then the part powers up, driving an active 0 V on the  
output. If the CLEAR pin is pulled low, then the part powers up  
with the voltage output channel in tristate mode. In both cases, the  
current output channel powers up in a tristate condition (0 mA).  
This allows the voltage and current outputs to be connected  
together if desired.  
Figure 51. Current Output Configuration  
RANGE DECODE  
FROM INTERFACE  
VSENSE+  
VOUT  
VIN  
(0V TO 4.096V)  
VOUT RANGE  
SCALING  
VREF  
VOUT  
SHORT FAULT  
VSENSE–  
To put the part into normal operation, the user must set the  
OUTEN bit in the control register to enable the output and, in  
the same write, set the output range configuration using the R3  
to R0 range bits. If the CLEAR pin is still high (active) during  
this write, the part automatically clears to its normal clear state  
as defined by the programmed range and by the CLRSEL pin or  
CLRSEL bit (see the Asynchronous Clear (CLEAR) section for  
more details). The CLEAR pin must be taken low to operate the  
part in normal mode.  
Figure 52. Voltage Output  
DRIVING INDUCTIVE LOADS  
When driving inductive or poorly defined loads, connect a 0.01 μF  
capacitor between IOUT and GND. This ensures stability with  
loads beyond 50 mH. There is no maximum capacitance limit.  
The capacitive component of the load may cause slower settling.  
Voltage Output Amplifier  
The voltage output amplifier is capable of generating both  
unipolar and bipolar output voltages. It is capable of driving a  
load of 1 kΩ in parallel with 1.2 μF (with an external compensa-  
tion capacitor on the COMP1 and COMP2 pins). The source  
and sink capabilities of the output amplifier can be seen in  
Figure 16. The slew rate is 2 V/μs.  
The CLEAR pin is typically driven directly from a microcontroller.  
In cases where the power supply for the AD5748 supply may be  
independent of the microcontroller power supply, the user can  
connect a weak pull-up resistor to DVCC or a pull-down resistor  
to ground to ensure that the correct power-up condition is  
achieved independent of the microcontroller. A 10 kΩ pull-  
up/pull-down resistor on the CLEAR pin should be sufficient  
for most applications.  
Internal to the device, there is a 2.5 MΩ resistor connected  
between the VOUT and VSENSE+ pins and similarly between  
the VSENSE− pin and the internal device ground. Should a  
fault condition occur, these resistors act to protect the AD5748  
by ensuring that the amplifier loop is closed so that the part  
does not enter into an open-loop condition.  
If hardware mode is selected, the part powers up to the condi-  
tions defined by the R3 to R0 range bits and the status of the  
OUTEN or CLEAR pin. It is recommended to keep the output  
disabled when powering up the part in hardware mode.  
The VSENSE− pin can work in a common-mode range of 3 V  
with respect to the remote load ground point.  
The current and voltage are output on separate pins and cannot  
be output simultaneously. This allows the user to tie both the  
current and voltage output pins together and configure the end  
system as a single-channel output.  
Rev. A | Page 24 of 32  
 
 
 
 
 
AD5748  
disabled, both the current and voltage channels go into tristate.  
The user must set the OUTEN bit to enable the output and  
simultaneously set the output range configuration.  
DEFAULT REGISTERS AT POWER-ON  
The AD5748 power-on reset circuit ensures that all registers are  
loaded with zero code.  
In hardware mode, the output can be enabled or disabled using  
the OUTEN pin. When the output is disabled, both the current  
and voltage channels both go into tristate. The user must write  
to the OUTEN pin to enable the output. It is recommended  
that the output be disabled when changing the ranges.  
In software SPI mode, the part powers up with all outputs dis-  
abled (OUTEN bit = 0). The user must set the OUTEN bit in  
the control register to enable the output and, in the same write,  
set the output range configuration using the R3 to R0 bits.  
If hardware mode is selected, the part powers up to the  
conditions defined by the R3 to R0 bits and the status of the  
OUTEN pin. It is recommended to keep the output disabled  
when powering up the part in hardware mode.  
SOFTWARE CONTROL  
Software control is enabled by connecting the HW SELECT pin  
to ground. In software mode, the AD5748 is controlled over a  
versatile 3-wire serial interface that operates at clock rates of up  
to 50 MHz. It is compatible with SPI, QSPI™, MICROWIRE,  
and DSP standards.  
RESET FUNCTION  
RESET  
In software mode, the part can be reset using the  
pin  
(active low) or the reset bit (reset = 1). A reset disables both the  
current and voltage outputs to their power-on condition. The  
user must write to the OUTEN bit to enable the output and, in  
Input Shift Register  
The input shift register is 16 bits wide. Data is loaded into the  
device MSB first as a 16-bit word under the control of a serial  
clock input, SCLK. Data is clocked in on the falling edge of  
SCLK. The input shift register consists of 16 control bits, as  
shown in Table 6. The timing diagram for this write operation  
is shown in Figure 2. The first three bits of the input shift register  
are used to set the hardware address of the AD5748 device on  
the printed circuit board (PCB). Up to eight devices can be  
addressed per board.  
RESET  
the same write, set the output range configuration. The  
pin is a level-sensitive input; the part stays in reset mode as long  
RESET  
as the  
pin is low. The reset bit clears to 0 following a  
reset command to the control register.  
In hardware mode, there is no reset. If using the part in hardware  
RESET  
mode, the  
pin should be tied high.  
OUTEN  
Bit D11, Bit D1, and Bit D0 must always be set to 0 during any  
write sequence.  
In software mode, the output can be enabled or disabled using  
the OUTEN bit in the control register. When the output is  
Table 6. Input Shift Register Contents for a Write Operation—Control Register  
MSB  
LSB  
D0  
0
D15  
D14  
D13  
D12  
D11  
D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
A2  
A1  
A0  
R/W  
0
R3  
R2  
R1  
R0  
CLRSEL  
OUTEN  
Clear  
RSET  
Reset  
0
Table 7. Input Shift Register Descriptions  
Bit  
Description  
A2, A1, A0  
Used in association with the AD2, AD1, and AD0 external pins to determine which part is being addressed by the system  
controller  
A2  
0
0
0
0
1
1
1
1
A1  
0
0
1
1
0
0
1
1
A0  
0
1
0
1
0
1
0
1
Function  
Addresses part with Pin AD2 = 0, Pin AD1 = 0, Pin AD0 = 0  
Addresses part with Pin AD2 = 0, Pin AD1 = 0, Pin AD0 = 1  
Addresses part with Pin AD2 = 0, Pin AD1 = 1, Pin AD0 = 0  
Addresses part with Pin AD2 = 0, Pin AD1 = 1, Pin AD0 = 1  
Addresses part with Pin AD2 = 1, Pin AD1 = 0, Pin AD0 = 0  
Addresses part with Pin AD2 = 1, Pin AD1 = 0, Pin AD0 = 1  
Addresses part with Pin AD2 = 1, Pin AD1 = 1, Pin AD0 = 0  
Addresses part with Pin AD2 = 1, Pin AD1 = 1, Pin AD0 = 1  
R/W  
Indicates a read from or a write to the addressed register  
Rev. A | Page 25 of 32  
 
 
 
AD5748  
Bit  
Description  
R3, R2, R1, R0  
Selects output configuration in conjunction with RSET  
RSET R3  
R2  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R1  
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R0  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output Configuration  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
4 mA to 21 mA (external 15 kΩ current sense resistor)  
0 mA to 21 mA (external 15 kΩ current sense resistor)  
N/A  
N/A  
N/A  
0 V to 5 V  
N/A  
N/A  
N/A  
N/A  
0 V to 10.5 V  
N/A  
10.5 V  
N/A  
N/A  
N/A  
4 mA to 21 mA (internal current sense resistor)  
0 mA to 21 mA (internal current sense resistor)  
N/A  
N/A  
N/A  
0 V to 5 V  
N/A  
N/A  
N/A  
N/A  
0 V to 10.5 V  
N/A  
10.5 V  
N/A  
N/A  
N/A  
CLRSEL  
Sets clear mode to zero scale or midscale. See the Asynchronous Clear (CLEAR) section  
CLRSEL  
Function  
0
1
Clear to 0 V  
Clear to midscale in unipolar mode; clear to zero scale in bipolar mode  
OUTEN  
Clear  
Output enable bit. This bit must be set to 1 to enable the outputs  
Software clear bit, active high  
RSET  
Select internal/external current sense resistor  
RSET  
Function  
1
0
Select internal current sense resistor; used with the R3 to R0 bits to select range  
Select external current sense resistor; used with the R3 to R0 bits to select range  
Reset  
Resets the part to its power-on state  
Rev. A | Page 26 of 32  
AD5748  
Readback Operation  
In hardware mode, there is no status register. The fault condi-  
tions (open circuit, short circuit, and overtemperature) are  
available on Pin IFAULT, Pin VFAULT, and Pin TEMP. If any  
one of these fault conditions is set, then a low is asserted on the  
specific fault pin. IFAULT, VFAULT, and TEMP are open-drain  
outputs and, therefore, can be connected together to allow the  
user to generate one interrupt to the system controller to commu-  
nicate a fault. If hardwired in this way, it is not possible to  
isolate which fault occurred in the system.  
Readback mode is activated by selecting the correct device address  
(A2, A1, A0) and then setting the R/ bit to 1. By default, the  
SDO pin is disabled. After having addressed the AD5748 for a  
W
W
read operation, setting R/ to 1 enables the SDO pin and SDO  
data is clocked out on the 5th rising edge of SCLK. After the data  
SYNC  
has been clocked out on SDO, a rising edge on  
disables  
(tristate) the SDO pin again. Status register data (see Table 8)  
and control register data are both available during the same  
read cycle.  
TRANSFER FUNCTION  
The AD5748 consists of an internal signal conditioning block  
that maps the analog input voltage to a programmed output  
range. The available analog input range is 0 V to 4.096 V.  
The status bits comprise four read-only bits. They are used to  
notify the user of specific fault conditions that occur, such as  
an open circuit or short circuit on the output, overtemperature  
error, or an interface error. If any of these fault conditions occurs,  
a hardware FAULT is also asserted low, which can be used as a  
hardware interrupt to the controller.  
For all ranges, both current and voltage, the AD5748 imple-  
ments a straight linear mapping function. 0 V maps to the  
lower end of the selected range; 4.096 V maps to the upper  
end of the selected range.  
See the Detailed Description of Features section for a full  
explanation of fault conditions.  
HARDWARE CONTROL  
Hardware control is enabled by connecting the HW SELECT  
pin to DVCC. In this mode, the R3, R2, R1, and R0 pins in  
conjunction with the RSET pin are used to configure the  
output range, as per Table 7.  
Table 8. Input Shift Register Contents for a Read Operation—Status Register  
MSB  
LSB  
D0  
D15  
D14 D13 D12 D11 D10 D9 D8 D7 D6  
A1 A0 R3 R2 R1 R0  
D5  
D4  
D3  
D2  
D1  
A2  
1
0
CLRSEL OUTEN RSET PEC error OVER TEMP IOUT fault VOUT fault  
Table 9. Status Bit Options  
Bit  
Description  
PEC Error  
VOUT Fault  
IOUT Fault  
OVER TEMP  
This bit is set if there is an interface error detected by CRC-8 error checking. See the Detailed Description of Features section.  
This bit is set if there is a short circuit on the VOUT pin.  
This bit is set is there is an open circuit on the IOUT pin.  
This bit is set if the AD5748 core temperature exceeds approximately 150°C.  
Rev. A | Page 27 of 32  
 
 
AD5748  
DETAILED DESCRIPTION OF FEATURES  
output stage has less than approximately 1 V of remaining  
drive capability. Thus, the fault output activates slightly  
before the compliance limit is reached. Because the compari-  
son is made within the feedback loop of the output amplifier,  
the output accuracy is maintained by its open-loop gain,  
and an output error does not occur before the fault output  
becomes active. If this fault is detected, the IFAULT pin is  
forced low.  
A short is detected on the voltage output pin (VOUT).  
The short-circuit current is limited to 15 mA. If this fault  
is detected, the VFAULT pin is forced low.  
If the core temperature of the AD5748 exceeds approx-  
imately 150°C. If this fault is detected, the TEMP pin is  
forced low.  
OUTPUT FAULT ALERT—SOFTWARE MODE  
In software mode, the AD5748 is equipped with one FAULT  
pin; this is an open-drain output allowing several AD5748  
devices to be connected together to one pull-up resistor for  
global fault detection. In software mode, the FAULT pin is  
forced active low by any one of the following fault scenarios:  
•
The voltage at IOUT attempts to rise above the compliance  
range, due to an open-loop circuit or insufficient power  
supply voltage. The internal circuitry that develops the  
fault output avoids using a comparator with window limits  
because this requires an actual output error before the fault  
output becomes active. Instead, the signal is generated when  
the internal amplifier in the output stage has less than  
approximately 1 V of remaining drive capability. Thus,  
the fault output activates slightly before the compliance  
limit is reached. Because the comparison is made within  
the feedback loop of the output amplifier, the output  
accuracy is maintained by its open-loop gain, and an output  
error does not occur before the fault output becomes active.  
A short is detected on the voltage output pin (VOUT). The  
short-circuit current is limited to 15 mA.  
•
•
VOLTAGE OUTPUT SHORT-CIRCUIT PROTECTION  
Under normal operation, the voltage output sinks and sources  
up to 12 mA and maintains the specified operation. The maxi-  
mum current that the voltage output delivers is 15 mA; this is  
the short-circuit current.  
•
•
ASYNCHRONOUS CLEAR (CLEAR)  
CLEAR is an active high clear that allows the voltage output  
to be cleared to either zero-scale code or midscale code and is  
user-selectable via the CLRSEL pin or the CLRSEL bit of the  
input shift register, as described in Table 7. (The clear select  
feature is a logical OR function of the CLRSEL pin and the  
CLRSEL bit.) The current loop output clears to the bottom of  
its programmed range. When the CLEAR signal is returned  
low, the output returns to its programmed value or a new value  
if programmed. A clear operation can also be performed via the  
clear command in the control register.  
An interface error is detected due to a packet error  
checking (PEC) failure. See the Packet Error Checking  
section.  
•
If the core temperature of the AD5748 exceeds  
approximately 150°C.  
OUTPUT FAULT ALERT—HARDWARE MODE  
In hardware mode, the AD5748 is equipped with three fault  
pins: VFAULT, IFAULT, and TEMP. These are open-drain  
outputs allowing several AD5748 devices to be connected  
together to one pull-up resistor for global fault detection. In  
hardware control mode, these fault pins are forced active by  
any one of the following fault scenarios:  
Table 10. CLRSEL Options  
Output Clear Value  
Unipolar Output  
CLRSEL Voltage Range  
Unipolar Current Output Range  
•
Open-circuit detect. The voltage at IOUT attempts to rise  
above the compliance range, due to an open-loop circuit  
or insufficient power supply voltage. The internal circuitry  
that develops the fault output avoids using a comparator  
with window limits because this requires an actual output  
error before the fault output becomes active. Instead, the  
signal is generated when the internal amplifier in the  
0
0 V  
Zero scale; for example:  
4 mA on the 4 mA to 21 mA range  
0 mA on the 0 mA to 21 mA range  
Midscale; for example:  
12.5 mA on the 4 mA to 21 mA range  
10.5 mA on the 0 mA to 21 mA range  
1
Midscale  
Rev. A | Page 28 of 32  
 
 
 
AD5748  
CURRENT SETTING RESISTOR  
PACKET ERROR CHECKING  
Referring to Figure 1, RSET is an internal sense resistor as part of  
the voltage-to-current conversion circuitry. The nominal value  
of the internal current sense resistor is 15 kΩ. To allow for over-  
range capability in current mode, the user can also select the  
internal current sense resistor to be 14.7 kΩ, giving a nominal  
2ꢀ overrange capability. This feature is available in the 0 mA  
to 21 mA and 4 mA to 21 mA current ranges.  
To verify that data has been received correctly in noisy environ-  
ments, the AD5748 offers the option of error checking based on  
an 8-bit (CRC-8) cyclic redundancy check. The device controlling  
the AD5748 should generate an 8-bit frame check sequence  
using the following polynomial:  
C(x) = x8 + x2 + x1 + 1  
This is added to the end of the data-word, and 24 data bits are  
The stability of the output current value over temperature is  
dependent on the stability of the value of RSET. As a method of  
improving the stability of the output current over temperature,  
an external low drift resistor can be connected to the REXT1  
and REXT2 pins of the AD5748, which can be used instead of  
the internal resistor. The external resistor is selected via the  
input shift register. If the external resistor option is not used,  
the REXT1 and REXT2 pins should be left floating.  
SYNC  
sent to the AD5748 before taking  
receives a 24-bit data frame, it performs the error check when  
SYNC  
high. If the AD5748  
goes high. If the check is valid, then the data is written  
to the selected register. If the error check fails, the FAULT pin  
goes low and Bit D3 of the status register is set. After reading  
this register, this error flag is cleared automatically and the  
FAULT pin goes high again.  
UPDATE ON SYNC HIGH  
SYNC  
SCLK  
D15  
(MSB)  
D0  
(LSB)  
16-BIT DATA  
SDIN  
16-BIT DATA TRANSER—NO ERROR CHECKING  
UPDATE AFTER SYNC HIGH  
ONLY IF ERROR CHECK PASSED  
SYNC  
SCLK  
SDIN  
D23  
(MSB)  
D8  
(LSB)  
D7  
D0  
8-BIT FCS  
16-BIT DATA  
FAULT GOES LOW IF  
ERROR CHECK FAILS  
FAULT  
16-BIT DATA TRANSER WITH ERROR CHECKING  
Figure 53. PEC Error Checking Timing  
Rev. A | Page 29 of 32  
 
 
AD5748  
APPLICATIONS INFORMATION  
TRANSIENT VOLTAGE PROTECTION  
LAYOUT GUIDELINES  
In any circuit where accuracy is important, careful consideration  
of the power supply and ground return layout helps to ensure  
the rated performance. The PCB on which the AD5748 is  
mounted should be designed so that the AD5748 lies on the  
analog plane.  
The AD5748 contains ESD protection diodes that prevent damage  
from normal handling. The industrial control environment can,  
however, subject I/O circuits to much higher transients. To protect  
the AD5748 from excessively high voltage transients, external  
power diodes and a surge current limiting resistor may be  
required, as shown in Figure 54. The constraint on the resistor  
value is that, during normal operation, the output level at IOUT  
must remain within its voltage compliance limit of AVDD − 2.75 V,  
and the two protection diodes and resistor must have appropri-  
ate power ratings. Further protection can be added with transient  
voltage suppressors if needed.  
The AD5748 should have ample supply bypassing of 10 μF  
in parallel with 0.1 μF on each supply located as close to the  
package as possible, ideally right up against the device. The  
10 μF capacitors are the tantalum bead type. The 0.1 μF capaci-  
tor should have low effective series resistance (ESR) and low  
effective series inductance (ESI) such as the common ceramic  
types, which provide a low impedance path to ground at high  
frequencies to handle transient currents due to internal logic  
switching.  
AVDD  
AVDD  
In systems where there are many devices on one board, it is often  
useful to provide some heat sinking capability to allow the power  
to dissipate easily.  
AD5748  
R
P
IOUT  
R
LOAD  
AD5748  
AVSS  
Figure 54. Output Transient Voltage Protection  
THERMAL CONSIDERATIONS  
It is important to understand the effects of power dissipation  
on the package and on junction temperature. The internal junction  
temperature should not exceed 125°C. The AD5748 is packaged  
in a 32-lead LFCSP 5, 5 mm × 5 mm package. The thermal  
impedance, θJA, is 28°C/W. It is important that the devices are  
not operated under conditions that cause the junction tempera-  
ture to exceed its junction temperature.  
AVSS  
PLANE  
BOARD  
Figure 55. Paddle Connection to Board  
Worst-case conditions occur when the AD5748 is operated from  
the maximum AVDD (26.4 V) while driving the maximum  
current (24 mA) directly to ground. The quiescent current of the  
AD5748 should also be taken into account, nominally ~4 mA.  
The AD5748 has an exposed paddle beneath the device. This  
paddle is connected to the AVSS supply for the part. For opti-  
mum performance, special considerations should be used to  
design the motherboard and to mount the package. For enhanced  
thermal, electrical, and board level performance, the exposed  
paddle on the bottom of the package is soldered to the correspond-  
ing thermal land paddle on the PCB. Thermal vias are designed  
into the PCB land paddle area to further improve heat dissipation.  
The following calculations estimate maximum power dissipation  
under these worst-case conditions, and determine maximum  
ambient temperature based on the power dissipation:  
Power Dissipation = 26.4 V × 28 mA = 0.7392 W  
Temp Increase = 28°C × 0.7392 W = 20.7°C  
The AVSS plane on the device can be increased (as shown in  
Figure 55) to provide a natural heat sinking effect.  
Maximum Ambient Temp = 125°C − 20.7°C = 104.3°C  
These figures assume that proper layout and grounding  
techniques are followed to minimize power dissipation,  
as outlined in the Layout Guidelines section.  
Rev. A | Page 30 of 32  
 
 
 
 
AD5748  
GALVANICALLY ISOLATED INTERFACE  
MICROPROCESSOR INTERFACING  
In many process control applications, it is necessary to provide  
an isolation barrier between the controller and the unit being  
controlled to protect and isolate the controlling circuitry from  
any hazardous common-mode voltages that may occur. The  
iCoupler® family of products from Analog Devices, Inc., provides  
voltage isolation in excess of 5.0 kV. The serial loading structure  
of the AD5748 makes it ideal for isolated interfaces because the  
number of interface lines is kept to a minimum. Figure 56 shows  
a 4-channel isolated interface using an ADuM1400. For further  
information, visit www.analog.com/icouplers.  
Microprocessor interfacing to the AD5748 is via a serial bus  
that uses a protocol compatible with microcontrollers and DSP  
processors. The communications channel is a 3-wire (minimum)  
SYNC  
interface consisting of a clock signal, a data signal, and a  
signal. The AD5748 requires a 16-bit data-word with data valid  
on the falling edge of SCLK.  
CONTROLLER  
ADuM14001  
V
V
V
V
V
V
V
V
OA  
OB  
OC  
OD  
IA  
TO  
SERIAL  
SCLK  
CLOCK OUT  
IB  
IC  
ID  
TO  
SDIN  
SERIAL  
DATA OUT  
TO  
SYNC  
SYNC OUT  
TO  
CLEAR  
CONTROL OUT  
1
ADDITIONAL PINS OMITTED FOR CLARITY.  
Figure 56. Isolated Interface  
Rev. A | Page 31 of 32  
 
 
AD5748  
OUTLINE DIMENSIONS  
5.00  
BSC SQ  
0.60 MAX  
0.60 MAX  
PIN 1  
INDICATOR  
25  
24  
32  
1
PIN 1  
INDICATOR  
0.50  
BSC  
TOP  
VIEW  
3.25  
3.10 SQ  
2.95  
EXPOSED  
PAD  
(BOTTOM VIEW)  
4.75  
BSC SQ  
0.50  
0.40  
0.30  
17  
16  
8
9
0.25 MIN  
0.80 MAX  
0.65 TYP  
3.50 REF  
12° MAX  
FOR PROPER CONNECTION OF  
THE EXPOSED PAD, REFER TO  
THE PIN CONFIGURATION AND  
FUNCTION DESCRIPTIONS  
0.05 MAX  
0.02 NOM  
1.00  
0.85  
0.80  
0.30  
0.23  
0.18  
COPLANARITY  
0.08  
0.20 REF  
SECTION OF THIS DATA SHEET.  
SEATING  
PLANE  
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2  
Figure 57. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]  
5 mm × 5 mm Body, Very Thin Quad  
(CP-32-2)  
Dimensions shown in millimeters  
ORDERING GUIDE  
Analog Input  
Range  
External  
Reference  
Temperature  
Range  
Package  
Package Description Option  
Model1  
TUE Accuracy  
AD5748ACPZ  
AD5748ACPZ-RL7  
0.3% VOUT  
0.3% VOUT  
,
,
0.5% IOUT  
0.5% IOUT  
0 V to 4.096 V  
0 V to 4.096 V  
4.096 V  
4.096 V  
−40°C to +105°C  
−40°C to +105°C  
32-Lead LFCSP_VQ  
32-Lead LFCSP_VQ  
CP-32-2  
CP-32-2  
1 Z = RoHS Compliant Part.  
©2010 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D08922-0-5/10(A)  
Rev. A | Page 32 of 32  
 
 

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