AD5750 [ADI]
Industrial Current/Voltage Output Driver, Programmable Ranges; 工业电流/电压输出驱动器，可编程范围
| 型号： | AD5750 |
| 厂家： | 
ADI |
| 描述： | Industrial Current/Voltage Output Driver, Programmable Ranges |
| 文件： | 总25页 (文件大小：252K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Industrial Current/Voltage
Output Driver,
Programmable Ranges
Preliminary Technical Data
AD5750
Voltage output is provided from a separate pin that can be
configured to provide 0V to 5V, 0V to 10V, ±5V or ±10V
output ranges. An over-range of 20% is available on the voltage
ranges.
FEATURES
Current Output Ranges: 4–20mA, 0–20mA or 0–24mA,
20ma, 24ma
B Grade - 0.1% Total Unadjusted Error (TUE)
A Grade - 0.3% Total Unadjusted Error (TUE)
5ppm/°C Output Drift
Analog outputs are short and open circuit protected and can
drive capacitive loads of 1uF and inductive loads of 0.1H.
The device is specified to operate with a power supply range
from ±12 V to ±24 V. Output loop compliance is 0 V to AVDD
– 2.5 V.
Voltage Output Ranges: 0-5V, 0-10V, 5V, 10V,
20% over-range
B Grade - 0.1% Total Unadjusted Error (TUE)
A Grade - 0.3% Total Unadjusted Error (TUE)
Flexible Serial Digital Interface
On-Chip Output Fault Detection
PEC Error Checking
The flexible serial interface is SPI and MICROWIRE
compatible and can be operated in 3-wire mode to minimize the
digital isolation required in isolated applications. The interface
also features an optional PEC error checking feature using
CRC-8 error checking, useful in industrial environments where
data communication corruption can occur.
Asynchronous CLEAR Function
Power Supply Range
AVDD : = +12V to +24V (+/-10%)
AVSS : = -12V to -24V (+/-10%)
Output Loop Compliance to AVDD – 2.5 V
Temperature Range: -40°C to +105°C
LFCSP Packages
The device also includes a power-on-reset function ensuring
that the device powers up in a known state and an
asynchronous CLEAR pin which sets the outputs to zero-scale /
mid-scale voltage output or the low end of the selected current
range.
APPLICATIONS
A HW SELECT pin is used to configure the part for hardware
or software mode on power up.
Process Control
Actuator Control
PLC
The total output error is typically ±0.1% in both current mode
and voltage mode.
GENERAL DESCRIPTION
The AD5750 is a single channel, low-cost, precision,
voltage/current output driver with hardware or software
programmable output ranges. The software ranges are
configured via an SPI/Microwire compatible serial interface.
The AD5750 targets applications in PLC and industrial process
control. The analog input to the AD5750 is provided from a
low voltage, single supply digital-to-analog converter and is
internally conditioned to provide the desired output
current/voltage range.
Table 1. Related Devices
Part Number
Description
AD5422
Single Channel, 16-Bit, Serial
Input Current Source and
Voltage Output DAC
The output current range is programmable across five current
ranges - 4–20mA, 0–20mA or 0–24mA, 20mꢀ ꢀnd 24mꢀ.
Rev. PrC
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
AD5750
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
HARDWARE CONTROL:........................................................ 20
Transfer Function....................................................................... 21
Features............................................................................................ 22
output fault alert – SOFTWARE MODE ................................ 22
output fault alert – HARDWARE MODE............................... 22
voltage output short circuit protection.................................... 22
Asynchronous Clear (CLEAR)................................................. 22
External current setting resistor............................................... 22
Applications Information.............................................................. 24
Transient voltage protection ..................................................... 24
Layout Guidelines....................................................................... 24
Galvanically Isolated Interface ................................................. 24
Microprocessor Interfacing....................................................... 24
Outline Dimensions....................................................................... 25
Ordering Guide .......................................................................... 25
Applications....................................................................................... 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Functional Block Diagram .............................................................. 3
Specifications..................................................................................... 4
Timing Characteristics ................................................................ 8
Absolute Maximum Ratings.......................................................... 10
ESD Caution................................................................................ 10
Pin Configuration and Function Descriptions........................... 11
Typical Performance Characteristics ........................................... 13
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 15
CURRENT OUTPUT Architecture......................................... 17
OUTEN........................................................................................ 17
Software control:......................................................................... 18
REVISION HISTORY
PrC – Preliminary Version. May 6, 2008
Rev. PrC | Page 2 of 25
Preliminary Technical Data
FUNCTIONAL BLOCK DIAGRAM
AD5750
GND
AVDD
COMP1 COMP2
DVCC GND
CLEAR
CLRSEL
VSENSE+
INPUT SHIFT
REGISTER
AND
CONTROL
LOGIC
SCLK/OUTEN*
SDIN/R0*
SYNC/RSEL*
SDO/VFAULT*
VOUT RANGE
SCALING
VOUT
VOUT SHORT FAULT
VSENSE-
HW SELECT
VIN
STATUS REG
VDD
R2
R3
VREF
IOUT RANGE
SCALING
RESET
REXT1
REXT2
RSET
Vx
IOUT
OVERTEMP
VOUT SHORT FAULT
IOUT OPEN FAULT
FAULT/TEMP*
NC/IFAULT*
POWER
ON
RESET
VSS
OUTPUT RANGE ERROR
AD5750
IOUT OPEN FAULT
AVSS
AD1/R2* AD0/R3*
AD2/R1*
Figure 1. Functional Block Diagram
* Denotes shared pin. Software mode denoted by regular text, hardware mode denoted by bold
text. E.G. for FAULT/TEMP pin, in software mode this pin will take on FAULT function. In
Hardware mode, this pin will take on TEMP function.
Rev. PrC | Page 3 of 25
AD5750
Preliminary Technical Data
SPECIFICATIONS
AVDD/AVSS=±±2V ꢀ(/ꢁ±0ꢂ% to ±2ꢃV ꢀ(/ꢁ±0ꢂ% , DVCC =2.7 V to 5.5 V, GND = 0 V. R
L
= 2 kΩ, C
L
= 200 pF, IOUT : R
L
= 300Ω,
HL =
50mH; All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
B grade1
A grade2
Unit
Test Conditions/Comments
0 to 4.096
1
0 to 4.096
1
V
INPUT VOLTAGE RANGE
Input Leakage Current
uA max
VOLTAGE OUTPUT
Output Voltage Ranges
0 to 5
0 to 10
0 to 5
0 to 10
V
V
AVDD needs to have minimum 1.1v headroom, or
> +11.1v.
-5 to +5
-10 to +10
-5 to +5
-10 to +10
V
V
AVDD/AVSS needs to have minimum 1.1v
headroom, or > +/-11.1v.
ACCURACY
Output unloaded
Bipolar Output
Total Unadjusted Error
(TUE)
0.1
0.3
% FSR max
Over temperature and supplies.
Relative Accuracy (INL)
Bipolar Zero Error
Bipolar Zero TC
Offset Error
Zero Scale Error
Zero Scale TC
Gain Error
Gain Error TC
Full Scale Error
Full Scale Error TC
0.02
0.01
TBD
0.015
0.015
TBD
0.005
TBD
0.02
0.01
TBD
0.015
0.015
TBD
0.005
TBD
% FSR max
% FSR typ
ppm % FSR max
% FSR typ
% FSR typ
ppm % FSR max
% FSR typ
ppm % FSR max
% FSR typ
Error at analog input = mid scale
Error at analog input = 10mv
Error at analog input = 0.0v
(Ideal Span – Measured Span)/Ideal Span
Error at analog input = 4.096v (FS)
0.015
TBD
0.015
TBD
ppm % FSR max
Unipolar Output
Total Unadjusted Error
(TUE)
0.1
0.1
% FSR max
Over temperature and supplies.
Relative Accuracy (INL)
Offset Error
Zero Scale Error
Zero Scale TC
Gain Error
Gain Error TC
0.02
0.01
0.015
TBD
0.003
TBD
0.01
0.02
0.01
0.015
TBD
0.003
TBD
0.01
% FSR max
% FSR typ
% FSR typ
ppm % FSR max
% FSR typ
ppm % FSR max
% FSR typ
ppm % FSR max
Error at analog input = 10mv
Error at analog input = 0.0v
(Ideal Span – Measured Span)/Ideal Span
Error at analog input = 4.096v (FS)
Full Scale Error
Full Scale Error TC
TBD
TBD
Output Voltage Over-Ranges
0 to 6
0 to 6
V
Programmable Over-Ranges.
See Features Section.
0 to 12
0 to 12
-6 to +6
-12 to +12
0.02
V
V
V
-6 to +6
-12 to +12
Overrange
Relative Accuracy (INL)
OUTPUT CHARACTERISTICS
0.02
% FSR max
Rev. PrC | Page 4 of 25
Preliminary Technical Data
AD5750
Parameter
B grade1
A grade2
Unit
Test Conditions/Comments
Short-Circuit Current
Load Conditions
Resistance
15
15
mA max
1
1
K Ohm min
For Specified Performance
Capacitance Load Stability
RL = ∞
RL = 2 kΩ
20
TBD
1
20
TBD
1
nF max
nF max
μF max
RL = ∞
External compensation capacitor of 4nF
connected.
0.1% Settling Time
10
10
Us
Specified with 200pF load
Slew Rate
1
1
V/μs typ
Output Noise
TBD
80
100
TBD
80
100
μV rms max
μV rms max
nV/√Hz typ
0.1 Hz to 10 Hz Bandwidth
100 kHz Bandwidth
Measured at 10KHz
Output Noise Spectral
Density
DC Output Impedance
DC PSRR
AC PSRR
0.3
10
TBD
0.3
10
TBD
Ω typ
μV/V
dB
200mV 50/60Hz Sinewavesuperimposed on
power supply voltage.
Power-On Glitch Energy
CURRENT OUTPUT
10
10
nV-sec typ
Output Current Ranges
0 to 24
0 to 20
4 to 20
20
0 to 24
0 to 20
4 to 20
20
mA
mA
mA
mA
mA
24
24
ACCURACY
Total Unadjusted Error (TUE)
TUE TC
0.1
5
0.3
5
% FSR max
ppm max
With External Precision Resistor
With External Precision Resistor
Bipolar Output
Relative Accuracy (INL)
Bipolar Zero Error
Bipolar Zero TC
Offset Error
0.02
0.0325
TBD
0.0175
0.0175
TBD
0.01
TBD
0.0125
TBD
0.02
0.0325
TBD
0.0175
0.0175
TBD
0.01
TBD
0.0125
TBD
% FSR max
% FSR typ
ppm % FSR max
% FSR typ
% FSR typ
ppm % FSR max
% FSR typ
ppm % FSR max
% FSR typ
Error at analog input = mid scale
Error at analog input = 10mv
Error at analog input = 0.0v
Zero Scale Error
Zero Scale TC
Gain Error
Gain Error TC
Full Scale Error
Full Scale Error TC
(Ideal Span – Measured Span)/Ideal Span
Error at analog input = 4.096v (FS)
ppm % FSR max
Unipolar Output
Relative Accuracy (INL)
Offset Error
0.02
0.01
0.01
TBD
0.15
TBD
0.01
TBD
0.02
0.01
0.01
TBD
0.15
TBD
0.01
TBD
% FSR max
% FSR typ
% FSR typ
ppm % FSR max
% FSR typ
ppm % FSR max
% FSR typ
ppm % FSR max
Error at analog input = 10mv
Error at analog input = 0.0v
Zero Scale Error
Zero Scale TC
Gain Error
Gain Error TC
Full Scale Error
Full Scale Error TC
(Ideal Span – Measured Span)/Ideal Span
Error at analog input = 4.096v (FS)
Rev. PrC | Page 5 of 25
AD5750
Preliminary Technical Data
Parameter
B grade1
A grade2
Unit
Test Conditions/Comments
Total Unadjusted Error (TUE)
TUE TC
0.3
20
50
0.3
20
50
% FSR max
ppm typ
ppm max
With Internal Resistor
With Internal Resistor
Bipolar Output
Relative Accuracy (INL)
Bipolar Zero Error
Bipolar Zero TC
Offset Error
0.02
0.0325
TBD
0.01
0.01
TBD
0.003
TBD
0.01
TBD
0.02
0.0325
TBD
0.01
0.01
TBD
0.003
TBD
0.01
TBD
% FSR max
% FSR typ
ppm % FSR max
% FSR typ
% FSR typ
ppm % FSR max
% FSR typ
ppm % FSR max
% FSR typ
Error at analog input = mid scale
Error at analog input = 10mv
Error at analog input = 0.0v
Zero Scale Error
Zero Scale TC
Gain Error
Gain Error TC
Full Scale Error
Full Scale Error TC
(Ideal Span – Measured Span)/Ideal Span
Error at analog input = 4.096v (FS)
ppm % FSR max
Unipolar Output
Relative Accuracy (INL)
Offset Error
0.02
0.01
0.01
TBD
0.005
TBD
0.01
TBD
0.02
0.01
0.01
TBD
0.005
TBD
0.01
TBD
% FSR max
% FSR typ
% FSR typ
ppm % FSR max
% FSR typ
ppm % FSR max
% FSR typ
ppm % FSR max
Error at analog input = 10mv
Error at analog input = 0.0v
Zero Scale Error
Zero Scale TC
Gain Error
Gain Error TC
Full Scale Error
Full Scale Error TC
(Ideal Span – Measured Span)/Ideal Span
Error at analog input = 4.096v (FS)
CURRENT MODE
OVERRANGES
0 to 24.5
0 to 24.5
mA
SEE FEATURES SECTION
0 to 20.4
4 to 20.4
0 to 20.4
4 to 20.4
mA
mA
SEE FEATURES SECTION
SEE FEATURES SECTION
OUTPUT CHARACTERISTICS
Current Loop Compliance
Voltage
AVDD – 2.5
AVDD – 2.5
V max
Resistive Load
See
See
kΩ max
Chosen such that compliance is not exceeded.
Comment
Comment
Inductive Load
0.1% Settling Time
0.1
10
0.1
10
H max
us
DC PSRR
Output Impedance
1
25
1
25
μA/V max
MΩ typ
REFERENCE INPUT
Reference Input
Reference Input Voltage
Input Leakage Current
DIGITAL INPUTS
4.096
1
4.096
1
V nom
uA max
1% for specified performance
DVCC = 2.7 V to 5.5 V, JEDEC compliant
VIH, Input High Voltage
VIL, Input Low Voltage
Input Current
2
0.8
1
2
0.8
1
V min
V max
μA max
pF typ
Per pin
Per pin
Pin Capacitance
10
10
Rev. PrC | Page 6 of 25
Preliminary Technical Data
AD5750
Parameter
B grade1
A grade2
Unit
Test Conditions/Comments
DIGITAL OUTPUTS
FAULT, IFAULT, TEMP, VFAULT
VOL, Output Low Voltage
VOL, Output Low Voltage
VOH, Output High Voltage
0.4
0.6
3.6
0.4
0.6
3.6
V max
V typ
V min
10kΩ pull-up resistor to DVCC
@ 2.5 Ma
10kΩ pull-up resistor to DVCC
SDO
VOL, Output Low Voltage
VOH, Output High Voltage
High Impedance Leakage
current
0.5
DVCC-0.5
TBD
0.5
DVCC-0.5
TBD
V max
V min
ua max
Sinking 200ua
Sourcing 200ua
High Impedance Output
Capacitance
20
20
pF max
POWER REQUIREMENTS
AVDD
AVSS
12 to 24
-12 to 24
12 to 24
-12 to 24
V min to V max
V min to V max
+/-10%
+/-10%
DVCC
Input Voltage
AVDD
2.7 to 5.5
TBD
2.7 to 5.5
TBD
V min to V max
mA
Internal supply disabled
Output unloaded
AVSS
TBD
TBD
mA
Output unloaded
DICC
TBD
TBD
TBD
TBD
mA max
mW typ
VIH = DVCC, VIL = GND, TBD mA typ
Power Dissipation
1 Temperature range: -40°C to +105°C; typical at +25°C.
2 Temperature range: -40°C to +105°C; typical at +25°C.
Rev. PrC | Page 7 of 25
AD5750
Preliminary Technical Data
TIMING CHARACTERISTICS
AVDD/AVSS=±±2V ꢀ(/ꢁ±0ꢂ% to ±2ꢃV ꢀ(/ꢁ±0ꢂ% , DVCC =2.7 V to 5.5 V, GND = 0 V. R
L
= 2 kΩ, C
L
= 200 pF, IOUT : R
L
= 300Ω,
HL =
50mH; All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2
Limit at TMIN, TMAX
Unit
Description
t1
t2
t3
t4
33
13
13
13
13
13
6
0
1
25
25
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
μs max
ns min
ns max
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
16th SCLK falling edge to SYNC rising edge
Minimum SYNC high time (WRITE MODE)
Data setup time
t5
t6
t7
t8
t10 , t9
t11
t12
Data hold time
CLEAR pulse high/low activation time
Minimum SYNC high time (READ MODE)
SCLK rising edge to SDO valid (SDO CL=20pf)
1 Guaranteed by characterization. Not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.
200µA
I
OL
TO OUTPUT
PIN
VOH(min)-VOL(max)
2
C
L
15pF
200µA
I
OH
SDO Load Timing.
Rev. PrC | Page 8 of 25
Preliminary Technical Data
AD5750
t1
SCLK
1
2
16
t2
t3
t6
t5
t4
SYNC
SDIN
t8
t7
DB15
DB0
CLEAR
t10
V
OUT
t9
Figure 2. Write Mode Timing Diagram
16
1
2
SCLK
SYNC
t11
X
A1
A0
X
X
X
X
X
A2
X
X
X
X
R=1
0
X
SDIN
SDO
t12
X
OVER
TEMP
VOUT
Fault
PEC
Error
IOUT
Fault
CLRSEL
OUTEN
RSEL
R0
X
X
X
R3
R2
R1
X
Figure 3. Readback Mode Timing Diagram
Rev. PrC | Page 9 of 25
AD5750
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise noted.
Transient currents of up to 100 mA do not cause SCR latch-up.
Table ꢃ.
Parameter
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
AVDD to GND
AVSS to GND
AVDD to AVSS
DVCC to GND
+VSENSE to GND
-VSENSE to GND
Digital Inputs to GND
−0.3V to 30v
+0.3 V to -30v
-0.3V to 60v
−0.3 V to +7 V
AVSS to AVDD
+/-5.0v
ESD CAUTION
−0.3 V to DVCC + 0.3 V or 7 V
(whichever is less)
Digital Outputs to GND
−0.3 V to DVCC + 0.3 V or 7V
(whichever is less)
REFIN/REFOUT to GND
VIN to GND
−0.3 V to +5 V
−0.3 V to +5 V
VOUT to GND
AVSS to AVDD
IOUT to GND
−0.3V to AVDD, +0.3V to AVSS
Operating Temperature Range
Industrial
−40°C to +105°C
−65°C to +150°C
125°C
Storage Temperature Range
Junction Temperature (TJ max)
32-Lead LFCSP Package
θJA Thermal Impedance
Lead Temperature
Soldering
28°C/W
JEDEC Industry Standard
J-STD-020
Rev. PrC | Page 10 of 25
Preliminary Technical Data
AD5750
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
24 VSENSE+
SDO/VFAULT
CLRSEL
PIN 1
INDICATOR
VOUT
VSENSE-
23
22
CLEAR
DVCC
GND
21 AVSS
COMP1
COMP2
IOUT
20
19
18
17
TOP VIEW
SYNC/RSEL
SCLK/OUTEN
SDIN/R0
AVDD
NC = NO CONNECT
Figure 4. LFCSP Pin Configuration
Table 5. Pin Function Descriptions
LFCSP Pin No.
Mnemonic
Description
1
SDO/VFAULT
In Software Mode, Serial Data Output. Used to clock data from the serial register in
readback mode. Data is clocked out on the rising edge of SCLK and is valid on the
falling edge of SCLK. Open Drain Output, must be connected to a pull up resistor.
In Hardware mode, acts as a SHORT circuit Fault alert pin. This pin is asserted low when
an SHORT circuit. Error is detected. Open drain output, must be connected to a pull-up
resistor.
2
3
CLRSEL
CLEAR
In Hardware or software mode, selects the clear value, either zero-scale or mid-scale
code. In Software mode, this pin is implemented as a logic OR with the internal CLRSEL
bit.
Active High Input. Asserting this pin sets the Output Current/Voltage to zero-scale code
or mid-scale code of range selected (user-selectable). CLEAR is a LOGIC OR with the
internal CLEAR bit.
4
5
6
DVCC
Digital Power Supply
Ground Connection.
GND
SYNC/RSEL
In Software Mode, Positive edge sensitive latch, a rising edge will parallel load the input
shift register data into the INPUT register, also updating the output.
In Hardware mode, this pin chooses whether internal/external current sense resistor is
used
7
8
9
SCLK/OUTEN
SDIN/RO
In Software Mode, Serial Clock Input. Data is clocked into the shift register on the falling
edge of SCLK. This operates at clock speeds up to 30 MHz.
In Hardware mode, this pin acts as an output enable pin.
In Software Mode, Serial Data Input. Data must be valid on the falling edge of SCLK.
In Hardware Mode, R0 is Range Decode Bit. This pin, in conjunction with R2, R3, R1
choose the output current/voltage range setting on the part.
AD2/R1
In Software Mode, AD2 is Device Addressing bit. This pin, in conjunction with AD1, AD0
allow up to 8 devices to be addressed on one bus.
In Hardware Mode, R1 is Range Decode Bit. This pin, in conjunction with R2, R3, R0
choose the output current/voltage range setting on the part.
10
AD1/R2
In Software Mode, AD1 is Device Addressing bit. This pin, in conjunction with AD2, AD0
allow up to 8 devices to be addressed on one bus.
Rev. PrC | Page 11 of 25
AD5750
Preliminary Technical Data
LFCSP Pin No.
Mnemonic
AD0/R3
Description
In Hardware Mode, R2 is Range Decode Bit. This pin, in conjunction with R3, R1, R0
choose the output current/voltage range setting on the part.
11
In Software Mode, AD0 is Device Addressing bit. This pin, in conjunction with AD1, AD2
allow up to 8 devices to be addressed on one bus.
In Hardware Mode, R3 is Range Decode Bit. This pin, in conjunction with R2, R1, R0
choose the output current/voltage range setting on the part.
12
13
REXT1
REXT 2
An external current setting resistor can be connected to this pin to improve the IOUT
temperature drift performance.
When using the Internal RSET resistor these pins must be left floating.
Reference Input
14
15
16
17
18
19
20
21
22
VREF
VIN
Analog Input (0-4.096v)
GND
Ground Connection.
AVDD
Positive Analog Supply Pin.
IOUT
COMP1
COMP2
AVSS
Current Output Pin
Optional compensation capacitor connection for the voltage output buffer
Optional compensation capacitor connection for the voltage output buffer
Negative Analog Supply Pin.
-VSENSE
Sense connection for the negative voltage output load connection. This pin must stay
within +/-3.0v of ground for correct operation.
23
VOUT
Buffered Analog Output Voltage.
24
+VSENSE
NC
Sense connection for the positive voltage output load connection.
No Connect Pin. Can be tied to GND.
25,26,27,28
29
HW SELECT
This part is used to configure the part to hardware/software mode.
HW SELECT = 0 selects Software Control.
HW SELECT = 1 selects Hardware Control.
30
31
RESET
Resets the part to its power on state.
FAULT/TEMP
In Software mode, acts as a general Fault alert pin. This pin is asserted low when an
open circuit, short circuit, over temperature or PEC Interface Error is detected. Open
drain output, must be connected to a pull-up resistor.
In Hardware mode, acts as an over temp FAULT pin. This pin is asserted low when an
over temperature Error is detected. Open drain output, must be connected to a pull-up
resistor.
32
NC/IFAULT
In Hardware mode, acts as a OPEN circuit Fault alert pin. This pin is asserted low when
an OPEN circuit. Error is detected. Open drain output, must be connected to a pull-up
resistor.
In Software mode, is a NC. Tie to GND.
Rev. PrC | Page 12 of 25
Preliminary Technical Data
AD5750
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 5.
Figure 8.
Figure 6.
Figure 9.
Figure 7.
Figure 10
Rev. PrC | Page 13 of 25
AD5750
Preliminary Technical Data
TERMINOLOGY
Output Voltage Settling Time
Current Loop Voltage Compliance
Output voltage settling time is the amount of time it takes for
the output to settle to a specified level for a full-scale input
change. A plot of settling time can be seen in Table TBD
The maximum voltage at the IOUT pin for which the output
currnet will be equal to the programmed value.
PowerꢁOn Glitch Energy
Slew Rate
Power-on glitch energy is the impulse injected into the analog
output when the AD5750 is powered-on. It is specified as the area
of the glitch in nV-sec.
The slew rate of a device is a limitation in the rate of change of
the output voltage. Slew rate is measured from 10% to 90% of
the output signal and is given in V/μs.
Power Supply Rejection Ratio ꢀPSRR%
PSRR indicates how the output is affected by changes in the
power supply voltage.
Total Unadjusted Error
Total unadjusted error (TUE) is a measure of the output error
taking all the various errors into account. TUE is expressed in %
FSR.
Rev. PrC | Page 14 of 25
AD5750
Preliminary Technical Data
THEORY OF OPERATION
Figures 11 and 12 shows a typical configuration of AD5750 in Software Mode (Figure 11) and in Hardware mode (Figure 12) in an
output module system. The HW SELECT pin chooses whether the part is configured in software or hardware mode. The analog input to
the AD5750 is provided from a low voltage, single supply digital-to-analog converter such as the AD5061 which provides an output
range of 0-4.096V. The supply and reference for the DAC, as well as the reference for the AD5750 can be supplied from a reference
such as the ADR392. The AD5750 can operate from supplies up to +26.4 volts.
In current mode, software selectable output ranges include ±20mA, ±24mA, 0-20 mA, 4mA–20mA or 0mA–24mA.
In voltage mode, software selectable output ranges include 0V–5V, 0V–10V, ±5V or ±10V. The current and voltage outputs are
available on separate pins. Only one output can be enabled at one time. The output range is selected by programming the range bits in
the control register.
VSS
VDD AGND
ADP1720
VSENSE+
VSENSE-
AD5750
ADR392
REFIN
VIN
VOUT
0-5V, 0-10V,
+/-5V, +/-10V
VOUT
RANGE
SCALE
VDD
REFIN
SCLK
SDI
SDO
SYNC1
AD566X
IOUT
MCU
IOUT
0-20ma, 0-24ma,
4-20ma, +/-20ma,
+/-24ma.
RANGE
SCALE
SERIAL
INTERFACE
VOUT SHORT FAULT
IOUT OPEN FAULT
OVERTEMP FAULT
RANGE ERROR
SYNC2
STATUS REGISTER
HW SELECT
FAULT
Figure 11. Typical System Configuration in Software Mode .Pull up resistors not shown for open drain outputs.
Rev. PrC | Page 15 of 25
AD5750
Preliminary Technical Data
VSS
VDD AGND
ADP1720
VSENSE+
VSENSE-
AD5750
ADR392
REFIN
VIN
VOUT
0-5V, 0-10V,
+/-5V, +/-10V
VOUT
RANGE
SCALE
VDD
REFIN
SCLK
SDI
SDO
SYNC1
AD566X
IOUT
MCU
IOUT
0-20ma, 0-24ma,
4-20ma, +/-20ma,
+/-24ma.
RANGE
SCALE
HW SELECT
OUTEN
DVCC
R3
R2
R1
OUTPUT
RANGE
SELECT
PINS
R0
IFAULT*
VFAULT*
TEMP
Figure 12. Typical System Configuration in Hardware Mode. Pull up resistors not shown for open drain outputs.
Rev. PrC | Page 16 of 25
Preliminary Technical Data
AD5750
Driving Large Capacitive Loads
CURRENT OUTPUT ARCHITECTURE
The voltage input from the analog input VIN core (0-4.096v) is
either converted to a current (see Figure 12) which is then
mirrored to the supply rail so that the application simply sees a
current source output with respect to an internal reference
voltage or it is buffered and scaled to output a software
selectable unipolar or bipolar voltage range (See Figure 13).
The Reference is used to provide internal offsets for range and
gain scaling. The selectable output range is programmable
through the digital interface.
The voltage output amplifier is capable of driving capacative
loads of up to 1uF with the addition of a non-polarised 4nF
compensation capacitor between the CCOMP1 and CCOMP2 pins.
Without the compensation capacitor, up to 20nF capacitive
loads can be driven.
POWER ON STATE OF AD5750
On Power-up, the AD5750 will sense whether hardware or
software mode is loaded and set the power up conditions
accordingly.
VDD
R2
R3
RANGE DECODE
FROM INTERFACE
In software SPI mode, the part will power up with all outputs
disabled (OUTEN bit=0). In disabled mode, both the current
and voltage outputs are put into tri-state mode. The user will
have to set the OUTEN bit in the control register to enable the
output and in the same write the user will also set the output
range configuration using the range bits.
REXT1
VIN
IOUT
RANGE
SCALING
RSET
VREF
REXT2
IOUT
VINT
R1
If hardware mode is selected, the part will power up to the
conditions defined by the range bits and the status of the
OUTEN pin. It is recommended to keep the output disabled
when powering up the part in hardware mode.
VSS
R4
IOUT OPEN FAULT
Figure 11. Current Output Configuration
RESET:
The AD5750 contains a reset function.
RANGE DECODE
FROM INTERFACE
In Software mode, the part can be reset using the RESET pin
(active low) or the RESET bit (RESET=1). A reset will disable
both the current and voltage outputs and put them in tri-state
mode. The user will have to write to the OUTEN bit to enable
the output and in the same write the user will also set the output
range configuration. The RESET pin is a level sensitive input -
the part will stay in RESET mode as long as RESET pin is low.
The RESET bit will clear to zero following a RESET command
to the control register.
+VSENSE
VOUT
VIN
(0-4.096V)
VOUT RANGE
SCALING
VOUT SHORT FAULT
VREF
-VSENSE
Figure 12. Voltage Output
Voltage Output Amplifier
The voltage output amplifier is capable of generating both
unipolar and bipolar output voltages. It is capable of driving a
load of 1 kΩ in parallel with 1.2 uF. The source and sink
capabilities of the output amplifier can be seen in Figure TBD.
The slew rate is 1 V/μs with a full-scale settling time of 10
μs.(10V step).
In hardware mode, there is no RESET. If using the part in
hardware mode the RESET pin should be tied high.
OUTEN
In Software mode, the output can be enabled/disabled using the
OUTEN bit in the control register. When the output is disabled,
both the current and voltage channels both go into tri-state. The
user will have to set the OUTEN bit to enable the output and at
this time the user will also set the output range configuration.
The current and voltage are output on separate pins and cannot
be output simultaneously. This allows the user to tie both the
current and voltage output pins together and configuring the
end system as “one channel” output.
In Hardware mode, the output can be enabled/disabled using
the OUTEN pin. When the output is disabled, both the current
and voltage channels both go into tri-state. The user will have
to write to the OUTEN pin to enable the output. It is
recommended that the output be disabled when changing the
ranges.
Rev. PrC | Page 17 of 25
AD5750
Preliminary Technical Data
SOFTWARE CONTROL:
Software control is enabled by connecting the HW SELECT pin to ground. In software mode, the AD5750 is controlled over a versatile 3-
wire serial interface that operates at clock rates up to 30 MHz. It is compatible with SPI®, QSPI™, MICROWIRE™, and DSP standards The
input shift register is 16 bits wide. Data is loaded into the device MSB first as a 16-bit word under the control of a serial clock input,
SCLK. Data is clocked in on the falling edge of SCLK. The input register consists of 16 control bits as shown in Table 5. The timing
diagram for this operation is shown in Figure 2. The first 3 bits of the Input Register are used to set the hardware address of the AD5750
device on the PCB board. Up to 8 devices can be addressed per board.
Bits D11, D1, D0 must always be set to 0 during any write sequence.
Table 3. Input Shift Register Format
MSB
D15
A2
LSB
D1 D0
D14 D13 D12
A1 A0
D11 D10 D9 D8 D7 D6
D5
D4
D3
D2
0
R3 R2 R1 R0 CLRSEL OUTEN
CLEAR RSEL RESET
0
0
R/W
Table 6. Input Shift Register Decoded
Register
A2, A1, A0
Used in association with External Pins AD2, AD1, AD0 to determine which part is
being addressed by the system controller.
A2
0
A1
0
A0
0
Function
Addresses Part with pins AD2=0, AD1=0, AD0=0
Addresses Part with pins AD2=0, AD1=0, AD0=1
Addresses Part with pins AD2=0, AD1=1, AD0=0
Addresses Part with pins AD2=0, AD1=1, AD0=1
Addresses Part with pins AD2=1, AD1=0, AD0=0
Addresses Part with pins AD2=1, AD1=0, AD0=1
Addresses Part with pins AD2=1, AD1=1, AD0=0
Addresses Part with pins AD2=1, AD1=1, AD0=1
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
W
Indicates a read from or a write to the addressed register.
R/
CLEAR
Software Clear Bit – Active High.
CLRSEL
Sets Clear Mode to zero scale or midscale. See Text.
CLRSEL
0
1
Clear to Zero Volts
Clear to Mid Scale in Unipolar Mode, Clear to Zero Scale in Bipolar Mode.
OUTEN
RSEL
Output Enable Bit. This bit must be set to 1 to enable the outputs.
Select Internal/External Current Sense Resistor.
RSEL
1
0
Select Internal Current Sense Resistor /*used with Range bits to select Range */
Select External Current Sense Resistor /*used with Range bits to select Range */
R3,R2,R1,R0
Selects output Configuration in conjunction with RSEL.
RSEL
R3
0
0
0
0
0
0
0
0
1
1
1
1
R2
0
0
0
0
1
1
1
1
0
0
0
0
R1
0
0
1
1
0
0
1
1
0
0
1
1
R0
0
1
0
1
0
1
0
1
0
1
0
1
Output Configuration
0
0
0
0
0
0
0
0
0
0
0
0
4-20MA
0-20MA
0-24MA
+/-20MA
+/-24MA
0-5V
External Current Sense Resistor 15k ohm.
External Current Sense Resistor 15k ohm.
External Current Sense Resistor 15k ohm.
External Current Sense Resistor 15k ohm.
External Current Sense Resistor 15k ohm.
0-10V
+/-5V
+/-10V
0-6.0V (20% over range)
0-12.0V (20% over range)
+/-6.0V (20% over range)
Rev. PrC | Page 18 of 25
Preliminary Technical Data
AD5750
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
+/-12.0V (20% over range)
+/-2.5v
N/A. If selected output will drive 0V.
N/A. If selected output will drive 0V.
4-20MA Internal Current Sense Resistor.
0-20MA Internal Current Sense Resistor.
0-24MA Internal Current Sense Resistor.
+/-20MA
+/-24MA
0-5V
0-10V
+/-5V
+/-10V
0-6.0V (20% over range)
0-12.0V (20% over range)
+/-6.0V (20% over range)
+/-12.0V (20% over range)
3.92ma – 20.4ma Internal Current Sense Resistor.
0ma – 20.4ma
0ma – 24.5ma
Internal Current Sense Resistor.
Internal Current Sense Resistor.
Reset
Resets the part to its Power on State
Readback Operation
Readback mode is invoked by selecting the correct device address (A2,A1,A0) and then setting the R/W bit to 1. By default the SDO pin is
disabled, after having addressed the AD5750 for a read operation, setting R/W to 1 will enable the SDO pin and SDO data will be clocked
out on the 5th rising edge of SCLK. After the data has been clocked out on SDO, a rising edge on SYNC will disable (tri- state) the SDO
pin once again. STATUS and CONTROL register data will be both available during the same read cycle. See Table 7 below.
Table 7. Input Shift Register Contents for a read operation
MSB
D15
A2
LSB
D14
D13
D12
1
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
A1
A0
0
R3
R2
R1
R0
CLRSEL
OUTEN
RSEL
OVER TEMP
IOUT Fault
Vout Fault
PEC Error Bit
The STATUS bits are 4 read only bits. They are used to notify the user of specific fault conditions that have arisen, such as open or short
circuit on the output, over temperature, or an interface error. If any one of these fault conditions occur a hardware FAULT is also asserted
low which can be used as a hardware interrupt to the controller.
Full explanation of fault conditions are given in the Features sections.
Table 9. STATUS Bits Options
Option
Description
PEC ERROR
VOUT FAULT
IOUT FAULT
OVER TEMP
Bit Set if there is an Interface Error detected by CRC-8 Error Checking. See features section.
Bit set if there is a short Circuit on VOUT pin.
Bit set is there is an open circuit on IOUT pin.
This bit will be set if the AD5750 core temperature exceeds approx. 150°C.
Rev. PrC | Page 19 of 25
AD5750
Preliminary Technical Data
HARDWARE CONTROL:
Hardware control is enabled by connecting the HW SELECT pin to DVCC. In this mode, pins R3,R2,R1,R0 along with RSEL pin are used
to configure the output range as per Table.
RSEL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
R2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
R0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Output Configuration
4-20MA
0-20MA
0-24MA
+/-20MA
+/-24MA
0-5V
External Current Sense Resistor 15k ohm.
External Current Sense Resistor 15k ohm.
External Current Sense Resistor 15k ohm.
External Current Sense Resistor 15k ohm.
External Current Sense Resistor 15k ohm.
0-10V
+/-5V
+/-10V
0-6.0V (20% over range)
0-12.0V (20% over range)
+/-6.0V (20% over range)
+/-12.0V (20% over range)
+/-2.5v
N/A. If selected output will drive 0V.
N/A. If selected output will drive 0V.
4-20MA Internal Current Sense Resistor.
0-20MA Internal Current Sense Resistor.
0-24MA Internal Current Sense Resistor.
+/-20MA
+/-24MA
0-5V
0-10V
+/-5V
+/-10V
0-6.0V (20% over range)
0-12.0V (20% over range)
+/-6.0V (20% over range)
+/-12.0V (20% over range)
3.92ma – 20.4ma Internal Current Sense Resistor.
0ma – 20.4ma
0ma – 24.5ma
Internal Current Sense Resistor.
Internal Current Sense Resistor.
Rev. PrC | Page 20 of 25
Preliminary Technical Data
AD5750
In hardware mode there is no status register. The fault
conditions; open circuit, short circuit and over temperature are
available on pins IFAULT, VFAULT and TEMP. If any one of
these fault conditions are set then a low is asserted on the
specific fault pin. IFAULT, VFAULT and TEMP are open drain
outputs and therefore can be connected together to allow the
user generate one interrupt to the system controller to
communicate a fault. If hardwired in this way, it will not be
possible to isolate which fault occurred in the system.
Vout = GAIN x VIN
For a bipolar voltage output range, the output voltage expression is
given by
Vout = ꢀGAIN x VIN – ꢀGAIN x ꢀVREF/2%% x VIN%
where:
VREF is the reference voltage applied at the REFIN pin.
Gain is an internal gain whose value depends on the output
range selected by the user as shown in
DEFAULT CONFIGURATION:
On initial power-up of the AD5750 the power-on-reset circuit
ensures that all registers are loaded with zero-code, as such the
default output is the current output with the 4mA to 20mA
range selected, the current output until a value is programmed
is 0mA. The voltage output pin will be in three-state. An
alternative current range or a voltage output range may be
selected via the CONTROL register.
Current Output
For a given current output range, the current output range is
chosen setting the bits R3,R2,R1,R10 in the Input Register or
pins. Transfer function will change depending on current range
selected.
TRANSFER FUNCTION
Voltage Output
For a unipolar voltage output range, the output voltage
expression is given by
Rev. PrC | Page 21 of 25
AD5750
Preliminary Technical Data
FEATURES
feedback loop of the output amplifier, the output
accuracy is maintained by its open-loop gain and an
output error does not occur before the FAULT output
becomes active.
OUTPUT FAULT ALERT – SOFTWARE MODE
In Software mode, the AD5750 is equipped with one FAULT
pin, this is an open-drain output allowing several AD5750
devices to be connected together to one pull-up resistor for
global fault detection. In software control mode, the FAULT pin
is forced active high by any one of the following fault scenarios;
If this fault is detected the IFAULT pin is forced low.
2) A short is detected on the voltage output pin. Short
circuit current limited to 25ma. If this fault is detected
the VFAULT pin is forced low.
1) The Voltage at IOUT attempts to rise above the
compliance range, due to an open-loop circuit or
insufficient power supply voltage. The internal
circuitry that develops the fault output avoids using a
comparator with “window limits” since this would
require an actual output error before the FAULT
output becomes active. Instead, the signal is generated
when the internal amplifier in the output stage has less
than approximately one volt of remaining drive
capability. Thus the FAULT output activates slightly
before the compliance limit is reached. Since the
comparison is made within the feedback loop of the
output amplifier, the output accuracy is maintained by
its open-loop gain and an output error does not occur
before the FAULT output becomes active.
3) If the core temperature of the AD5750 exceeds approx.
150°C. If this fault is detected the TEMP pin is forced
low.
VOLTAGE OUTPUT SHORT CIRCUIT PROTECTION
Under normal operation the voltage output will sink/source
5mA and maintain specified operation. The maximum current
that the voltage output will deliver is 15mA, this is the short
circuit current.
ASYNCHRONOUS CLEAR (CLEAR)
CLEAR is an active high clear that allows the voltage output to
be cleared to either zero-scale code or mid-scale code, user-
selectable via the CLRSEL pin or the CLRSEL bit of the INPUT
register as described in Table 6. (The Clear select feature is a
logical OR function of the CLR SELECT pin and the CLRSEL
bit). The Current loop output will clear to the bottom of its
programmed range. It is necessary to maintain CLEAR high for a
minimum amount of time (see Figure 2) to complete the
operation. When the CLEAR signal is returned low, the output
returns to its programmed value or a new value if programmed.
A clear operation can also be performed via the CLEAR
command in the control register.
2) A short is detected on the voltage output pin. Short
circuit current limited to 25ma.
3) An interface error is detected due to the PEC error
checking failure. See PEC error checking section.
4) A range change is detected without the user writing to
the Interface.
5) If the core temperature of the AD5750 exceeds approx.
150°C.
Table ±±. CLEAR SELECT Options
OUTPUT FAULT ALERT – HARDWARE MODE
CLR
Output CLR Value
SELECT
In hardware mode, the AD5750 is equipped with 3 FAULT pins,
VFAULT, IFAULT, TEMP. These are an open-drain outputs
allowing several AD5750 devices to be connected together to
one pull-up resistor for global fault detection. In hardware
control mode, these fault pins are forced active by any one of
the following fault scenarios;
Unipolar Output Voltage
Range
Bipolar Output
Range
0
1
0 V
Negative Full-Scale
0 V
Mid-Scale
Unipolar Current Output
Range
Bipolar Current
Output Range
1) Open Circuit Detect. The Voltage at IOUT attempts to
rise above the compliance range, due to an open-loop
circuit or insufficient power supply voltage. The
internal circuitry that develops the fault output avoids
using a comparator with “window limits” since this
would require an actual output error before the
FAULT output becomes active. Instead, the signal is
generated when the internal amplifier in the output
stage has less than approximately one volt of
0
1
Zero-Scale e.g.
4ma on 4-20ma
0ma on 0-20ma etc...
Zero Scale e.g.
-24ma on +/-24ma
Mid-Scale e.g.
12ma on 4-20ma
10ma on 0-20ma
Mid-Scale e.g.
0ma on +/-24ma
EXTERNAL CURRENT SETTING RESISTOR
Referring to Figure 1, RSET is an internal sense resistor as part
of the voltage to current conversion circuitry. The nominal
value of internal current sense resistor is 15k ohm. To allow for
overrange capability in current mode, the user can also select
remaining drive capability. Thus the FAULT output
activates slightly before the compliance limit is
reached. Since the comparison is made within the
Rev. PrC | Page 22 of 25
Preliminary Technical Data
AD5750
the internal current sense resistor to be 14.7K, giving a nominal
2% overrange capability. This feature is available in the 0-20ma,
4-20ma, +/-20ma current ranges.
PACKET ERROR CHECKING
To verify that data has been received correctly in noisy
environments, the AD5750 offers the option of error
checking based on an 8-bit (CRC-8) cyclic redundancy check.
The device controlling the AD5750 should generate an 8-bit
frame check sequence using the polynomial
The stability of the output current value over temperature is
dependent on the stability of the value of RSET. As a method of
improving the stability of the output current over temperature
an external low drift resistor can be connected to the RSET1 &
RSET2 pins of the AD5750 to be used instead of the internal
resistor RSET. The external resistor is selected via the input
register. If the external resistor option is not used the RSET1
and RSET2 pins should be left floating.
C(x) = x
8
+ x
2
+ x +1.
1
This is added to the end of the data word, and 24 data
bits are sent to the AD5750 before taking SYNC high.
If the AD5750 sees a 24-bit data frame, it will perform
the error check when SYNC goes high. If the check is valid,
then the data will be written to the selected register. If the error
check fails, the FAULT will go high and bit D4 of the Status
Register is set. After reading this register, this error flag is
cleared automatically and PEC goes high again.
PROGRAMMABLE OVER-RANGE MODES
The AD5750 contains an over range mode for most of the
available ranges. In voltage mode the over-range is typically
20% and in current mode the over-range is typically 2%. The
overranges are selected by configuring R3, R1, R1, R0 bits/pins
accordingly.
UPDATE ON SYNC HIGH
SYNC
In voltage mode the overranges are typically 20% providing
programmable output ranges of 0-6v, 0-12v, +/-6v and +/-12v.
The 0-4.096v analog input remains the same.
In current mode the overranges are typically 2%. In current
mode the overrange capability is only available on 3 ranges, 0-
20ma, 0-24ma, 4-20ma. For these ranges the analog input will
also vary, according to the table below.
SCLK
MSB
D15
LSB
D0
DIN
16-BIT DATA
16-BIT DATATRANSFER - NO ERROR CHECKING
UPDATE AFTER SYNC HIGH
ONLY IF ERROR CHECK PASSED
SYNC
Over Range
0-20.4ma
3.92-20.4ma
0-24.5ma
Analog Input
0.075v – 4.096v
0.06v-4.096v
0.065-4.096v
SCLK
DIN
MSB
D23
LSB
D8
D0
8-BIT FCS
D7
16 BIT DATA
PEC GOES LOW IF
ERROR CHECK FAILS
PEC
16-BIT DATA TRANSFER WITH ERROR CHECKING
For example, in 0-20.4ma range, an analog input of 0.075v will
output 0ma and 4.096v will output full scale 20.4ma.
Figure 13. PEC Error Checking Timing
Rev. PrC | Page 23 of 25
AD5750
Preliminary Technical Data
APPLICATIONS INFORMATION
TRANSIENT VOLTAGE PROTECTION
The AD5750 contains ESD protection diodes which prevent
damage from normal handling. The industrial control
environment can, however, subject I/O circuits to much higher
transients. In order to protect the AD5750 from excessively high
voltage transients , external power diodes and a surge current
limiting resistor may be required, as shown in Figure 15. The
constraint on the resistor value is that during normal operation
the output level at IOUT must remain within its voltage
compliance limit of AVDD – 2.0V and the two protection diodes
and resistor must have appropriate power ratings.
separate ground plane, but separating the lines helps). It is
essential to minimize noise on the REFIN line.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feed through the board. A
microstrip technique is by far the best, but not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to ground plane, while signal
traces are placed on the solder side.
GALVANICALLY ISOLATED INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that might occur. The
iCoupler® family of products from Analog Devices provides
voltage isolation in excess of 2.5 kV. The serial loading structure
of the AD5750 make it ideal for isolated interfaces because the
number of interface lines is kept to a minimum. Figure 16 shows
a 4-channel isolated interface to the AD5750 using an
ADuM1400. For further information, visit
AV
DD
AV
DD
R
P
AD5750
I
OUT
R
LOAD
AV
SS
http://www.analog.com/icouplers.
Figure 15. Output Transient Voltage Protection
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5750 is mounted should be designed so that the AD5750 lies
on the analog plane.
Controller
ADuM1400 *
V
V
OA
IA
To SCLK
Serial Clock Out
ENCODE
DECODE
DECODE
DECODE
DECODE
V
V
V
V
V
IB
IC
ID
OB
To SDIN
Serial Data Out
SYNC Out
ENCODE
ENCODE
ENCODE
OC
To SYNC
To CLEAR
The AD5750 should have ample supply bypassing of 10 μF in
parallel with 0.1 μF on each supply located as close to the
package as possible, ideally right up against the device. The 10
μF capacitors are the tantalum bead type. The 0.1 μF capacitor
should have low effective series resistance (ESR) and low
effective series inductance (ESI) such as the common ceramic
types, which provide a low impedance path to ground at high
frequencies to handle transient currents due to internal logic
switching.
V
OD
Control out
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure16. Isolated Interface
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5750 is via a serial bus that
uses protocol compatible with microcontrollers and DSP
processors. The communications channel is a 3-wire
(minimum) interface consisting of a clock signal, a data signal,
and a sync signal. The AD5750 require a 16-bit data-word with
data valid on the falling edge of SCLK.
The power supply lines of the AD5750 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with digital ground to
avoid radiating noise to other parts of the board and should
never be run near the reference inputs. A ground line routed
between the SDIN and SCLK lines helps reduce crosstalk
between them (not required on a multilayer board that has a
Rev. PRC | Page 24 of 25
Preliminary Technical Data
OUTLINE DIMENSIONS
AD5750
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
TOP
VIEW
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
4.75
BSC SQ
0.50
0.40
0.30
17
16
8
9
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 17. 32-Lead Lead Frame Chip Scale Package
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
TUE Accuracy
Temperature Range
Package Description
Package Option
AD5750ACPZ
AD5750BCPZ
0.3 %
0.1%
-40°C to 105°C
-40°C to 105°C
32 Lead LFCSP
32 Lead LFCSP
CP-32-2
CP-32-2
Rev. PrC | Page 25 of 25
PR07268-0-5/08(PrC)
相关型号：
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