AD5767 [ADI]

16-Channel, 16-Bit/12-Bit Voltage Output denseDACs;
AD5767
型号: AD5767
厂家: ADI    ADI
描述:

16-Channel, 16-Bit/12-Bit Voltage Output denseDACs

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16-Channel, 16-Bit/12-Bit  
Voltage Output denseDACs  
AD5766/AD5767  
Data Sheet  
voltage as low as −20 V or a maximum output voltage of up to  
+14 V. Each of the 16 channels can be monitored with an  
integrated output voltage multiplexer.  
FEATURES  
Complete 16-channel, 12-bit/16-bit DACs  
8 software-programmable output ranges: −20 V to 0 V,  
−16 V to 0 V, −10 V to 0 V, −10 V to +6 V, −12 V to +14 V,  
−16 V to +10 V, ±± V and ±10 V  
Integrated DAC output buffers with ±20 mA output current  
capability  
4 mm × 4 mm WLCSP package and 40-lead LFCSP package  
Integrated reference buffers  
2 dither signal input pins  
The AD5766/AD5767 have integrated output buffers that can  
sink or source up to 20 mA. In conjunction with these buffers, a  
low frequency signal can be superimposed onto each DAC output  
via dedicated dither pins. These dedicated dither pins simplify  
the system design by reducing the number of external components  
required for a similar external implementation, like operational  
amplifiers or resistors. The reduction of external components  
makes the AD5766/AD5767 suitable for indium phosphide Mach  
Zehnder modulator (InP MZM) biasing applications.  
Channel monitoring multiplexer  
1.8 V logic compatibility  
Temperature range: −40°C to +10±°C  
The devices incorporate a power-on reset (POR) circuit that  
ensures that the DAC outputs are clamped to ground on power  
up and remain at this level until the output range of the DAC is  
configured. The outputs of all DACs are updated through register  
configuration, with the added functionality of user-selectable  
DAC channels to be simultaneously updated.  
APPLICATIONS  
Mach Zehnder modulator bias control  
Optical networking  
Instrumentation  
Industrial automation  
Data acquisition systems  
Analog output modules  
The AD5766/AD5767 use a versatile 4-wire serial interface that  
operates at clock rates of up to 50 MHz for write mode and is  
compatible with serial peripheral interface (SPI), QSPI™,  
MICROWIRE™, and DSP interface standards. The AD5766/  
AD5767 also contain a VLOGIC pin intended for 1.8 V/3.3 V/5 V  
logic.  
GENERAL DESCRIPTION  
The AD5766/AD5767 are 16-channel, 16-bit/12-bit, voltage output  
denseDAC® digital-to-analog converters (DACs).  
The DACs generate output voltage ranges from an external 2.5 V  
reference. Depending on the voltage range selected, the midpoint  
of the output span can be adjusted, allowing a minimum output  
The AD5766/AD5767 are available in a 4 mm × 4 mm WLCSP  
package and a 40-lead LFCSP package. The AD5766/AD5767  
operate at a temperature range of −40°C to +105°C.  
FUNCTIONAL BLOCK DIAGRAM  
V
AV  
AV  
DD  
REF  
CC  
V
0
OUT  
RANGE  
SET DAC  
16-TO-1  
MUX  
AD5766/AD5767  
MUX_OUT  
V
LOGIC  
V
15  
OUT  
n
n
n
DAC  
INPUT  
V
V
0
1
DAC 0  
DAC 1  
SDI  
OUT  
OUT  
INPUT  
REGISTER 0  
REGISTER 0  
SHIFT  
REGISTER  
AND  
CONTROL  
LOGIC  
SCLK  
SYNC  
SDO  
INPUT  
REGISTER 1  
DAC  
REGISTER 1  
RESET  
DGND  
n
INPUT  
REGISTER 15  
DAC  
REGISTER 15  
V
15  
DAC 15  
OUT  
AV  
AGND  
SS  
AGND  
N0  
N1  
Figure 1.  
Rev. C  
Document Feedback  
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
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Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700 ©2017–2018 Analog Devices, Inc. All rights reserved.  
Technical Support  
www.analog.com  
 
 
 
 
AD5766/AD5767  
Data Sheet  
TABLE OF CONTENTS  
Features .............................................................................................. 1  
Register Details ............................................................................... 33  
Input Shift Register .................................................................... 33  
Monitor Mux Control................................................................ 34  
No Operation.............................................................................. 35  
Daisy-Chain Mode..................................................................... 35  
Write and Update Commands.................................................. 35  
Span Register............................................................................... 36  
Dither Power Control Register................................................. 36  
Write Input Data to All DAC Registers................................... 36  
Software Full Reset..................................................................... 37  
Select Register for Readback..................................................... 37  
Apply N0 or N1 Dither Signal to DACs Register................... 38  
Dither Scale................................................................................. 38  
Invert Dither Register................................................................ 39  
Applications Information .............................................................. 40  
Dither Configuration................................................................. 40  
Thermal Considerations............................................................ 40  
Microprocessor Interfacing....................................................... 40  
AD5766/AD5767 to SPI Interface............................................ 40  
Layout Guidelines....................................................................... 41  
Outline Dimensions....................................................................... 42  
Ordering Guide .......................................................................... 43  
Applications....................................................................................... 1  
General Description......................................................................... 1  
Functional Block Diagram .............................................................. 1  
Revision History ............................................................................... 3  
Specifications..................................................................................... 4  
AC Performance Characteristics ................................................ 8  
Timing Characteristics ................................................................ 9  
Absolute Maximum Ratings.......................................................... 11  
Thermal Resistance .................................................................... 11  
ESD Caution................................................................................ 11  
Pin Configurations and Function Descriptions ......................... 12  
Typical Performance Characteristics ........................................... 16  
Dither Characteristics................................................................ 25  
Terminology .................................................................................... 27  
Theory of Operation ...................................................................... 29  
Digital-to-Analog Converter .................................................... 29  
DAC Architecture....................................................................... 29  
Resistor String............................................................................. 29  
Power-On Reset (POR).............................................................. 29  
Dither ........................................................................................... 31  
Dither Power-Down Mode........................................................ 31  
Monitor Mux............................................................................... 31  
Serial Interface ............................................................................ 32  
Rev. C | Page 2 of 43  
Data Sheet  
AD5766/AD5767  
REVISION HISTORY  
1/2018—Rev. B to Rev. C  
Changes to Table 32 and Table 33.................................................37  
Changes to Dither Configuration Section ...................................40  
Updated Outline Dimensions........................................................42  
Changes to Ordering Guide...........................................................43  
Changes to Output Voltage Settling Time Parameter, Table 3 .........8  
Changes to Figure 6.........................................................................14  
Changes to Figure 11 ......................................................................16  
Changes to Figure 13 ......................................................................17  
Changes to Figure 37 ......................................................................21  
Change to Terminology Section....................................................27  
Changes to Figure 72 ......................................................................32  
Changes to Ordering Guide...........................................................43  
4/2017—Rev. 0 to Rev. A  
Added 40-Lead LFCSP Package....................................... Universal  
Changes to Features..........................................................................1  
Changes to General Description.....................................................1  
Changes to Functional Block Diagram, Figure 1..........................1  
Added Figure 6 and Added Table 7; Renumbered  
10/2017—Rev. A to Rev. B  
Added AD5766...................................................................Universal  
Changes to Features Section, Applications Section, and  
Sequentially......................................................................................12  
Changes to Figure 23 and Figure 24 .............................................16  
Added Figure 26..............................................................................17  
Changes to Figure 28 and Figure 29 .............................................17  
Changes to Dither DC Shift Section.............................................20  
Changes to Figure 43, Caption Only ............................................23  
Changes to Input Shift Register Section and Table 9 .................25  
Changes to Table 18 ........................................................................27  
Changes to Thermal Considerations Section..............................32  
Changes to Layout Guidelines Section and Added Figure 47...33  
Updated Outline Dimensions........................................................34  
Changes to Ordering Guide...........................................................35  
General Description Section............................................................1  
Changes to Table 1 ............................................................................4  
Added Table 2; Renumbered Sequentially.....................................7  
Changes to Table 3 ............................................................................8  
Changes to t14 and t15 Parameters, Table 4 and Figure 2...............9  
Changes to Figure 4.........................................................................10  
Change to AVCC Pin Description, Table 7 ....................................13  
Change to AVCC Pin Description, Table 8 ....................................15  
Changes to Figure 7 to Figure 12...................................................16  
Changes to Figure 13 to Figure 18 ................................................17  
Deleted Figure 30; Renumbered Sequentially .............................17  
Added Figure 19 to Figure 24; Renumbered Sequentially.........18  
Added Figure 29 and Figure 30 .....................................................19  
Added Figure 31 to Figure 36 ........................................................20  
Added Figure 37 to Figure 42 ........................................................21  
Added Figure 43 and Figure 46 .....................................................22  
Changes to Figure 49 ......................................................................23  
Added Figure 50 to Figure 54 ........................................................23  
Changes to Figure 56 ......................................................................24  
Added Figure 67 ..............................................................................26  
Changes to Digital-to-Analog Converter Section, DAC  
1/2017—Revision 0: Initial Version  
Architecture Section, and Power-On Reset (POR) Section..........29  
Added Figure 70 ..............................................................................30  
Changes to Dither Section and Dither Power-Down Mode  
Section ..............................................................................................31  
Changes to Table 10 ........................................................................33  
Added Table 17 and Table 19.........................................................35  
Changes to Dither Power Control Register Section, Table 26, Write  
Input Data to All DAC Registers Section, and Table 28 ...............36  
Rev. C | Page 3 of 43  
 
AD5766/AD5767  
SPECIFICATIONS  
Data Sheet  
AVCC = 2.97 V to 3.6 V, VLOGIC = 1.7 V to 5.5 V, AVDD = 2.97 V to 16 V, AVSS = −22 V to −7 V, AGND = DGND = 0 V, VREF = 2.5 V, output  
range = 5 V, VOUTx unloaded, all specifications TMIN to TMAX, typical specifications at TA = 25°C, dither powered on, unless otherwise noted.  
Table 1.  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
STATIC PERFORMANCE  
Resolution  
16  
12  
Bits  
Bits  
AD5766  
AD5767  
Relative Accuracy (INL)  
AD5766  
AD5767  
−16  
−1  
+16  
+1  
LSB  
LSB  
Differential Nonlinearity  
Bipolar Zero Error  
−1  
+1  
LSB  
mV  
mV  
mV  
mV  
mV  
ppm FSR/°C  
Guaranteed monotonic by design  
5 V range  
−10 V to +6 V range  
10 V range  
−12 V to +14 V range  
−16 V to +10 V range  
−85  
−110  
−120  
−145  
−145  
12  
13  
15  
16  
16  
2
+85  
+110  
+120  
+145  
+145  
Bipolar Zero Error Temperature  
Coefficient (TC)  
Zero-Scale Error  
All 0s loaded to DAC register  
−10 V to 0 V range  
5 V range  
−16 V to 0 V range  
−10 V to +6 V range  
−20 V to 0 V range  
10 V range  
−80  
−80  
25  
25  
35  
35  
35  
35  
45  
45  
2
+80  
+80  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
−110  
−110  
−130  
−130  
−140  
−140  
+110  
+110  
+130  
+130  
+140  
+140  
−12 V to +14 V range  
−16 V to +10 V range  
Zero-Scale Error Temperature  
Coefficient (TC)  
ppm FSR/°C  
Full-Scale Error  
All 1s loaded to DAC register.  
−10 V to 0 V range  
5 V range  
−16 V to 0 V range  
−10 V to +6 V range  
−20 V to 0 V range  
10 V range  
−0.9  
−0.9  
−0.8  
−0.8  
−0.7  
−0.7  
−0.6  
−0.6  
0.23  
0.23  
0.2  
+0.9  
+0.9  
+0.8  
+0.8  
+0.7  
+0.7  
+0.6  
+0.6  
% FSR  
% FSR  
% FSR  
% FSR  
% FSR  
% FSR  
% FSR  
% FSR  
0.2  
0.18  
0.18  
0.15  
0.15  
3
−12 V to +14 V range  
−16 V to +10 V range  
Full-Scale Error Drift  
Gain Error  
Gain Error Temperature  
Coefficient (TC)  
ppm FSR/°C  
% FSR  
ppm FSR/°C  
−0.4  
0.07  
2
+0.4  
Offset Error  
−80  
−80  
25  
25  
35  
35  
35  
35  
45  
45  
2
+80  
+80  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
µV/°C  
−10 V to 0 V range  
5 V range  
−16 V to 0 V range  
−10 V to +6 V range  
−20 V to 0 V range  
10 V range  
−110  
−110  
−130  
−130  
−140  
−140  
+110  
+110  
+130  
+130  
+140  
+140  
−12 V to +14 V range  
−16 V to +10 V range  
Offset Error Drift  
Rev. C | Page 4 of 43  
 
 
Data Sheet  
AD5766/AD5767  
Parameter  
Min  
−0.9  
−0.9  
−0.8  
−0.8  
−0.7  
−0.7  
−0.6  
−0.6  
Typ  
0.18  
Max  
+0.9  
+0.9  
+0.8  
+0.8  
+0.7  
+0.7  
+0.6  
+0.6  
Unit  
Test Conditions/Comments  
Total Unadjusted Error  
%FSR  
%FSR  
%FSR  
%FSR  
%FSR  
%FSR  
%FSR  
%FSR  
µV  
−10 V to 0 V range  
5 V range  
−16 V to 0 V range  
−10 V to +6 V range  
−20 V to 0 V range  
0.18  
0.15  
0.15  
0.13  
0.13  
0.12  
0.12  
10 V range  
−12 V to +14 V range  
−16 V to +10 V range  
Due to output voltage change  
Due to load current change (1 LSB)  
DC Crosstalk  
30  
35  
µV/mA  
OUTPUT CHARACTERISTICS  
Output Voltage Ranges1  
−20  
−16  
−10  
−10  
−12  
−16  
−5  
0
0
0
+6  
+14  
+10  
+5  
+10  
+20  
1
V
V
V
V
V
V
V
V
mA  
nF  
mA  
kHz  
−10  
−20  
Output Current  
Refer to the Thermal Considerations section  
Single channel only  
Capacitive Load Stability  
DC Output Impedance  
Short-Circuit Current  
Output Amplifier Bandwidth  
REFERENCE INPUT  
Reference Input Voltage  
Reference Range  
DC Input Impedance  
Input Current  
0.2  
60  
108  
2.5  
V
V
MΩ  
µA  
1% for specified performance  
Functional performance only  
2.375  
2.5  
2.625  
1
DITHER INPUTS  
For dither input to DAC output attenuation, see  
Figure 62 to Figure 65 for typical performance  
Dither Frequency  
Amplitude  
10  
100  
kHz  
kHz  
V p-p  
V
Lower −3 dB point  
Upper −3 dB point  
Peak-to-peak ac voltage  
Peak-to-peak ac and dc voltage  
See the Terminology section  
0.25  
AVCC  
0
DC Shift  
AD5766  
AD5767  
−2  
−1  
1
+2  
+1  
LSB  
LSB  
0.063  
Dither Transient  
Dither Selected Channel  
Dither Nonselected Channels  
Dither Crosstalk1  
Dither enabled/disabled, N0 and N1 floating  
AVCC = 2.97 V and AVCC = 3.6 V  
AVCC =2.97 V and AVCC = 3.6 V  
10 kHz dither frequency  
5
2
−70  
−55  
nV-sec  
nV-sec  
dB  
dB  
100 kHz dither frequency  
LOGIC INPUTS  
Input High Voltage, VIH  
Input Low Voltage, VIL  
Input Current  
0.7 × VLOGIC  
V
V
µA  
µA  
µA  
pF  
0.3 × VLOGIC  
+2  
+6  
−2  
−6  
Per pin  
RESET pin pulled high  
RESET pin pulled low  
Per pin  
−57  
+57  
Input Capacitance  
2
Rev. C | Page 5 of 43  
AD5766/AD5767  
Data Sheet  
Parameter  
Min  
Typ  
Max  
0.4  
Unit  
Test Conditions/Comments  
LOGIC OUTPUT  
Output Low Voltage  
Output High Voltage  
High Impedance Leakage  
Current  
V
V
µA  
Sinking 200 µA  
Sourcing 200 µA  
VLOGIC − 0.4  
−1  
+1  
High Impedance Output  
Capacitance  
5
pF  
VOLTAGE MONITOR PIN  
(MUX_OUT)  
Impedance  
1.3  
kΩ  
Three-State Leakage Current  
Continuous Current  
Glitch Impulse  
−1  
−1  
0.006  
+1  
+1  
µA  
mA  
nV-sec  
µs  
Die temperature below 105°C  
VOUTx glitch due to mux enable  
¼ to ¾ scale settling to 0.5 LSB, 5 V range  
and −10 V to 0 V range  
0.2  
12  
Voltage Settling Time  
POWER SUPPLIES  
AVDD  
AVSS  
AVCC  
VLOGIC  
2.97  
−22  
2.97  
1.7  
16  
V
V
V
V
V
AVDD − AVSS must be less than or equal to 30 V  
AVDD − AVSS must be less than or equal to 30 V  
−7  
3.6  
5.5  
Headroom/Footroom  
0.7  
2
Output voltage offset to 2 LSB for 20 mA  
output load; applies to AVDD and AVSS  
Output voltage offset to 1 LSB for 20 mA  
output load; applies to AVDD and AVSS  
V
Normal Mode  
AIDD  
AISS  
AICC  
ILOGIC  
6
9
mA  
mA  
mA  
µA  
All output ranges, −40°C to +105°C  
All output ranges, −40°C to +105°C  
All output ranges, −40°C to +105°C  
All output ranges, −40°C to +105°C,  
−11  
−9  
8.3  
0.02  
10  
1
V
IH = VLOGIC, VIL = DGND  
DC Power Supply Rejection  
Ratio (PSRR)  
50  
µV/V  
AVDD power supply  
50  
3
−80  
µV/V  
mV/V  
dB  
AVSS power supply  
AVCC power supply  
AVDD power supply, at 50 Hz  
AC Power Supply Rejection  
Ratio (PSRR)  
−80  
−50  
dB  
dB  
AVSS power supply, at 50 Hz  
AVCC power supply, at 50 Hz  
1 Output amplifier headroom requirement is 2 V minimum.  
Rev. C | Page 6 of 43  
Data Sheet  
AD5766/AD5767  
AVCC = 2.97 V to 3.6 V, VLOGIC = 1.7 V to 5.5 V, AVDD = 2.97 V to 16 V, AVSS = −22 V to −7 V, AGND = DGND = 0 V, VREF = 2.5 V, output  
ra nge = 5 V, V OUTx unloaded, all specifications TMIN to TMAX, typical specifications at TA = 25°C, dither powered off, unless otherwise noted.  
Table 2.  
Parameter  
Min  
−50  
−75  
−90  
−110  
−110  
Typ  
11  
12  
12  
13  
13  
Max  
+50  
+75  
+90  
+110  
+110  
Unit  
mV  
mV  
mV  
mV  
mV  
Test Conditions/Comments  
5 V range  
−10 V to +6 V range  
10 V range  
−12 V to +14 V range  
−16 V to +10 V range  
All 0s loaded to DAC register  
−10 V to 0 V range  
5 V range  
−16 V to 0 V range  
−10 V to +6 V range  
−20 V to 0 V range  
10 V range  
−12 V to +14 V range  
−16 V to +10 V range  
All 1s loaded to DAC register; all output ranges  
All output ranges  
−10 V to 0 V range  
5 V range  
−16 V to 0 V range  
−10 V to +6 V range  
−20 V to 0 V range  
10 V range  
BIPOLAR ZERO ERROR  
ZERO-SCALE ERROR  
−50  
−50  
−75  
−75  
−90  
−90  
−110  
−110  
−0.5  
−0.3  
−50  
−50  
−75  
−75  
−90  
−90  
−110  
−110  
15  
15  
20  
20  
25  
25  
35  
35  
+50  
+50  
+75  
+75  
+90  
+90  
+110  
+110  
+0.5  
+0.3  
+50  
+50  
+75  
+75  
+90  
+90  
+110  
+110  
+0.5  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
FULL-SCALE ERROR  
GAIN ERROR  
0.15  
% FSR  
% FSR  
mV  
mV  
mV  
mV  
mV  
mV  
mV  
0.07  
15  
15  
20  
20  
25  
25  
35  
35  
OFFSET ERROR  
−12 V to +14 V range  
−16 V to +10 V range  
All output ranges  
mV  
TOTAL UNADJUSTED ERROR −0.5  
0.12  
%FSR  
Rev. C | Page 7 of 43  
AD5766/AD5767  
Data Sheet  
AC PERFORMANCE CHARACTERISTICS  
AVCC = 2.97 V to 3.6 V, V LOGIC = 1.7 V to 5.5 V, AVDD = 2.97 V to 15 V, AV SS = −22 V to −7 V, AGND = DGND = 0 V, VREF = 2.5 V, output  
range = −10 V to 0 V, V OUTx unloaded, all specifications TMIN to TMAX, typical specifications at TA = 25°C, dither powered on, analog dither  
signals not applied, unless otherwise noted.  
Table 3.  
Parameter  
Min Typ Max Unit  
Test Conditions/Comments  
DYNAMIC PERFORMANCE1  
Output Voltage Settling Time  
AD5766  
16  
14  
µs  
µs  
¼ to ¾ scale settling to 0.5 LSB, 5 V range, and −10 V to 0 V range  
256 LSB step to 0.5 LSB  
AD5767  
10  
4
µs  
µs  
¼ to ¾ scale settling to 0.5 LSB, 5 V range, and −10 V to 0 V range  
32 LSB step to 0.5 LSB  
Slew Rate  
1
10  
8
1
2
15  
15  
−80  
−75  
375  
605  
750  
835  
280  
440  
470  
610  
V/µs  
nV-sec  
mV  
nV-sec  
nV-sec  
nV-sec  
nV-sec  
dB  
Digital-to-Analog Glitch Energy  
Glitch Impulse Peak Amplitude  
Digital Feedthrough  
Digital Crosstalk  
Analog Crosstalk  
DAC-to-DAC Crosstalk  
Total Harmonic Distortion  
1 LSB change around major carry for 10 V span  
VREF = 2.5 V 0.1 V p-p, frequency = 10 kHz, AVCC = 2.97 V and 3.6 V  
VREF = 2.5 V 0.1 V p-p, frequency = 10 kHz, AVCC = 3.6 V  
dB  
Output Noise Spectral Density1  
nV/√Hz −10 V to 0 V and 5 V ranges, frequency = 1 kHz  
nV/√Hz −16 V to 0 V and −10 V to +6 V ranges, frequency = 1 kHz  
nV/√Hz −20 V to 0 V and 10 V ranges, frequency = 1 kHz  
nV/√Hz −12 V to 14 V and −16 V to +10 V ranges, frequency = 1 kHz  
nV/√Hz −10 V to 0 V and 5 V ranges, frequency = 10 kHz  
nV/√Hz −16 V to 0 V and −10 V to +6 V ranges, frequency = 10 kHz  
nV/√Hz −20 V to 0 V and 10 V ranges, frequency = 10 kHz  
nV/√Hz −12 V to 14 V and −16 V to +10 V ranges, frequency = 10 kHz  
Dither disabled  
Output Noise2  
20  
23  
33  
38  
36  
45  
45  
45  
μV rms  
μV rms  
μV rms  
μV rms  
μV rms  
μV rms  
μV rms  
μV rms  
5 V range  
−10 V to 0 V range  
−10 V to +6 V range  
−16 V to 0 V range  
10 V range  
−20 V to 0 V range  
−16 V to 10 V range  
−12 V to 14 V range  
1 DAC code = midscale. AVDD = VOUT_MAX + 2 V. AVSS = VOUT_MIN − 2 V.  
2 0.1 Hz to 10 Hz. AVDD = VOUT_MAX + 2 V. AVSS = VOUT_MIN − 2 V.  
Rev. C | Page 8 of 43  
 
 
Data Sheet  
AD5766/AD5767  
TIMING CHARACTERISTICS  
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of AVDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2,  
Figure 3, and Figure 4. AVCC = 2.97 V to 3.6 V, VLOGIC = 1.7 V to 5.5 V, VREF = 2.5 V, all specifications −40°C to +105°C, dither powered on,  
unless otherwise noted.  
Table 4.  
Parameter Limit at TMIN, TMAX Unit  
Description  
1
t1  
20  
10  
10  
15  
15  
20  
5
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
ns min  
µs typ  
ns typ  
ns typ  
ns min  
ns max  
ns min  
µs typ  
SCLK cycle time  
SCLK high time  
SCLK low time  
SYNC falling edge to SCLK falling edge setup time  
SCLK falling edge to SYNC rising edge time  
Minimum SYNC high time (write mode)  
Data setup time  
t2  
t3  
t4  
t5  
t6  
t7  
t8  
5
Data hold time  
t9  
4
DAC output settling time, 32 code step to 0.5 LSB at 12-bit resolution (see Table 3)  
RESET2 pulse width low  
RESET2 pulse activation time  
t10  
t11  
t12  
t13  
t14  
t15  
100  
100  
10  
40  
80  
5
SYNC rising edge to SCLK falling edge  
SCLK rising edge to SDO valid (CL_SDO3 = 15 pF)  
Minimum SYNC high time (readback/daisy-chain mode)  
SYNC rising edge to SYNC rising edge (DAC register updates)  
1 Maximum SCLK frequency is 50 MHz for write mode and 10 MHz for readback mode.  
2 Minimum time between a reset and the subsequent successful write is typically 25 ns.  
3 CL_SDO is the capacitive load on the SDO output.  
Timing Diagrams  
t1  
SCLK  
1
2
24  
t2  
t3  
t6  
t4  
t5  
SYNC  
t15  
t8  
t7  
SDI  
D23  
D0  
t9  
V
OUT  
t10  
RESET  
t11  
V
OUT  
Figure 2. Serial Interface Timing Diagram  
Rev. C | Page 9 of 43  
 
 
 
AD5766/AD5767  
Data Sheet  
t1  
SCLK  
24  
48  
t3  
t2  
t5  
t14  
t12  
t4  
SYNC  
t8  
t7  
D23  
D0  
D23  
D0  
SDI  
INPUT WORD FOR DAC N  
INPUT WORD FOR DAC N – 1  
t13  
D23  
D0  
SDO  
UNDEFINED  
INPUT WORD FOR DAC N  
Figure 3. Daisy-Chain Timing Diagram  
SCLK  
1
24  
24  
1
t14  
SYNC  
SDI  
D23  
D23  
D0  
D23  
D23  
D0  
INPUT WORD SPECIFIES  
REGISTER TO BE READ  
NOP CONDITION  
1
D0  
D0  
SDO  
UNDEFINED  
HIGH-Z  
SELECTED REGISTER DATA  
CLOCKED OUT  
2
DB23  
DB0  
SDO  
SELECTED REGISTER DATA  
CLOCKED OUT  
1
SDO OUTPUT BUFFER ENABLED  
SDO OUTPUT BUFFER DISABLED  
2
Figure 4. Readback Timing Diagram  
Rev. C | Page 10 of 43  
 
 
Data Sheet  
AD5766/AD5767  
ABSOLUTE MAXIMUM RATINGS  
TA = 25°C, unless otherwise noted. Transient currents of up to  
100 mA do not cause silicon controlled rectifier (SCR) latch-up.  
THERMAL RESISTANCE  
Thermal performance is directly linked to printed circuit board  
(PCB) design and operating environment. Careful attention to  
PCB thermal design is required.  
Table 5.  
Parameter  
Rating  
θ
JA is the natural convection junction to ambient thermal  
AVDD to AGND  
−0.3 V to +34 V  
resistance measured in a one cubic foot sealed enclosure.  
AVSS to AGND  
+0.3 V to −34 V  
AVDD to AVSS  
AVCC to AGND  
AVCC to AGND  
VLOGIC to DGND  
Digital Inputs1 to DGND  
Digital Output (SDO) to DGND  
N0, N1 to AGND  
VREF to AGND  
−0.3 V to +34 V  
−0.3 V to +7 V  
−0.3 V to AVDD + 0.3 V  
−0.3 V to +7 V  
−0.3 V to VLOGIC + 0.3 V  
−0.3 V to VLOGIC + 0.3 V  
−0.3 V to AVCC + 0.3 V  
−0.3 V to AVCC + 0.3 V  
AVSS − 0.3 V to AVDD + 0.3 V  
−0.3 V to +0.3 V  
Table 6. Thermal Resistance  
Package Type  
CB-49-41  
CP-40-71  
θJA  
Unit  
°C/W  
°C/W  
53  
31.71  
1 Thermal impedance simulated values are based on JEDEC 2S2P thermal test  
board with 16 thermal vias. See JEDEC JESD51.  
ESD CAUTION  
VOUTx to AGND  
AGND to DGND  
Operating Temperature Range, −40°C to +105°C  
TA Industrial  
Storage Temperature Range  
Junction Temperature, TJ MAX  
Power Dissipation  
−65°C to +150°C  
150°C  
(TJ MAX − TA)/θJA  
Lead Temperature  
Soldering Reflow  
260°C, as per JEDEC J-STD-020  
1
RESET  
, SCLK,  
SYNC  
, and SDI.  
The digital inputs include  
Stresses at or above those listed under Absolute Maximum  
Ratings may cause permanent damage to the product. This is a  
stress rating only; functional operation of the product at these  
or any other conditions above those indicated in the operational  
section of this specification is not implied. Operation beyond  
the maximum operating conditions for extended periods may  
affect product reliability.  
Rev. C | Page 11 of 43  
 
 
 
AD5766/AD5767  
Data Sheet  
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS  
AD5766/AD5767  
1
DNC  
AV  
2
3
4
5
6
7
A
B
C
D
E
F
V
1
V
V
2
0
V
V
4
3
V
V
5
7
V
6
DNC  
OUT  
OUT  
OUT  
NIC  
NIC  
NIC  
OUT  
OUT  
NIC  
NIC  
NIC  
OUT  
OUT  
RESET  
SDI  
CC AGND  
DGND  
OUT  
MUX_OUT  
V
NIC  
NIC  
NIC  
DNC  
NIC  
LOGIC  
NIC  
AV  
AV  
SS  
DD  
N1  
SCLK  
SYNC  
DNC  
NIC  
SDO  
N0  
V
V
15 V  
12 V  
8
AGND  
REF  
OUT  
OUT  
OUT  
OUT  
G
DNC  
V
14 V  
OUT  
13 V  
11V  
10 V  
9
OUT  
OUT  
OUT  
TOP VIEW  
(BALL SIDE DOWN)  
Not to Scale  
NOTES  
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS.  
2. NIC = NO INTERNAL CONNECTION. THESE PINS SHOULD BE  
ROUTED TO THERMAL VIAS ON THE PCB TO AID WITH HEAT  
DISSIPATION. CONNECT THESE PINS TO GROUND.  
Figure 5. WLCSP Package Pin Configuration  
Table 7. 49-Ball WLCSP Pin Function Descriptions  
Pin No.  
Dither  
F1  
Mnemonic Description  
N0  
N1  
Dither Signal Input Pin 0. A signal connected to this pin can be added to the DAC outputs via  
register commands. If unused, connect this pin to ground. Refer to the Dither section for more  
information.  
Dither Signal Input Pin 1. A signal connected to this pin can be added to the DAC outputs via  
register commands. If unused, connect this pin to ground. Refer to the Dither section for more  
information.  
E1  
Logic Inputs and Outputs  
E7  
SCLK  
SYNC  
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial  
clock input. Data can be transferred at rates of up to 50 MHz for write mode and 10 MHz for  
readback and daisy-chain mode.  
Active Low Control Input. SYNC is the frame synchronization signal for the input data. When  
SYNC goes low, it powers on the SCLK and SDI buffers and enables the input shift register. Data  
is transferred in on the falling edges of the next 24 clocks. If SYNC is taken high before the 24th  
falling edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by  
the device.  
F7  
C7  
E6  
B7  
SDI  
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the  
falling edge of the serial clock input.  
Serial Data Output. This pin clocks data from the serial register in daisy-chain or readback mode.  
Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.  
Active Low Reset Input. Asserting this pin logic low returns the AD5766/AD5767 to the default  
power-on state. After this pin returns to logic high, the device comes out of the reset mode and  
is ready to accept a new SPI command. This pin can be left floating, because there is a weak  
internal pull-up resistor.  
SDO  
RESET  
Analog Outputs  
B3  
A2  
A3  
B4  
A4  
A5  
A6  
VOUT  
VOUT  
VOUT  
VOUT  
VOUT  
VOUT  
VOUT  
0
1
2
3
4
5
6
Analog Output Voltage from DAC 0.  
Analog Output Voltage from DAC 1.  
Analog Output Voltage from DAC 2.  
Analog Output Voltage from DAC 3.  
Analog Output Voltage from DAC 4.  
Analog Output Voltage from DAC 5.  
Analog Output Voltage from DAC 6.  
Rev. C | Page 12 of 43  
 
Data Sheet  
AD5766/AD5767  
Pin No.  
B5  
F5  
G6  
G5  
G4  
F4  
G3  
G2  
Mnemonic Description  
VOUT  
VOUT  
VOUT  
7
8
9
Analog Output Voltage from DAC 7.  
Analog Output Voltage from DAC 8.  
Analog Output Voltage from DAC 9.  
Analog Output Voltage from DAC 10.  
Analog Output Voltage from DAC 11.  
Analog Output Voltage from DAC 12.  
Analog Output Voltage from DAC 13.  
Analog Output Voltage from DAC 14.  
Analog Output Voltage from DAC 15.  
VOUT10  
VOUT11  
VOUT12  
VOUT13  
VOUT14  
VOUT15  
F3  
Power Supplies and  
Reference Input  
F2  
C6  
B1  
VREF  
VLOGIC  
AVCC  
Reference Input Voltage. For specified performance, VREFIN = 2.5 V.  
Digital Power Supply.  
Power Supply Input. The AD5766/AD5767 operates from 2.97 V to 3.6 V. Decouple AVCC with a  
10 µF capacitor in parallel with a 0.1 µF capacitor to analog ground.  
D1  
D7  
B2, F6  
B6  
AVDD  
AVSS  
AGND  
DGND  
Output Amplifier Positive Analog Supply.  
Output Amplifier Negative Analog Supply.  
Analog Ground.  
Digital Ground Pin.  
Channel Monitoring  
C1  
MUX_OUT  
Monitor Output. This pin acts as the output of a 16-to-1 channel multiplexer that can be  
programmed to multiplex one of 16 channels, Channel 0 to Channel 15, to the MUX_OUT pin.  
Do Not Connect  
A1, A7, C5, G1, G7  
No Internal Connection  
C2 to C4, D2 to D6,  
E2 to E5  
DNC  
NIC  
Do Not Connect. Do not connect to these pins.  
No Internal Connection. Route these pins to thermal vias on the PCB to aid with heat  
dissipation. Connect these pins to ground.  
Rev. C | Page 13 of 43  
AD5766/AD5767  
Data Sheet  
DNC  
DGND  
RESET  
1
2
3
4
5
6
7
8
9
30 DNC  
29 AGND  
28 AV  
27 MUX_OUT  
26 AV  
CC  
AD5766/  
AD5767  
V
LOGIC  
SDI  
DD  
AV  
25 NIC  
24 N1  
23 N0  
SS  
TOP VIEW  
SLCK  
SYNC  
SDO  
(Not to Scale)  
22 V  
REF  
AGND 10  
21 DNC  
NOTES  
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THESE PINS.  
2. NIC = NO INTERNAL CONNECTION. THESE PINS SHOULD BE  
ROUTED TO THERMAL VIAS ON THE PCB TO AID WITH HEAT  
DISSIPATION. THESE SHOULD BE CONNECTED TO GROUND.  
3. EXPOSED PAD (LFCSP PACKAGE ONLY). CONNECT THIS  
EXPOSED PAD TO THE POTENTIAL OF THE AV PIN, OR,  
SS  
ALTERNATIVELY, LEAVE IT ELECTRICALLY UNCONNECTED.  
IT IS RECOMMENDED THAT THE PAD BE THERMALLY  
CONNECTED TO A COPPER PLANE FOR ENHANCED  
THERMAL PERFORMANCE.  
Figure 6. LFCSP Package Pin Configuration  
Table 8. 40-Lead LFCSP Pin Function Descriptions  
Pin No.  
Dither  
23  
Mnemonic Description  
N0  
N1  
Dither Signal Input Pin 0. A signal connected to this pin can be added to the DAC outputs via  
register commands. If unused, connect this pin to ground. Refer to the Dither section for more  
information.  
Dither Signal Input Pin 1. A signal connected to this pin can be added to the DAC outputs via  
register commands. If unused, connect this pin to ground. Refer to the Dither section for more  
information.  
24  
Logic Inputs and Outputs  
7
SCLK  
SYNC  
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial  
clock input. Data can be transferred at rates of up to 50 MHz for write mode and 10 MHz for  
readback and daisy-chain mode.  
Active Low Control Input. SYNC is the frame synchronization signal for the input data. When  
SYNC goes low, it powers on the SCLK and SDI buffers and enables the input shift register. Data  
is transferred in on the falling edges of the next 24 clocks. If SYNC is taken high before the 24th  
falling edge, the rising edge of SYNC acts as an interrupt, and the write sequence is ignored by  
the device.  
8
5
9
3
SDI  
Serial Data Input. This device has a 24-bit shift register. Data is clocked into the register on the  
falling edge of the serial clock input.  
Serial Data Output. This pin clocks data from the serial register in daisy-chain or readback mode.  
Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK.  
Active Low Reset Input. Asserting this pin logic low returns the AD5766/AD5767 to the default  
power-on state. After this pin returns to logic high, the device comes out of the reset mode and  
is ready to accept a new SPI command. This pin can be left floating, because there is a weak  
internal pull-up resistor.  
SDO  
RESET  
Analog Outputs  
32  
33  
34  
35  
36  
37  
VOUT  
VOUT  
VOUT  
VOUT  
VOUT  
VOUT  
0
1
2
3
4
5
Analog Output Voltage from DAC 0.  
Analog Output Voltage from DAC 1.  
Analog Output Voltage from DAC 2.  
Analog Output Voltage from DAC 3.  
Analog Output Voltage from DAC 4.  
Analog Output Voltage from DAC 5.  
Rev. C | Page 14 of 43  
Data Sheet  
AD5766/AD5767  
Pin No.  
38  
39  
12  
13  
14  
15  
16  
17  
Mnemonic Description  
VOUT  
VOUT  
VOUT  
VOUT  
6
7
8
9
Analog Output Voltage from DAC 6.  
Analog Output Voltage from DAC 7.  
Analog Output Voltage from DAC 8.  
Analog Output Voltage from DAC 9.  
Analog Output Voltage from DAC 10.  
Analog Output Voltage from DAC 11.  
Analog Output Voltage from DAC 12.  
Analog Output Voltage from DAC 13.  
Analog Output Voltage from DAC 14.  
Analog Output Voltage from DAC 15.  
VOUT10  
VOUT11  
VOUT12  
VOUT13  
VOUT14  
VOUT15  
18  
19  
Power Supplies and  
Reference Input  
22  
4
28  
VREF  
VLOGIC  
AVCC  
Reference Input Voltage. For specified performance, VREFIN = 2.5 V.  
Digital Power Supply.  
Power Supply Input. The AD5766/AD5767 operates from 2.97 V to 3.6 V. Decouple AVCC with a  
10 µF capacitor in parallel with a 0.1 µF capacitor to analog ground.  
26  
6
10, 29  
2
AVDD  
AVSS  
AGND  
DGND  
Output Amplifier Positive Analog Supply.  
Output Amplifier Negative Analog Supply.  
Analog Ground.  
Digital Ground Pin.  
Channel Monitoring  
27  
MUX_OUT  
DNC  
Monitor Output. This pin acts as the output of a 16-to-1 channel multiplexer that can be  
programmed to multiplex one of 16 channels, Channel 0 to Channel 15, to the MUX_OUT pin.  
Do Not Connect  
1, 11, 21, 30, 40  
No Internal Connection  
20, 25, 31  
Do Not Connect. Do not connect to these pins.  
NIC  
No Internal Connection. Route these pins to thermal vias on the PCB to aid with heat  
dissipation. Connect these pins to ground.  
Not Applicable  
EPAD  
Exposed Pad. Connect this exposed pad to the potential of the AVSS pin, or, alternatively, leave it  
electrically unconnected. It is recommended that the exposed pad be thermally connected to a  
copper plane for enhanced thermal performance.  
Rev. C | Page 15 of 43  
AD5766/AD5767  
Data Sheet  
TYPICAL PERFORMANCE CHARACTERISTICS  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
12  
AV /AV = RANGE ± 2V  
DD SS  
AV /AV = RANGE ±2V  
DD  
SS  
AV = 3.3V  
CC  
= 25°C  
AV = 3.3V  
10  
CC  
T
A
T
= 25°C  
A
8
6
4
2
0
±5V RANGE  
–0.1  
–0.2  
–0.3  
–16V TO +10V RANGE  
–12V TO +14V RANGE  
–2  
–4  
–6  
–10V TO 0V RANGE  
–16V TO 0V RANGE  
–20V TO 0V RANGE  
–10V TO +10V RANGE  
–10V TO +6V RANGE  
0
500  
1000 1500 2000 2500 3000 3500 4000  
CODE  
0
10000  
20000  
30000  
40000  
50000  
60000  
CODE  
Figure 10. AD5767 INL Error vs. DAC Code (Bipolar Outputs)  
Figure 7. AD5766 INL Error vs. DAC Code (Unipolar Output)  
1.0  
0.6  
AV /AV = RANGE ±2V  
DD SS  
–20V TO 0V RANGE  
AV = 3.3V  
0.8  
0.6  
–16V TO 0V RANGE  
0.5  
CC  
–10V TO 0V RANGE  
T
= 25°C  
A
0.4  
0.4  
0.3  
0.2  
0.1  
0
0.2  
0
–0.2  
–0.4  
–0.6  
–0.8  
–1.0  
–0.1  
AV /AV = RANGE ± 2V  
DD SS  
±5V RANGE  
±10V RANGE  
–16V TO +10V RANGE  
–0.2  
–0.3  
AV = 3.3V  
CC  
–10V TO +6V RANGE  
–12V TO +14V RANGE  
T
= 25°C  
500  
A
0
1000 1500 2000 2500 3000 3500 4000  
CODE  
0
10000  
20000  
30000  
CODE  
40000  
50000  
60000  
Figure 11. AD5766 DNL Error vs. DAC Code (Bipolar Outputs)  
Figure 8. AD5767 INL Error vs. DAC Code (Unipolar Output)  
0.05  
12  
AV /AV = RANGE ± 2V  
DD SS  
AV /AV = RANGE ±2V  
AV = 3.3V  
DD  
SS  
CC  
= 25°C  
0.04  
0.03  
0.02  
0.01  
0
AV = 3.3V  
10  
8
T
CC  
A
T
= 25°C  
A
6
4
2
–0.01  
–0.02  
–0.03  
–0.04  
–0.05  
0
±5V RANGE  
–2  
–4  
–6  
–16V TO +10V RANGE  
–12V TO +14V RANGE  
±5V RANGE  
±10V RANGE  
–16V TO +10V RANGE  
–10V TO +6V RANGE  
–12V TO +14V RANGE  
–10V TO +10V RANGE  
–10V TO +6V RANGE  
0
500  
1000 1500 2000 2500 3000 3500 4000  
CODE  
0
10000  
20000  
30000  
CODE  
40000  
50000  
60000  
Figure 12. AD5767 DNL Error vs. DAC Code (Bipolar Outputs)  
Figure 9. AD5766 INL Error vs. DAC Code (Bipolar Outputs)  
Rev. C | Page 16 of 43  
 
 
 
 
Data Sheet  
AD5766/AD5767  
0.06  
0.04  
1.0  
AV /AV = RANGE ± 2V  
DD  
SS  
AV /AV = RANGE ±2V  
DD  
SS  
AV = 3.3V  
CC  
0.8  
0.6  
AV = 3.3V  
CC  
DITHER ENABLED  
T
= 25°C  
A
0.02  
0
0.4  
–0.02  
–0.04  
–0.06  
–0.08  
–0.10  
–0.12  
–0.14  
–0.16  
0.2  
0
–0.2  
–0.4  
–0.6  
–0.8  
–1.0  
±5V RANGE  
±10V RANGE  
–16V TO +10V RANGE  
–10V TO +6V RANGE  
–12V TO +14V RANGE  
–20V TO 0V RANGE  
–16V TO 0V RANGE  
–10V TO 0V RANGE  
0
10000  
20000  
30000  
CODE  
40000  
50000  
60000  
CODE  
Figure 13. AD5766 DNL Error vs. DAC Code (Unipolar Outputs)  
Figure 16. Total Unadjusted Error (TUE) vs. DAC Code (Bipolar Outputs)  
0.05  
0.8  
0.6  
0.4  
AV /AV = RANGE ± 2V  
DD SS  
AV = 3.3V  
CC  
= 25°C  
0.04  
0.03  
0.02  
0.01  
0
T
A
AV /AV = RANGE ± 2V  
DD SS  
0.2  
0
MIN INL  
MAX INL  
AV = 3.3V  
CC  
±5V RANGE  
–0.01  
–0.02  
–0.03  
–0.04  
–0.05  
–0.2  
–0.4  
–0.6  
–20V TO 0V RANGE  
–16V TO 0V RANGE  
–10V TO 0V RANGE  
0
500  
1000 1500 2000 2500 3000 3500 4000  
CODE  
–40  
–20  
0
20  
40  
60  
80  
100  
TEMPERATURE (°C)  
Figure 14. AD5767 DNL Error vs. DAC Code (Unipolar Outputs)  
Figure 17. INL Error vs. Temperature  
0.06  
0.04  
0.02  
0
0.14  
AV /AV = RANGE ± 2V  
DD SS  
0.12  
0.10  
0.08  
0.06  
0.04  
0.02  
0
AV = 3.3V  
CC  
= 25°C  
T
A
DITHER ENABLED  
AV /AV = RANGE ± 2V  
DD SS  
MIN INL  
AV = 3.3V  
CC  
MAX INL  
±5V RANGE  
–0.02  
–0.04  
–0.06  
–0.02  
–0.04  
–0.06  
–0.08  
–20V TO 0V RANGE  
–16V TO 0V RANGE  
–10V TO 0V RANGE  
–40  
–20  
0
20  
40  
60  
80  
100  
TEMPERATURE (°C)  
CODE  
Figure 15. Total Unadjusted Error (TUE) vs. DAC Code (Unipolar Outputs)  
Figure 18. DNL Error vs. Temperature  
Rev. C | Page 17 of 43  
 
AD5766/AD5767  
Data Sheet  
–19.0  
0.10  
0.09  
0.08  
0.07  
0.06  
0.05  
0.04  
0.03  
0.02  
0.01  
0
AV /AV = RANGE ± 2V  
DD  
CC  
SS  
AV /AV = RANGE ± 2V  
DD SS  
AV  
= 3.3V  
AV = 3.3V  
CC  
–19.5  
–20.0  
–20.5  
–21.0  
–21.5  
–22.0  
–22.5  
±5V RANGE  
–20V TO 0V RANGE  
–10V TO 0V RANGE  
±5V RANGE  
–16V TO 0V RANGE  
–10V TO +6V RANGE  
±10V RANGE  
–12V TO +14V AND –16V TO +10V RANGE  
–40  
–20  
0
20  
40  
60  
80  
100  
–40  
–20  
0
20  
40  
60  
80  
100  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 19. Zero-Scale Error vs. Temperature  
Figure 22. Gain Error vs. Temperature  
0.020  
0.015  
0.010  
0.005  
0
15  
10  
5
0
–20V TO 0V RANGE  
–10V TO 0V RANGE  
±5V RANGE  
–16V TO 0V RANGE  
–10V TO +6V RANGE  
±10V RANGE  
–5  
–10  
–15  
–20  
–25  
–30  
–12V TO +14V AND –16V TO +10V RANGE  
AV /AV = RANGE ± 2V  
DD  
CC  
SS  
AV  
= 3.3V  
AV /AV = RANGE ± 2V  
DD  
CC  
SS  
AV  
= 3.3V  
–10V TO +6V RANGE  
±5V RANGE  
±10V RANGE  
–12V TO +14V AND –16V TO +10V RANGE  
–40  
–20  
0
20  
40  
60  
80  
100  
–40  
–20  
0
20  
40  
60  
80  
100  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 20. Bipolar Zero Error vs. Temperature  
Figure 23. Offset Error vs. Temperature  
0.20  
0.18  
0.16  
0.14  
0.12  
0.10  
0.08  
0.06  
0.04  
0.02  
0
0.25  
0.20  
0.15  
0.10  
0.05  
0
AV /AV = RANGE ± 2V  
AV /AV = RANGE ± 2V  
AV  
DD  
CC  
SS  
DD  
CC  
SS  
= 3.3V  
AV  
= 3.3V  
–20V TO 0V RANGE  
–10V TO 0V RANGE  
±5V RANGE  
–16V TO 0V RANGE  
–10V TO +6V RANGE  
±10V RANGE  
–12V TO 14V AND –16V TO +10V RANGE  
–20V TO 0V RANGE  
–10V TO 0V RANGE  
±5V RANGE  
–16V TO 0V RANGE  
–10V TO +6V RANGE  
±10V RANGE  
–0.05  
–0.10  
–12V TO +14V AND –16V TO +10V RANGE  
–40  
–20  
0
20  
40  
60  
80  
100  
–40  
–20  
0
20  
40  
60  
80  
100  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 21. Full-Scale Error vs. Temperature  
Figure 24. Total Unadjusted Error vs. Temperature  
Rev. C | Page 18 of 43  
Data Sheet  
AD5766/AD5767  
6
0.05  
0.04  
±5V RANGE  
±5V RANGE  
AV /AV = RANGE ± 2V  
AV /AV = RANGE ± 2V  
DD  
SS  
= 3.3V  
DD  
CC  
SS  
= 3.3V  
0.03  
AV  
AV  
CC  
4
2
T
= 25°C  
0.02  
A
0.01  
0
–0.01  
–0.02  
–0.03  
–0.04  
–0.05  
–0.06  
–0.07  
–0.08  
–0.09  
–0.10  
0
–2  
–4  
–6  
10nF  
1nF  
–20  
–10  
0
10  
20  
30  
40  
50  
–20  
–10  
0
10  
20  
30  
40  
50  
60  
TIME (µs)  
TIME (µs)  
Figure 25. Full-Scale Settling Time (Rising Voltage Step)  
Figure 28. Output Voltage (VOUT) vs. Settling Time at Various Capacitive Loads  
6
4
1.0  
±5V RANGE  
AV /AV = RANGE ± 2V  
DD  
SS  
= 3.3V  
AV  
= 3.3V  
CC  
CODE: FULL-SCALE  
= 25°C  
AV  
CC  
T
= 25°C  
0.8  
0.6  
0.4  
0.2  
0
A
T
A
2
0
–2  
–4  
–6  
–20  
–10  
0
10  
20  
30  
40  
50  
0
2
4
6
8
10  
12  
14  
16  
18  
20  
TIME (µs)  
OUTPUT CURRENT (mA)  
Figure 26. Full-Scale Settling Time (Falling Voltage Step)  
Figure 29. Headroom vs. Output Current  
20  
0
–0.2  
–0.4  
–0.6  
–0.8  
–1.0  
AV /AV = RANGE ± 2V  
DD  
SS  
AV  
= 3.3V  
AV  
= 3.3V  
CC  
CC  
CODE: ZERO SCALE  
= 25°C  
15  
10  
5
T
= 25°C  
A
T
A
0
–5  
–10  
–15  
–12V TO +14V  
–20V TO 0V  
–0.06  
–0.04  
–0.02  
0
0.02  
0.04  
0.06  
–20  
–18 –16 –14 –12 –10  
–8  
–6  
–4  
–2  
0
V
CURRENT OUTPUT (A)  
OUT  
OUTPUT CURRENT (mA)  
Figure 27. Source and Sink Capability of Output Amplifier  
Figure 30. Footroom vs. Output Current  
Rev. C | Page 19 of 43  
AD5766/AD5767  
Data Sheet  
0.10  
0.08  
0.06  
0.04  
0.02  
0.00  
0.9  
0.7  
4
AV /AV = RANGE ± 2V  
DD SS  
0x7FFF TO 0x8000  
WLCSP PACKAGE  
2
0.5  
0
0.3  
–2  
–4  
–6  
–8  
–10  
0.1  
–0.02  
SYNC  
RESET  
–0.04  
–0.06  
–0.08  
–0.10  
–0.1  
–0.3  
–0.5  
±5V RANGE  
V
OUTx  
AV /AV = RANGE ±2V  
DD  
CC  
SS  
= 3.3V  
AV  
0
10  
20  
30  
40  
50  
60  
70  
80  
130  
132  
134  
136  
138  
TIME (µs)  
140  
142  
144  
TIME (µs)  
Figure 31. Hardware Reset Glitch  
Figure 34. Digital-to-Analog Glitch Impulse for WLCSP Package  
10  
8
0.6  
AV /AV = RANGE ± 2V  
0x7FFF TO 0x8000  
LFCSP PACKAGE  
±5V RANGE  
DD  
SS  
0.20  
0.10  
0
AV /AV = RANGE ± 2V  
0.4  
0.2  
DD  
SS  
6
4
0
2
–0.2  
–0.4  
–0.6  
–0.8  
–1.0  
–2  
–4  
–6  
–8  
–10  
AV  
AV  
DD  
SS  
CC  
–0.10  
–0.20  
–0.30  
AV , LOGIC  
V
OUTx  
0
10  
20  
30  
40  
50  
60  
70  
80  
6
8
10  
12  
14  
16  
18  
20  
TIME (µs)  
TIME (ms)  
Figure 35. Digital-to-Analog Glitch Impulse for LFCSP Package  
Figure 32. Power-Up Glitch  
5
0.30  
4
±5V RANGE  
0.25  
0.20  
0.15  
0.10  
0.05  
0
4
3
AV /AV = RANGE ± 2V  
0x0000 TO 0xFFFF  
DITHER ON  
DD SS  
2
WLCSP PACKAGE  
0
2
±5V RANGE  
AV /AV = RANGE ±2V  
DD  
CC  
SS  
= 3.3V  
–2  
–4  
–6  
–8  
–10  
AV  
SYNC  
RESET  
1
V
OUTx  
0
–1  
–2  
–3  
–0.05  
–0.10  
–0.15  
0
5
10  
15  
20  
25  
30  
35  
40  
45  
50  
60  
65  
70  
75  
80  
85  
TIME (µs)  
90  
95  
100 105 110  
TIME (µs)  
Figure 36. Analog Crosstalk for WLCSP Package (Dither Enabled)  
Figure 33. Output Span Enable Glitch  
Rev. C | Page 20 of 43  
Data Sheet  
AD5766/AD5767  
4
7
6
±5V RANGE  
±5V RANGE  
AV /AV = RANGE ± 2V  
0x0000 TO 0xFFFF  
DITHER ON  
3
AV /AV = RANGE ± 2V  
DD SS  
DD  
SS  
0x0000 TO 0xFFFF  
DITHER ON  
WLCSP PACKAGE  
5
2
1
4
LFCSP PACKAGE  
3
2
0
1
0
–1  
–1  
–2  
–3  
–2  
–3  
0
5
10  
15  
20  
25  
30  
35  
40  
45  
50  
0
10  
20  
30  
40  
50  
60  
70  
80  
TIME (µs)  
TIME (µs)  
Figure 40. DAC-to-DAC Crosstalk for WLCSP Package (Dither Enabled)  
Figure 37. Analog Crosstalk for LFCSP Package (Dither Enabled)  
5
3
±5V RANGE  
±5V RANGE  
4
3
AV /AV = RANGE ± 2V  
2
DD SS  
AV /AV = RANGE ± 2V  
DD SS  
0x0000 TO 0xFFFF  
DITHER ON  
LFCSP PACKAGE  
0x0000 TO 0xFFFF  
DITHER OFF  
WLCSP PACKAGE  
1
0
2
–1  
–2  
–3  
–4  
–5  
–6  
1
0
–1  
–2  
–3  
0
5
10  
15  
20  
25  
30  
35  
40  
45  
50  
0
5
10  
15  
20  
25  
30  
35  
40  
45  
50  
TIME (µs)  
TIME (µs)  
Figure 41. DAC-to-DAC Crosstalk for LFCSP Package (Dither Enabled)  
Figure 38. Analog Crosstalk for WLCSP Package (Dither Disabled)  
4
4
±5V RANGE  
±5V RANGE  
3
3
AV /AV = RANGE ± 2V  
DD SS  
AV /AV = RANGE ± 2V  
DD SS  
0x0000 TO 0xFFFF  
DITHER OFF  
WLCSP PACKAGE  
0x0000 TO 0xFFFF  
DITHER OFF  
LFCSP PACKAGE  
2
1
2
1
0
0
–1  
–2  
–3  
–4  
–5  
–6  
–7  
–1  
–2  
–3  
–4  
–5  
0
5
10  
15  
20  
25  
30  
35  
40  
45  
50  
0
5
10  
15  
20  
25  
30  
35  
40  
45  
50  
TIME (µs)  
TIME (µs)  
Figure 42. DAC-to-DAC Crosstalk for WLCSP Package (Dither Disabled)  
Figure 39. Analog Crosstalk for LFCSP Package (Dither Disabled)  
Rev. C | Page 21 of 43  
AD5766/AD5767  
Data Sheet  
5
4
100k  
10k  
1k  
AV /AV = RANGE ± 2V  
DD  
SS  
±5V RANGE  
AV = 3.3V  
CC  
AV /AV = RANGE ± 2V  
DD SS  
±5V RANGE  
MIDSCALE RANGE  
DITHER ON  
0x0000 TO 0xFFFF  
DITHER OFF  
LFCSP PACKAGE  
3
2
NOT SELECTED ON CHANNEL  
1
0
–1  
–2  
–3  
–4  
–5  
–6  
T
T
T
T
T
T
= –40°C  
= –20°C  
= 0°C  
= +25°C  
= +85°C  
= +105°C  
A
A
A
A
A
A
100  
1
10  
100  
1k  
10k  
100k  
0
5
10  
15  
20  
25  
30  
35  
40  
45  
50  
TIME (µs)  
FREQUENCY (Hz)  
Figure 43. DAC-to-DAC Crosstalk for LFCSP Package (Dither Disabled)  
Figure 46. Output Noise (NSD) vs. Frequency over Temperature  
0.00008  
800  
4
±5V RANGE  
MIDSCALE CODE  
700  
600  
0.00006  
2
500  
0.00004  
0.00002  
0
0
400  
300  
–2  
–4  
–6  
–8  
–10  
200  
100  
0
–100  
–200  
–300  
–400  
–500  
AV /AV = RANGE ± 2V  
DD  
SS  
–0.00002  
–0.00004  
–0.00006  
AV = V  
= 3.3V  
CC  
LOGIC  
T
= 25°C  
A
WLCSP PACKAGE  
0
1
2
3
4
5
6
7
8
9
10  
0
30  
60  
90  
120 150 180 210 240 270 300  
TIME (µs)  
TIME (µs)  
Figure 47. Digital Feedthrough for WLCSP Package  
Figure 44. Peak-to-Peak Noise (0.1 Hz to 10 Hz Bandwidth) with Dither Disabled  
500  
400  
300  
200  
100  
0
4
3000  
±5V RANGE  
MIDSCALE CODE  
2
2500  
0
2000  
1500  
1000  
500  
0
–2  
–4  
–6  
–8  
–10  
AV /AV = RANGE ± 2V  
DD  
SS  
–100  
–200  
–300  
–400  
AV = V  
= 3.3V  
CC  
LOGIC  
T
= 25°C  
A
LFCSP PACKAGE  
10  
100  
1k  
10k  
100k  
–50 –30  
–10  
10  
30  
50  
70  
90  
110  
FREQUENCY (Hz)  
TIME (µs)  
Figure 45. Noise Spectral Density (NSD) vs. Frequency  
Figure 48. Digital Feedthrough for LFCSP Package  
Rev. C | Page 22 of 43  
Data Sheet  
AD5766/AD5767  
4.1  
4.0  
3.9  
3.8  
3.7  
3.6  
3.5  
–6.70  
–6.75  
–6.80  
–6.85  
–6.90  
–6.95  
–7.00  
–7.05  
–7.10  
–7.15  
–7.20  
AV = RANGE –2V TO RANGE  
SS  
±10V RANGE  
2.9  
3.0  
3.1  
3.2  
AV  
3.3  
(V)  
3.4  
3.5  
3.6  
–12.5 –12.0  
–11.5  
–11.0  
–10.5  
–10.0  
–9.5  
AV (V)  
SS  
CC  
Figure 49. Supply Current (AICC) vs. Supply Voltage (AVCC  
)
Figure 51. Supply Current (AISS) vs. Supply Voltage (AVSS  
)
5.72  
6.30  
±10V RANGE  
AV = RANGE TO RANGE +2V  
6.25  
6.20  
6.15  
6.10  
6.05  
6.00  
5.95  
5.90  
5.85  
5.80  
5.75  
5.70  
DD  
5.70  
5.68  
5.66  
5.64  
5.62  
5.60  
±10V RANGE  
9.5  
10.0  
10.5  
11.0  
AV (V)  
11.5  
12.0  
12.5  
0
10000  
20000  
30000  
CODE  
40000  
50000  
60000  
DD  
Figure 50. Supply Current (AIDD) vs. Supply Voltage (AVDD  
)
Figure 52. Supply Current (AICC) vs. Code  
Rev. C | Page 23 of 43  
AD5766/AD5767  
Data Sheet  
14  
12  
10  
8
6.2  
6.1  
6.0  
5.9  
5.8  
±10V RANGE  
6
±5V RANGE  
4
–10 V TO 0 V RANGE  
–10 V TO +6 V RANGE  
–16 V TO 0V RANGE  
±10 V RANGE  
2
–20 V TO 0V RANGE  
–12V TO +14V RANGE  
–16V TO +10V RANGE  
0
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5  
0
10000  
20000  
30000  
CODE  
40000  
50000  
60000  
V
(V)  
LOGIC  
Figure 55. Logic Current (ILOGIC) vs. Logic Input Voltage (VLOGIC  
)
Figure 53. Supply Current (AIDD) vs. Code  
8
6
4
2
–6.6  
–6.7  
–6.8  
–6.9  
–7.0  
–7.1  
0
–2  
AI  
AI  
AI  
DD  
SS  
CC  
±10V RANGE  
–4  
–6  
–8  
–10  
–40  
–20  
0
20  
40  
60  
80  
100  
0
10000  
20000  
30000  
CODE  
40000  
50000  
60000  
TEMPERATURE (°C)  
Figure 56. Supply Current vs. Temperature  
Figure 54. Supply Current (AISS) vs. Code  
Rev. C | Page 24 of 43  
Data Sheet  
AD5766/AD5767  
DITHER CHARACTERISTICS  
700  
150  
100  
50  
±5V RANGE  
±5V RANGE  
600  
500  
400  
300  
200  
100  
0
0
–50  
–100  
–150  
–200  
–100  
–200  
0
5
10  
15  
20  
25  
0
5
10  
15  
20  
25  
TIME (µs)  
TIME (µs)  
Figure 57. Transient on Dither Selected Channel (Dither Enabled)  
Figure 60. Transient on Nondither Selected Channel (Dither Disabled)  
150  
650  
±5V RANGE  
±5V RANGE  
550  
450  
350  
250  
150  
50  
100  
50  
0
–50  
–100  
–150  
–50  
–150  
0
5
10  
15  
20  
25  
–0.3  
0
0.3  
0.6  
0.9  
1.2  
1.5  
TIME (µs)  
TIME (µs)  
Figure 58. Transient on Nondither Selected Channel (Dither Enabled)  
Figure 61. Dither DC Shift  
200  
0
±5V RANGE  
–0.5  
–1.0  
–1.5  
–2.0  
–2.5  
–3.0  
–3.5  
–4.0  
–4.5  
–5.0  
150  
100  
50  
±5V RANGE  
–10V TO 0V RANGE  
0
AV /AV = RANGE ± 2V  
DD  
SS  
= 5V  
–50  
–100  
AV  
CC  
DITHER SIGNAL: 0.25V p-p  
0
5
10  
15  
20  
25  
1k  
10k  
100k  
1M  
TIME (µs)  
FREQUENCY (Hz)  
Figure 59. Transient on Dither Selected Channel (Dither Disabled)  
Figure 62. Dither Input to DAC Output Attenuation vs. Frequency  
5 V Range and −10 V to 0 V Range)  
(
Rev. C | Page 25 of 43  
 
 
AD5766/AD5767  
Data Sheet  
0
–0.5  
–1.0  
–1.5  
–2.0  
–2.5  
–3.0  
–3.5  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
±5V RANGE  
AV = 5V  
CC  
–90  
–100  
–110  
–120  
–130  
–140  
–150  
–160  
–170  
–180  
–190  
±10V RANGE  
–20V TO 0V RANGE  
–4.0  
–4.5  
–5.0  
AV /AV = RANGE ± 2V  
DD SS  
AV = 5V  
CC  
DITHER SIGNAL: 0.25V p-p  
1k  
10k  
100k  
1M  
100  
1k  
10k  
FREQUENCY (Hz)  
100k  
FREQUENCY (Hz)  
Figure 63. Dither Input to DAC Output Attenuation vs. Frequency  
Figure 66. Total Harmonic Distortion (THD) vs. Frequency  
(
10 V Range and −20 V to 0 V Range)  
0
–0.5  
–1.0  
–1.5  
–2.0  
–2.5  
–3.0  
–3.5  
–4.0  
–4.5  
–5.0  
100  
AV /AV = RANGE ± 2V  
DD  
SS  
AV = 3.3V  
DD  
DITHER SIGNAL: 0.25v p-p  
50  
0
–50  
–100  
–150  
–10V TO +6V RANGE  
–16V TO 0V RANGE  
–20V TO 0V RANGE  
–10V TO 0V RANGE  
–16V TO +10V RANGE  
±10V  
–16V TO 0V RANGE  
–12V TO +14V RANGE  
–10V TO +6V RANGE  
±5V  
AV /AV = RANGE ± 2V  
DD  
SS  
= 5V  
AV  
CC  
DITHER SIGNAL: 0.25V p-p  
1M  
100k  
1k  
10k  
100k  
1M  
1k  
10k  
FREQUENCY (Hz)  
FREQUENCY (Hz)  
Figure 64. Dither Input to DAC Output Attenuation vs. Frequency  
(−10 V to +6 V Range and −16 V to 0 V Range)  
Figure 67. Dither Input to DAC Output Phase Shift vs. Frequency  
0
–0.5  
–1.0  
–1.5  
–2.0  
–2.5  
–3.0  
–12V TO +14V RANGE  
–16V TO +10V RANGE  
–3.5  
–4.0  
–4.5  
–5.0  
AV /AV = RANGE ± 2V  
DD SS  
AV = 5V  
CC  
DITHER SIGNAL: 0.25V p-p  
1k  
10k  
100k  
1M  
FREQUENCY (Hz)  
Figure 65. Dither Input to DAC Output Attenuation vs. Frequency  
(−12 V to +14 V Range and −16 V to +10 V Range)  
Rev. C | Page 26 of 43  
 
Data Sheet  
AD5766/AD5767  
TERMINOLOGY  
Total Unadjusted Error (TUE)  
Dither DC Shift  
Total unadjusted error is a measure of the output error taking  
all the various errors into account, namely INL error, offset  
error, gain error, and output drift over supplies, temperature,  
and time. TUE is expressed in % FSR.  
Dither dc shift is a measurement of the dc voltage difference  
between VOUTx (actual) and VOUTx (ideal) due to the coupling of  
a dither tone to the analog output. It is expressed in LSB.  
Dither Transient  
Relative Accuracy or Integral Nonlinearity (INL)  
Dither transient is the amplitude of the impulse injected into  
the analog outputs due to the enabling or disabling of the dither  
functionality on an output channel. The transients are measured  
the selected output channel and the other nonselected channels.  
It is specified in nV-sec.  
Relative accuracy or integral nonlinearity is a measurement of  
the maximum deviation, in LSBs, from a straight line passing  
through the endpoints of the DAC transfer function. Typical  
INL error vs. DAC code plots are shown in Figure 7 and Figure 10.  
Differential Nonlinearity (DNL)  
DC Power Supply Rejection Ratio (PSRR)  
Differential nonlinearity is the difference between the measured  
change and the ideal 1 LSB change between any two adjacent  
codes. A specified differential nonlinearity of 1 LSB maximum  
ensures monotonicity. This DAC is guaranteed monotonic by  
design. Typical DNL error vs. DAC code plots are shown in  
Figure 12 and Figure 14.  
PSRR indicates how the output of the DAC is affected by  
changes in the supply voltage. PSRR is the ratio of the change in  
V
OUTx to a change in AVDD for a full-scale output of the DAC. It  
is measured in V/V.  
Output Voltage Settling Time  
Output voltage settling time is the amount of time it takes for  
the output of a DAC to settle to a specified level for a ¼ to ¾  
full-scale input change and is measured from the rising edge  
Zero-Scale Error  
Zero-scale error is a measurement of the output error when  
zero code (0x0000) is loaded to the DAC register. Zero code  
error is expressed in mV.  
SYNC  
of  
.
Digital-to-Analog Glitch Impulse  
Zero-Scale Error Temperature Coefficient  
Zero code error drift is a measure of the change in zero code  
error with a change in temperature. It is expressed in µV/°C.  
Digital-to-analog glitch impulse is the impulse injected into the  
analog output when the input code in the DAC register changes  
state. It is normally specified as the area of the glitch in nV-sec,  
and is measured when the digital input code is changed by 1 LSB at  
the major carry transition (0x7FFF to 0x800 for the AD5767  
and 0x7FFF to 0x8000 for the AD5766).  
Bipolar Zero Error  
Bipolar zero error is the deviation of the analog output from the  
ideal half-scale output of 0 V when the DAC register is loaded  
with 0x2000.  
Digital Feedthrough  
Digital feedthrough is a measure of the impulse injected into  
the analog output of the DAC from the digital inputs of the  
DAC, but is measured when the DAC output is not updated. It  
is specified in nV-sec, and measured with a full-scale code change  
on the data bus, that is, from all 0s to all 1s and vice versa.  
Bipolar Zero Error Temperature Coefficient  
Bipolar zero drift is a measure of the change in the bipolar zero  
error with a change in temperature. It is expressed in µV/°C.  
Gain Error  
Gain error is a measure of the span error of the DAC. It is the  
deviation in slope of the DAC transfer characteristic from the  
ideal expressed as % FSR.  
DC Crosstalk  
DC crosstalk is the dc change in the output level of one DAC in  
response to a change in the output of another DAC. It is  
measured with a full-scale output change on one DAC (or  
power-down and power-up) while monitoring another DAC  
maintained at midscale. It is expressed in μV.  
Gain Error Temperature Coefficient  
Gain temperature coefficient is a measurement of the change in  
gain error with changes in temperature. It is expressed in ppm  
of FSR/°C.  
DC crosstalk due to load current change is a measure of the  
impact that a change in load current on one DAC has to  
another DAC kept at midscale. It is expressed in μV/mA.  
Offset Error  
Offset error is a measurement of the difference between VOUTx  
(actual) and VOUTx (ideal), expressed in mV, in the linear region  
of the transfer function. Offset error can be negative or positive.  
Digital Crosstalk  
Digital crosstalk is the glitch impulse transferred to the output  
of one DAC at midscale in response to a full-scale code change  
(all 0s to all 1s and vice versa) in the input register of another  
DAC. It is measured in standalone mode and is expressed in  
nV-sec.  
Offset Error Drift  
Offset error drift is a measurement of the change in offset error  
with a change in temperature. It is expressed in µV/°C.  
Rev. C | Page 27 of 43  
 
AD5766/AD5767  
Data Sheet  
Analog Crosstalk  
Output Noise Spectral Density  
Analog crosstalk is the glitch impulse transferred to the output  
of one DAC due to a change in the output of another DAC. It is  
measured by loading one of the input registers with a full-scale  
code change (all 0s to all 1s and vice versa), then executing a  
software LDAC command (see Table 21), and monitoring the  
output of the DAC whose digital code was not changed. The  
area of the glitch is expressed in nV-sec.  
Output noise spectral density is a measurement of the internally  
generated random noise. Random noise is characterized as a  
spectral density (nV/√Hz). It is measured by loading the DAC  
to midscale and measuring noise at the output. It is measured  
in nV/√Hz.  
DAC-to-DAC Crosstalk  
DAC-to-DAC crosstalk is the glitch impulse transferred to the  
output of one DAC due to a digital code change and subsequent  
analog output change of another DAC. It is measured by  
loading the attack channel with a full-scale code change (all 0s  
to all 1s and vice versa), using the write to and update commands  
while monitoring the output of the victim channel that is at  
midscale. The energy of the glitch is expressed in nV-sec.  
Rev. C | Page 28 of 43  
Data Sheet  
AD5766/AD5767  
THEORY OF OPERATION  
The input coding to the DAC is straight binary, the ideal output  
voltage is given by  
DIGITAL-TO-ANALOG CONVERTER  
The AD5766/AD5767 are 16-channel, 16-bit/12-bit, serial  
input, voltage output DACs capable of providing multiple  
output ranges with 20 mA output current capability. The  
available output voltage ranges are as follows:  
D
N
VOUT = Span×  
+ V  
MIN  
where:  
−20 V to 0 V  
−16 V to 0 V  
−10 V to 0 V  
−10 V to +6 V  
−12 V to +14 V  
−16 V to +10 V  
5 V  
Span is the full extent of the DAC output voltage range from the  
minimum to the maximum limit.  
D is the decimal equivalent of the binary code that is loaded to  
the DAC register.  
N is 4096 for the AD5767 (12-bit version), and 65536 for the  
AD5766 (16-bit version).  
V
MIN is the lowest voltage of the span.  
10 V  
RESISTOR STRING  
The devices operate from four supply voltages: AVCC, AVDD  
,
The resistor string section is shown in Figure 69. It is a  
simplified resistor string structure, each of Value R. The digital  
code loaded to the DAC register determines at which node on  
the string the voltage is connected to be fed into the output  
amplifier. The voltage is tapped off by closing one of the  
switches connecting the string to the amplifier. Because a string  
of resistors is used, the DAC is guaranteed to be monotonic.  
AVSS, and VLOGIC. AVCC is the power supply input voltage for the  
DACs and other low voltage circuitry, whereas AVDD and AVSS  
are the positive and negative analog supplies for the output  
amplifiers. The output amplifiers require +2 V of headroom and  
−2 V of footroom to drive 20 mA with a minimum output  
voltage error of less than 1 LSB. Table 9 shows the power supply  
requirements for the selected output range. VLOGIC defines the  
logic levels for the digital input and output signals.  
R
Table 9. Power Supply Requirements for the Selected  
Output Range  
R
TO OUTPUT  
AMPLIFIER  
Range (V)  
AVSS Maximum (V)  
AVDD Minimum (V)  
R
−20 to 0  
−16 to 0  
−10 to 0  
−10 to +6  
−12 to +14  
−16 to +10  
−5 to +5  
−22  
−18  
−12  
−12  
−14  
−18  
−7  
2.97  
2.97  
2.97  
8
16  
12  
R
R
7
−10 to +10  
−12  
12  
Figure 69. Resistor String  
DAC ARCHITECTURE  
The architecture of one DAC channel consists of a resistor  
string DAC followed by an output buffer amplifier. The voltage  
at the VREF pin provides the reference voltage for the all DAC  
channels. Figure 68 shows a block diagram of the DAC  
architecture.  
POWER-ON RESET (POR)  
The AD5766/AD5767 contain a POR circuit that controls the  
output voltage during power-up. The AD5766/AD5767 outputs  
are clamped to ground at power-up and remain powered up at  
this level until a valid write sequence is made to the span register  
to configure the output range of the DAC. At power-on, the  
dither functionality is also enabled.  
V
REF  
REFERENCE  
BUFFER  
A software executable reset function resets the DAC to the  
power-up state. Command 0111 is reserved for this reset  
function (see Table 30). A minimum time is required between a  
reset and a successful write (see the timing characteristics in  
Table 4). Figure 70 shows the programming sequence to follow  
to configure the AD5766/AD5767 upon power-on.  
DAC  
INPUT  
REGISTER  
RESISTOR  
STRING  
V
X
OUT  
REGISTER  
OUTPUT  
BUFFER AMPLIFIER  
Figure 68. DAC Architecture  
Rev. C | Page 29 of 43  
 
 
 
 
 
 
 
 
AD5766/AD5767  
Data Sheet  
POWER-ON  
(OUTPUTS CLAMPED TO GROUND, DITHER ENABLED)  
SOFTWARE FULL RESET  
DITHER FUNCTIONALITY CONFIGURATION  
DITHER POWER DOWN CONTROL REGISTER WRITE (ONE WRITE COMMAND)  
DITHER SCALE REGISTER WRITE (TWO WRITE COMMAND)  
INVERT DITHER REGISTER WRITE (TWO WRITE COMMAND)  
DAC OUTPUT CONFIGURATION  
• CONFIGURE DAISY-CHAIN MODE (IF REQUIRED)  
SPAN REGISER WRITE (ONE WRITE COMMAND)  
• WRITE REQUIRED CODE TO INPUT/DAC REGISTER  
OUPUT VOLTAGE RANGECHANGE  
Figure 70. Programming Sequence to Write/Enable the AD5766/AD5767 Outputs  
Rev. C | Page 30 of 43  
 
Data Sheet  
AD5766/AD5767  
in the power control register. To address the dither block  
DITHER  
power-down per channel function, D19 to D16 must be set to  
0001 (see Table 26). Table 27 shows how the state of the Bit D16  
corresponds to the mode of operation of the device. The dither  
functionality of any or all DACs can be powered down to the  
selected mode by setting the corresponding 16 bits (D15 to D0)  
to 1.  
External dither signals can be coupled onto any DAC output by  
writing the appropriate value to the dither registers. The dither  
signals are applied to the N0 and N1 input pins (see Figure 71).  
If dither is not required, connect these pins to AGND. The  
dither signals amplitude have a maximum peak-to-peak voltage  
(ac voltage) of 0.25 V p-p, and the absolute input voltage (ac  
and dc voltage) must not exceed the range of 0 V to AVCC. The  
dither signals can be attenuated and/or inverted internally on a  
per channel basis if required. Dither signals in the range of 10  
kHz to 100 kHz can be applied to the dither input pins. Due to  
the nature of the internal dither circuitry, the dc value of the  
output can shift (see Table 1) and the shift can be compensated for.  
For the recommended configuration of the dither functionality,  
see the Applications Information section.  
Ensure that all channels are powered up before writing to the  
span register.  
MONITOR MUX  
The AD5766/AD5767 contain a channel monitor function that  
consists of an analog multiplexer addressed via the serial  
interface, allowing any channel output to be routed to the  
common MUX_OUT pin for external monitoring.  
Because the MUX_OUT pin is not buffered, the amount of  
current drawn from this pin creates a voltage drop across the  
switches, which in turn leads to an error in the voltage being  
monitored. Therefore, the MUX_OUT pin must be connected  
to only high impedance inputs or externally buffered.  
DITHER POWER-DOWN MODE  
The AD5766/AD5767 contain a dither block power-down  
mode per channel. Command 0101 is reserved for the power-  
down function (see Table 10). The power-down mode is  
software-programmable by setting four bits, Bit D19 to Bit D16,  
V
V
DAC0  
DAC 0  
V
DAC0  
SELECT N0/N1/NO  
DITHER SIGNAL  
V
AC p-p  
t
DITHER SCALE  
INVERT DITHER  
V
INVERTED SIGNAL  
100%  
75%  
BAND-PASS  
N0  
FILTER  
50%  
25%  
NOT INVERTED SIGNAL  
V
N0p-p  
t
DITHER SCALE  
INVERT DITHER  
V
INVERTED SIGNAL  
100%  
75%  
BAND-PASS  
FILTER  
N1  
NOT INVERTED SIGNAL  
50%  
25%  
V
N1p-p  
t
Figure 71. Dither Signal Generation  
Rev. C | Page 31 of 43  
 
 
 
 
AD5766/AD5767  
Data Sheet  
to be addressed clocks out at the same time that the second  
register to be read is being addressed.  
SERIAL INTERFACE  
SYNC  
The AD5766/AD5767 4-wire (  
interface is compatible with SPI, QSPI, and MICROWIRE  
interface standards as well as most digital signal processors  
, SCLK, SDI, and SDO)  
Daisy-Chain Operation  
Daisy chaining minimizes the number of port pins required  
from the controlling IC. As shown in Figure 72, the SDO pin of  
one package must be tied to the SDI pin of the next package. To  
enable daisy-chain mode, the DC_EN bit in Table 15 must be  
high. When two AD5766/AD5767 devices are daisy-chained,  
48 bits of data are required. The first 24 bits are assigned to U2,  
and the second 24 bits are assigned to U1, as shown in Figure 72.  
SYNC  
SYNC  
(DSPs). The write sequence begins after bringing the  
line  
low, maintaining this line low until the complete data-word is  
loaded from the SDI pin. Data is loaded into the AD5766/AD5767  
at the SCLK falling edge transition (see Figure 2). When a rising  
SYNC  
edge is detected on  
, the serial data-word is decoded  
according to the instructions in Table 10. The command must  
be a multiple of 24; otherwise, the device ignores the command.  
The AD5766/AD5767 contain an SDO pin to allow the user to  
daisy-chain multiple devices together or to read back the  
contents of the status register.  
Keep the  
respective serial registers.  
SYNC  
pin low until all 48 bits are clocked into their  
The  
pin is then pulled high to complete the operation.  
To prevent data from mislocking (for example, due to noise) the  
device includes an internal counter; if the SCLK falling edges  
count is not a multiple of 24, the device ignores the command.  
A valid clock count is 24, 48, 72, and so on. The counter resets  
Readback Operation  
The contents of the status registers can be read back via the  
SDO pin. Figure 4 shows how the registers are decoded. After a  
register has been addressed for a read, the next 24 clock cycles  
clock the data out on the SDO pin. The clocks must be applied  
while SYNC is low. For a read of a single register, the no  
operation (NOP) function clocks out the data. Alternatively, if  
more than one register is to be read, the data of the first register  
SYNC  
when  
returns high.  
Daisy-chain mode is disabled by default and is enabled using  
the daisy-chain control register (see Table 15).  
AD5766/  
AD5767  
AD5766/  
AD5767  
MOSI  
SDI U1 SDO  
SDI U2 SDO  
MICROCONTROLLER  
MISO SCLK SS  
SYNC SCLK  
SYNC SCLK  
Figure 72. Daisy-Chain Block Diagram  
Rev. C | Page 32 of 43  
 
 
Data Sheet  
AD5766/AD5767  
REGISTER DETAILS  
INPUT SHIFT REGISTER  
The input shift register of the AD5766/AD5767 are 24 bits wide. Data is loaded MSB first (D23). The first four bits are the command bits,  
C3 to C0 (see Figure 73), followed by the 4-bit DAC address bits (see Table 11), and finally the data bits. The 24-bit data-word is  
SYNC  
transferred to the input register on the 24 falling edges of SCLK and are updated on the rising edge of  
.
D23 (MSB)  
D0 (LSB)  
D1 D0  
C3  
C2  
C1  
C0  
A3  
A2  
A1  
A0  
D15 D14 D13 D12 D11 D10  
D9  
D8  
D7  
D6  
D5  
D4  
D3  
D2  
DATA BITS  
COMMAND BITS  
ADDRESS BITS  
Figure 73. Input Shift Register Content  
Table 10. Command Definitions1  
C3 C2 C1 C0 A3 A2 A1 A0 Name  
Description  
0
0
0
0
0
0
0
0
NOP/monitor mux control  
No operation (all zeros register). Monitor mux control  
register (D4 = 1) determines whether a DAC output or no  
output is switched out on the MUX_OUT pin.  
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0
0
0
1
Daisy-chain mode  
Enables/disables the SDO output buffer for daisy-chain  
mode.  
A32 A22 A12 A02 Write to DACx input register Writes data to the input register for the selected DAC  
channel.  
A32 A22 A12 A02 Write to input register and  
DAC register  
Writes data to the input register and DAC register for the  
selected DAC channel.  
Updates the selected DAC register with data from the  
corresponding input register.  
X
X
X
X
Software load DAC (LDAC)  
0
0
0
1
1
1
0
0
0
0
1
1
X
X
0
X
X
0
X
X
0
X
0
1
Span  
Reserved  
Dither power control  
Selects the output span of the AD5766/AD5767.  
Not applicable.  
Powers up/down dither functionality of individual DAC  
channels.  
0
1
1
0
X
0
X
0
X
0
X
0
Write input data to all DAC  
registers  
Software full reset  
Writes data to input registers and DAC registers for all DAC  
channels.  
Writing 0x1234 to this register resets the AD5766/AD5767.  
Selects the register to read back for a selected DAC  
channel.  
0
1
1
0
1
0
1
0
A32 A22 A12 A02 Select register for readback  
1
1
1
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Apply N0 or N1 dither signal Selects whether dither on N0, dither on N1, or no dither is  
to DACs (DAC 7 to DAC 0) applied to each DAC output.  
Apply N0 or N1 dither signal Selects whether dither on N0, dither on N1, or no dither is  
to DACs (DAC 15 to DAC 8)  
applied to each DAC output.  
Dither scale (DAC 7 to  
DAC 0)  
Scales the dither signal applied to the selected DAC  
outputs.  
Dither scale (DAC 15 to  
DAC 8)  
Scales the dither signal applied to the selected DAC  
outputs.  
Invert dither  
Inverts the dither signal applied to the selected DAC  
outputs.  
1
1
1
1
1
1
0
1
X
X
X
X
X
X
X
X
Reserved  
Reserved  
Not applicable.  
Not applicable.  
1 X means don’t care.  
2 See Table 11 for the address bit setting.  
Rev. C | Page 33 of 43  
 
 
 
 
AD5766/AD5767  
Data Sheet  
Table 11 shows the DAC x address commands. For applications using the WLCSP package that do not require all 16 channels, do not use  
Channel 8 because it is more sensitive to crosstalk and digital feedthrough.  
Table 11. DAC x Address Commands  
Address  
A3  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
A2  
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
A1  
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
A0  
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Selected DAC  
DAC 0  
DAC 1  
DAC 2  
DAC 3  
DAC 4  
DAC 5  
DAC 6  
DAC 7  
DAC 8  
DAC 9  
DAC 10  
DAC 11  
DAC 12  
DAC 13  
DAC 14  
DAC 15  
MONITOR MUX CONTROL  
The monitor mux control command determines whether one of the DAC outputs or none is switched out on the MUX_OUT pin  
depending on the desired D[4:0] value. To assert the no operation command, write all zeros to the D15 to D0 bits.  
Table 12. Monitor Mux Control Register  
D23  
D22  
D21  
D20  
D19  
D18  
D17  
D16  
D1± to D±  
D4 to D0  
0
0
0
0
0
0
0
0
Don’t care  
VOUT_SEL  
Table 13. Output Voltage Selection from Mux  
VOUT_SEL, Bits[4:0]1  
Mux Output  
No output is switched out  
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VOUT  
VOUT  
VOUT  
VOUT  
VOUT  
VOUT  
VOUT  
VOUT  
VOUT  
VOUT  
VOUT10  
VOUT11  
VOUT12  
VOUT13  
VOUT14  
VOUT15  
0
1
2
3
4
5
6
7
8
9
1 X means don’t care.  
Rev. C | Page 34 of 43  
 
 
Data Sheet  
AD5766/AD5767  
NO OPERATION  
Writing all zeros does not vary the state of the device.  
Table 14. No Operation Register  
D23  
D22  
D21  
D20  
D19  
D18  
D17  
D16  
D1± to D0  
0000 0000 0000 0000  
0
0
0
0
0
0
0
0
DAISY-CHAIN MODE  
To use the daisy-chain mode, enable the DC_EN bit in the daisy-chain control register. This bit is linked to the internal SDO buffer. If the  
functionality is not required, set the DC_EN bit to 0 to save the power consumed by the SDO buffer.  
Table 15. Daisy-Chain Control Register  
D23  
D22  
D21  
D20  
D19  
D18  
D17  
D16  
D1± to D1  
D0  
0
0
0
0
0
0
0
1
Don’t care  
DC_EN  
Table 16. Daisy-Chain Enable/Disable Bit Description  
DC_EN  
Description  
0
1
Daisy chain disabled (default)  
Daisy chain enabled  
WRITE AND UPDATE COMMANDS  
Write to DAC x Input Register  
This command allows the user to write to the dedicated input register of each DAC individually. The output of the DAC does not change  
its value until a write to the software LDAC register occurs with the appropriate bit set to include the addressed channel in the update.  
Table 17. AD5766 Write to DAC x Input Register  
D23  
D22  
D21  
D20  
D19 to D16  
D1± to D0  
0
0
0
1
DAC x address (see Table 11)  
Input register data  
Table 18. AD5767 Write to DAC x Input Register  
D23  
D22  
D21  
D20  
D19 to D16  
D1± to D4  
D3 to D0  
0
0
0
1
DAC x address (see Table 11)  
Input register data  
Don’t care  
Write to Input Register and DAC Register  
This command writes directly to the selected DAC register and updates the output accordingly.  
Table 19. AD5766 Write to DACx Input and DAC Register  
D23  
D22  
D21  
D20  
D19 to D16  
D1± to D0  
0
0
1
0
DAC x address (see Table 11)  
Input register data  
Table 20. AD5767 Write to DACx Input and DAC Register  
D23  
D22  
D21  
D20  
D19 to D16  
D1± to D4  
D3 to D0  
0
0
1
0
DAC x address (see Table 11)  
Input register data  
Don’t care  
Software LDAC Register  
This command copies data from the selected input registers to the corresponding DAC registers and the outputs update accordingly.  
Table 21. Software LDAC Register  
D23  
D22  
D21  
D20  
D19 to D16  
D1± to D0  
0
0
1
1
Don’t care  
LDAC (bit for each channel)  
Table 22. LDAC Bit Description  
LDAC  
Description  
0
1
Do not update channel  
Update channel  
Rev. C | Page 35 of 43  
 
 
 
 
 
AD5766/AD5767  
Data Sheet  
SPAN REGISTER  
This register selects the output span of the AD5766/AD5767. See Table 24 and Table 25. Always issue a software reset before writing to the  
span register.  
Table 23. Span Register  
D23  
D22  
D21  
D20  
D19 to D±  
D4 to D3  
D2 to D0  
0
1
0
0
Don’t care  
P[1:0] (power-up condition)  
S[2:0] (span)  
Table 24. Span Selection  
S2  
S1  
S0  
0
Output Voltage Range  
0
0
−20 V to 0 V  
0
0
1
−16 V to 0 V  
0
1
0
−10 V to 0 V  
0
1
1
1
1
0
0
1
1
0
1
0
−12 V to +14 V  
−16 V to +10 V  
−10 V to +6 V  
−5 V to +5 V  
−10 V to +10 V  
1
1
1
Table 25. Power-Up Condition Selection  
P1  
P0  
Power-Up Condition  
Zero scale  
0
0
0
1
Midscale  
1
Don’t care  
Full scale  
DITHER POWER CONTROL REGISTER  
The dither power control register with D[19:16] = 0001 powers up or powers down the dither functionality of the individual DACs. It is  
recommended to power down the selected channel dither block during the first write to the AD5766/AD5767 if no dither tone is input on  
to the dither inputs N0 or N1.  
Table 26. Dither Power Control Register  
D23 D22 D21 D20 D19 D18 D17 D16 D1± to D0  
0
1
0
1
0
0
0
1
Power-down bit for each channel dither block (for example, D15 = DAC 15,  
D8 = DAC 8, and D0 = DAC 0)  
Table 27. Dither Power Control  
D16  
Operating Mode  
0
1
Normal operation (default)  
Powered down  
WRITE INPUT DATA TO ALL DAC REGISTERS  
This command writes the data in D[15:0] to the DAC register of all DACs and sets all DAC outputs to the same value. For the  
AD5766/AD5767, the data is written in D[15:0] for the 16-bit resolution DAC and in D[15:4] for the 12-bit resolution version.  
Table 28. AD5766 Write Input Data to All DAC Registers  
D23  
D22  
D21  
D20  
D19 to D16  
D1± to D0  
0
1
1
0
Don’t care  
DAC register data  
Table 29. AD5767 Write Input Data to All DAC Registers  
D23  
D22  
D21  
D20  
D19 to D16  
D1± to D4  
D3 to D0  
0
1
1
0
Don’t care  
DAC register data  
Don’t care  
Rev. C | Page 36 of 43  
 
 
 
 
 
 
 
Data Sheet  
AD5766/AD5767  
SOFTWARE FULL RESET  
Writing 0x1234 initiates a reset routine, which returns the AD5766/AD5767 to the power-on state.  
Table 30. Software Full Reset Register  
D23  
D22  
D21  
D20  
D19 to D16  
D1± to D12  
D11 to D8  
D7 to D4  
D3 to D0  
0
1
1
1
0000  
0001  
0010  
0011  
0100  
SELECT REGISTER FOR READBACK  
This command selects which registers to read back (see Table 31). After issuing this command, the contents of the selected registers are  
clocked out on the SDO on the next 24-bit frame (see Table 32).  
Table 31. Initiate Readback Register  
D23  
D22  
D21  
D20  
D19 to D16  
D1± to D0  
1
0
0
0
DAC x address (see Table 11)  
Don’t care  
Table 32. Readback Data Register  
D23 D22 D21 D20 D19 to D16  
D1± to D10 D9  
000000 Invert  
dither  
D8 to D7  
D6 to D±  
D4  
D3  
D2 to D0  
1
0
0
0
DAC x address  
(see Table 11)  
Dither scale Dither  
signal  
Reserved Reserved  
Span S[2:0]  
Table 33. Readback Register Data Functions  
Bit Name  
Description  
Span S[2:0]  
Span register  
D2  
0
0
0
0
1
1
1
1
D1  
0
0
1
1
0
0
1
1
D0  
Output Voltage Range  
−20 V to 0 V  
−16 V to 0 V  
0
1
0
1
0
1
0
1
−10 V to 0 V  
−12 V to +14 V  
−16 V to +10 V  
−10 V to +6 V  
−5 V to +5 V  
−10 V to +10 V  
Reserved  
This is a reserved bit; ignore its contents  
Dither Signal  
Apply N0 or N1 dither signal to DACs register  
D6  
0
0
1
1
D±  
0
1
0
1
Dither Setting  
No dither applied  
N0 dither applied  
N1 dither applied  
No dither applied  
Dither Scale  
Invert Dither  
Dither scale register  
D8  
0
D7  
0
Scaling Factor  
No scaling  
0
1
1
1
0
1
75% scaling  
50% scaling  
25% scaling  
Invert dither register  
D9  
0
1
Dither Mode  
Dither signal is not inverted  
Dither signal is inverted  
Rev. C | Page 37 of 43  
 
 
 
 
 
AD5766/AD5767  
Data Sheet  
APPLY N0 OR N1 DITHER SIGNAL TO DACs REGISTER  
These commands determine which dither signal, N0 or N1, is applied to the selected DACs. Couple the dither signals to the AD5766/  
AD5767 outputs after the dither signals are configured and the clamp to ground is removed by writing to the span register. Refer to the  
Applications Information section for a more information.  
Table 34. Apply N0 or N1 Dither Signal to DACs Register (DAC 7 to DAC 0)  
D23 to D20  
D19 to D16  
D1± to D14  
D13 to D12  
D11 to D10  
D9 to D8 D7 to D6 D± to D4 D3 to D2 D1 to D0  
1001  
Don’t care  
DAC 7  
DAC 6  
DAC 5  
DAC 4 DAC 3 DAC 2 DAC 1 DAC 0  
Table 35. Apply N0 or N1 Dither Signal to DACs Register (DAC 15 to DAC 8)  
D23 to D20  
D19 to D16  
D1± to D14  
D13 to D12  
D11 to D10  
D9 to D8 D7 to D6 D± to D4 D3 to D2 D1 to D0  
1010  
Don’t care  
DAC 15  
DAC 14  
DAC 13  
DAC 12 DAC 11 DAC 10 DAC 9 DAC 8  
Table 36 shows the dither scaling setting using Bits[D15:D14] as an example. To apply the N0 dither to DAC 7 (see Table 34), set D15 to 0  
and D14 to 1. The same dither selection settings apply to the other bits, Bits[D13:D12], Bits[D11:D10], Bits[D9:D8], Bits[D7:D6],  
Bits[D5:D4], Bits[D3:D2], and Bits[D1:D0] in Table 34 and Table 35.  
Table 36. Dither Selection for DAC x (DAC 0 to DAC 15)  
D1±  
D14  
Dither Setting  
0
0
1
1
0
1
0
1
No dither applied  
N0 dither signal applied  
N1 dither signal applied  
No dither applied  
DITHER SCALE  
This command scales the dither before it is applied to the selected channel.  
Table 37. Dither Scaling Register (DAC 7 to DAC 0)  
D23 to  
D20  
D19 to D16  
D1± to D14  
D13 to D12  
D11 to D10  
D9 to D8  
D7 to D6  
D± to D4  
D3 to D2  
D1 to D0  
1100  
Don’t care  
DAC 7  
DAC 6  
DAC 5  
DAC 4  
DAC 3  
DAC 2  
DAC 1  
DAC 0  
Table 38. Dither Scaling Register (DAC 15 to DAC 8)  
D23 to  
D20  
D19 to D16  
D1± to D14  
D13 to D12  
D11 to D10  
D9 to D8  
D7 to D6  
D± to D4  
D3 to D2  
D1 to D0  
1101  
Don’t care  
DAC 15  
DAC 14  
DAC 13  
DAC 12  
DAC 11  
DAC 10  
DAC 9  
DAC 8  
Table 39 shows the dither scaling setting using Bits[D15:D14] as an example. To apply 25% scaling to DAC 7 (see Table 37), set D15 to 1  
and D14 to 1. The same dither scaling settings apply to the other bits, Bits[D13:D12], Bits[D11:D10], Bits[D9:D8], Bits[D7:D6],  
Bits[D5:D4], Bits[D3:D2], and Bits[D1:D0] in Table 34 and Table 35.  
Table 39. Apply Dither Signal to DAC x (DAC 0 to DAC 15)  
D1±  
D14  
Scaling Factor  
0
0
1
1
0
1
0
1
No scaling  
75% scaling  
50% scaling  
25% scaling  
Rev. C | Page 38 of 43  
 
 
 
 
 
 
 
Data Sheet  
AD5766/AD5767  
INVERT DITHER REGISTER  
This command inverts the dither applied to the selected DACs when the appropriate bit is set to 0.  
Table 40. Invert Dither Register  
D23  
D22  
D21  
D20  
D19 to D16  
D1± to D0  
1
0
1
1
Don’t care  
Dx (invert dither bit for each channel)  
Table 41. Invert Dither  
Dx  
Dither Mode  
0
1
Dither signal is not inverted (default)  
Dither signal is inverted  
Rev. C | Page 39 of 43  
 
AD5766/AD5767  
Data Sheet  
APPLICATIONS INFORMATION  
The power required on the AVDD rail for the AD5766/AD5767  
to supply the 16 channels and 6 mA typical supply current is  
DITHER CONFIGURATION  
The AD5766/AD5767 contain two dither input pins to allow dither  
tone signals to be coupled to any of the 16 DAC output channels.  
12 V × (32 mA + 6 mA) = 0.456 W  
Next, add power dissipated by the AVSS, AVCC, and VLOGIC rails  
(input power) as follows:  
Operate the AD5766/AD5767 using the dither functionality to  
minimize the transient amplitude seen on the DAC outputs when  
the dither functionality is enabled or disabled. The recommended  
configuration of the dither functionality is as follows:  
0.456 W + (−12 V × −9 mA) + (3.3 V × 8.3 mA) + (3.3 V ×  
0.02 μA) = 0.59 W  
1. After the AD5766/AD5767 power up, the input dither  
signals must be configured by writing to the dither scale  
register and the invert dither register if required.  
2. Configure the AD5766/AD5767 in normal operating mode  
before applying dither by programming the span register.  
3. Write to the apply N0 or N1 dither signal to DACs register  
to couple the N0/N1 input dither signals to any DAC  
output, VOUTx.  
To calculate the power dissipated by the AD5766/AD5767, use  
the following equation:  
P
DISS = Input Power Output Power  
For example,  
0.59 W − (32 mA × 1 V) = 0.558 W  
Then, calculate the die temperature,  
0.558 W × 53°C/W = 29.57°C  
Enabling the dither feature on a channel can increase its  
sensitivity to digital feedthrough.  
Using the following equation to calculate the maximum  
permitted ambient temperature:  
THERMAL CONSIDERATIONS  
T
A MAX = TJ MAX Die Temperature  
For example,  
150°C − 29.57° = 120°C  
Up to 20 mA can be sourced from each channel on the  
AD5766/AD5767; thus, it is important to understand the effects  
of power dissipation on the package and its effects on junction  
temperature. The internal junction temperature must not  
exceed 150°C. The AD5766/AD5767 are packaged in a 49-ball,  
4 mm × 4mm WLCSP and a 40-lead 6 mm × 6 mm LFCSP  
package. The thermal impedance, θJA, is specified in the  
Absolute Maximum Ratings section. It is important that the  
device is not operated under conditions that cause the junction  
temperature to exceed the maximum temperature specified in  
the Absolute Maximum Ratings section.  
The θJA specification assumes that proper layout and grounding  
techniques are followed to minimize power dissipation, as  
outlined in the Layout Guidelines section  
MICROPROCESSOR INTERFACING  
Microprocessor interfacing to the AD5766/AD5767 is via a  
serial bus that uses a standard protocol compatible with DSPs  
and microcontrollers. The communications channel requires a  
4-wire serial interface consisting of a clock signal, a data input  
signal, a data output signal, and a synchronization signal. The  
device requires a 24-bit data-word with data valid on the falling  
edge of SCLK.  
The Thermal Calculation Example (WLCSP) section details  
how to calculate the die temperature and maximum permitted  
ambient temperature. The quiescent current of the AVDD, AVSS,  
AVCC, and VLOGIC pins must also be included in the calculation  
of the junction temperature. These calculations use the typical  
supply currents specified in Table 1.  
AD5766/AD5767 TO SPI INTERFACE  
The SPI interface of the AD5766/AD5767 is designed to be easily  
connected to industry-standard DSPs and microcontrollers.  
Figure 74 shows the AD5766/AD5767 connected to the Analog  
Devices, Inc., ADSP-BF531 Blackfin® DSP. The Blackfin has an  
integrated SPI port that can be connected directly to the SPI  
pins of the AD5766/AD5767.  
Thermal Calculation Example (WLCSP)  
For this thermal calculation example, all 16 channels are  
enabled with the 10 V output voltage range used. Each channel  
is drawing 2 mA for a +1V output voltage.  
AVDD = Span + 2 V = 12 V  
AVSS = Span − 2 V = −12 V  
AD5766/AD5767  
ADSP-BF531  
AVCC = VLOGIC = 3.3 V  
where Span is the output voltage range, 10 V.  
The current required to supply 16 channels (output power) is  
2 mA × 16 = 32 mA  
SPISELx  
SCK  
SYNC  
SCLK  
DIN  
MOSI  
MISO  
SDO  
PF8  
RESET  
Figure 74. ADSP-BF531 SPI Interface  
Rev. C | Page 40 of 43  
 
 
 
 
 
 
 
Data Sheet  
AD5766/AD5767  
at right angles to each other to reduce feedthrough effects  
LAYOUT GUIDELINES  
through the board. The best board layout technique is the  
microstrip technique, where the component side of the board is  
dedicated to the ground plane only, and the signal traces are  
placed on the solder side. However, this technique is not always  
possible with a 2-layer board.  
In any circuit where accuracy is important, careful consideration  
of the power supply and ground return layout helps to ensure  
the rated performance. The PCB on which the AD5766/AD5767  
are mounted must be designed so that the AD5766/AD5767 lay  
on the analog plane. Ensure that the board has separate analog  
and digital sections. If the AD5766/AD5767 are in a system  
where other devices require an AGND to DGND connection,  
make the connection at one point only. Keep this ground point  
as close as possible to the AD5766/AD5767.  
It is often useful to provide some heat sinking capability to  
allow the power to dissipate easily.  
For the WLCSP package, heat is transferred through the solder  
balls to the PCB board. θJA thermal impedance is dependent on  
board construction. More copper layers enable heat to be  
removed more effectively.  
The AD5766/AD5767 must have ample supply bypassing of 10 µF  
in parallel with 0.1 µF on each supply, located as close to the  
package as possible, ideally right up against the device. The  
10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor  
must have low effective series resistance (ESR) and low effective  
series inductance (ESI). Ceramic capacitors, for example, provide  
a low impedance path to ground at high frequencies to handle  
transient currents due to internal logic switching.  
The LFCSP package of the AD5766/AD5767 have an exposed  
pad beneath the device. Connect this pad to the AVSS supply of  
the device. For optimum performance, use special  
consideration when designing the motherboard and mounting  
the package. For enhanced thermal, electrical, and board level  
performance, solder the exposed pad on the bottom of the  
package to the corresponding thermal land pad on the PCB.  
Design thermal vias into the PCB land pad area to improve heat  
dissipation further.  
Ensure that the power supply line has as large a trace as possible  
to provide a low impedance path and reduce glitch effects on  
the supply line. Shield clocks and other fast switching digital  
signals from other parts of the board by using a digital ground.  
Avoid crossover of digital and analog signals if possible. When  
traces cross on opposite sides of the board, ensure that they run  
The AVSS plane on the device can be increased (as shown in  
Figure 75) to provide a natural heat sinking effect.  
AV  
SS  
PLANE  
BOARD  
Figure 75. Exposed Pad Connection to Board  
Rev. C | Page 41 of 43  
 
 
AD5766/AD5767  
Data Sheet  
OUTLINE DIMENSIONS  
4.000  
3.960 SQ  
3.920  
7
6
5
4
3
2
1
A
BALL A1  
IDENTIFIER  
B
C
D
E
F
3.00 REF  
SQ  
G
0.50  
BSC  
TOP VIEW  
(BALL SIDE DOWN)  
BOTTOM VIEW  
(BALL SIDE UP)  
0.380  
0.355  
0.330  
0.650  
0.595  
0.540  
END VIEW  
COPLANARITY  
0.05  
0.340  
0.320  
0.300  
SEATING  
PLANE  
0.270  
0.240  
0.210  
Figure 76. 49-Ball Wafer Level Chip Scale Package [WLCSP]  
(CB-49-4)  
Dimensions shown in millimeters  
DETAIL A  
(JEDEC 95)  
6.10  
6.00 SQ  
5.90  
0.30  
0.25  
0.18  
PIN 1  
INDICATOR  
PIN 1  
INDIC ATOR AREA OPTIONS  
(SEE DETAIL A)  
31  
40  
1
30  
0.50  
BSC  
4.70  
EXPOSED  
PAD  
4.60 SQ  
4.50  
10  
21  
11  
20  
0.45  
0.40  
0.35  
0.20 MIN  
TOP VIEW  
END VIEW  
BOTTOM VIEW  
FOR PROPER CONNECTION OF  
THE EXPOSED PAD, REFER TO  
THE PIN CONFIGURATION AND  
FUNCTION DESCRIPTIONS  
0.80  
0.75  
0.70  
0.05 MAX  
0.02 NOM  
SECTION OF THIS DATA SHEET.  
COPLANARITY  
0.08  
0.203 REF  
SEATING  
PLANE  
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD-5  
Figure 77. 40-Lead Lead Frame Chip Scale Package [LFCSP]  
6 mm × 6 mm and 0.75 mm Package Height  
(CP-40-7)  
Dimensions shown in millimeters  
Rev. C | Page 42 of 43  
 
Data Sheet  
AD5766/AD5767  
ORDERING GUIDE  
2
Model1  
Resolution (Bits) Temperature Range Package Description  
Package Option  
,
AD5766BCBZ-RL7  
AD5766BCPZ-RL7  
AD5767BCBZ-RL7  
AD5767BCPZ-RL7  
EVAL-AD5766SD2Z  
EVAL-AD5767SD2Z  
EVAL-SDP-CB1Z  
16  
16  
12  
12  
−40°C to +105°C  
−40°C to +105°C  
−40°C to +105°C  
−40°C to +105°C  
49-Ball Wafer Level Chip Scale Package [WLCSP]  
40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-7  
CB-49-4  
49-Ball Wafer Level Chip Scale Package [WLCSP]  
40-Lead Lead Frame Chip Scale Package [LFCSP] CP-40-7  
CB-49-4  
Evaluation Board  
Evaluation Board  
Controller Board  
1 Z = RoHS Compliant Part.  
2 To interface with the EVAL-AD5767SD2Z an EVAL-SDP-CB1Z is also required.  
©2017–2018 Analog Devices, Inc. All rights reserved. Trademarks  
and registered trademarks are the property of their respective  
owners.  
D1±14±-0-1/18(C)  
Rev. C | Page 43 of 43  
 

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