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AD5821AD-WAFER [ADI]

120 mA, Current Sinking, 10-Bit, I2C DAC; 120毫安，吸收电流， 10位， I2C DAC
AD5821AD-WAFER
型号： AD5821AD-WAFER
厂家： ADI    ADI
描述：

120 mA, Current Sinking, 10-Bit, I2C DAC
120毫安，吸收电流， 10位， I2C DAC
文件： 总16页 (文件大小：433K)
中文：  中文翻译
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120 mA, Current Sinking,  
10-Bit, I2C DAC  
AD5821A  
Industrial  
FEATURES  
Heater controls  
Fan controls  
Current sink: 120 mA  
Available in 3 × 3 array WLCSP package  
2-wire, (I2C-compatible) 1.8 V serial interface  
10-bit resolution  
Integrated current sense resistor  
Power supply range: 2.7 V to 5.5 V  
Guaranteed monotonic over all codes  
Power down to 0.5 μA typical  
Internal reference  
Cooler (Peltier) controls  
Solenoid controls  
Valve controls  
Linear actuator controls  
Light controls  
Current loop controls  
GENERAL DESCRIPTION  
Ultralow noise preamplifier  
Power-down function  
Power-on reset  
The AD5821A is a single, 10-bit digital-to-analog converter  
(DAC) with output current sinking capability of 120 mA. It  
features an internal reference and operates from a single 2.7 V  
to 5.5 V supply. The DAC is controlled via a 2-wire, I2C®-  
compatible serial interface that operates at clock rates up to  
400 kHz.  
APPLICATIONS  
Consumer  
Lens autofocus  
Image stabilization  
Optical zoom  
Shutters  
Iris/exposure  
Neutral density (ND) filters  
Lens covers  
The AD5821A incorporates a power-on reset circuit that  
ensures the DAC output powers up to 0 V and remains there until  
a valid write takes place. It has a power-down feature that reduces  
the current consumption of the device to 1 μA maximum.  
The AD5821A is designed for autofocus, image stabilization,  
and optical zoom applications in camera phones, digital still  
cameras, and camcorders.  
Camera phones  
Digital still cameras  
Camera modules  
Digital video cameras/camcorders  
Camera-enabled devices  
Security cameras  
Web/PC cameras  
The AD5821A is also suitable for many industrial applications,  
such as controlling temperature, light, and movement without  
derating over temperatures ranging from −30°C to +85°C.  
The I2C 7-bit address for the AD5821A is 0xC.  
FUNCTIONAL BLOCK DIAGRAM  
V
XSHUTDOWN  
DGND  
DD  
REFERENCE  
POWER-ON  
RESET  
V
DD  
D1  
SDA  
2
SCL  
10-BIT  
I C SERIAL  
INTERFACE  
I
SINK  
CURRENT  
OUTPUT DAC  
R
SENSE  
3.3Ω  
R
AD5821A  
DGND  
AGND  
Figure 1.  
Rev. 0  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rights of third parties that may result from its use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks and registeredtrademarks arethe property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2008 Analog Devices, Inc. All rights reserved.  
 
AD5821A  
TABLE OF CONTENTS  
Features .............................................................................................. 1  
Typical Performance Characteristics ..............................................7  
Terminology.................................................................................... 10  
Theory of Operation ...................................................................... 11  
Serial Interface............................................................................ 11  
I2C Bus Operation ...................................................................... 11  
Data Format ................................................................................ 11  
Power Supply Bypassing and Grounding................................ 12  
Applications Information.............................................................. 14  
Outline Dimensions....................................................................... 15  
Ordering Guide .......................................................................... 15  
Consumer Applications ................................................................... 1  
Industrial Applications .................................................................... 1  
General Description......................................................................... 1  
Functional Block Diagram .............................................................. 1  
Revision History ............................................................................... 2  
Specifications..................................................................................... 3  
AC Specifications.......................................................................... 4  
Timing Specifications .................................................................. 4  
Absolute Maximum Ratings............................................................ 5  
Pin Configuration and Function Descriptions............................. 6  
REVISION HISTORY  
10/08—Revision 0: Initial Version  
Rev. 0 | Page 2 of 16  
 
AD5821A  
SPECIFICATIONS  
VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance (RL) = 25 Ω connected to VDD. All specifications TMIN to TMAX, unless  
otherwise noted.  
Table 1.  
B Version1  
Parameter  
Min  
Typ  
Max  
Unit  
Test Conditions/Comments  
DC PERFORMANCE  
VDD = 3.6 V to 4.5 V; device operates over 2.7 V to 5.5 V  
with reduced performance  
Resolution  
10  
1.5  
Bits  
LSB  
LSB  
mA  
mA  
117 μA/LSB  
Relative Accuracy2  
Differential Nonlinearity2, 3  
Zero-Code Error2, 4  
Offset Error @ Code 162  
Gain Error2  
4
1
Guaranteed monotonic over all codes  
All 0s loaded to DAC  
0
0.5  
0.5  
1
0.6  
0.5  
% of FSR at 25°C  
μA/°C  
LSB/°C  
Offset Error Drift4, 5  
Gain Error Drift2, 5  
10  
0.2  
OUTPUT CHARACTERISTICS  
Minimum Sink Current4  
Maximum Sink Current  
Output Current During XSHUTDOWN5  
Output Compliance5  
3
120  
80  
mA  
mA  
nA  
V
XSHUTDOWN = 0  
Output voltage range over which maximum 120 mA  
sink current is available  
0.6  
VDD  
VDD  
Output Compliance5  
0.48  
V
Output voltage range over which 90 mA sink current  
is available  
To 10% of FS, coming out of power-down mode; VDD = 5 V  
Power-Up Time5  
LOGIC INPUTS (XSHUTDOWN)5  
20  
3
μs  
Input Current  
1
0.54  
μA  
V
V
Input Low Voltage, VINL  
Input High Voltage, VINH  
Pin Capacitance  
VDD = 2.7 V to 5.5 V  
VDD = 2.7 V to 5.5 V  
1.26  
pF  
LOGIC INPUTS (SCL, SDA)5  
Input Low Voltage, VINL  
Input High Voltage, VINH  
Input Low Voltage, VINL  
Input High Voltage, VINH  
Input Leakage Current, IIN  
Input Hysteresis, VHYST  
Digital Input Capacitance, CIN  
Glitch Rejection6  
−0.3  
1.26  
−0.3  
1.4  
+0.54  
VDD + 0.3  
+0.54  
VDD + 0.3  
1
V
V
V
V
μA  
V
pF  
ns  
VDD = 2.7 V to 3.6 V  
VDD = 2.7 V to 3.6 V  
VDD = 3.6 V to 5.5 V  
VDD = 3.6 V to 5.5 V  
VIN = 0 V to VDD  
0.05 VDD  
6
50  
Pulse width of spike suppressed  
POWER REQUIREMENTS  
VDD  
IDD (Normal Mode)  
2.7  
5.5  
1
V
mA  
0.5  
0.5  
IDD specification is valid for all DAC codes;  
VINH = 1.8 V, VINL = GND, VDD = 2.7 V to 3.6 V  
VINH = 1.8 V, VINL = GND, VDD = 3 V  
IDD (Power-Down Mode)7  
μA  
1 Temperature range for the B version is −30°C to +85°C.  
2 See the Terminology section.  
3 Linearity is tested using a reduced code range: Code 32 to Code 1023.  
4 To achieve near zero output current, use the power-down feature.  
5 Guaranteed by design and characterization; not production tested. XSHUTDOWN is active low. SDA and SCL pull-up resistors are tied to 1.8 V.  
6 Input filtering on both the SCL and the SDA inputs suppress noise spikes that are less than 50 ns.  
7 XSHUTDOWN is active low.  
Rev. 0 | Page 3 of 16  
 
 
 
 
 
 
 
AD5821A  
AC SPECIFICATIONS  
VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, RL = 25 Ω connected to VDD, unless otherwise noted.  
Table 2.  
B Version1, 2  
Parameter  
Min Typ  
250  
Max Unit  
Test Conditions/Comments  
Output Current Settling Time  
Slew Rate  
μs  
mA/μs  
VDD = 3.6 V, RL = 25 Ω, LL = 680 μH, ¼ scale to ¾ scale change (0x100 to 0x300)  
0.3  
Major Code Change Glitch  
Impulse  
Digital Feedthrough3  
0.15  
nA-sec  
1 LSB change around major carry  
0.06  
nA-sec  
1 Temperature range for the B version is −40°C to +85°C.  
2 Guaranteed by design and characterization; not production tested.  
3 See the Terminology section.  
TIMING SPECIFICATIONS  
VDD = 2.7 V to 3.6 V. All specifications TMIN to TMAX, unless otherwise noted.  
Table 3.  
B Version  
Limit at TMIN, TMAX  
Parameter1  
Unit  
Description  
fSCL  
t1  
t2  
t3  
t4  
400  
2.5  
0.6  
1.3  
0.6  
100  
0.9  
0
0.6  
0.6  
1.3  
300  
0
kHz max  
μs min  
μs min  
μs min  
μs min  
ns min  
μs max  
μs min  
μs min  
μs min  
μs min  
ns max  
ns min  
ns max  
ns max  
ns min  
pF max  
SCL clock frequency  
SCL cycle time  
tHIGH, SCL high time  
tLOW, SCL low time  
tHD, STA, start/repeated start condition hold time  
tSU, DAT, data setup time  
tHD, DAT, data hold time  
t5  
t6  
2
t7  
t8  
t9  
t10  
tSU, STA, setup time for repeated start  
tSU, STO, stop condition setup time  
tBUF, bus free time between a stop condition and a start condition  
tR, rise time of both SCL and SDA when receiving  
Can be CMOS driven  
t11  
250  
300  
20 + 0.1 CB  
tF, fall time of SDA when receiving  
tF, fall time of both SCL and SDA when transmitting  
3
CB  
400  
Capacitive load for each bus line  
1 Guaranteed by design and characterization; not production tested.  
2 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VINH MIN of the SCL signal) to bridge the undefined region of the SCL falling edge.  
3 CB is the total capacitance of one bus line in pF. tR and tF are measured between 0.3 VDD and 0.7 VDD  
.
Timing Diagram  
SDA  
t3  
t4  
t9  
t10  
t11  
SCL  
t2  
t7  
t1  
t8  
t4  
t6  
t5  
START  
CONDITION  
REPEATED  
START  
CONDITION  
STOP  
CONDITION  
Figure 2. 2-Wire Serial Interface Timing Diagram  
Rev. 0 | Page 4 of 16  
 
 
 
 
AD5821A  
ABSOLUTE MAXIMUM RATINGS  
TA = 25°C, unless otherwise noted.  
Table 4.  
Parameter  
Stresses above those listed under Absolute Maximum Ratings  
may cause permanent damage to the device. This is a stress  
rating only; functional operation of the device at these or any  
other conditions above those indicated in the operational  
section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect  
device reliability.  
Rating  
VDD to AGND  
VDD to DGND  
AGND to DGND  
SCL, SDA to DGND  
XSHUTDOWN to DGND  
ISINK to AGND  
−0.3 V to +5.5 V  
−0.3 V to VDD + 0.3 V  
−0.3 V to +0.3 V  
−0.3 V to VDD + 0.3 V  
−0.3 V to VDD + 0.3 V  
−0.3 V to VDD + 0.3 V  
Operating Temperature Range  
Industrial (B Version)  
Storage Temperature Range  
ESD CAUTION  
−30°C to +85°C  
−65°C to +150°C  
150°C  
Junction Temperature (TJ MAX  
WLCSP Power Dissipation  
θJA Thermal Impedance1  
)
(TJ MAX − TA)/θJA  
Mounted on 4-Layer Board  
Lead Temperature, Soldering  
Maximum Peak Reflow Temperature2  
95°C/W  
260°C ( 5°C)  
1 To achieve the optimum θJA, it is recommended that the AD5821A be  
soldered on a 4-layer board.  
2 As per JEDEC J-STD-020C.  
Rev. 0 | Page 5 of 16  
 
 
AD5821A  
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS  
3
2
1
A
B
C
VIEW FROM BALL SIDE  
Figure 3. Pin Configuration  
Table 5. Pin Function Descriptions  
Pin Number  
Mnemonic  
Description  
A1  
A2  
A3  
B1  
B2  
B3  
C1  
C2  
C3  
ISINK  
NC  
Output Current Sink.  
No Connection.  
Power-Down. Asynchronous power-down signal, active low.  
Analog Ground Pin.  
Digital Ground Pin.  
I2C Interface Signal.  
Digital Ground Pin.  
Digital Supply Voltage.  
I2C Interface Signal.  
XSHUTDOWN  
AGND  
DGND  
SDA  
DGND  
VDD  
SCL  
1515µm  
NC  
I
SINK  
XSHUTDOWN  
AGND  
DGND  
1690µm  
SDA  
V
DD  
SCL  
DGND  
Figure 4. Metallization Photo  
Dimensions shown in microns (μm)  
Rev. 0 | Page 6 of 16  
 
AD5821A  
TYPICAL PERFORMANCE CHARACTERISTICS  
2.0  
VERT = 50µs/DIV  
INL V = 3.8V  
DD  
TEMP = 25°C  
1.5  
1.0  
0.5  
0
3
HORIZ = 468µA/DIV  
–0.5  
CH3  
M50.0µs  
CODE  
Figure 5. Typical INL vs. Code Plot  
Figure 8. Settling Time for a 4-LSB Step (VDD = 3.6 V)  
0.6  
0.5  
0.4  
0.3  
0.2  
0.1  
0
DNL V = 3.8V  
TEMP = 25°C  
DD  
VERT = 2µA/DIV  
4.8µA p-p  
1
–0.1  
–0.2  
–0.3  
HORIZ = 2s/DIV  
CH1  
M2.0s  
CODE  
Figure 6. Typical DNL vs. Code Plot  
Figure 9. 0.1 Hz to 10 Hz Noise Plot (VDD = 3.6 V)  
92.0  
0.14  
0.12  
0.10  
0.08  
0.06  
0.04  
0.02  
0
I
@ +25°C  
OUT  
91.5  
91.0  
90.5  
90.0  
89.5  
89.0  
88.5  
88.0  
I
@ –40°C  
OUT  
I
@ +85°C  
OUT  
–6  
–6  
–6  
–6  
–6  
250.0  
–6 –6  
300.0 333.1  
53.5  
100.0  
150.0  
200.0  
TIME  
CODE  
Figure 7. ¼ to ¾ Scale Settling Time (VDD = 3.6 V)  
Figure 10. Sink Current vs. Code vs. Temperature (VDD = 3.6 V)  
Rev. 0 | Page 7 of 16  
 
 
 
AD5821A  
2000  
1800  
1600  
1400  
1200  
1000  
800  
0.45  
0.40  
0.35  
0.30  
0.25  
0.20  
0.15  
0.10  
0.05  
0
V
= 3.6V  
DD  
V
= 4.5V  
DD  
V
= 3.8V  
DD  
600  
400  
200  
0
10  
–40 –30 –20 –10  
0
15 25 35 45 55 65 75 85  
100  
1k  
10k  
100k  
FREQUENCY (Hz)  
TEMPERATURE (°C)  
Figure 11. AC Power Supply Rejection Ratio (VDD = 3.6 V)  
Figure 14. Zero-Code Error vs. Temperature vs. Supply Voltage  
3.5  
1.5  
V
= 4.5V  
DD  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0
1.0  
0.5  
POSITIVE INL (V = 3.8V) POSITIVE INL (V = 4.5V)  
DD DD  
V
= 3.8V  
DD  
0
POSITIVE INL (V = 3.6V)  
DD  
–0.5  
–1.0  
–1.5  
–2.0  
NEGATIVE INL (V = 3.6V)  
DD  
NEGATIVE INL (V = 3.8V)  
DD  
–0.5  
–1.0  
V
= 3.6V  
DD  
NEGATIVE INL (V = 4.5V)  
DD  
–40 –30 –20 –10  
0
15 25 35 45 55 65 75 85  
–40 –30 –20 –10  
0
15 25 35 45 55 65 75 85  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 12. INL vs. Temperature vs. Supply Voltage  
Figure 15. Full-Scale Error vs. Temperature vs. Supply Voltage  
1.0  
0.8  
1.4  
V
V
= 5.5V  
= 4.5V  
DD  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
DD  
0.6  
POSITIVE DNL (V = 3.6V)  
DD  
V
V
= 3.6V  
= 2.7V  
DD  
DD  
0.4  
POSITIVE DNL (V = 4.5V)  
DD  
0.2  
0
POSITIVE DNL (V = 3.8V)  
DD  
NEGATIVE DNL (V = 3.8V)  
DD  
–0.2  
–0.4  
–0.6  
–0.8  
–1.0  
NEGATIVE DNL (V = 4.5V)  
DD  
NEGATIVE DNL (V = 3.6V)  
DD  
–40 –30 –20 –10  
0
15 25 35 45 55 65 75 85  
–50  
–30  
–10  
10  
30  
50  
70  
90  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 13. DNL vs. Temperature vs. Supply Voltage  
Figure 16. SCL and SDA Logic High Level (VINH) vs.  
Temperature and Supply Voltage  
Rev. 0 | Page 8 of 16  
AD5821A  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
V
= 5.5V  
DD  
V
= 4.5V  
DD  
V
= 5.5V  
DD  
V
= 4.5V  
DD  
V
= 3.6V  
DD  
V
= 3.6V  
DD  
V
= 2.7V  
DD  
V
= 2.7V  
DD  
–50  
–30  
–10  
10  
30  
50  
70  
90  
–50  
–30  
–10  
10  
30  
50  
70  
90  
TEMPERATURE (°C)  
TEMPERATURE (°C)  
Figure 17. SCL and SDA Logic Low Level (VINL) vs.  
Temperature and Supply Voltage  
Figure 19. DNL vs. XSHUTDOWN Logic Low Level (VINL) vs.  
Temperature and Supply Voltage  
1.4  
1.3  
1.2  
1.1  
1.0  
0.9  
0.8  
0.7  
0.6  
0.5  
0.4  
V
V
V
= 5.5V  
= 4.5V  
= 3.6V  
DD  
DD  
DD  
V
= 2.7V  
DD  
–50  
–30  
–10  
10  
30  
50  
70  
90  
TEMPERATURE (°C)  
Figure 18. XSHUTDOWN Logic High Level (VINH) vs.  
Temperature and Supply Voltage  
Rev. 0 | Page 9 of 16  
AD5821A  
TERMINOLOGY  
Relative Accuracy  
Digital-to-Analog Glitch Impulse  
For the DAC, relative accuracy or integral nonlinearity (INL)  
is a measurement of the maximum deviation, in LSB, from a  
straight line passing through the endpoints of the DAC trans-  
fer function. A typical INL vs. code plot is shown in Figure 5.  
This is the impulse injected into the analog output when the  
input code in the DAC register changes state. It is normally  
specified as the area of the glitch in nanoampere seconds  
(nA-sec) and is measured when the digital input code is  
changed by 1 LSB at the major carry transition.  
Differential Nonlinearity (DNL)  
Differential nonlinearity is the difference between the measured  
change and the ideal 1 LSB change between any two adjacent  
codes. A specified differential nonlinearity of 1 LSB maximum  
ensures monotonicity. This DAC is guaranteed monotonic by  
design. A typical DNL vs. code plot is shown in Figure 6.  
Digital Feedthrough  
Digital feedthrough is a measurement of the impulse injected  
into the analog output of the DAC from the digital inputs of  
the DAC, but it is measured when the DAC output is not  
updated. It is specified in nanoampere seconds (nA-sec) and  
measured with a full-scale code change on the data bus, that is,  
from all 0s to all 1s and vice versa.  
Zero-Code Error  
Zero-code error is a measurement of the output error when zero  
code (0x0000) is loaded to the DAC register. Ideally, the output  
is 0 mA. The zero-code error is always positive in the AD5821A  
because the output of the DAC cannot go below 0 mA. This is  
due to a combination of the offset errors in the DAC and output  
amplifier. Zero-code error is expressed in milliamperes (mA).  
Offset Error  
Offset error is a measurement of the difference between ISINK  
(actual) and IOUT (ideal) in the linear region of the transfer  
function, expressed in milliamperes (mA). Offset error is  
measured on the AD5821A with Code 16 loaded into the DAC  
register.  
Gain Error  
Gain error is a measurement of the span error of the DAC. It is  
the deviation in slope of the DAC transfer characteristic from  
the ideal, expressed as a percent of the full-scale range.  
Offset Error Drift  
Offset error drift is a measurement of the change in offset error  
with a change in temperature. It is expressed in microvolts per  
degree Celsius (μV/°C).  
Gain Error Drift  
Gain error drift is a measurement of the change in gain error  
with changes in temperature. It is expressed in LSB/°C.  
Rev. 0 | Page 10 of 16  
 
AD5821A  
THEORY OF OPERATION  
The AD5821A is a fully integrated, 10-bit DAC with 120 mA  
output current sink capability. It is intended for driving voice  
coil actuators in applications such as lens autofocus, image  
stabilization, and optical zoom. The circuit diagram is shown in  
Figure 20. A 10-bit current output DAC coupled with Resistor R  
generates the voltage that drives the noninverting input of the  
operational amplifier. This voltage also appears across the RSENSE  
resistor and generates the sink current required to drive the  
voice coil.  
When the bus is idle, SCL and SDA are both high. The master  
device initiates a serial bus operation by generating a start  
condition, which is defined as a high-to-low transition on the  
SDA low while SCL is high. The slave device connected to the  
bus responds to the start condition and shifts in the next eight  
data bits under control of the serial clock.  
These eight data bits consist of a 7-bit address, plus a read/write  
W
(R/ ) bit that is 0 if data is to be written to a device, and 1 if  
data is to be read from a device. Each slave device on an I2C bus  
must have a unique address. The address of the AD5821A is  
0001100; however, 0001101, 0001110, and 0001111 address the  
part because the last two bits are unused/don’t cares (see Figure 22  
Resistor R and Resistor RSENSE are interleaved and matched.  
Therefore, the temperature coefficient and any nonlinearities  
over temperature are matched, and the output drift over tempera-  
ture is minimized. Diode D1 is an output protection diode.  
W
and Figure 23). Because the address plus the R/ bit always  
V
XSHUTDOWN  
DGND  
DD  
equals eight bits of data, the write address of the AD5821A is  
00011000 (0x18) and the read address is 00011001 (0x19) (see  
Figure 22 and Figure 23).  
REFERENCE  
POWER-ON  
RESET  
V
DD  
W
At the end of the address data, after the R/ bit, the slave  
D1  
SDA  
SCL  
device that recognizes its own address responds by generating  
an acknowledge (ACK) condition. This is defined as the slave  
device pulling SDA low while SCL is low before the ninth clock  
pulse and keeping it low during the ninth clock pulse. Upon  
receiving the ACK, the master device can clock data into the  
AD5821A in a write operation, or it can clock it out in a read  
operation. Data must change either during the low period of the  
clock (because SDA transitions during the high period define a  
start condition), or during a stop condition, as described in the  
Data Format section.  
10-BIT  
2
I C SERIAL  
I
SINK  
CURRENT  
INTERFACE  
OUTPUT DAC  
R
SENSE  
R
3.3Ω  
AD5821A  
DGND  
AGND  
Figure 20. Block Diagram Showing Connection to Voice Coil  
SERIAL INTERFACE  
The AD5821A is controlled using the industry-standard I2C  
2-wire serial protocol. Data can be written to or read from the  
DAC at data rates of up to 400 kHz. After a read operation, the  
contents of the input register are reset to all 0s.  
I2C data is divided into blocks of eight bits, and the slave generates  
an ACK at the end of each block. Because the AD5821A requires  
10 bits of data, two data-words must be written to it when a  
write operation occurs, or read from it when a read operation  
occurs. At the end of a read or write operation, the AD5821A  
acknowledges the second data byte. The master generates a stop  
condition, defined as a low-to-high transition on SDA while SCL  
is high, to end the transaction.  
I2C BUS OPERATION  
An I2C bus operates with one or more master devices that  
generate the serial clock (SCL) and read and write data on  
the serial data line (SDA) to and from slave devices such as  
the AD5821A. On all devices on an I2C bus, the SDA pin is  
connected to the SDA line and the SCL pin connected to the  
SCL line of the master device. I2C devices can only pull the bus  
lines low; pulling high is achieved by pull-up resistors, RP. The  
value of RP depends on the data rate, bus capacitance, and the  
maximum load current that the I2C device can sink (3 mA for a  
standard device).  
DATA FORMAT  
Data is written to the AD5821A high byte first, MSB first, and is  
shifted into the 16-bit input register. After all data is shifted in,  
data from the input register is transferred to the DAC register.  
Because the DAC requires only 10 bits of data, not all bits of the  
input register data are used. The MSB is reserved for an active-  
high, software-controlled, power-down function.  
1.8V  
The data format is shown in Table 6. When referring to this table,  
note that Bit 14 is unused; Bit 13 to Bit 4 correspond to the DAC  
data bits, D9 to D0; and Bit 3 to Bit 0 are unused.  
R
R
P
P
SDA  
SCL  
During a read operation, data is read in the same bit order.  
2
2
2
I C MASTER  
I C SLAVE  
I C SLAVE  
AD5821A  
DEVICE  
DEVICE  
DEVICE  
Figure 21. Typical I2C Bus  
Rev. 0 | Page 11 of 16  
 
 
 
AD5821A  
1
9
1
1
9
SCL  
0
0
0
1
1
X
X
R/W  
PD  
X
D9 D8 D7 D6 D5 D4  
D3 D2 D1 D0  
X
X
X
X
SDA  
START BY  
MASTER  
ACK BY  
AD5821A  
ACK BY  
AD5821A  
ACK BY STOP BY  
AD5821A MASTER  
FRAME 1  
FRAME 2  
MOST SIGNIFICANT  
DATA BYTE  
FRAME 3  
LEAST SIGNIFICANT  
DATA BYTE  
SERIAL BUS  
ADDRESS BYTE  
Figure 22. Write Operation  
1
9
1
1
9
SCL  
0
0
0
1
1
X
X
R/W  
PD  
X
D9 D8 D7 D6 D5 D4  
D3 D2 D1 D0  
X
X
X
X
SDA  
START BY  
MASTER  
ACK BY  
AD5821A  
ACK BY  
AD5821A  
ACK BY STOP BY  
AD5821A MASTER  
FRAME 1  
FRAME 2  
MOST SIGNIFICANT  
DATA BYTE  
FRAME 3  
LEAST SIGNIFICANT  
DATA BYTE  
SERIAL BUS  
ADDRESS BYTE  
Figure 23. Read Operation  
Table 6. Data Format  
High Byte  
Low Byte  
Serial Data- Bit  
Bit  
14  
Bit  
13  
Bit  
12  
Bit  
11  
Bit  
10  
Bit  
9
Bit  
8
Bit  
7
Bit  
6
Bit  
5
Bit  
4
Bit  
3
Bit  
2
Bit  
1
Bit  
0
Words  
15  
Serial Data  
Bits  
Input  
Register  
Function  
SD7  
SD6  
R14  
X
SD5  
R13  
D9  
SD4  
R12  
D8  
SD3  
R11  
D7  
SD2  
R10  
D6  
SD1 SD0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0  
R15  
R9  
R8  
R7  
R6  
R5  
R4  
R3  
X
R2  
X
R1  
X
R0  
X
XSHUTDOWN1  
D5  
D4  
D3  
D2  
D1  
D0  
1 XSHUTDOWN = soft power-down; X = unused/don’t care; and D9 to D0 = AC data.  
V
BATTERY  
POWER SUPPLY BYPASSING AND GROUNDING  
When accuracy is important in an application, it is beneficial  
to consider power supply and ground return layout on the PCB.  
The PCB for the AD5821A should have separate analog and digital  
power supply sections. Where shared AGND and DGND is  
necessary, the connection of grounds should be made at only  
one point, as close as possible to the AD5821A.  
L
C
VOICE  
COIL  
V
COIL  
R
C
V
DD  
TRACE  
RESISTANCE  
R
AD5821A  
T
DGND  
I
SINK  
Pay special attention to the layout of the AGND return path and,  
and trace it between the voice coil motor and ISINK to minimize  
any series resistance. Figure 24 shows the output current sink  
of the AD5821A and illustrates the importance of reducing the  
effective series impedance of AGND and the trace resistance  
between the motor and ISINK. The voice coil is modeled using  
Inductor LC and Resistor RC. The current through the voice coil  
Q1  
SDA  
SCL  
V
DROP  
R
R
SENSE  
XSHUTDOWN  
AGND  
DGND  
R
G
is effectively a dc current that results in a voltage drop, VCOIL  
,
GROUND  
RETURN  
when the AD5821A is sinking current. The effect of any series  
inductance is minimal.  
L
G
Figure 24. Effect of PCB Trace Resistance and Inductance  
Rev. 0 | Page 12 of 16  
 
 
 
 
 
 
AD5821A  
When sinking the maximum current of 120 mA, the maximum  
voltage drop allowed across RSENSE is 400 mV, and the minimum  
drain to source voltage of Q1 is 200 mV. This means that the  
AD5821A output has a compliance voltage of 600 mV. If VDROP  
falls below 600 mV, the output transistor, Q1, can no longer  
operate properly and ISINK may not be maintained as a constant.  
Using another example, if  
VBAT = 3.6 V  
RG = 0.5 Ω  
RT = 0.5 Ω  
I
SINK = 90 mA  
When sinking 90 mA, the maximum voltage drop allowed across  
V
DROP = 480 mV (compliance voltage specification at 90 mA)  
RSENSE is 300 mV, and the minimum drain to source voltage of  
Then the largest value of resistance of the voice coil, RC, is  
Q1 is 180 mV. This means that the AD5821A output has a  
compliance voltage of 480 mV. If VDROP falls below 480 mV, the  
output transistor, Q1, can no longer operate properly and ISINK  
may not be maintained as a constant. As ISINK decreases, the  
voltage required across the transistor, Q1, also decreases and,  
therefore, lower supplies can be used with the voice coil motor.  
VBAT −[VDROP + (ISINK × RT ) + (ISINK × RG )]  
RC =  
=
ISINK  
3.6V− [480 mV + 2 × (90 mA × 0.5 ꢀ)]  
=33.66ꢀ  
90 mA  
As the current increases to 120 mA through the voice coil,  
For this reason, it is important to minimize any series impedance  
on both the ground return path and interconnect between the  
AD5821A and the motor. It is also important to note that for  
lower values of ISINK the compliance voltage of the output stage  
also decreases. This decrease allows the user to either use voice  
coil motors with high resistance values or decrease the power  
supply voltage on the voice coil motor. The compliance voltage  
decreases as the ISINK current decreases.  
VCOIL increases. VDROP decreases and eventually approaches the  
minimum specified compliance voltage of 600 mV (or 480 mV,  
if ISINK = 90 mA). The ground return path is modeled by the  
components RG and LG. The trace resistance between the voice  
coil and the AD5821A is modeled as RT. The inductive effects of  
LG influence RSENSE and RC equally, and because the current is  
maintained as a constant, it is not as critical as the purely resistive  
component of the ground return path. When the maximum sink  
current is flowing through the motor, the resistive elements, RT and  
RG, may have an impact on the voltage headroom of Q1 and  
could, in turn, limit the maximum value of RC because of  
voltage compliance.  
The power supply of the AD5821A, or the regulator used to supply  
the AD5821A, should be decoupled. Best practice power supply  
decoupling recommends that the power supply be decoupled  
with a 10 μF capacitor. Ideally, this 10 μF capacitor should be of  
a tantalum bead type. However, if the power supply or regulator  
supply is well regulated and clean, such decoupling may not be  
required. The AD5821A should be decoupled locally with a  
0.1 μF ceramic capacitor, and this 0.1 ꢁF capacitor should be  
located as close as possible to the VDD pin. The 0.1 μF capacitor  
should be ceramic with a low effective series resistance and  
effective series inductance. The 0.1 μF capacitor provides a low  
impedance path to ground for high transient currents.  
For example, if  
VBAT = 3.6 V  
RG = 0.5 Ω  
RT = 0.5 Ω  
I
SINK = 120 mA  
DROP = 600 mV (compliance voltage)  
V
The power supply line should have as large a trace as possible to  
provide a low impedance path and reduce glitch effects on the  
supply line. Clocks and other fast switching digital signals should  
be shielded from other parts of the board by digital ground.  
Avoid crossover of digital and analog signals, if possible. When  
traces cross on opposite sides of the board, they should run at  
right angles to each other to reduce feedthrough effects through  
the board. The best technique is to use a multilayer board with  
ground and power planes, where the component side of the  
board is dedicated to the ground plane only and the signal  
traces are placed on the solder side. However, this is not always  
possible with a 2-layer board.  
Then the largest value of resistance of the voice coil, RC, is  
VBAT −[VDROP + (ISINK × RT ) + (ISINK × RG )]  
RC =  
=
ISINK  
3.6 V −[600 mV + 2×(120 mA ×0.5 ꢀ)]  
= 24 ꢀ  
120 mA  
Rev. 0 | Page 13 of 16  
AD5821A  
APPLICATIONS INFORMATION  
The AD5821A is designed to drive both spring-preloaded and  
nonspring linear motors used in applications such as lens auto-  
focus, image stabilization, or optical zoom. The operation principle  
of the spring-preloaded motor is that the lens position is controlled  
by the balancing of a voice coil and spring. Figure 25 shows the  
transfer curve of a typical spring-preloaded linear motor for  
autofocus. The key points of this transfer function are displace-  
ment or stroke, which is the actual distance the lens moves in  
millimeters (mm) and the current through the motor, measured  
in milliamps (mA).  
Figure 26 shows a typical application circuit for the AD5821A.  
0.5  
0.4  
0.3  
0.2  
START  
CURRENT  
0.1  
A start current is associated with spring-preloaded linear  
motors, which is a threshold current that must be exceeded for  
any displacement in the lens to occur. The start current is usually  
20 mA or greater; the rated stroke or displacement is usually  
0.25 mm to 0.4 mm; and the slope of the transfer curve is  
approximately 10 μm/mA or less.  
10 20 30 40 50 60 70 80 90 100 110 120  
SINK CURRENT (mA)  
Figure 25. Spring-Preloaded Voice Coil Stroke vs. Sink Current  
The AD5821A is designed to sink up to 120 mA, which is more  
than adequate for available commercial linear motors or voice  
coils. Another factor that makes the AD5821A the ideal solu-  
tion for these applications is the monotonicity of the device,  
ensuring that lens positioning is repeatable for the application  
of a given digital word.  
V
DD  
V
CC  
0.1µF  
2
6
V
DD  
POWER-ON  
RESET  
VOICE  
COIL  
REFERENCE  
1
XSHUTDOWN  
R
R
P
P
D1  
SDA  
SCL  
10-BIT  
3
4
2
I C SERIAL  
I
8
SINK  
CURRENT  
INTERFACE  
OUTPUT DAC  
2
2
I C MASTER  
DEVICE  
I C SLAVE  
DEVICE  
R
R
SENSE  
AD5821A  
5
7
V
DD  
V
CC  
+
+
10µF  
0.1µF  
10µF  
Figure 26. Typical Application Circuit  
Rev. 0 | Page 14 of 16  
 
 
 
AD5821A  
OUTLINE DIMENSIONS  
0.65  
0.59  
0.53  
1.575  
1.515  
1.455  
SEATING  
PLANE  
3
2
1
A
B
C
0.35  
0.32  
0.29  
BALL 1  
IDENTIFIER  
1.750  
1.690  
1.630  
0.50 BSC  
BALL PITCH  
TOP VIEW  
(BALL SIDE DOWN)  
0.28  
0.24  
0.20  
BOTTOM VIEW  
(BALL SIDE UP)  
Figure 27. 9-Ball Wafer Level Chip Scale Package [WLCSP]  
(CB-9-1)  
Dimensions shown in millimeters  
ORDERING GUIDE  
Model  
Temperature Range  
Package Description  
Package Option  
CB-9-1  
CB-9-1  
Branding  
AD5821ABCBZ-REEL71  
AD5821ABCBZ-REEL1  
AD5821A-WAFER  
AD5821AD-WAFER  
EVAL-AD5821AEBZ1  
−30°C to +85°C  
−30°C to +85°C  
−40°C to +85°C  
−40°C to +85°C  
9-Ball Wafer Level Chip Scale Package (WLCSP)  
9-Ball Wafer Level Chip Scale Package (WLCSP)  
Bare Die Wafer  
Bare Die Wafer on Film  
Evaluation Board  
1X  
1X  
1 Z = RoHS Compliant Part.  
Rev. 0 | Page 15 of 16  
 
 
AD5821A  
NOTES  
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent  
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.  
©2008 Analog Devices, Inc. All rights reserved. Trademarks and  
registered trademarks are the property of their respective owners.  
D07796-0-10/08(0)  
Rev. 0 | Page 16 of 16  
 
 

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