AD586JNZ_技术文档

Complete Dual, 16-Bit, High Accuracy,

Serial Input, Bipolar Voltage Output DACs

Preliminary Technical Data

AD5762R

FEATURES

GENERAꢀ DESCRIPTION

Complete dual, 16-bit digital-to-analog

converters (DACs)

Programmable output range: 10 V, 10.2564 V,

or 10.5263 V

1 ꢀSB max INꢀ error, 1 ꢀSB max DNꢀ error

ꢀow noise: 60 nV/√Hz

Settling time: 10 µs max

The AD5762R is a dual, 16-bit, serial input, bipolar voltage

output digital-to-analog converter that operates from supply

voltages of 11ꢀ. ꢁ up to 16ꢀ5 ꢀ Nominal full-scale output

range is 1ꢂ ꢀ The AD5762R provides integrated output

amplifiers, reference buffers and proprietary power-up/power-

down control circuitryꢀ The parts also feature a digital I/O port,

which is programmed via the serial interface and an analog

temperature sensorꢀ The part incorporates digital offset and

gain adjust registers per channelꢀ

Integrated reference buffers

Internal reference: 10 ppm/°C

On-chip die temperature sensor

Output control during power-up/brownout

Programmable short-circuit protection

Simultaneous updating via ꢀDAC

Asynchronous CꢀR to zero code

Digital offset and gain adjust

The AD5762R is a high performance converter that offers

guaranteed monotonicity, integral nonlinearity (INL) of 1 LSB,

low noise, and 1ꢂ µs settling timeꢀ The AD5762R includes an

on-chip 5 ꢁ reference with a reference tempco of 1ꢂ ppm/°C

maximumꢀ During power-up (when the supply voltages are

changing), ꢁOUT is clamped to ꢂ ꢁ via a low impedance pathꢀ

ꢀogic output control pins

DSP-/microcontroller-compatible serial interface

Temperature range: −40°C to +85°C

iCMOS™ process technology¹

The AD5762R uses a serial interface that operates at clock rates

of up to 3ꢂ MHz and is compatible with DSP and

microcontroller interface standardsꢀ Double buffering allows

the simultaneous updating of all DACsꢀ The input coding is

programmable to either twos complement or offset binary

formatsꢀ The asynchronous clear function clears all DAC

registers to either bipolar zero or zero scale depending on the

coding usedꢀ The AD5762R is ideal for both closed-loop servo

control and open-loop control applicationsꢀ The AD5762R is

available in a 32-lead TQFP, and offers guaranteed

APPꢀICATIONS

Industrial automation

Open-/closed-loop servo control

Process control

Data acquisition systems

Automatic test equipment

Automotive test and measurement

High accuracy instrumentation

specifications over the −.ꢂ°C to +85°C industrial temperature

rangeꢀ See Figure 1, the functional block diagramꢀ

¹For analog systems designers within industrial/instrumentation equipment

OEMs who need high performance ICs at higher voltage levels, iCMOS is a

technology platform that enables the development of analog ICs capable of

30 V and operating at 15 V supplies while allowing dramatic reductions in

power consumption and package size, and increased AC and DC

performance.

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD5762R

Preliminary Technical Data

TABLE OF CONTENTS

Features ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 1

Data Registerꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 25

Coarse Gain Register ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 25

Fine Gain Registerꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 25

Offset Register ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 25

Offset and Gain Adjustment Worked Exampleꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 27

AD5762R Featuresꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 28

Analog Output Control ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 28

Digital Offset and Gain Controlꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 28

Programmable Short-Circuit Protection ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 28

Digital I/O Portꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 28

die Temperature Sensorꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 28

Local Ground Offset Adjustꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 28

Applications Informationꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 29

Typical Operating Circuit ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 29

Layout Guidelinesꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 3ꢂ

Galvanically Isolated Interface ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 3ꢂ

Microprocessor Interfacingꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 3ꢂ

Evaluation Boardꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 32

Outline Dimensionsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 33

Ordering Guide ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 33

Applicationsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 1

General Descriptionꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 1

Revision History ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 2

Functional Block Diagram ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 3

Specificationsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ .

AC Performance Characteristicꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 6

Timing Characteristicsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 7

Absolute Maximum Ratingsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 1ꢂ

ESD Cautionꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 1ꢂ

Pin Configuration and Function Descriptionsꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 11

Terminology ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 13

Typical Performance Characteristics ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 15

Theory of Operation ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 21

DAC Architectureꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 21

Reference Buffersꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 21

Serial Interface ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 21

Simultaneous Updating via

ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 22

LDAC

Transfer Functionꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 23

Asynchronous Clear ( )ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 23

CLR

Function Register ꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀꢀ 2.

REVISION HISTORY

Preliminary Revision PrA December 10, 2007

Rev. PrA | Page 2 of 33

Preliminary Technical Data

FUNCTIONAL BLOCK DIAGRAM

AD5762R

REFGND

PGND AV

AV

SS

REFA

RSTOUT

RSTIN

REFOUT

DD

SS

DD

VOLTAGE

MONITOR

AND

DV

CC

+5V

REFERENCE

BUFFERS

AD5762R

DGND

CONTROL

ISCC

16

G1

16

INPUT

REG A

DAC

REG A

DAC A

SDIN

SCLK

SYNC

SDO

VOUTA

INPUT SHIFT

REGISTER

AND

CONTROL

LOGIC

G2

GAIN REG A

AGNDA

OFFSET REG A

INPUT

REG B

DAC

REG B

DAC B

VOUTB

AGNDB

D0

D1

G2

GAIN REG B

OFFSET REG B

REFERENCE

BUFFERS

TEMP

SENSOR

BIN/2SCOMP

REFB

CLR

LDAC

TEMP

Figure 1. Functional Block Diagram

Rev. PrA | Page 3 of 33

AD5762R

Preliminary Technical Data

SPECIFICATIONS

Aꢁ_DD= 11ꢀ. ꢁ to 16ꢀ5 ꢁ, Aꢁ_SS= −11ꢀ. ꢁ to −16ꢀ5 ꢁ, AGND = DGND = REFGND = PGND = ꢂ ꢁ; REFA, REFB = 5 ꢁ external;

Dꢁ_CC= 2ꢀ7 ꢁ to 5ꢀ25 ꢁ, R_LOAD= 1ꢂ kΩ, C_L= 2ꢂꢂ pFꢀ All specifications T_MINto T_MAX, unless otherwise notedꢀ

Table 1.

Parameter

C Grade²

Unit

Test Conditions/Comments

ACCURACY

Outputs unloaded

Resolution

16

1

Bits

Relative Accuracy (INL)

Differential Nonlinearity

Bipolar Zero Error

LSB max

mV max

Guaranteed monotonic

2

At 25°C; error at other temperatures

obtained using bipolar zero TC

Bipolar Zero TC³

Zero-Scale Error

2

ppm FSR/°C max

mV max

At 25°C; error at other temperatures

obtained using zero scale TC

Zero-Scale TC³

Gain Error

2

0.02

ppm FSR/°C max

% FSR max

At 25°C; error at other temperatures

obtained using gain TC

Gain TC³

DC Crosstalk³

2

0.5

ppm FSR/°C max

LSB max

REFERENCE INPUT/OUTPUT

Reference Input³

Reference Input Voltage

DC Input Impedance

Input Current

Reference Range

Reference Output

Output Voltage

Reference TC

5

1

10

1/7

V nominal

MΩ min

µA max

1% for specified performance

Typically 100 MΩ

Typically 30 nA

V min/V max

4.997/5.003

10

1

V min/V max

ppm/°C max

MΩ min

At 25°C

Load³

Output Noise³

18

µV p-p typ

(0.1 Hz to 10 Hz)

Noise Spectral Density³

Output Voltage Drift vs. Time

Line Regulation

Load Regulation

Thermal Hysteresis

75

40

50

TBD

nV/√Hz typ

At 10 kHz

ppm/500hr typ

ppm/1000hr typ

ppm/V typ

ppm/mA typ

ppm typ

OUTPUT CHARACTERISTICS³

Output Voltage Range⁴

10.5263

V min/V max

ppm FSR/500 hours typ

ppm FSR/1000 hours typ

mA typ

AV_DD/AV_SS

=

11.4 V, REFA, REFB = 5V

16.5 V, REFA, REFB = 7V

14

13

15

10

1

Output Voltage Drift vs. Time

Short Circuit Current

Load Current

RI_SCC= 6 kΩ, see Figure 31

For specified performance

mA max

Capacitive Load Stability

R_L= ∞

R_L= 10 kΩ

200

1000

0.3

pF max

Ω max

DC Output Impedance

Rev. PrA | Page 4 of 33

Preliminary Technical Data

AD5762R

Parameter

DIGITAL INPUTS³

C Grade²

Unit

Test Conditions/Comments

DV_CC= 2.7 V to 5.25 V, JEDEC compliant

V_IH, Input High Voltage

V_IL, Input Low Voltage

Input Current

2

0.8

1

V min

V max

µA max

pF max

Per pin

Pin Capacitance

10

DIGITAL OUTPUTS (D0, D1, SDO)³

Output Low Voltage

Output High Voltage

Output Low Voltage

0.4

DV_CC− 1

0.4

V max

V min

V max

DV_CC= 5 V 5%, sinking 200 µA

DV_CC= 5 V 5%, sourcing 200 µA

DV_CC= 2.7 V to 3.6 V,

sinking 200 µA

Output High Voltage

DV_CC− 0.5

V min

DV_CC= 2.7 V to 3.6 V,

sourcing 200 µA

High Impedance Leakage Current

High Impedance Output Capacitance

DIE TEMPERATURE SENSOR³

Output Voltage at 25°C

Output Voltage Scale Factor

Output Voltage Range

Output Load Current

Power-On Time

1

5

µA max

pF typ

SDO only

1.4

5

1.175/1.9

200

80

V typ

Die temperature

mV/°C typ

V min/V max

µA max

−40°C to 105°C

Current source only

ms typ

POWER REQUIREMENTS

AV_DD/AV_SS

11.4/16.5

2.7/5.25

V min/V max

DV_CC

Power Supply Sensitivity³

∆V_OUT/∆ΑV_DD

AI_DD

AI_SS

DI_CC

−85

3.5

2.75

1.2

dB typ

mA/channel max

mA max

Outputs unloaded

V_IH= DV_CC, V_IL= DGND, 750 µA typ

12 V operation output unloaded

Power Dissipation

140

mW typ

²Temperature range : -40°C to +85°C; typical at 25°C. Device functionality is guaranteed to +105°C with degraded performance.

³Guaranteed by design and characterization; not production tested.

⁴Output amplifier headroom requirement is 1.4 V minimum.

Rev. PrA | Page 5 of 33

AD5762R

Preliminary Technical Data

AC PERFORMANCE CHARACTERISTIC

Aꢁ_DD= 11ꢀ. ꢁ to 16ꢀ5 ꢁ, Aꢁ_SS= −11ꢀ. ꢁ to −16ꢀ5 ꢁ, AGND = DGND = REFGND = PGND = ꢂ ꢁ; REFA, REFB= 5 ꢁ external;

Dꢁ_CC= 2ꢀ7 ꢁ to 5ꢀ25 ꢁ, R_LOAD= 1ꢂ kΩ, C_L= 2ꢂꢂ pFꢀ All specifications T_MINto T_MAX, unless otherwise notedꢀ Guaranteed by design and

characterization, not production testedꢀ

Table 2.

Parameter

C Grade

Unit

Test Conditions/Comments

Full-scale step to 1 LSB

512 LSB step settling

DYNAMIC PERFORMANCE¹

Output Voltage Settling Time

8

10

2

µs typ

µs max

µs typ

Slew Rate

5

8

25

80

8

2

0.1

45

1

V/µs typ

nV-s typ

mV max

dB typ

nV-s typ

LSB p-p typ

µV rms max

kHz typ

Digital-to-Analog Glitch Energy

Glitch Impulse Peak Amplitude

Channel-to-Channel Isolation

DAC-to-DAC Crosstalk

Digital Crosstalk

Digital Feedthrough

Output Noise (0.1 Hz to 10 Hz)

Output Noise (0.1 Hz to 100 kHz)

1/f Corner Frequency

Effect of input bus activity on DAC outputs

Output Noise Spectral Density

Complete System Output Noise Spectral Density²

60

80

nV/√Hz typ

Measured at 10 kHz

¹Guaranteed by design and characterization; not production tested.

²Includes noise contributions from integrated reference buffers,16-bit DAC and output amplifier.

Rev. PrA | Page 6 of 33

Preliminary Technical Data

TIMING CHARACTERISTICS

AD5762R

Aꢁ_DD= 11ꢀ. ꢁ to 16ꢀ5 ꢁ, Aꢁ_SS= −11ꢀ. ꢁ to −16ꢀ5 ꢁ, AGND = DGND = REFGND = PGND = ꢂ ꢁ; REFA, REFB= 5 ꢁ external;

Dꢁ_CC= 2ꢀ7 ꢁ to 5ꢀ25 ꢁ, R_LOAD= 1ꢂ kΩ, C_L= 2ꢂꢂ pFꢀ All specifications T_MINto T_MAX, unless otherwise notedꢀ

Table 3.

Parameter^{1, 2, 3}

ꢀimit at T_MIN, T_MAX

Unit

Description

t₁

t₂

t₃

t₄

33

13

40

2

ns min

µs min

ns min

ns max

µs max

ns min

µs max

ns max

ns min

µs min

ns min

SCLK cycle time

SCLK high time

SCLK low time

SYNC falling edge to SCLK falling edge setup time

24^thSCLK falling edge to SYNC rising edge

Minimum SYNC high time

4

t₅

t₆

t₇

t₈

t₉

Data setup time

Data hold time

SYNC rising edge to LDAC falling edge (all DACs updated)

SYNC rising edge to LDAC falling edge (single DAC updated)

LDAC pulse width low

5

1.4

400

10

500

10

2

t₁₀

t₁₁

t₁₂

t₁₃

t₁₄

LDAC falling edge to DAC output response time

DAC output settling time

CLR pulse width low

CLR pulse activation time

5, 6

t₁₅

25

13

2

SCLK rising edge to SDO valid

SYNC rising edge to SCLK falling edge

SYNC rising edge to DAC output response time (LDAC = 0)

LDAC falling edge to SYNC rising edge

t₁₆

t₁₇

t₁₈

170

¹Guaranteed by design and characterization; not production tested.

²All input signals are specified with t_r= t_f= 5 ns (10% to 90% of DV_CC) and timed from a voltage level of 1.2 V.

³See Figure 2, Figure 3, and Figure 4.

⁴Standalone mode only.

⁵Measured with the load circuit of Figure 5.

⁶Daisy-chain mode only.

Rev. PrA | Page 7 of 33

AD5762R

Preliminary Technical Data

t₁

SCLK

SYNC

1

2

24

t₃

t₂

t₆

t₄

t₅

t₈

t₇

DB23

SDIN

DB0

t₁₀

t₉

LDAC

t₁₈

t₁₂

t₁₁

VOUT

LDAC = 0

t₁₂

t₁₇

VOUT

CLR

t₁₃

t₁₄

VOUT

Figure 2. Serial Interface Timing Diagram

t₁

SCLK

24

48

t₃

t₂

t₆

t₅

t₁₆

t₄

SYNC

SDIN

t₈

t₇

DB23

DB0

DB23

DB0

INPUT WORD FOR DAC N

INPUT WORD FOR DAC N–1

t₁₅

DB23

DB0

SDO

t₉

UNDEFINED

INPUT WORD FOR DAC N

t₁₀

LDAC

Figure 3. Daisy Chain Timing Diagram

Rev. PrA | Page 8 of 33

Preliminary Technical Data

AD5762R

SCLK

24

48

SYNC

DB23

DB0

DB23

DB0

SDIN

SDO

NOP CONDITION

INPUT WORD SPECIFIES

REGISTER TO BE READ

DB23

DB0

UNDEFINED

SELECTED REGISTER DATA

CLOCKED OUT

Figure 4. Readback Timing Diagram

200µA

I

OL

V

(MIN) OR

(MAX)

TO OUTPUT

OH

OL

C

L

50pF

200µA

I

OH

Figure 5. Load Circuit for SDO Timing Diagram

Rev. PrA | Page 9 of 33

AD5762R

Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C unless otherwise notedꢀ Transient currents of up to

1ꢂꢂ mA do not cause SCR latch-upꢀ

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the deviceꢀ This is a stress

rating only; functional operation of the device at these or any

other conditions above those listed in the operational sections

of this specification is not impliedꢀ Exposure to absolute

maximum rating conditions for extended periods may affect

device reliabilityꢀ

Table 4.

Parameter

Rating

AV_DDto AGND, DGND

AV_SSto AGND, DGND

DV_CCto DGND

−0.3 V to +17 V

+0.3 V to −17 V

−0.3 V to +7 V

Digital Inputs to DGND

−0.3 V to DV_CC+ 0.3 V or 7 V

(whichever is less)

Digital Outputs to DGND

REFA, REFB to AGND, PGND

REFOUT to AGND

−0.3 V to DV_CC+ 0.3 V

−0.3 V to AV_DD+ 0.3V

AV_SSto AV_DD

TEMP

AV_SSto AV_DD

VOUTA, VOUTB to AGND

AGND to DGND

AV_SSto AV_DD

−0.3 V to +0.3 V

Operating Temperature Range

Industrial

Storage Temperature Range

Junction Temperature (T_Jmax)

32-Lead TQFP

−40°C to +85°C

−65°C to +150°C

150°C

θ_JAThermal Impedance

θ_JCThermal Impedance

Lead Temperature

65°C/W

12°C/W

JEDEC Industry Standard

J-STD-020

Soldering

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the

human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. PrA | Page 10 of 33

Preliminary Technical Data

AD5762R

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

32

25

1

24

NC

SYNC

SCLK

SDIN

SDO

CLR

LDAC

D0

PIN 1

NC

INDICATOR

VOUTA

AGNDA

AGNDB

AD5762R

TOP VIEW

(Not to Scale)

VOUTB

NC

D1

NC

8

17

9

16

Figure 6. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1

SYNC

Active Low Input. This is the frame synchronization signal for the serial interface.

While SYNC is low, data is transferred in on the falling edge of SCLK.

2

SCLK

Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK.

This operates at clock speeds up to 30 MHz.

3

4

SDIN

SDO

Serial Data Input. Data must be valid on the falling edge of SCLK.

Serial Data Output. Used to clock data from the serial register in daisy-chain or

readback mode.

5¹

6

CLR¹

Negative Edge Triggered Input. Asserting this pin sets the DAC registers to 0x0000.

LDAC

Load DAC. Logic input. This is used to update the DAC registers and consequently

the analog outputs. When tied permanently low, the addressed DAC register is

updated on the rising edge of SYNC. If LDAC is held high during the write cycle, the

DAC input register is updated but the output update is held off until the falling edge

of LDAC. In this mode, all analog outputs can be updated simultaneously on the

falling edge of LDAC. The LDAC pin must not be left unconnected.

7, 8

D0, D1

D0 and D1 form a digital I/O port. The user can set up these pins as inputs or outputs

that are configurable and readable over the serial interface. When configured as

inputs, these pins have weak internal pull-ups to DV_CC. When programmed as

outputs, D0 and D1 are referenced by DV_CCand DGND.

9

RSTOUT

RSTIN

Reset Logic Output. This is the output from the on-chip voltage monitor used in the

reset circuit. If desired, it can be used to control other system components.

Reset Logic Input. This input allows external access to the internal reset logic.

Applying a Logic 0 to this input clamps the DAC outputs to 0 V. In normal operation,

RSTIN should be tied to Logic 1. Register values remain unchanged.

10

11

12

13, 31

14

15, 30

16

DGND

DV_CC

AV_DD

PGND

AV_SS

Digital Ground Pin.

Digital Supply Pin. Voltage ranges from 2.7 V to 5.25 V.

Positive Analog Supply Pins. Voltage ranges from 11.4 V to 16.5 V.

Ground Reference Point for Analog Circuitry.

Negative Analog Supply Pins. Voltage ranges from –11.4 V to –16.5 V.

ISCC

This pin is used in association with an optional external resistor to AGND to program

the short-circuit current of the output amplifiers. Refer to the Features section for

further details.

17

18

NC

No Internal Connection

Rev. PrA | Page 11 of 33

AD5762R

Preliminary Technical Data

Pin No. Mnemonic

Description

19

VOUTB

Analog Output Voltage of DAC B. Buffered output with a nominal full-scale output range

of 10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load.

20

21

22

AGNDB

AGNDA

VOUTA

Ground Reference Pin for DAC B Output Amplifier.

Ground Reference Pin for DAC A Output Amplifier.

Analog Output Voltage of DAC A. Buffered output with a nominal full-scale output range

of 10 V. The output amplifier is capable of directly driving a 10 kΩ, 200 pF load.

23

24

25

NC

REFA

Do not connect to this pin

External Reference Voltage. Reference input range is 1 V to 7 V; programs the full-

scale output voltage. REFA = 5 V for specified performance.

26

27

REFB

External Reference Voltage. Reference input range is 1 V to 7 V; programs the full-

scale output voltage. REFB = 5 V for specified performance.

Reference Output. This is the reference output from the internal voltage reference.

The internal reference is 5 V 3 mV at 25°C, with a reference tempco of 10 ppm/°C.

REFOUT

28

29

REFGND

TEMP

Reference Ground Return for the Reference Generator and Buffers.

This pin provides an output voltage proportional to temperature. The output voltage

is 1.4 V typical at 25°C die temperature; variation with temperature is 5 mV/°C.

32

BIN/2sCOMP

Determines the DAC Coding. This pin should be hardwired to either DV_CCor DGND.

When hardwired to DV_CC, input coding is offset binary. When hardwired to DGND,

input coding is twos complement (see Table 6).

¹Internal pull-up device on this logic input. Therefore, it can be left floating and defaults to a logic high condition.

Rev. PrA | Page 12 of 33

Preliminary Technical Data

TERMINOLOGY

AD5762R

Relative Accuracy or Integral nonlinearity (INL)

Gain Error

For the DAC, relative accuracy or integral nonlinearity (INL) is

a measure of the maximum deviation, in LSBs, from a straight

line passing through the endpoints of the DAC transfer

functionꢀ A typical INL vsꢀ code plot can be seen in Figure 7ꢀ

Gain error is a measure of the span error of the DACꢀ It is the

deviation in slope of the DAC transfer characteristic from the

ideal, expressed as a percentage of the full-scale rangeꢀ A plot of

gain error vsꢀ temperature can be seen in Figure 23ꢀ

Differential Nonlinearity (DNL)

Total Unadjusted Error

Differential nonlinearity is the difference between the measured

change and the ideal 1 LSB change between any two adjacent

codesꢀ A specified differential nonlinearity of 1 LSB maximum

ensures monotonicityꢀ This DAC is guaranteed monotonicꢀ A

typical DNL vsꢀ code plot can be seen in Figure 9ꢀ

Total unadjusted error (TUE) is a measure of the output error

considering all the various errorsꢀ A plot of total unadjusted

error vsꢀ reference can be seen in Figure 19ꢀ

Zero-Scale Error TC

Zero-scale error TC is a measure of the change in zero-scale

error with a change in temperatureꢀ Zero-scale error TC is

expressed in ppm FSR/°Cꢀ

Monotonicity

A DAC is monotonic if the output either increases or remains

constant for increasing digital input codeꢀ The AD5762R is

monotonic over its full operating temperature rangeꢀ

Gain Error TC

Gain error TC is a measure of the change in gain error with

changes in temperatureꢀ Gain Error TC is expressed in

(ppm of FSR)/°Cꢀ

Bipolar Zero Error

Bipolar zero error is the deviation of the analog output from the

ideal half-scale output of ꢂ ꢁ when the DAC register is loaded with

ꢂx8ꢂꢂꢂ (offset binary coding) or ꢂxꢂꢂꢂꢂ (twos complement

coding)ꢀ A plot of bipolar zero error vsꢀ temperature can be seen in

Figure 22ꢀ

Digital-to-Analog Glitch Energy

Digital-to-analog glitch impulse is the impulse injected into the

analog output when the input code in the DAC register changes

stateꢀ It is normally specified as the area of the glitch in nꢁ-s and is

measured when the digital input code is changed by 1 LSB at the

major carry transition (ꢂx7FFF to ꢂx8ꢂꢂꢂ) (see Figure 28)ꢀ

Bipolar Zero TC

Bipolar zero TC is the measure of the change in the bipolar zero

error with a change in temperatureꢀ It is expressed in ppm FSR/°Cꢀ

Digital Feedthrough

Full-Scale Error

Digital feedthrough is a measure of the impulse injected into

the analog output of the DAC from the digital inputs of the

DAC but is measured when the DAC output is not updatedꢀ It is

specified in nꢁ-s and measured with a full-scale code change on

the data bus, that is, from all ꢂs to all 1s and vice versaꢀ

Full-scale error is a measure of the output error when full-scale

code is loaded to the DAC registerꢀ Ideally the output voltage

should be 2 × ꢁ_REF− 1 LSBꢀ Full-scale error is expressed in

percentage of full-scale rangeꢀ

Negative Full-Scale Error/Zero Scale Error

Power Supply Sensitivity

Negative full-scale error is the error in the DAC output voltage

when ꢂxꢂꢂꢂꢂ (offset binary coding) or ꢂx8ꢂꢂꢂ (twos

complement coding) is loaded to the DAC registerꢀ Ideally, the

output voltage should be −2 × ꢁ_REFꢀ A plot of zero-scale error vsꢀ

temperature can be seen in Figure 21ꢀ

Power supply sensitivity indicates how the output of the DAC is

affected by changes in the power supply voltageꢀ

DC Crosstalk

DC crosstalk is the dc change in the output level of one DAC in

response to a change in the output of another DACꢀ It is

measured with a full-scale output change on one DAC while

monitoring another DAC, and is expressed in LSBsꢀ

Output Voltage Settling Time

Output voltage settling time is the amount of time it takes for

the output to settle to a specified level for a full-scale input

changeꢀ

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse transferred to the

output of one DAC due to a digital code change and subsequent

output change of another DACꢀ This includes both digital and

analog crosstalkꢀ It is measured by loading one of the DACs

with a full-scale code change (all ꢂs to all 1s and vice versa) with

Slew Rate

The slew rate of a device is a limitation in the rate of change of

the output voltageꢀ The output slewing speed of a voltage-

output D/A converter is usually limited by the slew rate of the

amplifier used at its outputꢀ Slew rate is measured from 1ꢂ% to

9ꢂ% of the output signal and is given in ꢁ/µsꢀ

low and monitoring the output of another DACꢀ The

LDAC

energy of the glitch is expressed in nꢁ-sꢀ

Rev. PrA | Page 13 of 33

AD5762R

Preliminary Technical Data

Channel-to-Channel Isolation

Digital Crosstalk

Channel-to-channel isolation is the ratio of the amplitude of the

signal at the output of one DAC to a sine wave on the reference

input of another DACꢀ It is measured in dBꢀ

Digital crosstalk is a measure of the impulse injected into the

analog output of one DAC from the digital inputs of another

DAC but is measured when the DAC output is not updatedꢀ It is

specified in nꢁ-s and measured with a full-scale code change on

the data bus, that is, from all ꢂs to all 1s and vice versaꢀ

Reference TC

Reference TC is a measure of the change in the reference output

voltage with a change in temperatureꢀ It is expressed in ppm/°Cꢀ

Rev. PrA | Page 14 of 33

Preliminary Technical Data

AD5762R

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

T

= 25°C

T

V

= 25°C

/V = ±12V

DD SS

A

V

/V = ±15V

0.8

DD SS

REFIN = 5V

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

0

10000

20000

30000

40000

50000

60000

0

10000

20000

30000

40000

50000

60000

DAC CODE

Figure 7. Integral Nonlinearity Error vs. Code,

V_DD/V_SS15 V

Figure 10. Differential Nonlinearity Error vs. Code,

=

V_DD/V_SS

=

12 V

1.0

0.8

0.5

0.4

0.3

0.2

0.1

0

T

V

= 25°C

A

T = 25°C

A

/V = ±12V

DD SS

V

/V = ±15V

DD SS

REFIN = 5V

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.1

–0.2

10000

20000

30000

40000

50000

60000

–40

–20

0

20

40

60

80

100

DAC CODE

TEMPERATURE (°C)

Figure 8. Integral Nonlinearity Error vs. Code,

V_DD/V_SS12 V

Figure 11. Integral Nonlinearity Error vs. Temperature,

V_DD/V_SS15 V

=

1.0

0.8

0.5

0.4

0.3

0.2

0.1

0

T

= 25°C

A

T

= 25°C

/V = ±12V

A

V

/V = ±15V

DD SS

V

DD SS

REFIN = 5V

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.1

–40

10000

20000

30000

40000

50000

60000

–20

0

20

40

60

80

100

DAC CODE

TEMPERATURE (°C)

Figure 9. Differential Nonlinearity Error vs. Code,

V_DD/V_SS15 V

Figure 12. Integral Nonlinearity Error vs. Temperature,

V_DD/V_SS12 V

=

Rev. PrA | Page 15 of 33

AD5762R

Preliminary Technical Data

0.15

0.10

0.05

0

0.15

0.10

T

= 25°C

A

REFIN = 5V

0.05

0

–0.05

–0.10

–0.15

–0.20

–0.05

–0.10

–0.15

–0.20

–0.25

T

V

= 25°C

A

/V = ±15V

DD SS

REFIN = 5V

–0.25

–40

–20

0

20

40

60

80

100

11.4

12.4

13.4

14.4

15.4

16.4

TEMPERATURE (°C)

SUPPLY VOLTAGE (V)

Figure 13. Differential Nonlinearity Error vs. Temperature,

V_DD/V_SS= 15 V

Figure 16. Differential Nonlinearity Error vs. Supply Voltage

0.15

0.8

T

= 25°C

A

0.6

0.4

0.10

0.05

0.2

0

–0.05

–0.10

–0.15

–0.20

–0.25

–0.2

–0.4

–0.6

–0.8

–1.0

T

V

= 25°C

A

/V = ±12V

DD SS

REFIN = 5V

–40

–20

0

20

40

60

80

100

1

2

3

4

5

6

7

TEMPERATURE (°C)

REFERENCE VOLTAGE (V)

Figure 14. Differential Nonlinearity Error vs. Temperature,

V_DD/V_SS= 12 V

Figure 17. Integral Nonlinearity Error vs. Reference Voltage, V_DD/V_SS

16.5 V

=

0.5

0.4

0.3

0.2

0.1

0

0.4

T

= 25°C

T

= 25°C

A

REFIN = 5V

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.1

–0.2

11.4

12.4

13.4

14.4

15.4

16.4

1

2

3

4

5

6

7

SUPPLY VOLTAGE (V)

REFERENCE VOLTAGE (V)

Figure 15. Integral Nonlinearity Error vs. Supply Voltage

Figure 18. Differential Nonlinearity Error vs. Reference Voltage, V_DD/V_SS

16.5 V

=

Rev. PrA | Page 16 of 33

Preliminary Technical Data

AD5762R

0.8

0.6

0.4

0.2

0

REFIN = 5V

V

/V = ±15V

DD SS

V

/V = ±15V

DD SS

0.6

0.4

0.2

0

V

/V = ±12V

DD SS

V

/V = ±12V

DD SS

–0.2

–0.4

–40

–0.4

–40

–20

0

20

40

60

80

100

–20

0

20

40

60

80

100

TEMPERATURE (°C)

Figure 19. Total Unadjusted Error vs. Reference Voltage,

Figure 22. Bipolar Zero Error vs. Temperature

V_DD/V_SS

= 16.5 V

14

13

12

11

10

9

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

T

= 25°C

REFIN = 5V

A

REFIN = 5V

|I

DD

|

V

/V = ±12V

DD SS

V

/V = ±15V

DD SS

|I

SS

|

8

11.4

–0.2

–40

12.4

13.4

V

14.4

/V (V)

15.4

16.4

–20

0

20

40

60

80

100

TEMPERATURE (°C)

DD SS

Figure 20. I_DD/I_SSvs. V_DD/V_SS

Figure 23. Gain Error vs. Temperature

0.25

0.20

0.15

0.10

0.05

0

0.0014

0.0013

0.0012

0.0011

0.0010

0.0009

0.0008

0.0007

0.0006

T

= 25°C

REFIN = 5V

V

/V = ±15V

DD SS

A

5V

V

/V = ±12V

DD SS

–0.05

–0.10

–0.15

–0.20

–0.25

3V

–40

–20

0

20

40

60

80

100

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

TEMPERATURE (°C)

V

LOGIC

Figure 21. Zero-Scale Error vs. Temperature

Figure 24. DI_CCvs. Logic Input Voltage

Rev. PrA | Page 17 of 33

AD5762R

Preliminary Technical Data

7000

–4

–6

T

= 25°C

A

REFIN = 5V

RI = 6kΩ

6000

5000

4000

3000

2000

1000

0

SCC

V

/V = ±15V

DD SS

–8

–10

–12

–14

–16

–18

–20

–22

–24

–26

V

/V = ±12V

DD SS

V

/V = ±12V,

DD SS

REFIN = 5V,

= 25°C,

T

A

0x8000 TO 0x7FFF,

500ns/DIV

–1000

–10

–5

0

5

10

–2.0–1.5–1.0–0.5

0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

TIME (µs)

SOURCE/SINK CURRENT (mA)

Figure 25. Source and Sink Capability of Output Amplifier with Positive

Full Scale Loaded

Figure 28. Major Code Transition Glitch Energy, V_DD/V_SS

= 12 V

10000

T

= 25°C

A

REFIN = 5V

RI = 6kΩ

9000

8000

7000

6000

5000

4000

3000

2000

1000

0

V

/V = ±15V

DD SS

SCC

MIDSCALE LOADED

REFIN = 0V

15V SUPPLIES

12V SUPPLIES

4

–1000

–12

–7

–2

3

8

50µV/DIV

CH4

SOURCE/SINK CURRENT (mA)

CH4 50.0µV

M1.00s

26µV

Figure 26. Source and Sink Capability of Output Amplifier with Negative

Full Scale Loaded

Figure 29. Peak-to-Peak Noise (100 kHz Bandwidth)

V

/V = ±12V,

DD SS

T

V

/V = ±15V

= 25°C

DD SS

REFIN = 5V, T = 25°C,

RAMP TIME = 100µs,

LOAD = 200pF||10kꢀ

A

T

A

REFIN = 5V

1

2

3

1

1µs/DIV

CH1 –120mV

B

CH1 3.00V

M1.00µs

CH1 10.0V

CH2 10.0V

M100µs A CH1

29.60%

7.80mV

W

B

CH3 10.0mV

T

W

Figure 27. Full-Scale Settling Time

Figure 30. VOUT vs. V_DD/V_SSon Power-Up

Rev. PrA | Page 18 of 33

Preliminary Technical Data

AD5762R

10

9

8

7

6

5

4

3

2

1

0

V

/V = ±15V

DD SS

= 25°C

T

V

/V = ±12V

= 25°C

A

DD SS

REFIN = 5V

T

A

1

5µV/DIV

A CH1

0

20

40

60

(kꢀ)

80

100

120

M1.00s

18mV

RI

SCC

Figure 34. REFOUT Output Noise 0.1 Hz to 10 Hz

Figure 31. Short-Circuit Current vs. RI_SCC

T

V

/V = ±12V

DD SS

T

= 25°C

A

1

2

3

B

CH1 10.0V

CH3 5.00V

CH2 10.0V

M400µs A CH1

29.60%

7.80mV

W

T

Figure 32. REFOUT Turn-On Transient

Figure 35. REFOUT Load Regulation

V

/V = ±12V

DD SS

T

= 25°C,

A

10µF CAPACITOR ON REF

OUT

1

50µV/DIV

A CH1

CH1 50.0µV

M1.00s

15µV

Figure 36. REFOUT Histogram of Thermal Hysteresis

Figure 33. REFOUT Output Noise 100 kHz Bandwidth

Rev. PrA | Page 19 of 33

AD5762R

Preliminary Technical Data

Figure 37. TEMP Voltage vs. Temperature

Rev. PrA | Page 20 of 33

Preliminary Technical Data

THEORY OF OPERATION

AD5762R

The AD5762R is a dual, 16-bit, serial input, bipolar voltage output

DAC and operates from supply voltages of 11ꢀ. ꢁ to 16ꢀ5 ꢁ and

has a buffered output voltage of up to 1ꢂꢀ5263 ꢀ Data is written to

the AD5762R in a 2.-bit word format, via a 3-wire serial interfaceꢀ

The AD5762R also offers an SDO pin, which is available for daisy

chaining or readbackꢀ

SERIAꢀ INTERFACE

The AD5762R is controlled over a versatile 3-wire serial

interface that operates at clock rates of up to 3ꢂ MHz and is

compatible with SPI®, QSPI™, MICROWIRE™, and DSP

standardsꢀ

Input Shift Register

The AD5762R incorporates a power-on reset circuit, which

ensures that the DAC registers power up loaded with ꢂxꢂꢂꢂꢂꢀ

The AD5762R features a digital I/O port that can be

programmed via the serial interface, an analog die temperature

sensor, on-chip 1ꢂ ppm/°C voltage reference, on-chip reference

buffers and per channel digital gain and offset registersꢀ

The input shift register is 2. bits wideꢀ Data is loaded into the

device MSB first as a 2.-bit word under the control of a serial

clock input, SCLKꢀ The input register consists of a read/write

bit, three register select bits, three DAC address bits and 16 data

bits as shown in Table 7ꢀ The timing diagram for this operation

is shown in Figure 2ꢀ

DAC ARCHITECTURE

Upon power-up, the DAC registers are loaded with zero code

(ꢂxꢂꢂꢂꢂ) and the outputs are clamped to ꢂ ꢁ via a low

impedance pathꢀ The outputs can be updated with the zero code

The DAC architecture of the AD5762R consists of a 16-bit

current mode segmented R-2R DACꢀ The simplified circuit

diagram for the DAC section is shown in Figure 38ꢀ

value by asserting either

or

ꢀ The corresponding

LDAC CLR

output voltage depends on the state of the BIN/ pinꢀ If

2sCOMP

pin is tied to DGND, then the data coding is

The four MSBs of the 16-bit data word are decoded to drive 15

switches, E1 to E15ꢀ Each of these switches connects one of the

15 matched resistors to either AGND or IOUTꢀ The remaining

12 bits of the data word drive switches Sꢂ to S11 of the 12-bit R-

2R ladder networkꢀ

the BIN/

2sCOMP

twos complement and the outputs update to ꢂ ꢀ If the

BIN/ pin is tied to Dꢁ_CC, then the data coding is offset

2sCOMP

binary and the outputs update to negative full scaleꢀ To have the

outputs power-up with zero code loaded to the outputs, the

R

V

REF

pin should be held low during power-upꢀ

CLR

2R

Standalone Operation

The serial interface works with both a continuous and noncon-

tinuous serial clockꢀ A continuous SCLK source can only be

R/8

E15

E14

E1

S0

S11

S10

I

OUT

used if

is held low for the correct number of clock cyclesꢀ

SYNC

In gated clock mode, a burst clock containing the exact number

of clock cycles must be used and must be taken high after

V

OUT

AGND

SYNC

the final clock to latch the dataꢀ The first falling edge of

4 MSBs DECODED INTO

15 EQUAL SEGMENTS

12-BIT, R-2R LADDER

SYNC

starts the write cycleꢀ Exactly 2. falling clock edges must be

applied to SCLK before is brought back high againꢀ If

Figure 38. DAC Ladder Structure

REFERENCE BUFFERS

SYNC

is brought high before the 2.^thfalling SCLK edge, then

The AD5762R can operate with either an external or an internal

referenceꢀ The reference input has an input range up to 7 ꢀ This

input voltage is then used to provide a buffered positive and

negative reference for the DAC coresꢀ The positive reference is

given by

SYNC

the data written is invalidꢀ If more than 2. falling SCLK edges

are applied before is brought high, then the input data is

SYNC

also invalidꢀ The input register addressed is updated on the

rising edge of ꢀ In order for another serial transfer to take

SYNC

must be brought low againꢀ After the end of the

+ ꢁ_REF= 2 × ꢁ_REFIN

place,

SYNC

serial data transfer, data is automatically transferred from the

input shift register to the addressed registerꢀ

While the negative reference to the DAC cores is given by

−ꢁ_REF= −2 × ꢁ_REFIN

When the data has been transferred into the chosen register of

the addressed DAC, all DAC registers and outputs can be

These positive and negative reference voltages (along with the

gain register values) define the output ranges of the DACsꢀ

updated by taking

lowꢀ

LDAC

Rev. PrA | Page 21 of 33

AD5762R

Preliminary Technical Data

AD5762R*

SDIN

68HC11*

MOSI

A continuous SCLK source can only be used if

low for the correct number of clock cyclesꢀ In gated clock mode,

a burst clock containing the exact number of clock cycles must

is held

SYNC

SCK

PC7

PC6

SCLK

SYNC

LDAC

be used and

must be taken high after the final clock to

SYNC

latch the dataꢀ

Readback Operation

MISO

SDO

Before a readback operation is initiated, the SDO pin must be

enabled by writing to the function register and clearing the

SDO DISABLE bit; this bit is cleared by defaultꢀ Readback mode

SDIN

is invoked by setting the R/ bit = 1 in the serial input register

writeꢀ With R/ = 1, Bit A2 to Bit Aꢂ, in association with Bit

W

AD5762R*

SCLK

REG2, Bit REG1, and Bit REGꢂ, select the register to be readꢀ

The remaining data bits in the write sequence are don’t careꢀ

During the next SPI write, the data appearing on the SDO

output contain the data from the previously addressed registerꢀ

For a read of a single register, the NOP command can be used

in clocking out the data from the selected register on SDOꢀ The

readback diagram in Figure . shows the readback sequenceꢀ For

example, to read back the fine gain register of Channel A on the

AD5762R, the following sequence should be implemented:

SYNC

LDAC

SDO

SDIN

AD5762R*

SCLK

1ꢀ Write ꢂxAꢂXXXX to the AD5762R input registerꢀ This

configures the AD5762R for read mode with the fine gain

register of Channel A selectedꢀ Note that all the data bits,

DB15 to DBꢂ, are don’t careꢀ

SYNC

LDAC

SDO

2ꢀ Follow this with a second write, a NOP condition,

ꢂxꢂꢂXXXXꢀ During this write, the data from the fine gain

register is clocked out on the SDO line, that is, data clocked

out contains the data from the fine gain register in Bit DB5 to

Bit DBꢂꢀ

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 39. Daisy Chaining the AD5762R

Daisy-Chain Operation

SIMUꢀTANEOUS UPDATING VIA

ꢀDAC

For systems that contain several devices, the SDO pin can be

used to daisy chain several devices togetherꢀ This daisy-chain

mode can be useful in system diagnostics and in reducing the

Depending on the status of both

and

, and after

LDAC

SYNC

data has been transferred into the input register of the DACs,

there are two ways in which the DAC registers and DAC

outputs can be updatedꢀ

number of serial interface linesꢀ The first falling edge of

SYNC

starts the write cycleꢀ The SCLK is continuously applied to the

input shift register when is lowꢀ If more than 2. clock

SYNC

Individual DAC Updating

pulses are applied, the data ripples out of the shift register and

appears on the SDO lineꢀ This data is clocked out on the rising

edge of SCLK and is valid on the falling edgeꢀ By connecting the

SDO of the first device to the SDIN input of the next device in

the chain, a multidevice interface is constructedꢀ Each device in

the system requires 2. clock pulsesꢀ Therefore, the total number

of clock cycles must equal 2.N, where N is the total number of

AD5762R devices in the chainꢀ When the serial transfer to all

In this mode,

is held low while data is being clocked into

LDAC

the input shift registerꢀ The addressed DAC output is updated

on the rising edge of

ꢀ

SYNC

Simultaneous Updating of All DACs

In this mode, is held high while data is being clocked

LDAC

into the input shift registerꢀ All DAC outputs are updated by

taking low any time after has been taken highꢀ

devices is complete,

is taken highꢀ This latches the input

SYNC

LDAC

SYNC

data in each device in the daisy chain and prevents any further

data from being clocked into the input shift registerꢀ The serial

clock can be a continuous or a gated clockꢀ

The update now occurs on the falling edge of

ꢀ

LDAC

Rev. PrA | Page 22 of 33

Preliminary Technical Data

AD5762R

OUTPUT

I/V AMPLIFIER

The output voltage expression for the AD5762R is given by

16-BIT

DAC

V

REFIN

V

OUT

D

⎡

⎤

V_OUT= −2×V_REFIN+ 4×V_REFIN

⎢

⎥

65536

⎣

⎦

DAC

REGISTER

LDAC

where:

D is the decimal equivalent of the code loaded to the DACꢀ

_REFINis the reference voltage applied at the REFA, REFB pinsꢀ

V

INPUT

REGISTER

ASYNCHRONOUS CꢀEAR (

)

CꢀR

SCLK

SYNC

SDIN

INTERFACE

LOGIC

SDO

is a negative edge triggered clear that allows the outputs to

CLR

be cleared to either ꢂ ꢁ (twos complement coding) or negative

Figure 40. Simplified Serial Interface of Input Loading Circuitry

for One DAC Channel

full scale (offset binary coding)ꢀ It is necessary to maintain

low for a minimum amount of time (see Figure 2) for the

CLR

TRANSFER FUNCTION

operation to completeꢀ When the

signal is returned high,

CLR

the output remains at the cleared value until a new value is

programmedꢀ If at power-on is at ꢂ ꢁ, then all DAC

Table 6 shows the ideal input code to output voltage

relationship for the AD5762R for both offset binary and twos

complement data codingꢀ

CLR

outputs are updated with the clear valueꢀ A clear can also be

initiated through software by writing the command ꢂxꢂ.XXXX

to the AD5762Rꢀ

Table 6. Ideal Output Voltage to Input Code Relationship for

the AD5762R

Digital Input

Analog Output

Offset Binary Data Coding

MSB

ꢀSB V_OUT

1111 1111

1000 0000

0111 1111

0000 0000

1111

0000

1111

0000

1111

0001

0000

1111

0000

+2 V_REFIN× (32767/32768)

+2 V_REFIN× (1/32768)

0 V

−2 V_REFIN× (1/32768)

−2 V_REFIN× (32767/32768)

Twos Complement Data Coding

MSB

ꢀSB V_OUT

0111 1111

0000 0000

1111 1111

1000 0000

1111

0000

1111

0000

1111

0001

0000

1111

0000

+2 V_REFIN× (32767/32768)

+2 V_REFIN× (1/32768)

0 V

−2 V_REFIN× (1/32768)

−2 V_REFIN× (32767/32768)

Rev. PrA | Page 23 of 33

AD5762R

Preliminary Technical Data

Table 7. AD5762R Input Register Format

MSB

LSB

DB23

DB22

0

DB21

REG2

DB20

REG1

DB19

REG0

DB18

A2

DB17

A1

DB16

A0

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

W

R/

DATA

Table 8. Input Register Bit Functions

Register

Function

R/W

Indicates a read from or a write to the addressed register.

REG2, REG1, REG0

Used in association with the address bits to determine if a read or write operation is to the data register, offset

register, gain register, or function register.

REG2

REG1

REG0

Function

0

1

0

1

0

1

0

1

Function Register

Data Register

Coarse Gain Register

Fine Gain Register

Offset Register

A2, A1, A0

D15:D0

These bits are used to decode the DAC channels.

A2

A1

0

A0

0

Channel Address

DAC A

0

1

DAC B

1

0

BOTH DACs

Data Bits.

FUNCTION REGISTER

The function register is addressed by setting the three REG bits to ꢂꢂꢂꢀ The values written to the address bits and the data bits determine

the function addressedꢀ The functions available via the function register are outlined in Table 9 and Table 1ꢂꢀ

Table 9. Function Register Options

REG2 REG1 REG0 A2 A1 A0

DB15:DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

NOP, Data = Don’t Care

Don’t Care

Local-

Ground-

Offset Adjust

D1 Direction D1

Value

D0

Direction

D0

Value

SDO

Disable

0

1

0

1

CLR, Data = Don’t Care

LOAD, Data = Don’t Care

Table 10. Explanation of Function Register Options

Option

Description

NOP

No operation instruction used in readback operations.

Local-Ground-

Offset Adjust

Set by the user to enable local-ground-offset adjust function. Cleared by the user to disable local-ground-offset adjust

function (default). Refer to Features section for further details.

D0/D1

Direction

Set by the user to enable D0/D1 as outputs. Cleared by the user to enable D0/D1 as inputs (default). Refer to the Features

section for further details.

D0/D1 Value

I/O Port Status Bits. Logic values written to these locations determine the logic outputs on the D0 and D1 pins when

configured as outputs. These bits indicate the status of the D0 and D1 pins when the I/O port is active as an input. When

enabled as inputs, these bits are don’t cares during a write operation.

SDO Disable

CLR

LOAD

Set by the user to disable the SDO output. Cleared by the user to enable the SDO output (default).

Addressing this function resets the DAC outputs to 0 V in twos complement mode and negative full scale in binary mode.

Addressing this function updates the DAC registers and consequently the analog outputs.

Rev. PrA | Page 24 of 33

Preliminary Technical Data

AD5762R

DATA REGISTER

The data register is addressed by setting the three REG bits to ꢂ1ꢂꢀ The DAC address bits select with which DAC channel the data transfer

is to take place (see Table 8)ꢀ The data bits are in positions DB15 to DBꢂ for the AD5762R as shown in Table 11ꢀ

Table 11. Programming the AD5762R Data Register

REG2

REG1

REG0

A2

A1

A0

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

0

1

0

DAC Address

16-Bit DAC Data

COARSE GAIN REGISTER

The coarse gain register is addressed by setting the three REG bits to ꢂ11ꢀ The DAC address bits select with which DAC channel the data

transfer is to take place (see Table 8)ꢀ The coarse gain register is a 2-bit register and allows the user to select the output range of each DAC

as shown in Table 13ꢀ

Table 12. Programming the AD5762R Coarse Gain Register

REG2

REG1

REG0

A2

A1

A0

DB15 …. DB2

DB1

DB0

0

1

DAC Address

Don’t Care

CG1

CG0

Table 13. Output Range Selection

Output Range

10 V (default)

10.2564 V

CG1

CG0

0

1

0

1

0

10.5263 V

FINE GAIN REGISTER

The fine gain register is addressed by setting the three REG bits to 1ꢂꢂꢀ The DAC address bits select with which DAC channel the data

transfer is to take place (see Table 8)ꢀ The AD5762R fine gain register is a 6-bit register and allows the user to adjust the gain of each DAC

channel by −32 LSBs to +31 LSBs in 1 LSB steps as shown in Table 1. and Table 15ꢀ The adjustment is made to both the positive full-scale

points and the negative full-scale points simultaneously, each point being adjusted by ½ of one stepꢀ The fine gain register coding is twos

complementꢀ

Table 14. Programming AD5762R Fine Gain Register

REG2

REG1

REG0

A2

A1

A0

DB15:DB6

DB5

DB4

DB3

DB2

DB1

DB0

1

0

DAC Address

Don’t Care

FG5

FG4

FG3

FG2

FG1

FG0

Table 15. AD5762R Fine Gain Register Options

Gain Adjustment

FG5

FG4

FG3

FG2

FG1

FG0

+31 LSBs

+30 LSBs

0

-

1

-

1

-

1

-

1

-

1

0

-

No Adjustment (default)

0

-

0

-

0

-

0

-

0

-

0

-

−31 LSBs

−32 LSBs

1

0

1

0

OFFSET REGISTER

The offset register is addressed by setting the three REG bits to 1ꢂ1ꢀ The DAC address bits select with which DAC channel the data

transfer is to take place (see Table 8)ꢀ The AD5762R offset register is an 8-bit register and allows the user to adjust the offset of each

channel by −16 LSBs to +15ꢀ875 LSBs in steps of ⅛ LSB as shown in Table 16 and Table 17ꢀ The offset register coding is twos complementꢀ

Table 16. Programming the AD5762R Offset Register

REG2

REG1

REG0

A2

A1

A0

DB15:DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

1

0

1

DAC Address

Don’t Care

OF7

OF6

OF5

OF4

OF3

OF2

OF1

OF0

Rev. PrA | Page 25 of 33

AD5762R

Preliminary Technical Data

Table 17. AD5762R Offset Register options

Offset Adjustment

OF7

OF6

OF5

OF4

OF3

OF2

OF1

OF0

+15.875 LSBs

+15.75 LSBs

0

-

1

-

1

-

1

-

1

-

1

-

1

-

1

0

-

No Adjustment (default)

0

-

0

-

0

-

0

-

0

-

0

-

0

-

0

-

−15.875 LSBs

−16 LSBs

1

0

1

0

Rev. PrA | Page 26 of 33

Preliminary Technical Data

AD5762R

Removing Gain Error

OFFSET AND GAIN ADJUSTMENT WORKED

EXAMPꢀE

The AD5762R can eliminate a gain error at negative full-scale

output in the range of −9ꢀ77 mꢁ to +9ꢀ.6 mꢁ with a step size of

½ of a 16-bit LSBꢀ

Using the information provided in the previous section, the

following worked example demonstrates how the AD5762R

functions can be used to eliminate both offset and gain errorsꢀ

As the AD5762R is factory calibrated, offset and gain errors

should be negligibleꢀ However, errors can be introduced by the

system that the AD5762R is operating within, for example, a

voltage reference value that is not equal to +5 ꢁ introduces a

gain errorꢀ An output range of 1ꢂ ꢁ and twos complement

data coding is assumedꢀ

Calculate the step size of the gain adjustment

20

2¹⁶× 2

Gain Adjust Step Size =

=152.59 µV

Measure the gain error by programming ꢂx8ꢂꢂꢂ to the data

register and measuring the resulting output voltageꢀ The gain

error is the difference between this value and −1ꢂ ꢁ, for this

example, the gain error is −1ꢀ2 m ꢀ

Removing Offset Error

The AD5762R can eliminate an offset error in the range of −.ꢀ88

mꢁ to +.ꢀ8. mꢁ with a step size of ⅛ of a 16-bit LSBꢀ

How many gain adjustment steps does this value represent?

Measured Gain Value

Gain Step Size

1.2 mV

Number of Steps =

=

= 8 Steps

152.59 µV

Calculate the step size of the offset adjustment,

2ꢂ

Offset Adjust Step Size =

= 38ꢀ1. µV

¹⁶× 8

The gain error measured is negative (in terms of magnitude);

therefore, a positive adjustment of eight steps is requiredꢀ The

gain register is 6 bits wide and the coding is twos complement,

the required gain register value can be determined as follows:

2

Measure the offset error by programming ꢂxꢂꢂꢂꢂ to the data

register and measuring the resulting output voltage, for this

example the measured value is +61. µ ꢀ

Convert adjustment value to binary; ꢂꢂ1ꢂꢂꢂꢀ

How many offset adjustment steps does this value represent?

The value to be programmed to the gain register is simply this

binary numberꢀ

Measured Offset Value

Offset Step Size

614 µV

Numberof Steps =

=

=16 Steps

38.14 µV

The offset error measured is positive, therefore, a negative

adjustment of 16 steps is requiredꢀ The offset register is 8 bits

wide and the coding is twos complementꢀ The required offset

register value can be calculated as follows:

Convert adjustment value to binary; ꢂꢂꢂ1ꢂꢂꢂꢂꢀ

Convert this to a negative twos complement number by

inverting all bits and adding 1; 1111ꢂꢂꢂꢂꢀ

1111ꢂꢂꢂꢂ is the value that should be programmed to the offset

registerꢀ

Note: This twos complement conversion is not necessary in the

case of a positive offset adjustmentꢀ The value to be

programmed to the offset register is simply the binary

representation of the adjustment valueꢀ

Rev. PrA | Page 27 of 33

AD5762R

Preliminary Technical Data

AD5762R FEATURES

If the ISCC pin is left unconnected, the short circuit current

limit defaults to 5 mAꢀ It should be noted that limiting the short

circuit current to a small value can affect the slew rate of the

output when driving into a capacitive load, therefore, the value

of short-circuit current programmed should take into account

the size of the capacitive load being drivenꢀ

ANAꢀOG OUTPUT CONTROꢀ

In many industrial process control applications, it is vital that

the output voltage be controlled during power-up and during

brownout conditionsꢀ When the supply voltages are changing,

the ꢁOUT pins are clamped to ꢂ ꢁ via a low impedance pathꢀ

To prevent the output amp being shorted to ꢂ ꢁ during this

time, transmission gate G1 is also opened (see Figure .1)ꢀ These

conditions are maintained until the power supplies stabilize and

a valid word is written to the DAC registerꢀ At this time, G2

opens and G1 closesꢀ Both transmission gates are also externally

DIGITAꢀ I/O PORT

The AD5762R contain a 2-bit digital I/O port (D1 and Dꢂ),

these bits can be configured as inputs or outputs independently,

and can be driven or have their values read back via the serial

interfaceꢀ The I/O port signals are referenced to Dꢁ_CCand

DGNDꢀ When configured as outputs, they can be used as

control signals to multiplexers or can be used to control

calibration circuitry elsewhere in the systemꢀ When configured

as inputs, the logic signals from limit switches, for example can

be applied to Dꢂ and D1 and can be read back via the digital

interfaceꢀ

controllable via the Reset In (

) control inputꢀ For

RSTIN

instance, if

is driven from a battery supervisor chip, the

RSTIN

input is driven low to open G1 and close G2 on power-

RSTIN

off or during a brownoutꢀ Conversely, the on-chip voltage

detector output ( ) is also available to the user to

RSTOUT

control other parts of the systemꢀ The basic transmission gate

functionality is shown in Figure .1ꢀ

RSTOUT

RSTIN

DIE TEMPERATURE SENSOR

The on-chip die temperature sensor provides a voltage output

that is linearly proportional to the centigrade temperature scaleꢀ

Its nominal output voltage is 1ꢀ. ꢁ at +25°C die temperature,

varying at 5 mꢁ/°C, giving a typical output range of 1ꢀ175 ꢁ to

1ꢀ9 ꢁ over the full temperature rangeꢀ Its low output impedance,

and linear output simplify interfacing to temperature control

circuitry and A/D convertersꢀ The temperature sensor is

provided as more of a convenience rather than a precise feature;

it is intended for indicating a die temperature change for

recalibration purposesꢀ

VOLTAGE

MONITOR

AND

CONTROL

G1

VOUTA

AGNDA

G2

Figure 41. Analog Output Control Circuitry

DIGITAꢀ OFFSET AND GAIN CONTROꢀ

ꢀOCAꢀ GROUND OFFSET ADJUST

The AD5762R incorporates a digital offset adjust function with

The AD5762R incorporates a local-ground-offset adjust feature

which when enabled in the function register adjusts the DAC

outputs for voltage differences between the individual DAC

ground pins and the REFGND pin ensuring that the DAC

output voltages are always with respect to the local DAC ground

pinꢀ For instance, if pin AGNDA is at +5 mꢁ with respect to the

REFGND pin and ꢁOUTA is measured with respect to

AGNDA then a −5mꢁ error results, enabling the local-ground-

offset adjust feature adjusts ꢁOUTA by +5 mꢁ, eliminating the

errorꢀ

a

16 LSB adjust range and ꢂꢀ125 LSB resolutionꢀ The gain

register allows the user to adjust the AD5762R’s full-scale

output rangeꢀ The full-scale output can be programmed to

achieve full-scale ranges of 1ꢂ ꢁ, 1ꢂꢀ25 ꢁ, and 1ꢂꢀ5 ꢀ A fine

gain trim is also availableꢀ

PROGRAMMABꢀE SHORT-CIRCUIT PROTECTION

The short-circuit current of the output amplifiers can be pro-

grammed by inserting an external resistor between the ISCC

pin and PGNDꢀ The programmable range for the current is

5ꢂꢂ µA to 1ꢂ mA, corresponding to a resistor range of 12ꢂ kΩ

to 6 kΩ ꢀ The resistor value is calculated as follows:

60

R =

Isc

Rev. PrA | Page 28 of 33

Preliminary Technical Data

AD5762R

APPLICATIONS INFORMATION

TYPICAꢀ OPERATING CIRCUIT

Precision Voltage Reference Selection

To achieve the optimum performance from the AD5762R over

its full operating temperature range, an external voltage

reference must be usedꢀ Thought should be given to the

selection of a precision voltage referenceꢀ The voltage applied to

the reference input is used to provide a buffered positive and

negative reference for the DAC coresꢀ Therefore, any error in

the voltage reference is reflected in the outputs of the deviceꢀ

Figure .2 shows the typical operating circuit for the AD5762Rꢀ

The only external components needed for this precision 16-bit

DAC are decoupling capacitors on the supply pins and reference

inputs, and an optional short-circuit current setting resistorꢀ

Because the AD5762R incorporates a voltage reference and

reference buffers, it eliminates the need for an external bipolar

reference and associated buffersꢀ This leads to an overall savings

in both cost and board spaceꢀ

There are four possible sources of error to consider when

choosing a voltage reference for high accuracy applications:

initial accuracy, temperature coefficient of the output voltage,

long term drift, and output voltage noiseꢀ

In Figure .2, ꢁ_DDand ꢁ_SSare both connected to 15 ꢁ, but ꢁ_DD

and ꢁ_SScan operate with supplies from 11ꢀ. ꢁ to 16ꢀ5 ꢀ In

Figure .2, AGNDA and AGNDB are connected to REFGNDꢀ

+15V –15V

Initial accuracy error on the output voltage of an external refer-

ence could lead to a full-scale error in the DACꢀ Therefore, to

minimize these errors, a reference with low initial accuracy

error specification is preferredꢀ Choosing a reference with an

output trim adjustment, such as the ADR.25, allows a system

designer to trim system errors out by setting the reference

voltage to a voltage other than the nominalꢀ The trim ad-

justment can also be used at temperature to trim out any errorꢀ

10µF

100nF

TEMP

+5V

BIN/2sCOMP

32 31 30 29 28 27 26 25

Long term drift is a measure of how much the reference output

voltage drifts over timeꢀ A reference with a tight long-term drift

specification ensures that the overall solution remains relatively

stable over its entire lifetimeꢀ

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

SYNC

SCLK

SDIN

SDO

SYNC

NC

SCLK

SDIN

SDO

CLR

LDAC

D0

VOUTA

AGNDA

AGNDB

VOUTB

NC

VOUTA

VOUTB

AD5762R

LDAC

D0

The temperature coefficient of a reference’s output voltage

affects INL, DNL, and TUEꢀ A reference with a tight

temperature coefficient specification should be chosen to

reduce the dependence of the DAC output voltage on ambient

conditionsꢀ

NC

D1

9

10 11 12 13 14 15 16

RSTOUT

RSTIN

10µF

In high accuracy applications, which have a relatively low noise

budget, reference output voltage noise needs to be consideredꢀ

Choosing a reference with as low an output noise voltage as

practical for the system resolution required is importantꢀ

Precision voltage references such as the ADR.35 (XFET design)

produce low output noise in the ꢂꢀ1 Hz to 1ꢂ Hz regionꢀ

However, as the circuit bandwidth increases, filtering the output

of the reference may be required to minimize the output noiseꢀ

100nF

10µF

+5V

+15V –15V

Figure 42. Typical Operating Circuit

Table 18. Some Precision References Recommended for Use with the AD5762R

Part No. Initial Accuracy(mV Max) ꢀong-Term Drift (ppm Typ) Temp Drift (ppm/°C Max) 0.1 Hz to 10 Hz Noise (µV p-p Typ)

ADR435

ADR425

ADR02

ADR395

AD586

6

5

6

30

50

15

3

25

10

3.4

15

5

2.5

4

Rev. PrA | Page 29 of 33

AD5762R

Preliminary Technical Data

LAYOUT GUIDELINES

1

µCONTROLLER

ADuM1400

In any circuit where accuracy is important, careful consider-

ation of the power supply and ground return layout helps to

ensure the rated performanceꢀ The printed circuit board on

which the AD5762R is mounted should be designed so that the

analog and digital sections are separated and confined to

certain areas of the boardꢀ If the AD5762R is in a system where

multiple devices require an AGND-to-DGND connection, the

connection should be made at one point onlyꢀ The star ground

point should be established as close as possible to the deviceꢀ

The AD5762R should have ample supply bypassing of 1ꢂ µF in

parallel with ꢂꢀ1 µF on each supply located as close to the

package as possible, ideally right up against the deviceꢀ The 1ꢂ

µF capacitors are the tantalum bead typeꢀ The ꢂꢀ1 µF capacitor

should have low effective series resistance (ESR) and low

effective series inductance (ESI) such as the common ceramic

types, which provide a low impedance path to ground at high

frequencies to handle transient currents due to internal logic

switchingꢀ

V

IA

OA

OB

OC

OD

ENCODE

DECODE

SERIAL CLOCK OUT

TO SCLK

TO SDIN

TO SYNC

TO LDAC

V

IB

IC

ID

SERIAL DATA OUT

SYNC OUT

CONTROL OUT

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 43. Isolated Interface

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5762R is via a serial bus

that uses standard protocol compatible with microcontrollers

and DSP processorsꢀ The communications channel is a 3-wire

(minimum) interface consisting of a clock signal, a data signal,

and a synchronization signalꢀ The AD5762R requires a 2.-bit

data-word with data valid on the falling edge of SCLKꢀ

The power supply lines of the AD5762R should use as large a

trace as possible to provide low impedance paths and reduce

the effects of glitches on the power supply lineꢀ Fast switching

signals, such as clocks, should be shielded with digital ground

to avoid radiating noise to other parts of the board, and should

never be run near the reference inputsꢀ A ground line routed

between the SDIN and SCLK lines helps reduce cross-talk

between them (not required on a multilayer board, which has a

separate ground plane, however, it is helpful to separate the

lines)ꢀ It is essential to minimize noise on the reference inputs,

because it couples through to the DAC outputꢀ Avoid crossover

of digital and analog signalsꢀ Traces on opposite sides of the

board should run at right angles to each otherꢀ This reduces the

effects of feed through on the boardꢀ A microstrip technique is

recommended, but not always possible with a double-sided

boardꢀ In this technique, the component side of the board is

dedicated to ground plane, while signal traces are placed on the

solder sideꢀ

For all the interfaces, the DAC output update can be done

automatically when all the data is clocked in, or it can be done

under the control of LDACꢀ The contents of the DAC register

can be read using the readback functionꢀ

AD5762R to MC68HC11 Interface

Figure .. shows an example of a serial interface between the

AD5762R and the MC68HC11 microcontrollerꢀ The serial

peripheral interface (SPI) on the MC68HC11 is configured for

master mode (MSTR = 1), clock polarity bit (CPOL = ꢂ), and the

clock phase bit (CPHA = 1)ꢀ The SPI is configured by writing to the

SPI control register (SPCR) (see the 68HC11User Manual)ꢀ SCK of

the MC68HC11 drives the SCLK of the AD5762R, the MOSI

output drives the serial data line (DIN) of the AD5762R, and the

MISO input is driven from SDOꢀ The SYNC is driven from one of

the port lines, in this case PC7ꢀ

GAꢀVANICAꢀꢀY ISOꢀATED INTERFACE

In many process control applications, it is necessary to provide

an isolation barrier between the controller and the unit being

controlled to protect and isolate the controlling circuitry from

any hazardous common-mode voltages that might occurꢀ

Isocouplers provide voltage isolation in excess of 2ꢀ5 kꢁꢀ The

serial loading structure of the AD5762R makes it ideal for

isolated interfaces, because the number of interface lines is kept

to a minimumꢀ Figure .3 shows a .-channel isolated interface

to the AD5762R using an ADuM1.ꢂꢂꢀ For more information,

go to wwwꢀanalogꢀcomꢀ

Rev. PrA | Page 30 of 33

Preliminary Technical Data

AD5762R

When data is being transmitted to the AD5762R, the SYNC line

(PC7) is taken low and data is transmitted MSB firstꢀ Data

appearing on the MOSI output is valid on the falling edge of

SCKꢀ Eight falling clock edges occur in the transmit cycle, so, in

order to load the required 2.-bit word, PC7 is not brought high

until the third 8-bit word has been transferred to the DACs

input shift registerꢀ

The 8XC51 transmits data in 8-bit bytes with only eight falling

clock edges occurring in the transmit cycleꢀ Because the DAC

expects a 2.-bit word, SYNC (P3ꢀ3) must be left low after the

first eight bits are transferredꢀ After the third byte has been

transferred, the P3ꢀ3 line is taken highꢀ The DAC can be

LDAC

updated using

via P3ꢀ. of the 8XC51ꢀ

AD5762R to ADSP2101/ADSP2103 Interface

1

MC68HC11¹

AD5762R

An interface between the AD5762R and the ADSP21ꢂ1/

ADSP21ꢂ3 is shown in Figure .6ꢀ The ADSP21ꢂ1/ ADSP21ꢂ3

should be set up to operate in the SPORT transmit alternate

framing modeꢀ The ADSP21ꢂ1/ADSP21ꢂ3 are programmed

through the SPORT control register and should be configured

as follows: internal clock operation, active low framing, and 2.-

bit word lengthꢀ

MISO

MOSI

SCK

PC7

SDO

SDIN

SCLK

SYNC

Transmission is initiated by writing a word to the TX register

after the SPORT has been enabledꢀ As the data is clocked out of

the DSP on the rising edge of SCLK, no glue logic is required to

interface the DSP to the DACꢀ In the interface shown, the DAC

output is updated using the LDAC pin via the DS ꢀ Alterna-

tively, the LDAC input could be tied permanently low, and then

the update takes place automatically when TFS is taken highꢀ

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 44. AD5762R to MC68HC11 Interface

LDAC is controlled by the PC6 port outputꢀ The DAC can be

updated after each 3-byte transfer by bringing LDAC lowꢀ This

example does not show other serial lines for the DACꢀ For

example, if CLR were used, it could be controlled by port

output PC5ꢀ

AD5762R¹

ADSP2101/

ADSP2103¹

AD5762R to 8XC51 Interface

DR

DT

SDO

The AD5762R requires a clock synchronized to the serial dataꢀ

For this reason, the 8XC51 must be operated in Mode ꢂꢀ In this

mode, serial data enters and exits through RXD, and a shift

clock is output on TXDꢀ

SDIN

SCLK

TFS

SYNC

LDAC

RFS

FO

P3ꢀ3 and P3ꢀ. are bit programmable pins on the serial port and

SYNC

LDAC

are used to drive

and

, respectivelyꢀ The 8CX51

1

provides the LSB of its SBUF register as the first bit in the data

streamꢀ The user must ensure that the data in the SBUF register

is arranged correctly, because the DAC expects MSB firstꢀ When

data is to be transmitted to the DAC, P3ꢀ3 is taken lowꢀ Data on

RXD is clocked out of the microcontroller on the rising edge of

TXD and is valid on the falling edgeꢀ As a result, no glue logic is

required between this DAC and the microcontroller interfaceꢀ

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 46. AD5762R to ADSP2101/ADSP2103 Interface

AD5762R to PIC16C6x/7x Interface

The PIC16C6x/7x synchronous serial port (SSP) is configured

as an SPI master with the clock polarity bit set to ꢂꢀ This is done

by writing to the synchronous serial port control register

(SSPCON)ꢀ See the PIC16/17 Microcontroller User Manualꢀ In

AD5762R¹

8XC51¹

SYNC

this example, I/O port RA1 is being used to pulse

and

enable the serial port of the AD5762Rꢀ This microcontroller

transfers only eight bits of data during each serial transfer

operation; therefore, three consecutive write operations are

neededꢀ Figure .7 shows the connection diagramꢀ

RxD

SDIN

TxD

P3.3

P3.4

SCLK

SYNC

LDAC

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 45. AD5762R to 8XC51 Interface

Rev. PrA | Page 31 of 33

AD5762R

Preliminary Technical Data

AD5762R¹

PIC16C6x/7x¹

EVAꢀUATION BOARD

The AD5762R performance can be evaluated via the AD576.R

evaluation boardꢀ

SDI/RC4

SDO/RC5

SCLK/RC3

RA1

SDO

SDIN

SCLK

SYNC

The AD576.R comes with a full evaluation board to aid

designers in evaluating the high performance of the part with a

minimum of effortꢀ All that is required with the evaluation

board is a power supply and a PCꢀ The AD576.R evaluation kit

includes a populated, tested AD576.R printed circuit boardꢀ

The evaluation board interfaces to the USB interface of the PCꢀ

Software is available with the evaluation board, which allows

the user to easily program the AD576.Rꢀ The software runs on

any PC that has Microsoft® Windows® 2ꢂꢂꢂ/XP installedꢀ

1

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 47. AD5762R to PIC16C6x/7x Interface

An application note is available that gives full details on

operating the evaluation boardꢀ

Rev. PrA | Page 32 of 33

Preliminary Technical Data

OUTLINE DIMENSIONS

AD5762R

1.20

MAX

0.75

0.60

0.45

9.00 BSC SQ

25

32

1

24

PIN 1

7.00

BSC SQ

TOP VIEW

(PINS DOWN)

0° MIN

1.05

1.00

0.95

0.20

0.09

7°

8

17

3.5°

0.15

0.05

9

16

0°

SEATING

PLANE

0.08 MAX

COPLANARITY

VIEW A

0.80

0.45

0.37

0.30

BSC

LEAD PITCH

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026ABA

Figure 48. 32-Lead Thin Plastic Dual Flat Package [TQFP]

(SU-32-2)

Dimensions shown in millimeters

ORDERING GUIDE¹

Internal

Reference

Package

Option

Model

Function

INꢀ

1 LSB max

Temperature

−40°C to +85°C

Package Description

32-lead TQFP

AD5762RCSUZ

AD5762RCSUZ-REEL7

Dual 16-bit DAC

+5V

SU-32-2

registered trademarks are the property of their respective owners.

PR07248-0-12/07(PrA)

Rev. PrA | Page 33 of 33


型号：	AD586JNZ
厂家：	ADI
描述：	High Precision 5 V Reference
文件：	总33页 (文件大小：489K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD586JNZ [ADI]

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