AD5934YRSZ [ADI]
250 kSPS, 12-Bit Impedance Converter, Network Analyzer; 250 kSPS时， 12位阻抗转换器，网络分析仪
| 型号： | AD5934YRSZ |
| 厂家： | 
ADI |
| 描述： | 250 kSPS, 12-Bit Impedance Converter, Network Analyzer |
| 文件： | 总32页 (文件大小：520K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
250 kSPS, 12-Bit Impedance Converter,
Network Analyzer
AD5934
FEATURES
GENERAL DESCRIPTION
Programmable output peak-to-peak excitation voltage
to a max frequency of 100 kHz
Programmable frequency sweep capability with
serial I2C® interface
Frequency resolution of 27 bits (<0.1 Hz)
Impedance measurement range from 100 Ω to 10 MΩ
Phase measurement capability
The AD5934 is a high precision impedance converter system
solution which combines an on-board frequency generator with
a 12-bit, 250 kSPS, analog-to-digital converter (ADC). The
frequency generator allows an external complex impedance to
be excited with a known frequency. The response signal from
the impedance is sampled by the on-board ADC and a discrete
Fourier transform (DFT) is processed by an on-board DSP
engine. The DFT algorithm returns a real (R) and imaginary (I)
data-word at each output frequency.
System accuracy of 0.5%
2.7 V to 5.5 V power supply operation
Temperature range −40°C to +125°C
16-lead SSOP package
The magnitude of the impedance and relative phase of the
impedance at each frequency point along the sweep is easily
calculated using the following two equations:
APPLICATIONS
Electrochemical analysis
Bioelectrical impedance analysis
Impedance spectroscopy
Complex impedance measurement
Corrosion monitoring and protection equipment
Biomedical and automotive sensors
Proximity sensing
2
2
Magnitude= R + I
Phase =Tan−1(I / R)
Table 1. Related Devices
Part No.
Description
Nondestructive testing
Material property analysis
AD5933
2.7 V to 5.5 V. 1 MSPS, 12-bit impedance, with
internal temperature sensor, 16-lead SSOP.
Fuel/battery cell condition monitoring
FUNCTIONAL BLOCK DIAGRAM
MCLK
AVDD
DVDD
DDS
CORE
DAC
(27 BITS)
R
VOUT
OUT
SCL
SDA
2
I C
INTERFACE
Z(ω)
AD5934
REAL
IMAGINARY
REGISTER REGISTER
RFB
VIN
1024-POINT DFT
ADC
(12 BITS)
GAIN
LPF
VDD/2
AGND
DGND
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2005 Analog Devices, Inc. All rights reserved.
AD5934
TABLE OF CONTENTS
Gain Factor Temperature Variation......................................... 16
Impedance Error ........................................................................ 16
Performing a Frequency Sweep .................................................... 18
Register Map ................................................................................... 19
Control Register ......................................................................... 19
Start Frequency Register ........................................................... 20
Frequency Increment Register.................................................. 20
Number of Increments Register ............................................... 21
Number of Settling Time Cycles Register............................... 21
Status Register............................................................................. 22
Real and Imaginary Data Registers (16 Bits).......................... 22
Serial Bus Interface......................................................................... 23
General I2C Timing.................................................................... 23
Writing/Reading to the AD5934.............................................. 24
Block Write.................................................................................. 24
AD5934 Read Operations ......................................................... 25
Typical Applications ....................................................................... 26
Biomedical: Noninvasive Blood impedance Measurement.. 26
Sensor/Complex Impedance Measurement............................ 26
Electro-Impedance Spectroscopy............................................. 27
Choosing a Reference for the AD5934........................................ 28
Layout and Configuration............................................................. 29
Power Supply Bypassing and Grounding................................ 29
Outline Dimensions....................................................................... 30
Ordering Guide .......................................................................... 30
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Specifications..................................................................................... 3
I2C Serial Interface Timing Characteristics .................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Descriptions.............................................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 10
System Description......................................................................... 11
Transmit Stage............................................................................. 12
Frequency Sweep Command Sequence................................... 13
Receive Stage ............................................................................... 13
DFT Operation ........................................................................... 13
Impedance Calculation.................................................................. 14
Magnitude Calculation .............................................................. 14
Gain Factor Calculation ............................................................ 14
Impedance Calculation Using Gain Factor............................. 14
Gain Factor Variation with Frequency .................................... 14
Two-Point Calibration ............................................................... 15
Two-Point Gain Factor Calculation......................................... 15
Gain Factor Setup Configuration............................................. 15
Gain Factor Recalculation......................................................... 15
REVISION HISTORY
6/05—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
AD5934
SPECIFICATIONS
Test conditions unless otherwise stated: VDD = 3.3 V, MCLK = 16.776 MHz, 2 V p-p output excitation voltage @ 30 kHz, 200 kΩ
connected between Pin 5 and Pin 6. Feedback resistor = 200 kΩ connected between Pin 4 and Pin 5. PGA gain = ×1.
Table 2.
Y Version1
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
SYSTEM
Impedance Range
0.001
10
MΩ
Total System Accuracy
System Impedance Error Drift
TRANSMIT STAGE
0.5
30
%
ppm/°C
Output Frequency Range2
1
100
kHz
Hz
Output Frequency Resolution
0.1
<0.1 Hz resolution achievable using
DDS techniques.
MCLK Frequency
16.776
MHz
Maximum system clock frequency.
TRANSMIT OUTPUT VOLTAGE
Range 1
AC Output Excitation Voltage3
1.98
1.48
V p-p
V
Refer to Figure 4 for output voltage
distribution.
DC bias of the AC excitation signal.
See Figure 5.
DC Bias4
DC Output Impedance
Short-Circuit Current to Ground
at VOUT
200
5.8
Ω
mA
TA = 25°C.
TA = 25°C.
Range 2
AC Output Excitation Voltage3
DC Bias4
0.97
0.76
V p-p
V
See Figure 6.
DC bias of output excitation signal.
See Figure 7.
DC Output Impedance
2.4
kΩ
Short-Circuit Current to Ground
at VOUT
0.25
mA
Range 3
AC Output Excitation Voltage3
DC Bias4
0.383
0.31
V p-p
V
See Figure 8.
DC bias of output excitation signal.
See Figure 9.
DC Output Impedance
1
kΩ
Short-Circuit Current to Ground
at VOUT
0.20
mA
Range 4
AC Output Excitation Voltage3
DC Bias4
0.198
0.173
V p-p
V
See Figure 10.
DC bias of output excitation signal.
See Figure 11.
DC Output Impedance
600
Ω
Short-Circuit Current to Ground
at VOUT
0.15
mA
Short-Circuit Current to Ground
SYSTEM AC CHARACTERISTICS
Signal-to-Noise Ratio
Total Harmonic Distortion
Spurious-Free Dynamic Range
Wide Band (0 MHz to 1 MHz)
Narrowband ( 5 kHz)
0.15
mA
60
−52
dB
dB
−56
−85
dB
dB
Rev. 0 | Page 3 of 32
AD5934
Y Version1
Typ
Parameter
Min
Max
Unit
Test Conditions/Comments
RECEIVE STAGE
Input Leakage Current
Input Capacitance5
1
0.01
nA
fF
To VIN pin.
Pin capacitance between VOUT and
GND.
Feedback Capacitance CFB
3
pF
Feedback capacitance around current-
to-voltage amplifier; appears in parallel
with feedback resistor.
ANALOG-TO-DIGITAL CONVERTER5
Resolution
12
bits
Sampling Rate
250
kSPS
ADC throughput rate.
LOGIC INPUTS
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Current6
Input Capacitance
POWER REQUIREMENTS
VDD
0.7 × VDD
0.3 × VDD
1
7
μA
pF
TA =25°C.
TA = 25°C.
2.7
5.5
15
25
V
IDD (Normal Mode )
10
17
7
mA
mA
mA
VDD = 3.3 V.
VDD = 5.5 V.
VDD = 3.3 V; see the Control Register
section.
IDD (Standby Mode)
9
0.7
1
mA
μA
μA
VDD = 5.5 V.
VDD = 3.3 V.
VDD = 5.5 V.
IDD (Power-Down Mode)
5
8
1 Temperature range for Y version = −40°C to +125°C, typical at 25°C.
2 The lower limit of the output excitation frequency can be lowered by scaling the clock supplied to the AD5934.
3 The peak-to-peak value of the AC output excitation voltage scales with supply voltage according to the formula given below. VDD is the supply voltage.
2
Output ExcitationVoltage (V p - p) =
×VDD
3.3
4 The DC bias value of the Output excitation voltage scales with supply voltage according to the formula given below. VDD is the supply voltage.
2
Output Excitation BiasVoltage (V) =
×VDD
3.3
5 Guaranteed by design or characterization, not production tested. Input capacitance at the VOUT pin is equal to pin capacitance divided by open-loop gain of current-
to-voltage amplifier.
6 The accumulation of the currents into Pin 8, Pin 15, and Pin 16.
Rev. 0 | Page 4 of 32
AD5934
I2C SERIAL INTERFACE TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V. All specifications TMIN to TMAX, unless otherwise noted.1
Table 3.
Parameter2
Limit at TMIN, TMAX
Unit
Description
FSCL
t1
t2
t3
t4
400
2. 5
0. 6
1. 3
0. 6
100
0. 9
0
0. 6
0. 6
1. 3
300
0
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
SCL clock frequency
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD
,
STA, start/repeated start condition hold time
DAT, data setup time
DAT, data hold time
t5
t6
tSU
tHD
tHD
,
3
,
,
DAT, data hold time
t7
t8
t9
t10
tSU,
STA, setup time for repeated start
tSU, STO, stop condition setup time
tBUF, bus free time between a stop and a start condition
tF, rise time of SDA when transmitting
tR, rise time of SCL and SDA when receiving (CMOS compatible)
tF, fall time of SCL and SDA when transmitting
tF, fall time of SDA when receiving (CMOS compatible)
tF, fall time of SDA when receiving
t11
300
0
250
20 + 0.1 CB
400
4
tF, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
CB
1 See Figure 2.
2 Guaranteed by design and characterization, not production tested.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH MIN of the SCL signal) in order to bridge the undefined SCL’s falling edge.
4 CB is the total capacitance of one bus line in pF. Note that tR and tF are measured between 0.3 VDD and 0.7 VDD.
SDA
t9
t11
t4
t3
t10
SCL
t4
t6
t2
t5
t7
t8
t1
REPEATED
START
CONDITION
STOP
CONDITION
START
CONDITION
Figure 2. I2C Interface Timing Diagram
Rev. 0 | Page 5 of 32
AD5934
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise note
Table 4.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
DVDD to GND
AVDD1 to GND
AVDD2 to GND
SDA/SCL to GND
VOUT to GND
VIN to GND
MCLK to GND
−0.3 V to + 7. 0 V
−0.3 V to + 7. 0 V
−0.3 V to + 7. 0 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
Operating Temperature Range
Extended Industrial (Y Grade)
Storage Temperature Range
Maximum Junction Temperature
SSOP Package
−40°C to +125°C
−65°C to +160°C
150°C
θJA Thermal Impedance
θJC Thermal Impedance
Reflow Soldering (Pb-Free)
Peak Temperature
139°C/W
136°C/W
260°C
Time at Peak Temperature
10 sec to 40 sec
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 32
AD5934
PIN CONFIGURATION AND DESCRIPTIONS
NC
NC
1
2
3
4
5
6
7
8
16 SCL
15 SDA
NC
14 AGND2
13 AGND1
12 DGND
11 AVDD2
10 AVDD1
AD5934
TOP VIEW
(Not to Scale)
RFB
VIN
VOUT
NC
MCLK
9
DVDD
NC = NO CONNECT
Figure 3. Pin Configuration
It is recommended to tie all supply connections (Pin 9, Pin 10, and Pin 11) and run from a single supply between 2.7 V and 5.5 V. It is also
recommended to connect all ground signals together (Pin 12, Pin 13, and Pin 14).
Table 5. Pin Function Descriptions
Pin No.
1, 2, 3, 7
4
Mnemonic Description/comment
NC
No Connect.
RFB
External Feedback Resistor. Connected from Pin 4 to Pin 5 and used to set the gain of the current-to-voltage
amplifier on the receive side.
5
VIN
Input to Receive Transimpedance Amplifier. Presents a virtual earth voltage of VDD/2.
6
8
9
10
11
12
13
14
15
16
VOUT
MCLK
DVDD
AVDD1
AVDD2
DGND
AGND1
AGND2
SDA
Excitation Voltage Signal Output.
Master Clock for the System. Supplied by user.
Digital Supply Voltage.
Analog Supply Voltage 1.
Analog Supply Voltage 2.
Digital Ground.
Analog Ground 1.
Analog Ground 2.
I2C Data Input.
SCL
I2C Clock Input.
Rev. 0 | Page 7 of 32
AD5934
TYPICAL PERFORMANCE CHARACTERISTICS
30
25
20
15
10
5
35
MEAN = 0.7543
SIGMA = 0.0099
MEAN = 1.9824
SIGMA = 0.0072
30
25
20
15
10
5
0
0
1.92
0.68 0.70 0.72 0.74 0.76 0.78 0.80 0.82 0.84 0.86
1.94
1.96
1.98
2.00
2.02
2.04
2.06
VOLTAGE (V)
VOLTAGE (V)
Figure 4. Range 1: Output Excitation Voltage Distribution VDD = 3.3 V
Figure 7. Range 2: DC Bias Distribution VDD = 3.3 V
30
30
MEAN = 0.3827
SIGMA = 0.00167
MEAN = 1.4807
SIGMA = 0.0252
25
20
15
10
5
25
20
15
10
5
0
0
0.370
0.375
0.380
0.385
0.390
0.395
0.400
1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75
VOLTAGE (V)
VOLTAGE (V)
Figure 8. Range 3: Output Excitation Voltage Distribution VDD = 3.3 V
Figure 5. Range 1: DC Bias Distribution VDD = 3.3 V
30
30
MEAN = 0.9862
SIGMA = 0.0041
MEAN = 0.3092
SIGMA = 0.0014
25
20
15
10
5
25
20
15
10
5
0
0.95
0
0.96
0.97
0.98
0.99
1.00
1.01
1.02
0.290
0.295
0.300
0.305
0.310
0.315
0.320
VOLTAGE (V)
VOLTAGE (V)
Figure 6. Range 2: Output Excitation Voltage Distribution VDD = 3.3 V
Figure 9. Range 3: DC Bias Distribution VDD = 3.3 V
Rev. 0 | Page 8 of 32
AD5934
15.8
15.3
14.8
14.3
13.8
13.3
12.8
12.3
11.8
11.3
10.8
30
25
20
15
10
5
MEAN = 0.1982
SIGMA = 0.0008
AVDD1, AVDD2, DVDD CONNECTED TOGETHER.
OUTPUT EXCITATION FREQUENCY = 30kHz
RFB, Z
= 100kΩ
CALIBRATION
0
0
2
4
6
8
10
12
14
16
18
0.192
0.194
0.196
0.198
0.200
0.202
0.204
0.206
MCLK FREQUENCY (MHz)
VOLTAGE (V)
Figure 12. Typical Supply Current vs. AD5934 Clock Frequency
Figure 10. Range 4: Output Excitation Voltage Distribution VDD = 3.3 V
0.4
30
VDD = 3.3V
MEAN = 0.1792
SIGMA = 0.0024
T
= 25°C
A
0.2
0
f = 32kHz
25
20
15
10
5
–0.2
–0.4
–0.6
–0.8
–1.0
0
0
50
100
150
200
250
300
350
400
0.160 0.165 0.170 0.175 0.180 0.185 0.190 0.195 0.200 0.205
PHASE (Degrees)
VOLTAGE (V)
Figure 13. Typical AD5934 Phase Error
Figure 11. Range 4: DC Bias Distribution VDD = 3.3 V
Rev. 0 | Page 9 of 32
AD5934
TERMINOLOGY
Total System Accurac y
Signal-to-Noise Ratio (SNR)
The AD5934 can accurately measure a range of impedance
values to less than 0.5% of the correct impedance value for
supply voltages between 2.7 V to 5.5 V.
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency. The value for SNR is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
Along with the frequency of interest, harmonics of the
fundamental frequency and images of these frequencies are
present at the output of a DDS device. The spurious-free
dynamic range refers to the largest spur or harmonic present in
the band of interest. The wideband SFDR gives the magnitude
of the largest harmonic or spur relative to the magnitude of the
fundamental frequency in the 0 to Nyquist bandwidth. The
narrow-band SFDR gives the attenuation of the largest spur
or harmonic in a bandwidth of 200 kHz, about the
fundamental frequency.
THD is the ratio of the rms sum of harmonics to the
fundamental, where V1 is the rms amplitude of the
fundamental and V2, V3, V4, V5, and V6 are the rms
amplitudes of the second through the sixth harmonics.
For the AD5934, THD is defined as
V22 +V32 +V42 +V52 +V 2
6
THD(db) = 20 log
V1
Rev. 0 | Page 10 of 32
AD5934
SYSTEM DESCRIPTION
MCLK
DDS
CORE
(27 BITS)
DAC
R
VOUT
OUT
COS
SIN
SCL
MICROCONTROLLER
SDA
2
I C
INTERFACE
Z(ω)
AD5934
REAL
IMAGINARY
REGISTER REGISTER
RFB
VIN
MAC CORE
(1024 DFT)
PROGRAMMABLE
GAIN AMPLIFIER
MCLK
WINDOWING
OF DATA
X5
X1
ADC
(12 BITS)
LPF
VDD/2
Figure 14. AD5934 Block Overview
The AD5934 is a high precision impedance converter system
solution which combines an on-board frequency generator with a
12-bit, 250 kSPS ADC. The frequency generator allows an external
complex impedance to be excited with a known frequency. The
response signal from the impedance is sampled by the on-board
ADC and DFT processed by an on-board DSP engine. The DFT
algorithm returns both a real (R) and imaginary (I) data-word at
each frequency point along the sweep. The impedance magnitude
and phase is easily calculated using the following equations:
The AD5934 permits the user to perform a frequency sweep with
a user-defined start frequency, frequency resolution, and number
of points in the sweep. In addition, the device allows the user to
program the peak-to-peak value of the output sinusoidal signal as
an excitation to the external unknown impedance connected
between the VOUT and VIN pins.
Table 6 gives the four possible output peak-to-peak voltages and
the corresponding dc bias levels for each range.
Table 6.
Magnitude= R2 + I2
Output Excitation Voltage Amplitude
Output DC Bias Level
Phase =Tan−1(I /R)
Range 1: 1.98 V p-p
Range 2: 0.99 V p-p
1.48 V
0.74V
To characterize an impedance profile Z(ω), generally a frequency
sweep is required like that shown in Figure 15.
Range 3: 383 mV p-p
Range 4: 198 mV p-p
0.31 V
0.179 V
The excitation signal for the transmit stage is provided on-chip
using DDS techniques which permit subhertz resolution. The
receive stage receives the input signal current from the unknown
impedance, performs signal processing, and digitizes the result.
The clock for the DDS is generated from an external reference
clock which is provided by the user at MCLK.
FREQUENCY
Figure 15.
Rev. 0 | Page 11 of 32
AD5934
TRANSMIT STAGE
As shown in Figure 16, the transmit stage of the AD5934 is made
up of a 27-bit phase accumulator DDS core which provides the
output excitation signal at a particular frequency. The input to the
phase accumulator is taken from the contents of the START
FREQUENCY register (see RAM Locations 82h, 83h, and 84h).
Although the phase accumulator offers 27 bits of resolution, the
START FREQUENCY register has the 3 most significant bits
(MSBs) set to 0 internally; therefore the user has the ability to
program only the lower 24 bits of the START FREQUENCY
register.
Equation 2, based on the master clock frequency and the required
increment frequency output from the DDS.
⎛
⎜
⎞
⎟
(2)
RequiredFrequencyIncrement
27
×2
⎜
⎜
⎟
⎟
Frequency Increment Code =
MCLK
⎛
⎜
⎝
⎞
⎟
⎠
⎜
⎟
16
⎝
⎠
For example, if the user requires the sweep to have a resolution of
10 Hz and has a 16 MHz clock signal connected to MCLK, the
code that needs to be programmed is given by
The AD5934 offers a frequency resolution programmable by the
user down to 0.1 Hz. The frequency resolution is programmed via
a 24-bit word loaded serially over the I2C interface to the
FREQUENCY INCREMENT register.
⎛
⎜
⎞
⎟
10 Hz
16 MHz
⎜
⎜
⎜
⎝
⎟
⎟
⎟
⎠
Frequency Increment Code =
≡ 00053E hexidecimal
⎛
⎜
⎞
⎟
16
⎝
⎠
The frequency sweep is fully described by the programming of
three parameters: the START FREQUENCY, the FREQUENCY
INCREMENT, and the NUMBER OF INCREMENTS.
The user programs 00 hex to Register 85 h, 05 hex to
Register 86 h, and finally 3E hex to Register 87 h.
NUMBER OF INCREMENTS
START FREQUENCY
This is a 9-bit word that represents the number of frequency
points in the sweep. The number is programmed to the on-board
RAM at Address 88 h and Address 89 h (see the Register Map
section). The maximum number of points that can be
programmed is 511.
This is a 24-bit word that is programmed to the on-board RAM at
Address 82h, Address 83h, and Address 84h (see the Register Map
section). The required code loaded to the START FREQUENCY
register is the result of the formula shown in Equation 1, based on
the master clock frequency and the required start frequency
output from the DDS.
For example, if the sweep needs 150 points, the user programs
00 hex to Register 88 h and 96 hex to Register 89 h.
⎛
⎞
⎜
⎟
(1)
Required Output Start Frequency
27
× 2
⎜
⎜
⎟
⎟
Once the three parameter values have been programmed, the
sweep is initiated by issuing a Start Frequency Sweep command
to the CONTROL register at Address 80 h and Address 81 h
(see the Register Map section). Bit 2 in the STATUS register
(Register 8F h) indicates the completion of the frequency
measurement for each sweep point. Incrementing to the next
frequency sweep point is under the control of the user. The
measured result is stored in two registers (94 h, 95 h and 96 h,
97 h) which should be read before issuing an Increment
Frequency command to the CONTROL register to move to the
next sweep point. There is the facility to repeat the current
frequency point measurement by issuing a Repeat Frequency
command to the CONTROL register. This has the benefit of
allowing the user to average successive readings. When the
frequency sweep has completed all frequency points, Bit 3 in the
STATUS register is set, indicating completion of the sweep. Once
this bit is set further increments are disabled.
Start Frequency Code =
MCLK
⎛
⎜
⎝
⎞
⎟
⎠
⎜
⎟
16
⎝
⎠
For example, if the user requires the sweep to begin at 30 kHz and
has a 16 MHz clock signal connected to MCLK. The code that
needs to be programmed is given by
⎛
⎞
⎜
⎟
30 kHz
16 MHz
16
⎜
⎜
⎜
⎝
⎟
⎟
⎟
⎠
27
×2 ≡ 3D70A3 hexidecimal
Start Frequency Code =
⎛
⎜
⎞
⎟
⎝
⎠
The user programs 3D hex to Register 82 h, 70 hex to
Register 83 h, and A3 hex to Register 84 h.
FREQUENCY INCREMENT
This is a 24-bit word that is programmed to the on-board
RAM at Address 85 h, Address 86 h, and Address 87 h (see
the Register Map section). The required code loaded to the
frequency increment register is the result of the formula shown in
Rev. 0 | Page 12 of 32
AD5934
FREQUENCY SWEEP COMMAND SEQUENCE
RECEIVE STAGE
The following sequence must be followed to implement a
frequency sweep.
The receive stage comprises a current–to-voltage amplifier,
followed by a programmable gain amplifier (PGA), antialiasing
filter, and ADC. The receive stage schematic is shown in
Figure 17. The unknown impedance is connected between the
VOUT and VIN pins. The first stage current-to-voltage amplifier
configuration means that a voltage present at the VIN pin is a
virtual ground with a dc value set at VDD/2. The signal current
that is developed across the unknown impedance flows into the
VIN pin and develops a voltage signal at the output of the current-
to-voltage converter. The gain of the current-to voltage amplifier
is determined by a user-selectable feedback resistor connected
between Pins 4 (RFB) and Pin 5 (VIN). It is important for the user
to choose a feedback resistance value which, in conjunction with
the selected gain of the PGA stage, maintains the signal within the
linear range of the ADC (0 V to VDD).
1. Enter standby mode.
Prior to issuing a Start Frequency Sweep command, the device
must be placed in a standby mode by issuing an Enter Standby
Mode command to the CONTROL register (Register 80 h). In
this mode, the VOUT and VIN pins are connected internally to
ground so there is no dc bias across the external impedance or
between the impedance and ground.
2. Enter initialize mode.
In general, high Q complex circuits require a long time to
reach steady state. To facilitate the measurement of such
impedances, this mode allows the user full control of the
settling time requirement before entering start frequency
sweep mode where the impedance measurement takes place.
The PGA allows the user to gain the output of the current-to-
voltage amplifier by a factor of 5 or 1 depending upon the status
of Bit D8 in the CONTROL register (see the Register Map section
Register 81h). The signal is then low-pass filtered and presented
to the input of the 12-bit, 250 kSPS ADC.
An Initialize with Start Frequency Command to the
CONTROL register enters initialize mode. In this mode the
impedance is excited with the programmed start frequency
but no measurement takes place. The user times out the
required settling time before issuing a Start Frequency
Sweep command to the CONTROL register to enter the
start frequency sweep mode.
RFB
R
5 × R
C
3. Enter start frequency sweep mode.
R
The user enters this mode by issuing a Start Frequency Sweep
command to the control register. In this mode, the ADC
starts measuring after the programmed Number of Settling
Time Cycles has elapsed. The user can program an integer
number of output frequency cycles (settling time cycles) to
Register 8A h and Register 8B h before beginning the
measurement at each frequency point (see Figure 28).
VIN
R
VDD/2
ADC
LPF
Figure 17. AD5934 Receive Stage
The digital data from the ADC is passed directly to the DSP core
of the AD5934 which performs a DFT on the sampled data.
The DDS output signal is passed through a programmable gain
stage in order to generate the four ranges of peak-to-peak output
excitation signals listed in Table 6. The peak-to-peak output
excitation voltage is selected by setting Bit D10 and Bit D9 in
the CONTROL register—see the Control Register section—
and is made available at the VOUT pin.
DFT OPERATION
A DFT is calculated for each frequency point in the sweep. The
AD5934 DFT algorithm is represented by
X( f ) = 1023
(
x(n)(cos(n)− jsin(n))
)
∑
n=0
R(GAIN)
where X(f) is the power in the signal at the frequency point f, x(n)
is the ADC output, with the cos(n) and sin(n) the sampled test
vectors provided by the DDS core at the frequency f.
PHASE
ACCUMULATOR
(27 BITS)
DAC
VOUT
VBIAS
The multiplication is accumulated over 1024 samples for each
frequency point. The result is stored in two, 16-bit registers
representing the real and imaginary components of the result. The
data is stored in twos complement format.
Figure 16. AD5934 Transmit Stage
Rev. 0 | Page 13 of 32
AD5934
IMPEDANCE CALCULATION
MAGNITUDE CALCULATION
IMPEDANCE CALCULATION USING GAIN FACTOR
The first step in impedance calculation for each frequency point is
to calculate the magnitude of the DFT at that point.
The next example illustrates how the calculated gain factor
derived previously is used to measure an unknown impedance.
For this example, assume that the unknown impedance = 510 kΩ.
The DFT magnitude is given by
After measuring the unknown impedance at a frequency of
30 kHz, assume that the real and imaginary registers contain the
following data:
2
2
Magnitude= R + I
where R is the real number stored at Register Address 94 h and
Register Address 95 h and I is the imaginary number stored at
Register Address 96 h and Register Address 97 h.
Real register: = 0AEB hex = −1473 decimal
Imaginary register: = 0DB3 hex = 3507 decimal
Magnitude = ((−1473)2 + (3507)2 ) = 3802.863
For example, assume the results in the real and imaginary registers
are as follows at a frequency point:
Then the measured impedance at the frequency point is given by
1
Real register: = 038B hex = 907 decimal
Imaginary register: = 0204 hex = 516 decimal
Magnitude= (9072 + 5162 ) = 1043.506
Impedance
=
GAIN FACTOR × Magnitude
1
=
ꢀ
515.819273 E − 12 × 3802.863
= 509.791 kꢀ
To convert this number into an impedance, it must be multiplied
by a scaling factor called the gain factor. The gain factor is
calculated during the calibration of the system with a known
impedance connected between the VOUT and VIN pins.
GAIN FACTOR VARIATION WITH FREQUENCY
Because the AD5934 has a finite frequency response, the gain
factor also shows a variation with frequency. This results in
an error in the impedance calculation over a frequency range.
Figure 18 shows an impedance profile based on a single-point
gain factor calculation. To minimize this error, the frequency
sweep should be limited to as small a frequency range as possible.
Once the gain factor has been calculated, it can be used in the
calculation of any unknown impedance between the VOUT and
VIN pins.
GAIN FACTOR CALCULATION
An example of a gain factor calculation follows, with these
assumptions:
101.5
VDD = 3.3V
Output excitation voltage = 2 V (p-p)
Calibration impedance value, ZCALIBRATION = 200 kΩ
PGA gain = ×1
Current to voltage amplifier gain resistor = 200 kΩ
Calibration frequency = 30 kHz
CALIBRATION FREQUENCY = 60kHz
T
= 25°C
A
101.0
100.5
100.0
99.5
MEASURED CALIBRATION IMPEDANCE = 100kΩ
Then typical contents of the real and imaginary register after a
frequency point conversion would be
Real register: = F9C hex = -3996 decimal
Imaginary register: = 227E hex = 8830 decimal
99.0
Magnitude = (−39962 + (8830)2 = 9692.106
98.5
⎛
⎞
1
54
56
58
60
62
64
66
⎜
⎜
⎟
⎟
Impedance
FREQUENCY (kHz)
ADMITTANCE
Code
⎛
⎜
⎝
⎞
⎟
⎠
⎝
⎠
GAIN FACTOR =
GAIN FACTOR =
=
Magnitude
Figure 18. Impedance Profile Using a Single-Point Gain Factor Calculation
1
⎛
⎞
⎜
⎟
200 kꢀ
⎜
⎜
⎜
⎝
⎟
⎟
⎟
⎠
= 515.819E − 12
9692.106
Rev. 0 | Page 14 of 32
AD5934
TWO-POINT CALIBRATION
GAIN FACTOR SETUP CONFIGURATION
Alternatively it is possible to minimize this error by assuming that
the frequency variation is linear and adjusting the gain factor with
a 2-point calibration. Figure 19 shows an impedance profile based
on a 2-point GAIN FACTOR calculation.
When calculating the GAIN FACTOR, it is important that
the receive stage is operating in its linear region. This requires
careful selection of the excitation signal range, current-to-voltage
gain resistor and PGA gain. The gain through the system shown in
Figure 20 is given by
101.5
VDD = 3.3V
CALIBRATION FREQUENCY = 60kHz
T
= 25°C
A
Gain Setting Resistor
101.0
100.5
100.0
99.5
MEASURED CALIBRATION IMPEDANCE = 100kΩ
Output ExcitationVoltage Range ×
×PGA Gain
ZUNKNOWN
CURRENT TO VOLTAGE
GAIN SETTING RESISTOR
RFB
Z
UNKNOWN
VOUT
VIN
VDD
ADC
99.0
LPF
PGA
(X1 OR X5)
98.5
54
56
58
60
62
64
66
Figure 20. AD5934 System Voltage Gain
FREQUENCY (kHz)
Figure 19. Impedance Profile Using a 2-Point Gain Factor Calculation
For this example, assume the following system settings:
VDD = 3.3 V
TWO-POINT GAIN FACTOR CALCULATION
Gain setting resistor = 200 kΩ
This is an example of a 2-point GAIN FACTOR calculation
assuming the following:
Z
UNKNOWN = 200 kΩ
PGA setting = ×1
Output excitation voltage = 2 V (p-p)
Calibration impedance value, ZUNKNOWN = 100.0 kΩ
PGA gain = ×1
The peak-to-peak voltage presented to the ADC input is
2 V p-p. However had the user chosen a PGA gain of ×5, the
voltage would saturate the ADC.
Supply voltage = 3.3 V
Current to voltage amplifier gain resistor = 100 kΩ
Calibration frequencies at = 55 kHz and 65 kHz
GAIN FACTOR RECALCULATION
The GAIN FACTOR must be recalculated for a change in any of
the following parameters:
Typical values of the GAIN FACTOR calculated at the two
calibration frequencies read
•
•
•
Current-to-voltage gain setting resistor
Output excitation voltage
PGA gain
Gain factor calculated at 55 kHz = 1.031224E-09
Gain factor calculated at 65 kHz = 1.035682E-09
Difference in gain factor (ΔGF) = 1.035682E-09 −
1.031224E-09 = 4.458000E-12
Frequency span of sweep (ΔF) = 10 kHz
Therefore the GAIN FACTOR required at 60 kHz is given by
4.458000E -12
10 kHz
⎛
⎜
⎝
⎞
⎠
×5 kHz +1.031224E -09
⎟
Required gain factor = 1.033453E-9
The impedance is calculated as previously described in the
Impedance Calculation section.
Rev. 0 | Page 15 of 32
AD5934
GAIN FACTOR TEMPERATURE VARIATION
Range 2 (1 kΩ to 10 kΩ)
The typical impedance error variation with temperature is in the
order of 30 ppm/°C. Figure 21 shows an impedance profile with a
variation in temperature for 100 kΩ impedance using a 2-point
gain factor calibration.
Output excitation voltage = 2 V p-p
Calibration impedance value, ZCALIBRATION = 1 kΩ
PGA gain = ×1
101.5
Supply voltage = 3.3 V
Current-to-voltage amplifier gain resistor = 1 kΩ
+125°C
101.0
100.5
100.0
99.5
2.0
RFB = 1kΩ
CALIBRATION IMPEDANCE = 1kΩ
A
1.8
T
= 25°C
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
+25
°
C
5kΩ
10kΩ
–40
°
C
99.0
VDD = 3.3V
CALIBRATION FREQUENCY = 60kHz
MEASURED CALIBRATION IMPEDANCE = 100k
Ω
98.5
54
56
58
60
62
64
66
FREQUENCY (kHz)
Figure 21. Impedance Profile Variation with Temperature Using a 2-Point Gain
Factor Calculation
10
35
60
100
FREQUENCY (kHz)
IMPEDANCE ERROR
Figure 23. Range 2: Typical % Impedance Error over Frequency
Minimizing the impedance range under test optimizes the
AD5934 measurement performance. Below are examples of the
AD5934 performance when operating in the six different
impedance ranges. The gain factor is calculated with a precision
resistor in each case.
Range 3 (10 kΩ to 100 kΩ)
Output excitation voltage = 2 V p-p
Calibration impedance value, ZCALIBRATION = 10 kΩ
PGA gain = ×1
Supply voltage = 3.3 V
Current-to-voltage amplifier gain resistor = 10 kΩ
Range 1 (0.1 kΩ to 1 kΩ)
Output excitation voltage = 2 V p-p
Calibration impedance value, ZCALIBRATION = 100 Ω
PGA gain = ×1
Supply voltage = 3.3 V
Current-to-voltage amplifier gain resistor = 100 Ω
0.3
RFB = 10kΩ
CALIBRATION IMPEDANCE = 10kΩ
50kΩ
T
= 25°C
A
0.2
0.1
100kΩ
7
RFB = 0.1kΩ
0
CALIBRATION IMPEDANCE = 0.1kΩ
6
5
4
3
2
1
0
T
= 25°C
A
–0.1
–0.2
–0.3
0.5kΩ
1kΩ
10
35
60
100
FREQUENCY (kHz)
Figure 24. Range 3: Typical % Impedance Error over Frequency
10
35
60
100
FREQUENCY (kHz)
Figure 22. Range 1: Typical % Impedance Error over Frequency
Rev. 0 | Page 16 of 32
AD5934
Range 4 (100 kΩ to 1 MΩ)
Range 6 (9 MΩ to 10 MΩ)
Output excitation voltage = 2 V p-p
Calibration impedance value, ZCALIBRATION = 100 kΩ
PGA gain = ×1
Output excitation voltage = 2 V p-p
Calibration impedance value, ZCALIBRATION = 9 MΩ
PGA gain = ×1
Supply voltage = 3.3 V
Supply voltage = 3.3 V
Current-to-voltage amplifier gain resistor = 100 kΩ
Current to voltage amplifier gain resistor = 9 MΩ
1.0
4
RFB = 10MΩ
500kΩ
CALIBRATION IMPEDANCE = 10MΩ
0.5
1MΩ
T
= 25°C
2
0
A
0
–0.5
–1.0
–1.5
–2.0
–2
–4
–6
–8
–10
9.5MΩ
10MΩ
–2.5
RFB = 100kΩ
–3.0
–3.5
CALIBRATION IMPEDANCE = 100kΩ
T
= 25°C
A
10
35
60
100
10
35
60
100
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 25. Range 4: Typical % Impedance Error over Frequency
Figure 27. Range 6: Typical % Impedance Error over Frequency
Range 5 (1 MΩ to 2 MΩ)
Output excitation voltage = 2 V p-p
Calibration impedance value, ZCALIBRATION = 100 kΩ
PGA gain = ×1
Supply voltage = 3.3 V
Current to voltage amplifier gain resistor = 100 kΩ
3
RFB = 1MΩ
CALIBRATION IMPEDANCE = 1MΩ
T
= 25°C
A
1
–1
–3
–5
–7
–9
1.5MΩ
2MΩ
10
35
60
100
FREQUENCY (kHz)
Figure 26. Range 5: Typical % Impedance Error over Frequency
Rev. 0 | Page 17 of 32
AD5934
PERFORMING A FREQUENCY SWEEP
PROGRAM FREQUENCY SWEEP PARAMETERS
INTO RELEVANT REGISTERS
(1) START FREQUENCY REGISTER
(2) NUMBER OF INCREMENTS REGISTER
(3) FREQUENCY INCREMENT REGISTER
PLACE THE AD5934 INTO STANDBY MODE.
RESET: BY ISSUING A RESET COMMAND TO
CONTROL REGISTER THE DEVICE IS PLACED
IN STANDBY MODE.
PROGRAM INITIALIZE WITH START
FREQUENCY COMMAND TO THE CONTROL
REGISTER.
PROGRAM START FREQUENCY SWEEP
COMMAND IN THE CONTROL REGISTER, AFTER
A SUFFICIENT AMOUNT OF SETTLING TIME
HAS ELAPSED.
POLL STATUS REGISTER TO CHECK IF
THE DFT CONVERSION IS COMPLETE.
N
Y
PROGRAM THE INCREMENT FREQUENCY OR
THE REPEAT FREQUENCY COMMAND TO THE
CONTROL REGISTER.
READ VALUES FROM REAL AND
IMAGINARY DATA REGISTER.
Y
POLL STATUS REGISTER TO CHECK IF
FREQUENCY SWEEP IS COMPLETE.
N
Y
PROGRAM THE AD5934
INTO POWER-DOWN MODE.
Figure 28. Frequency Sweep Flow Chart
Rev. 0 | Page 18 of 32
AD5934
REGISTER MAP
Table 7.
Register Name
Register Address
80 h
81 h
Register Data
D15 to D8
D7 to D0
Read/Write Register
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read Only
CONTROL
START FREQUENCY
82 h
83 h
84 h
D23 to D16
D15 to D8
D7 to D0
FREQUENCY INCREMENT
85 h
86 h
87 h
D23 to D16
D15 to D8
D7 to D0
NUMBER OF INCREMENTS
88 h
89 h
D15 to D8
D7 to D0
NUMBER OF SETTLING TIME CYCLES
8A h
8B h
D15 to D8
D7 to D0
STATUS
8F h
D7 to D0
REAL DATA
94 h
95 h
D15 to D8
D7 to D0
Read Only
Read Only
IMAGINARY DATA
96 h
97 h
D15 to D8
D7 to D0
Read Only
Read Only
CONTROL REGISTER
Table 8. 16-Bit Register
Table 9. Control Register Map
80 h
81 h
D15 to D8
D7 to D0
Read or Write
Read or Write
Bit
D15 D14 D13 D12
0
0
0
0
0
0
0
1
No operation
Initialize with Start
Frequency
Start Frequency Sweep
Increment Frequency
Repeat Frequency
No operation
No operation
Power down mode
Standby mode
No operation
No operation
The CONTROL register is a 16-bit register that sets the AD5934
control modes. The 4 MSBs of the CONTROL register are
decoded to provide control functions, such as performing a
frequency sweep, powering down the part, and various other
control functions defined in the CONTROL register map.
0
0
0
1
1
1
1
1
1
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
1
0
0
1
0
1
0
1
The user may choose to write only to Register Location 80 h
and not to alter the contents of 81 h. Note that the CONTROL
register should not be written to as part of a Block Write
command. The CONTROL register also allows the user to
program the excitation voltage and set the system clock. A
Reset command to the CONTROL register does not reset any
programmed values associated with the sweep (that is, Start
frequency, number of increments, frequency increment). After
a Reset command, an Initialize with Start Frequency command
must be issued to the CONTROL register to restart the
frequency sweep sequence (see Figure 28).
D11
No operation
D10 D9
Output voltage range
Range 1 ( 2.0 V p-p typ)
Range 3 (200 mV p-p typ)
Range 4 (400 mV p-p typ)
Range 2 (1.0 V p-p typ)
PGA gain 0 = ×5, 1 = ×1
Reserved. Set to 0.
Reserved. Set to 0.
Reserved. Set to 0.
Reset
External System clock.
Must be set to 1.
Must be Set to 0.
Reserved. Set to 0.
Reserved. Set to 0.
0
0
1
1
0
1
0
1
D8
D7
D6
D5
D4
D3
Default value upon reset: D15 to D0 reset to A0 00H upon
power-up. The AD5934 contains a 16-bit control register
(Address 80h and 81h) that sets the AD5934 control modes.
1
0
D2
D1
D0
Rev. 0 | Page 19 of 32
AD5934
CONTROL Register Decode
START FREQUENCY REGISTER
Table 10. 24-Bit Register
Initialize with Start Frequency
82 h
83 h
84 h
D23 to D16
D15 to D8
D7 to D0
Read or Write
Read or Write
Read or Write
This command enables the DDS to output the programmed
start frequency for an indefinite time. It is used is to excite the
unknown impedance initially. When the output unknown
impedance has settled after a time determined by the user, the
user must initiate a Start Frequency Sweep command to begin
the frequency sweep.
The START FREQUENCY register contains the 24-bit digital
representation of the frequency from where the subsequent
frequency sweep is initiated. For example, if the user requires
the sweep to start from frequency 30 kHz (using a 16.00 MHz
clock), then the user programs 3D hex to Register Location
82 h, 70 hex to Register Location 83h, and A3 hex to
Register Location 84 h. This ensures the output frequency starts at
30 kHz.
Start Frequency Sweep
In this mode the ADC starts measuring after the programmed
number of settling time cycles has elapsed. The user has the
ability to program an integer number of output frequency cycles
(settling time cycles) to Register 8A h and Register 8B h before
the commencement of the measurement at each frequency
point. See Figure 28.
The code to be programmed to the START FREQUENCY
register is
Increment Frequency
⎛
⎞
⎜
⎟
30 kHz
16 MHz
The Increment Frequency command is used to step to the next
frequency point in the sweep. This usually happens after data
from the previous step has been transferred and verified by the
DSP. When the AD5934 receives this command, it waits for the
programmed number of settling time cycles before beginning
the ADC conversion process.
27
⎜
⎜
⎟
⎟
Start Frequency Code =
× 2 ≡ 3D70A3 hexidecimal
⎛
⎜
⎝
⎞
⎟
⎠
⎜
⎝
⎟
⎠
16
Default value upon reset: D23 to D0 are not reset on power-up.
After a Reset command the contents of this register are not reset.
Repeat Frequency
FREQUENCY INCREMENT REGISTER
There is the facility to repeat the current frequency point
measurement by issuing a Repeat Frequency command to the
CONTROL register. This has the benefit of allowing the user to
average successive readings.
Table 11.
85 h
86 h
87 h
D23 to D16
D15 to D8
D7 to D0
Read or Write
Read or Write
Read or Write
Power-Down
The FREQUENCY INCREMENT register contains a 24-bit
representation of the frequency increment between consecutive
frequency points along the sweep. For example, if the user
requires an increment step of 30 Hz using a 16.0 MHz clock, the
user should program 00 hex to Register Location 85 h, 0F hex to
Register Location 86 h and BA hex to Register Location 87 h.
The default state on power-up of the AD5934 is power-down
mode. The CONTROL register contains the code
1010000000000000 (A000h). In this mode both the output and
input VOUT and VIN pins are connected internally to GND.
Standby Mode
Powers up the part for general operation; in standby mode the
VIN and VOUT pins are internally connected to ground.
The formula for calculating the increment frequency is given by
⎛
⎞
⎜
⎟
10 Hz
16 MHz
Reset
27
⎜
⎜
⎟
⎟
Frequency Increment Code =
× 2 ≡ 00053E hexidecimal
A Reset command allows the user to interrupt a sweep. The
START FREQUENCY, NUMBER OF INCREMENTS, and
FREQUENCY INCREMENT register contents are not
overwritten. An Initialize with Start Frequency command is
required to restart the Frequency Sweep command sequence.
⎛
⎜
⎝
⎞
⎟
⎠
⎜
⎝
⎟
⎠
16
The user programs 00 hex to Register 85 h, 05 hex to
Register 86 h, and 3E hex to Register 87 h.
Output Voltage Range
This allows the user to program the excitation voltage range at
VOUT.
Default value upon reset: D23 to D0 are not reset on power-up.
After a Reset command, the contents of this register are not reset.
PGA Gain
This allows the user to amplify the response signal into the
ADC by a multiplication factor of ×5 or ×1.
Rev. 0 | Page 20 of 32
AD5934
NUMBER OF INCREMENTS REGISTER
Table 12. 16-Bit Register
Bits D15 to D9 = Don’t care
88 h
89 h
D15 to D8
D7 to D0
Read or Write
Read or Write
Integer number stored in binary
format
Bits D8 to D0 = Number of frequency increments
This register determines the number of frequency points in the frequency sweep. The number of points is represented by a 9-bit word,
D8 to D0. D9 to D15 are don’t care bits. This register in conjunction with the START FREQUENCY register and the INCREMENT
FREQUENCY registers determine the frequency sweep range for the sweep operation. The maximum number of increments which can
be programmed is 511.
Default value upon reset: D8 to D0 are not reset on power-up. After a Reset command, the contents of this register are not reset.
NUMBER OF SETTLING TIME CYCLES REGISTER
Table 13. 16-Bit Register
D15 to D11 = Don’t Care
D10 to D9 = 2-Bit Decode
D8 = MSB Number of Settling Time Cycles
D10 D9
8A h
D15 to D8
Read or Write
Integer number stored in binary format
0
0
1
1
0
1
0
1
Default
Number Cycles × 2
Reserved
Number Cycles × 4
Number of Settling Time Cycles
8B h
D7 to D0
Read or Write
This register determines the number of output excitation cycles that are allowed to pass through the unknown impedance, after receipt of
a Start, Increment, or Repeat Frequency command, before the ADC is triggered to perform a conversion of the response signal. The
SETTLING TIME CYCLES register value determines the delay between a Frequency Start/Increment/Repeat command and the time an
ADC conversion commences. The number of cycles is represented by a 9-bit word, D8 to D0. The value programmed into the SETTLING
TIME CYCLES register can be increased by a factor of 2 or 4 depending upon the status of bits D10 to D9. The 5 most significant bits,
D15 to D11, are don’t care bits. The maximum number of output cycles that can be programmed is 511 × 4 = 2044 cycles. For example,
consider an excitation signal of 30 kHz. The maximum delay between the programming of this frequency and the time that this signal is
first sampled by the ADC is ≈ 511 × 4 × 33.33 μs = 68.126 ms. The ADC takes 1024 samples, and the result is stored as real and imaginary
data in Register 94 h to Register 97 h. The conversion process takes approximately 1 ms using a 16.777 MHz clock.
Default value upon reset: D10 to D0 are not reset on power-up. After a Reset command, the contents of this register are not reset.
Rev. 0 | Page 21 of 32
AD5934
Valid Real/Imaginary Data
STATUS REGISTER
Set when data processing for the current frequency point is
finished, indicating real/imaginary data available for reading.
Reset when a DDS Start/Increment/Repeat command is issued.
Also this bit is reset to 0 when a Reset command is issued to the
CONTROL register.
Table 14. 8-Bit Register
8F h
D7 to D0
Read Only
Bits
The STATUS register is used to confirm that particular
measurement tests have been successfully completed. Each of
the bits from D7 to D0 indicates the status of specific
functionality of the AD5934.
Frequency Sweep Complete
Set when data processing for the last frequency point in the sweep
is complete. Reset when a Start Frequency Sweep command is
issued to the CONTROL register. This bit is also reset when a
Reset command is issued to the CONTROL register.
D0, and Bit D4 to Bit D7 are treated as don’t care bits, these bits
do not indicate the status of any measurement
The status of bit D1 indicates the status of a frequency point
impedance measurement. This bit is set when the AD5934
has completed the current frequency point impedance
measurement. This indicates that there is valid real and
imaginary data in Register 93 h to Register 97 h. This bit is
reset on receipt of a Start, Increment, Repeat Frequency, or
Reset command. This bit is also reset on power-up.
REAL AND IMAGINARY DATA REGISTERS (16 BITS)
Table 16. Real Data
94 h
D15 to D8
Read Only
Read Only
Twos complement
data
95 h
D7 to D0
Table 17. Imaginary Data
The status of bit D2 indicates the status of the programmed
frequency sweep. This bit is set when all programmed
increments to the NUMBER of INCREMENTS register are
complete. This bit is reset on power-up and on receipt of a
Reset command.
96 h
D15 to D8
Read Only
Twos complement
data
97 h
D7 to D0
Read Only
These registers contain a digital representation of the real
and imaginary components of the impedance measured for
the current frequency point. The values are stored in 16-bit,
twos complement format. To convert this number to an actual
Table 15. STATUS Register
STATUS Register
Address
Control Word
0000 0001
0000 0010
0000 0100
0000 1000
0001 0000
0010 0000
0100 0000
1000 0000
Function
impedance value, the magnitude— (Real2 and Imaginary2 ) —
8F h
8F h
8F h
8F h
8F h
8F h
8F h
8F h
Reserved
must be multiplied by an admittance/code number (called a
gain factor) to give the admittance, and the result inverted to
give impedance. The gain factor varies for each ac excitation
voltage/gain combination.
Valid real/imaginary data
Frequency sweep complete
Reserved
Reserved
Reserved
Default value upon reset: These registers are not reset on
power-up or on receipt of a Reset command. Note that the data
in these registers is only valid if Bit D1 in the STATUS register
is set, indicating that the processing at the current frequency
point is complete.
Reserved
Reserved
Rev. 0 | Page 22 of 32
AD5934
SERIAL BUS INTERFACE
Control of the AD5934 is carried out via the 12C-compliant
serial interface protocol. The AD5934 is connected to this bus
as a slave device under the control of a master device. The
AD5934 has a 7-bit serial bus slave address. When the device is
powered up, it has a default serial bus address, 0001101 (0D hex)
Data is sent over the serial bus in sequences of nine clock
pulses, 8 bits of data followed by an acknowledge bit, which can
be from the master or slave device. Data transitions on the data
line must occur during the low period of the clock signal and
remain stable during the high period, because a low-to-high
transition when the clock is high may be interpreted as a stop
signal. If the operation is a write operation, the first data byte
after the slave address is a command byte. This tells the slave
device what to expect next. It may be an instruction telling the
slave device to expect a block write, or it may be a register
address that tells the slave where subsequent data is to be
written. Because data can flow in only one direction as defined
by the R/W bit, it is not possible to send a command to a slave
device during a read operation. Before performing a read
operation, it is sometimes necessary to perform a write
operation to tell the slave what sort of read operation to expect
and/or the address from which data is to be read.
GENERAL I2C TIMING
The general I2C protocol operates as described in this section.
Figure 29 shows the timing diagram for general read and write
operations using the I2C-compliant interface.
The master initiates data transfer by establishing a start
condition, defined as a high to low transition on the serial data
line (SDA) while the serial clock line (SCL) remains high. This
indicates that a data stream follows. The slave responds to the
start condition and shifts in the next 8 bits, consisting of a 7-bit
slave address (MSB first) plus an R/W bit, which determines the
direction of the data transfer—that is, whether data is written to
or read from the slave device (0 = write, 1 = read).
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the 10th clock pulse to assert a stop condition. In
read mode, the master device releases the SDA line during the
low period before the ninth clock pulse, but the slave device
does not pull it low. This is known as a no acknowledge
(NACK). The master then takes the data line low during the low
period before the 10th clock pulse, then high during the 10th
clock pulse to assert a stop condition.
The slave responds by pulling the data line low during the low
period before the ninth clock pulse, known as the acknowledge
bit, and holding it low during the high period of this clock
pulse. All other devices on the bus remain idle while the
selected device waits for data to be read from or written to it.
If the R/W bit is 0, then the master writes to the slave device.
If the R/W bit is 1, the master reads from the slave device.
SCL
SDA
0
0
0
1
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
R/W
START COND
BY MASTER
ACK. BY
MASTER/SLAVE
ACK. BY
AD5934
SLAVE ADDRESS BYTE
REGISTER ADDRESS
Figure 29.
Rev. 0 | Page 23 of 32
AD5934
WRITING/READING TO THE AD5934
The interface specification defines several different protocols
for different types of read and write operations. This section
describes the protocols used in the AD5934. The figures in this
section use the following abbreviations:
In the AD5934, the write byte protocol is also used to set a
pointer to a register location. This is used for a subsequent
single-byte read from the same address or block read or write
starting at that address.
S
P
R
W
A
A
Start
Stop
Read
Write
To set a register pointer, the following sequence is applied:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
Acknowledge
No acknowledge write byte/command byte
3. The addressed slave device asserts ACK on SDA.
4. The master sends a pointer command code (see Table 18, a
pointer command = 1011 0000).
User Command Codes
The command codes in Table 18 are used for reading/writing to
the interface. They are further explained in this section, but are
grouped here for easy reference.
5. The slave asserts ACK on SDA.
6. The master sends a data byte (a register location where
pointer is to point).
Table 18.
Command Code
7. The slave asserts ACK on SDA.
Code
Name
Code Description
8. The master asserts a stop condition on SDA to end the
transaction.
1010 0000 Block
Write
This command is used when writing
multiple bytes to the RAM. See the
Block Write section.
This command is used when reading
multiple bytes from RAM/memory.
See the Block Read section.
SLAVE
ADDRESS
POINTER COMMAND
1011 0000
REGISTER LOCATION
TO POINT TO
S
W
A
A
A
P
1010 0001 Block
Read
Figure 31. Setting Pointer to Register Address
1011 0000 Address This command enables the user to set
Pointer
the address pointer to any location in
the memory. The data contains the
address of the register where the
pointer should be pointing.
BLOCK WRITE
In this operation, the master device writes a block of data to a
slave device. The start address for a block write must previously
have been set. In the case of the AD5934 this is done by setting
a pointer to set the register address.
Write Byte/Command Byte
In this operation the master device sends a byte of data to the
slave device. The write byte can either be a data byte write to a
RAM location or can be a command operation. To write data to
a register the command sequence is as follows:
1. The master device asserts a start condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
3. The addressed slave device asserts ACK on SDA.
1. The master device asserts a start condition on SDA.
4. The master sends an 8-bit command code (1010 0000) that
tells the slave device to expect a block write.
2. The master sends the 7-bit slave address followed by the
write bit (low).
5. The slave asserts ACK on SDA.
3. The addressed slave device asserts ACK on SDA.
4. The master sends a register address.
5. The slave asserts ACK on SDA.
6. The master sends a data byte that tells the slave device the
number of data bytes to be sent to it.
7. The slave asserts ACK on SDA.
8. The master sends the data bytes.
6. The master sends a data byte.
9. The slave asserts ACK on SDA after each data byte.
7. The slave asserts ACK on SDA.
10. The master asserts a stop condition on SDA to end the
transaction.
8. The master asserts a stop condition on SDA to end the
transaction.
SLAVE
ADDRESS
BLOCK
WRITE
NUMBER
BYTES WRITE
S
W
A
A
A
BYTE 0
A
BYTE 1
A
BYTE 2
A
P
SLAVE
REGISTER
ADDRESS
REGISTER
DATA
S
W
A
A
A
P
ADDRESS
Figure 32. Writing a Block Write
Figure 30. Writing Register Data to Register Address
Rev. 0 | Page 24 of 32
AD5934
AD5934 READ OPERATIONS
The AD5934 uses the following I2C read protocols:
Block Read
In this operation, the master device reads a block of data from a
slave device. The start address for a block read must previously
have been set by setting a pointer.
Receive Byte
In the AD5934, the receive byte protocol is used to read a single
byte of data from a register location whose address has
previously been set by setting the address pointer.
1. The master device asserts a START condition on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (low).
In this operation, the master device receives a single byte from a
slave device as follows:
3. The addressed slave device asserts ACK on SDA.
1. The master device asserts a start condition on SDA.
4. The master sends a command code (1010 0001) that tells
the slave device to expect a block read.
2. The master sends the 7-bit slave address followed by the
read bit (high).
5. The slave asserts ACK on SDA.
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
6. The master sends a byte count data byte that tells the slave
how many data bytes to expect.
7. The slave asserts ACK on SDA.
5. The master asserts NACK on SDA (slave needs to check
that master has received data).
8. The master asserts a repeat start condition on SDA. This is
required to set the read bit high.
6. The master asserts a stop condition on SDA and the
transaction ends.
9. The master sends the 7-bit slave address followed by the
read bit (high).
SLAVE
ADDRESS
REGISTER
DATA
S
R
A
A
P
10. The slave asserts ACK on SDA.
11. The master receives the data bytes.
Figure 33. Reading Register Data
12. The master asserts ACK on SDA after each data byte.
13. A NACK is generated after the last byte to signal the end of
the read.
14. The master asserts a stop condition on SDA to end the
transaction.
SLAVE
ADDRESS
BLOCK
READ
NUMBER
BYTES READ
S
W
A
A
A
S
SLAVE
ADDRESS
R
A
BYTE 0
A
BYTE 1
A
BYTE 2
A
P
Figure 34. Performing a Block Read
Rev. 0 | Page 25 of 32
AD5934
TYPICAL APPLICATIONS
This section describes typical applications for the AD5934.
BIOMEDICAL: NONINVASIVE BLOOD IMPEDANCE
MEASUREMENT
SENSOR/COMPLEX IMPEDANCE MEASUREMENT
The operational principle of a capacitive proximity sensor is
based on the change of a capacitance in a RLC resonant circuit.
This leads to changes in the resonant frequency of the RLC
circuit, which can be evaluated as shown Figure 36.
When a known strain of a virus is added to a blood sample
that already contains a virus, a chemical reaction takes place
whereby the impedance of the blood under certain conditions
changes. By characterizing this effect across different
frequencies it is possible to detect a specific strain of virus.
For example, a strain of the disease exhibits a certain
characteristic impedance at one frequency but not at another,
therefore the requirement to sweep different frequencies to
check for different viruses. The AD5934, with its 27-bit phase
accumulator, allows for sub-Hz frequency tuning.
It is first required to tune the RLC circuit to the area of
resonance. At the resonant frequency, the impedance of the
RLC circuit is at a maximum. Therefore, a programmable
frequency sweep and tuning capability is required, which is
provided by the AD5934.
RESONANT
FREQUENCY
CHANGE IN
RESONANCE DUE
TO APPROACHING
OBJECT
The AD5934 can be used to inject a stimulus signal through
the blood sample via a probe. The response signal is analyzed
and the effective impedance of the blood is tabulated. The
AD5934 is ideal for this application because it allows the user to
tune to the specific frequency required for each test.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ADuC702x
TOP VIEW
(Not to Scale)
AD5934
TOP VIEW
(Not to Scale)
RFB
F
O
FREQUENCY (Hz)
Figure 36. Detecting a Change in Resonant Frequency
An example of the use of this type of sensor is for a train
proximity measurement system. The magnetic fields of the
train approaching on the track change the resonant frequency
to an extent that can be characterized. This information can be
sent back to a mainframe system to show the train location
on the network.
PROBE
7V
ADR43x
2
6
0.1μF
10μF
4
Another application for the AD5934 is in parked vehicle
detection. The AD5934 is placed in an embedded unit
connected to a coil of wire underneath the parking location.
The AD5934 outputs a single frequency within the 80 kHz to
100 kHz frequency range, depending upon the wire
Figure 35. Measuring a Blood Sample for a Strain of Virus
composition. The wire can be modeled as a resonant circuit.
The coil is calibrated with a known impedance value and at a
known frequency. The impedance of the loop is monitored
constantly. If a car is parked over the coil, the impedance of the
coil changes and the AD5934 detects the presence of the car.
Rev. 0 | Page 26 of 32
AD5934
ELECTRO-IMPEDANCE SPECTROSCOPY
The AD5934 has found use in the area of corrosion monitoring.
Corrosion in a metal such as aluminum, which is used in air
craft and ships, requires continuous assessment because the
metal is exposed to a wide variety of conditions such as temper-
ature and moisture. The AD5934 offers an accurate and
compact solution for this type of measurement compared to the
large and expensive existing units on the market.
To ensure that the measurement itself does not introduce a
corrosive effect, the metal needs to be excited with minimal
voltage, typically in the 200 mV region which the AD5934 is
capable of outputting. A nearby processor or control unit
like the ADuc702x would log a single impedance sweep from
0.1 kHz to 100 kHz every 10 minutes and download the results
back to a control unit. In order to achieve system accuracy
from the 0.1 kHz to 1 kHz region, the system clock needs to be
scaled down from the 16.776 MHz nominal clock frequency to
500 kHz, typically. The clock scaling can be achieved digitally
using an external direct digital synthesizer like the AD9834
as a programmable divider, which supplies a clock signal to
MCLK and which can be controlled digitally by the nearby
microprocessor.
Mathematically the corrosion of a metal is modeled using a
RC network which consists of a resistance,Rs, in series with a
parallel resistor and capacitor, Rp and Cp. A system metal
would typically have values as follows: Rs 10 Ω to 10 kΩ,
Rp 1 kΩ to 1 MΩ, and Cp 5 μf to 70 μf.
The frequency range of interest when monitoring corrosion is
0.1 Hz to 100 kHz.
Rev. 0 | Page 27 of 32
AD5934
CHOOSING A REFERENCE FOR THE AD5934
To achieve the best performance from the AD5934, thought
should be given to the choice of a precision voltage reference.
The AD5934 has three reference inputs: (AVDD1, AVDD2, and
DVDD). It is recommended that the voltage on these reference
inputs be run from the same voltage supply.
This requires less than 100 μA of quiescent current. It also
provides very good noise performance at 8 μV p-p in the
0.1 Hz to 10 Hz range.
Long-term drift is a measure of how much the reference drifts
over time. A reference with a tight long-term drift specification
ensures that the overall solution remains stable during its entire
lifetime. A reference with a tight temperature coefficient
specification should be chosen to reduce temperature
dependence of the system output voltage on ambient
conditions.
There are four possible sources of error that should be
considered when choosing a voltage reference for high accuracy
applications: initial accuracy, ppm drift, long-term drift, and
output voltage noise. To minimize these errors, a reference with
high initial accuracy is preferred. Also, choosing a reference
with an output trim adjustment, such as a device in the
ADR43X family, allows a system designer to trim system errors
by setting a reference voltage to a voltage other than the
nominal. The trim adjustment can also be used at temperature
to trim out any error.
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise needs to be considered.
Choosing a reference with as low an output noise voltage as
practical for the system noise resolution required is important.
Precision voltage references such as the ADR433 produce low
output noise in the 0.1 Hz to 10 Hz region. Examples of some
recommended precision references for use as supply to the
AD5934 are shown in Table 19.
Because the supply current required by the AD5934 is
extremely low, the parts are ideal for low supply applications.
The ADR395 voltage reference is recommended in this case.
Table 19. List of Precision References for theAD5934
Part No.
ADR433B
ADR433A
ADR434B
ADR434A
ADR435B
ADR435A
ADR439B
ADR439A
Initial Accuracy (mV max)
Output Voltage (V)
Temp. Drift (ppm/°C max)
0.1 Hz to 10 Hz Noise (μV p-p typ)
1.4
4.0
1.5
5
2
6
3. 0
3. 0
4. 096
4. 096
5.0
5.0
4.5
4.5
3
10
3
10
3
10
3
3.75
3.75
6.25
6.25
8
8
7.5
7.5
2
5.4
10
Rev. 0 | Page 28 of 32
AD5934
LAYOUT AND CONFIGURATION
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, carefully consider the
power supply and ground return layout on the board. The
printed circuit board containing the AD5934 should have
separate analog and digital sections, each having its own area
of the board. If the AD5934 is in a system where other devices
require an AGND-to-DGND connection, the connection
should be made at one point only. This ground point should be
as close as possible to the AD5934.
The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects on the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.
The power supply to the AD5934 should be bypassed with
10 μF and 0.1 μF capacitors. The capacitors should be physically
as close as possible to the device, with the 0.1 μF capacitor
ideally right up against the device. The 10 μF capacitors are the
tantalum bead type. It is important that the 0.1 μF capacitor has
low effective series resistance (ESR) and effective series
inductance (ESI); common ceramic types of capacitors are
suitable. The 0.1 μF capacitor provides a low impedance path to
ground for high frequencies caused by transient currents due to
internal logic switching.
Rev. 0 | Page 29 of 32
AD5934
OUTLINE DIMENSIONS
6.50
6.20
5.90
16
9
8
5.60
5.30
5.00
8.20
7.80
7.40
1
PIN 1
1.85
1.75
1.65
2.00 MAX
0.25
0.09
8
4
0
0.95
0.75
0.55
0.38
0.22
0.05 MIN
SEATING
PLANE
0.65
BSC
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-150-AC
Figure 37. 16-Lead Shrink Small Outline Package [SSOP]
(RS-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD5934YRSZ1
AD5934YRSZ-REEL71
EVAL-AD5934EB
Temperature Range
Package Description
Package Option
RS-16
RS-16
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
16-Lead Shrink Small Outline Package (SSOP)
16-Lead Shrink Small Outline Package (SSOP)
Evaluation Board
1 Z = Pb-free part.
Rev. 0 | Page 30 of 32
AD5934
NOTES
Rev. 0 | Page 31 of 32
AD5934
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©
2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05325–0–6/05(0)
Rev. 0 | Page 32 of 32
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