AD620BRZ-REEL7 [ADI]
INSTRUMENTATION AMPLIFIER, 85uV OFFSET-MAX, 1MHz BAND WIDTH, PDSO8, MS-021-AA, SOIC-8;
| 型号： | AD620BRZ-REEL7 |
| 厂家： | 
ADI |
| 描述： | INSTRUMENTATION AMPLIFIER, 85uV OFFSET-MAX, 1MHz BAND WIDTH, PDSO8, MS-021-AA, SOIC-8 放大器 光电二极管 |
| 文件： | 总20页 (文件大小：410K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Cost Low Power
Instrumentation Amplifier
AD620
FEATURES
Easy to use
CONNECTION DIAGRAM
Gain set with one external resistor
(Gain range 1 to 10,000)
1
2
3
4
8
7
6
5
R
R
G
G
+V
–IN
+IN
S
Wide power supply range ( 2.3 V to 18 V)
Higher performance than 3 op amp IA designs
Available in 8-lead DIP and SOIC packaging
Low power, 1.3 mA max supply current
Excellent dc performance (B grade)
50 μV max, input offset voltage
0.6 μV/°C max, input offset drift
1.0 nA max, input bias current
100 dB min common-mode rejection ratio (G = 10)
Low noise
9 nV/√Hz @ 1 kHz, input voltage noise
0.28 μV p-p noise (0.1 Hz to 10 Hz)
Excellent ac specifications
120 kHz bandwidth (G = 100)
15 μs settling time to 0.01%
OUTPUT
REF
–V
S
AD620
TOP VIEW
Figure 1. 8-Lead PDIP (N), CERDIP (Q), and SOIC (R) Packages
PRODUCT DESCRIPTION
The AD620 is a low cost, high accuracy instrumentation
amplifier that requires only one external resistor to set gains of
1 to 10,000. Furthermore, the AD620 features 8-lead SOIC and
DIP packaging that is smaller than discrete designs and offers
lower power (only 1.3 mA max supply current), making it a
good fit for battery-powered, portable (or remote) applications.
The AD620, with its high accuracy of 40 ppm maximum
nonlinearity, low offset voltage of 50 μV max, and offset drift of
0.6 μV/°C max, is ideal for use in precision data acquisition
systems, such as weigh scales and transducer interfaces.
Furthermore, the low noise, low input bias current, and low power
of the AD620 make it well suited for medical applications, such
as ECG and noninvasive blood pressure monitors.
APPLICATIONS
Weigh scales
ECG and medical instrumentation
Transducer interface
Data acquisition systems
Industrial process controls
Battery-powered and portable equipment
The low input bias current of 1.0 nA max is made possible with
the use of Superϐeta processing in the input stage. The AD620
works well as a preamplifier due to its low input voltage noise of
9 nV/√Hz at 1 kHz, 0.28 μV p-p in the 0.1 Hz to 10 Hz band,
and 0.1 pA/√Hz input current noise. Also, the AD620 is well
suited for multiplexed applications with its settling time of 15 μs
to 0.01%, and its cost is low enough to enable designs with one
in-amp per channel.
Table 1. Next Generation Upgrades for AD620
30,000
Part
Comment
25,000
20,000
15,000
10,000
5,000
0
3 OP AMP
IN-AMP
AD8221
AD8222
AD8226
AD8220
AD8228
AD8295
AD8429
Better specs at lower price
Dual channel or differential out
Low power, wide input range
JFET input
Best gain accuracy
+2 precision op amps or differential out
Ultra low noise
(3 OP-07s)
AD620A
G
R
0
5
10
15
20
SUPPLY CURRENT (mA)
Figure 2. Three Op Amp IA Designs vs. AD620
Rev. H
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703© 2003–2011 Analog Devices, Inc. All rights reserved.
AD620
TABLE OF CONTENTS
Specifications .....................................................................................3
RF Interference............................................................................15
Common-Mode Rejection.........................................................16
Grounding....................................................................................16
Ground Returns for Input Bias Currents.................................17
AD620ACHIPS Information.........................................................18
Outline Dimensions........................................................................19
Ordering Guide ...........................................................................20
Absolute Maximum Ratings ............................................................5
ESD Caution ..................................................................................5
Typical Performance Characteristics..............................................6
Theory of Operation.......................................................................12
Gain Selection..............................................................................15
Input and Output Offset Voltage ..............................................15
Reference Terminal.....................................................................15
Input Protection ..........................................................................15
REVISION HISTORY
7/11—Rev. G to Rev. H
Changes to Input Protection section ............................................15
Deleted Figure 9 ..............................................................................15
Changes to RF Interference section..............................................15
Edit to Ground Returns for Input Bias Currents section...........17
Added AD620CHIPS to Ordering Guide....................................19
Deleted Figure 3.................................................................................1
Added Table 1 ....................................................................................1
Moved Figure 2..................................................................................1
Added ESD Input Diodes to Simplified Schematic ....................12
Changes to Input Protection Section............................................15
Added Figure 41; Renumbered Sequentially...............................15
Changes to AD620ACHIPS Information Section ......................18
Updated Ordering Guide ...............................................................20
7/03—Data Sheet Changed from Rev. E to Rev. F
Edit to FEATURES............................................................................1
Changes to SPECIFICATIONS .......................................................2
Removed AD620CHIPS from ORDERING GUIDE ...................4
Removed METALLIZATION PHOTOGRAPH...........................4
Replaced TPCs 1–3...........................................................................5
Replaced TPC 12...............................................................................6
Replaced TPC 30...............................................................................9
Replaced TPCs 31 and 32...............................................................10
Replaced Figure 4............................................................................10
Changes to Table I...........................................................................11
Changes to Figures 6 and 7............................................................12
Changes to Figure 8 ........................................................................13
Edited INPUT PROTECTION section........................................13
Added new Figure 9........................................................................13
Changes to RF INTERFACE section ............................................14
12/04—Rev. F to Rev. G
Updated Format.................................................................. Universal
Change to Features............................................................................1
Change to Product Description.......................................................1
Changes to Specifications.................................................................3
Added Metallization Photograph....................................................4
Replaced Figure 4-Figure 6 ..............................................................6
Replaced Figure 15............................................................................7
Replaced Figure 33..........................................................................10
Replaced Figure 34 and Figure 35.................................................10
Replaced Figure 37..........................................................................10
Changes to Table 3 ..........................................................................13
Changes to Figure 41 and Figure 42 .............................................14
Changes to Figure 43 ......................................................................15
Change to Figure 44........................................................................17
Edit to GROUND RETURNS FOR INPUT BIAS CURRENTS
section...............................................................................................15
Updated OUTLINE DIMENSIONS.............................................16
Rev. H | Page 2 of 20
AD620
SPECIFICATIONS
Typical @ 25°C, VS = ±±5 V, and RL = 2 kΩ, unless otherwise noted.
Table 2.
AD620S1
AD620A
AD620B
Parameter
GAIN
Gain Range
Gain Error2
G = 1
Conditions Min
G = 1 + (49.4 kΩ/RG)
1
Typ Max
Min
Typ Max
Min
Typ Max
Unit
10,000
1
10,000
1
10,000
VOUT
= 10 V
0.03 0.10
0.15 0.30
0.15 0.30
0.40 0.70
0.01 0.02
0.10 0.15
0.10 0.15
0.35 0.50
0.03 0.10
0.15 0.30
0.15 0.30
0.40 0.70
%
%
%
%
G = 10
G = 100
G = 1000
Nonlinearity
G = 1–1000
G = 1–100
Gain vs. Temperature
VOUT = −10 V to +10 V
RL = 10 kΩ
RL = 2 kΩ
10
10
40
95
10
10
40
95
10
10
40
95
ppm
ppm
G = 1
Gain >12
10
−50
10
−50
10
−50
ppm/°C
ppm/°C
VOLTAGE OFFSET
Input Offset, VOSI
(Total RTI Error = VOSI + VOSO/G)
VS = 5 V
to 15 V
30
125
185
1.0
15
50
85
0.6
30
125
225
1.0
μV
Overtemperature
Average TC
VS = 5 V
to 15 V
μV
VS = 5 V
to 15 V
0.3
0.1
0.3
μV/°C
Output Offset, VOSO
VS = 15 V
VS = 5 V
VS = 5 V
to 15 V
VS = 5 V
to 15 V
400
1000
1500
2000
200 500
750
400
1000
1500
2000
μV
μV
μV
Overtemperature
Average TC
1000
5.0
15
2.5
7.0
5.0
15
μV/°C
Offset Referred to the
Input vs. Supply (PSR)
VS = 2.3 V
to 18 V
G = 1
G = 10
G = 100
G = 1000
80
95
110
110
100
120
140
140
80
100
120
140
140
80
95
110
110
100
120
140
140
dB
dB
dB
dB
100
120
120
INPUT CURRENT
Input Bias Current
Overtemperature
Average TC
Input Offset Current
Overtemperature
Average TC
0.5
2.0
2.5
0.5
1.0
1.5
0.5
2
4
nA
nA
pA/°C
nA
nA
3.0
0.3
3.0
0.3
8.0
0.3
1.0
1.5
0.5
0.75
1.0
2.0
1.5
1.5
8.0
pA/°C
INPUT
Input Impedance
Differential
Common-Mode
Input Voltage Range3
10||2
10||2
10||2
10||2
10||2
10||2
GΩ_pF
GΩ_pF
V
VS = 2.3 V −VS + 1.9
to 5 V
+VS − 1.2
−VS + 1.9
+VS − 1.2
−VS + 1.9
+VS − 1.2
Overtemperature
−VS + 2.1
−VS + 1.9
+VS − 1.3
+VS − 1.4
−VS + 2.1
−VS + 1.9
+VS − 1.3
+VS − 1.4
−VS + 2.1
−VS + 1.9
+VS − 1.3
+VS − 1.4
V
V
VS = 5 V
to 18 V
Overtemperature
−VS + 2.1
+VS − 1.4
−VS + 2.1
+VS + 2.1
−VS + 2.3
+VS − 1.4
V
Rev. H | Page 3 of 20
AD620
AD620S1
AD620A
AD620B
Parameter
Conditions
Min
Typ Max
Min
Typ Max
Min
Typ Max
Unit
Common-Mode Rejection
Ratio DC to 60 Hz with
1 kΩ Source Imbalance VCM = 0 V to 10 V
G = 1
73
93
110
110
90
80
90
73
93
110
110
90
dB
dB
dB
dB
G = 10
G = 100
G = 1000
110
130
130
100
120
120
110
130
130
110
130
130
OUTPUT
Output Swing
RL = 10 kΩ
VS = 2.3 V −VS +
+VS − 1.2
−VS + 1.1
+VS − 1.2
−VS + 1.1
+VS − 1.2
V
to 5 V
1.1
Overtemperature
−VS + 1.4
−VS + 1.2
+VS − 1.3
+VS − 1.4
−VS + 1.4
−VS + 1.2
+VS − 1.3
+VS − 1.4
−VS + 1.6
−VS + 1.2
+VS − 1.3
+VS − 1.4
V
V
VS = 5 V
to 18 V
Overtemperature
Short Circuit Current
DYNAMIC RESPONSE
−VS + 1.6
+VS – 1.5
−VS + 1.6
+VS – 1.5
–VS + 2.3
+VS – 1.5
V
mA
18
18
18
Small Signal –3 dB Bandwidth
G = 1
G = 10
G = 100
G = 1000
Slew Rate
1000
800
120
12
1000
800
120
12
1000
800
120
12
kHz
kHz
kHz
kHz
V/μs
0.75
1.2
0.75
1.2
0.75
1.2
Settling Time to 0.01%
G = 1–100
G = 1000
10 V Step
15
150
15
150
15
150
μs
μs
NOISE
Total RTI Noise = (e2ni ) + (eno /G)2
Voltage Noise, 1 kHz
Input, Voltage Noise, eni
Output, Voltage Noise, eno
RTI, 0.1 Hz to 10 Hz
G = 1
9
72
13
100
9
72
13
100
9
72
13
100
nV/√Hz
nV/√Hz
3.0
0.55
0.28
100
10
3.0
6.0
3.0
6.0
μV p-p
μV p-p
μV p-p
fA/√Hz
pA p-p
G = 10
0.55 0.8
0.28 0.4
100
0.55 0.8
0.28 0.4
100
G = 100–1000
Current Noise
0.1 Hz to 10 Hz
REFERENCE INPUT
RIN
f = 1 kHz
10
10
20
50
20
50
20
50
kΩ
μA
V
IIN
VIN+, VREF = 0
60
+VS − 1.6
60
+VS − 1.6
60
+VS − 1.6
Voltage Range
Gain to Output
POWER SUPPLY
Operating Range4
Quiescent Current
−VS + 1.6
0.0001
−VS + 1.6
−VS + 1.6
1
1
0.0001
1
0.0001
2.3
18
2.3
18
2.3
18
V
VS = 2.3 V
to 18 V
0.9
1.1
1.3
0.9
1.1
1.3
0.9
1.1
1.3
mA
Overtemperature
1.6
1.6
1.6
mA
°C
TEMPERATURE RANGE
For Specified Performance
−40 to +85
−40 to +85
−55 to +125
1 See Analog Devices military data sheet for 883B tested specifications.
2 Does not include effects of external resistor RG.
3 One input grounded. G = 1.
4 This is defined as the same supply range that is used to specify PSR.
Rev. H | Page 4 of 20
AD620
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Stresses above those listed under Absolute Maximum Ratings
Rating
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other condition s above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Supply Voltage
18 V
650 mW
VS
Internal Power Dissipation1
Input Voltage (Common-Mode)
Differential Input Voltage
Output Short-Circuit Duration
Storage Temperature Range (Q)
Storage Temperature Range (N, R)
Operating Temperature Range
AD620 (A, B)
25 V
Indefinite
−65°C to +150°C
−65°C to +125°C
−40°C to +85°C
−55°C to +125°C
ESD CAUTION
AD620 (S)
Lead Temperature Range
(Soldering 10 seconds)
300°C
1 Specification is for device in free air:
8-Lead Plastic Package: θJA = 95°C
8-Lead CERDIP Package: θJA = 110°C
8-Lead SOIC Package: θJA = 155°C
Rev. H | Page 5 of 20
AD620
TYPICAL PERFORMANCE CHARACTERISTICS
(@ 25°C, VS = 15 V, RL = 2 kΩ, unless otherwise noted.)
2.0
1.5
1.0
50
SAMPLE SIZE = 360
40
30
+I
B
–I
B
0.5
0
20
10
–0.5
–1.0
–1.5
–2.0
0
–80
–40
0
40
80
–75
–25
25
75
125
175
TEMPERATURE (°C)
INPUT OFFSET VOLTAGE (
μ
V)
Figure 6. Input Bias Current vs. Temperature
Figure 3. Typical Distribution of Input Offset Voltage
2.0
1.5
50
40
SAMPLE SIZE = 850
30
20
10
0
1.0
0.5
0
0
–1200
–600
0
600
1200
1
2
3
4
5
WARM-UP TIME (Minutes)
INPUT BIAS CURRENT (pA)
Figure 7. Change in Input Offset Voltage vs. Warm-Up Time
Figure 4. Typical Distribution of Input Bias Current
1000
50
40
30
SAMPLE SIZE = 850
GAIN = 1
100
GAIN = 10
20
10
10
GAIN = 100, 1,000
GAIN = 1000
BW LIMIT
1
0
–400
–200
0
200
400
1
10
100
1k
10k
100k
FREQUENCY (Hz)
INPUT OFFSET CURRENT (pA)
Figure 5. Typical Distribution of Input Offset Current
Figure 8. Voltage Noise Spectral Density vs. Frequency (G = 1−1000)
Rev. H | Page 6 of 20
AD620
1000
100
10
1
1000
10
100
FREQUENCY (Hz)
Figure 9. Current Noise Spectral Density vs. Frequency
Figure 12. 0.1 Hz to 10 Hz Current Noise, 5 pA/Div
100,000
10,000
1000
FET INPUT
IN-AMP
AD620A
100
10
TIME (1 SEC/DIV)
1k
10k
100k
1M
10M
SOURCE RESISTANCE (Ω)
Figure 13. Total Drift vs. Source Resistance
Figure 10. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1)
160
140
120
100
80
G = 1000
G = 100
G = 10
G = 1
60
40
20
0
TIME (1 SEC/DIV)
0.1
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 11. 0.1 Hz to 10 Hz RTI Voltage Noise (G = 1000)
Figure 14. Typical CMR vs. Frequency, RTI, Zero to 1 kΩ Source Imbalance
Rev. H | Page 7 of 20
AD620
35
180
G = 10, 100, 1000
160
30
25
140
120
G = 1000
G = 1
20
15
100
80
G = 100
G = 10
G = 1
10
5
60
40
G = 1000
G = 100
0
20
0.1
1M
1k
10k
100k
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 15. Positive PSR vs. Frequency, RTI (G = 1−1000)
Figure 18. Large Signal Frequency Response
180
160
+V –0.0
S
–0.5
–1.0
–1.5
140
120
100
80
G = 1000
+1.5
+1.0
+0.5
G = 100
G = 10
G = 1
60
40
20
–V +0.0
S
0
5
10
15
20
0.1
1
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
SUPPLY VOLTAGE
± Volts
Figure 16. Negative PSR vs. Frequency, RTI (G = 1−1000)
Figure 19. Input Voltage Range vs. Supply Voltage, G = 1
1000
+V –0.0
S
–0.5
–1.0
–1.5
R
= 10kΩ
L
100
10
1
R
= 2kΩ
L
+1.5
+1.0
+0.5
R
= 2kΩ
L
R
= 10kΩ
L
–V +0.0
0.1
100
S
5
10
15
20
1k
10k
100k
1M
10M
0
FREQUENCY (Hz)
SUPPLY VOLTAGE ± Volts
Figure 17. Gain vs. Frequency
Figure 20. Output Voltage Swing vs. Supply Voltage, G = 10
Rev. H | Page 8 of 20
AD620
30
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
= ±15V
S
G = 10
20
10
0
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0
100
1k
10k
LOAD RESISTANCE (Ω)
Figure 21. Output Voltage Swing vs. Load Resistance
Figure 24. Large Signal Response and Settling Time, G = 10 (0.5 mV = 0.01%)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 25. Small Signal Response, G = 10, RL = 2 kΩ, CL = 100 pF
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 22. Large Signal Pulse Response and Settling Time
G = 1 (0.5 mV = 0.01%)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 23. Small Signal Response, G = 1, RL = 2 kΩ, CL = 100 pF
Figure 26. Large Signal Response and Settling Time, G = 100 (0.5 mV = 0.01%)
Rev. H | Page 9 of 20
AD620
20
15
10
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TO 0.01%
TO 0.1%
5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
0
0
5
10
OUTPUT STEP SIZE (V)
15
20
Figure 27. Small Signal Pulse Response, G = 100, RL = 2 kΩ, CL = 100 pF
Figure 30. Settling Time vs. Step Size (G = 1)
1000
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
10
1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1
10
100
1000
GAIN
Figure 28. Large Signal Response and Settling Time,
G = 1000 (0.5 mV = 0.01% )
Figure 31. Settling Time to 0.01% vs. Gain, for a 10 V Step
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 32. Gain Nonlinearity, G = 1, RL = 10 kΩ (10 μV = 1 ppm)
Figure 29. Small Signal Pulse Response, G = 1000, RL = 2 kΩ, CL = 100 pF
Rev. H | Page 10 of 20
AD620
1k
10T
Ω
10k
Ω
10kΩ*
INPUT
10V p-p
100k
Ω
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
OUT
+V
7
S
2
11k
Ω
1k
Ω
100
Ω
1
G = 1000
G = 1
AD620
6
G = 10
G = 100
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
49.9
Ω
499
Ω
5.49kΩ
5
8
3
4
–V
S
*ALL RESISTORS 1% TOLERANCE
Figure 33. Gain Nonlinearity, G = 100, RL = 10 kΩ
(100 μV = 10 ppm)
Figure 35. Settling Time Test Circuit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 34. Gain Nonlinearity, G = 1000, RL = 10 kΩ
(1 mV = 100 ppm)
Rev. H | Page 11 of 20
AD620
THEORY OF OPERATION
The input transistors Q1 and Q2 provide a single differential-
pair bipolar input for high precision (Figure 36), yet offer 10×
lower input bias current thanks to Superϐeta processing.
+V
S
V
B
I2
I1
20µA
20µA
Feedback through the Q1-A1-R1 loop and the Q2-A2-R2 loop
maintains constant collector current of the input devices Q1
and Q2, thereby impressing the input voltage across the external
gain setting resistor RG. This creates a differential gain from the
inputs to the A1/A2 outputs given by G = (R1 + R2)/RG + 1. The
unity-gain subtractor, A3, removes any common-mode signal,
yielding a single-ended output referred to the REF pin potential.
A1
A2
10kΩ
C2
C1
10kΩ
10kΩ
OUTPUT
REF
A3
10kΩ
+V
+V
S
S
The value of RG also determines the transconductance of the
preamp stage. As RG is reduced for larger gains, the
R1
R2
Q1
Q2
+IN
– IN
R3
400Ω
R4
400Ω
R
transconductance increases asymptotically to that of the input
transistors. This has three important advantages: (a) Open-loop
gain is boosted for increasing programmed gain, thus reducing
gain related errors. (b) The gain-bandwidth product
(determined by C1 and C2 and the preamp transconductance)
increases with programmed gain, thus optimizing frequency
response. (c) The input voltage noise is reduced to a value of
9 nV/√Hz, determined mainly by the collector current and base
resistance of the input devices.
G
GAIN
SENSE
GAIN
SENSE
–V
S
Figure 36. Simplified Schematic of AD620
The AD620 is a monolithic instrumentation amplifier based on
a modification of the classic three op amp approach. Absolute
value trimming allows the user to program gain accurately
(to 0.15% at G = 100) with only one resistor. Monolithic
construction and laser wafer trimming allow the tight matching
and tracking of circuit components, thus ensuring the high level
of performance inherent in this circuit.
The internal gain resistors, R1 and R2, are trimmed to an
absolute value of 24.7 kΩ, allowing the gain to be programmed
accurately with a single external resistor.
The gain equation is then
49.4kΩ
RG
G =
+1
49.4kΩ
G−1
RG =
Make vs. Buy: a Typical Bridge Application Error Budget
The AD620 offers improved performance over “homebrew”
three op amp IA designs, along with smaller size, fewer
components, and 10× lower supply current. In the typical
application, shown in Figure 37, a gain of 100 is required to
amplify a bridge output of 20 mV full-scale over the industrial
temperature range of −40°C to +85°C. Table 4 shows how to
calculate the effect various error sources have on circuit
accuracy.
Rev. H | Page 12 of 20
AD620
Note that for the homebrew circuit, the OP07 specifications for
input voltage offset and noise have been multiplied by √2. This
is because a three op amp type in-amp has two op amps at its
inputs, both contributing to the overall input error.
Regardless of the system in which it is being used, the AD620
provides greater accuracy at low power and price. In simple
systems, absolute accuracy and drift errors are by far the most
significant contributors to error. In more complex systems
with an intelligent processor, an autogain/autozero cycle
removes all absolute accuracy and drift errors, leaving only the
resolution errors of gain, nonlinearity, and noise, thus allowing
full 14-bit accuracy.
10V
10kΩ*
10kΩ*
OP07D
R
G
AD620A
499
Ω
R = 350
R = 350
Ω
Ω
R = 350Ω
10k
Ω
Ω
**
**
REFERENCE
100Ω**
OP07D
10k
R = 350
Ω
AD620A MONOLITHIC
INSTRUMENTATION
AMPLIFIER, G = 100
OP07D
10kΩ*
10kΩ*
SUPPLY CURRENT = 1.3mA MAX
"HOMEBREW" IN-AMP, G = 100
*0.02% RESISTOR MATCH, 3ppm/
**DISCRETE 1% RESISTOR, 100ppm/
SUPPLY CURRENT = 15mA MAX
°
C TRACKING
°
C TRACKING
PRECISION BRIDGE TRANSDUCER
Figure 37. Make vs. Buy
Table 4. Make vs. Buy Error Budget
Error, ppm of Full Scale
Error Source
AD620 Circuit Calculation
“Homebrew” Circuit Calculation
AD620
Homebrew
ABSOLUTE ACCURACY at TA = 25°C
Input Offset Voltage, μV
Output Offset Voltage, μV
Input Offset Current, nA
CMR, dB
125 μV/20 mV
1000 μV/100 mV/20 mV
2 nA ×350 Ω/20 mV
(150 μV × √2)/20 mV
((150 μV × 2)/100)/20 mV
(6 nA ×350 Ω)/20 mV
6,250
500
18
10,607
150
53
500
110 dB(3.16 ppm) ×5 V/20 mV
(0.02% Match × 5 V)/20 mV/100
791
Total Absolute Error
7,559
11,310
DRIFT TO 85°C
Gain Drift, ppm/°C
Input Offset Voltage Drift, μV/°C
Output Offset Voltage Drift, μV/°C
(50 ppm + 10 ppm) ×60°C
1 μV/°C × 60°C/20 mV
15 μV/°C × 60°C/100 mV/20 mV
100 ppm/°C Track × 60°C
(2.5 μV/°C × √2 × 60°C)/20 mV
(2.5 μV/°C × 2 × 60°C)/100 mV/20 mV
3,600
3,000
450
6,000
10,607
150
Total Drift Error
7,050
16,757
RESOLUTION
Gain Nonlinearity, ppm of Full Scale
Typ 0.1 Hz to 10 Hz Voltage Noise, μV p-p
40 ppm
0.28 μV p-p/20 mV
40 ppm
40
14
54
40
27
67
(0.38 μV p-p × √2)/20 mV
Total Resolution Error
Grand Total Error
14,663
28,134
G = 100, VS = 15 V.
(All errors are min/max and referred to input.)
Rev. H | Page 13 of 20
AD620
5V
20k
Ω
Ω
7
3
8
3k
Ω
3kΩ
REF
IN
G = 100
499
6
AD620B
DIGITAL
DATA
OUTPUT
Ω
3k
Ω
3kΩ
5
10k
ADC
1
2
4
AGND
AD705
20k
Ω
0.6mA
MAX
1.7mA
0.10mA
1.3mA
MAX
Figure 38. A Pressure Monitor Circuit that Operates on a 5 V Single Supply
Pressure Measurement
Medical ECG
Although useful in many bridge applications, such as weigh
scales, the AD620 is especially suitable for higher resistance
pressure sensors powered at lower voltages where small size and
low power become more significant.
The low current noise of the AD620 allows its use in ECG
monitors (Figure 39) where high source resistances of 1 MΩ or
higher are not uncommon. The AD620’s low power, low supply
voltage requirements, and space-saving 8-lead mini-DIP and
SOIC package offerings make it an excellent choice for battery-
powered data recorders.
Figure 38 shows a 3 kΩ pressure transducer bridge powered
from 5 V. In such a circuit, the bridge consumes only 1.7 mA.
Adding the AD620 and a buffered voltage divider allows the
signal to be conditioned for only 3.8 mA of total supply current.
Furthermore, the low bias currents and low current noise,
coupled with the low voltage noise of the AD620, improve the
dynamic range for better performance.
Small size and low cost make the AD620 especially attractive for
voltage output pressure transducers. Since it delivers low noise
and drift, it also serves applications such as diagnostic
noninvasive blood pressure measurement.
The value of capacitor C1 is chosen to maintain stability of
the right leg drive loop. Proper safeguards, such as isolation,
must be added to this circuit to protect the patient from
possible harm.
+3V
PATIENT/CIRCUIT
PROTECTION/ISOLATION
R1
10k
R3
0.03Hz
24.9k
Ω
C1
Ω
R
8.25k
HIGH-
PASS
OUTPUT
1V/mV
G
AD620A
G = 143
Ω
R2
24.9k
FILTER
R4
1M
G = 7
Ω
Ω
OUTPUT
AMPLIFIER
AD705J
–3V
Figure 39. A Medical ECG Monitor Circuit
Rev. H | Page 14 of 20
AD620
Precision V-I Converter
INPUT AND OUTPUT OFFSET VOLTAGE
The AD620, along with another op amp and two resistors,
makes a precision current source (Figure 40). The op amp
buffers the reference terminal to maintain good CMR. The
output voltage, VX, of the AD620 appears across R1, which
converts it to a current. This current, less only the input bias
current of the op amp, then flows out to the load.
The low errors of the AD620 are attributed to two sources,
input and output errors. The output error is divided by G when
referred to the input. In practice, the input errors dominate at
high gains, and the output errors dominate at low gains. The
total VOS for a given gain is calculated as
Total Error RTI = input error + (output error/G)
Total Error RTO = (input error × G) + output error
REFERENCE TERMINAL
+V
S
7
V
3
8
IN+
+ V
X
–
R
AD620
6
G
The reference terminal potential defines the zero output voltage
and is especially useful when the load does not share a precise
ground with the rest of the system. It provides a direct means of
injecting a precise offset to the output, with an allowable range
of 2 V within the supply voltages. Parasitic resistance should be
kept to a minimum for optimum CMR.
R1
1
2
5
V
IN–
4
I
L
–V
S
AD705
[(V ) – (V )] G
IN+ IN–
V
x
I =
=
L
R1
R1
LOAD
INPUT PROTECTION
The AD620 safely withstands an input current of 60 mA for
several hours at room temperature. This is true for all gains and
power on and off, which is useful if the signal source and
amplifier are powered separately. For longer time periods, the
input current should not exceed 6 mA.
Figure 40. Precision Voltage-to-Current Converter (Operates on 1.8 mA, 3 V)
GAIN SELECTION
The AD620 gain is resistor-programmed by RG, or more
precisely, by whatever impedance appears between Pins 1 and 8.
The AD620 is designed to offer accurate gains using 0.1% to 1%
resistors. Table 5 shows required values of RG for various gains.
Note that for G = 1, the RG pins are unconnected (RG = ∞). For
any arbitrary gain, RG can be calculated by using the formula:
For input voltages beyond the supplies, a protection resistor
should be placed in series with each input to limit the current to
6 mA. These can be the same resistors as those used in the RFI
filter. High values of resistance can impact the noise and AC
CMRR performance of the system. Low leakage diodes (such as
the BAV199) can be placed at the inputs to reduce the required
protection resistance.
49.4kΩ
RG =
G −1
+SUPPLY
To minimize gain error, avoid high parasitic resistance in series
with RG; to minimize gain drift, RG should have a low TC—less
than 10 ppm/°C—for the best performance.
R
R
+IN
–IN
Table 5. Required Values of Gain Resistors
V
OUT
AD620
1% Std Table
Value of RG(Ω)
Calculated 0.1% Std Table
Calculated
Gain
Gain
1.990
4.984
9.998
19.93
50.40
100.0
199.4
495.0
991.0
Value of RG(Ω )
49.3 k
12.4 k
5.49 k
2.61 k
1.01 k
499
REF
49.9 k
12.4 k
5.49 k
2.61 k
1.00 k
499
2.002
4.984
9.998
19.93
49.91
100.0
199.4
501.0
1,003.0
–SUPPLY
Figure 41. Diode Protection for Voltages Beyond Supply
249
249
RF INTERFERENCE
100
98.8
All instrumentation amplifiers rectify small out of band signals.
The disturbance may appear as a small dc voltage offset. High
frequency signals can be filtered with a low pass R-C network
placed at the input of the instrumentation amplifier. Figure 42
demonstrates such a configuration. The filter limits the input
49.9
49.3
Rev. H | Page 15 of 20
AD620
signal according to the following relationship:
1
+V
S
– INPUT
FilterFreqDIFF
=
AD648
100
100
Ω
Ω
2πR(2CD +CC )
AD620
1
V
OUT
R
G
FilterFreqCM
=
2πRCC
–V
S
REFERENCE
where CD ≥10CC.
+ INPUT
–V
S
CD affects the difference signal. CC affects the common-mode
signal. Any mismatch in R × CC degrades the AD620 CMRR. To
avoid inadvertently reducing CMRR-bandwidth performance,
make sure that CC is at least one magnitude smaller than CD.
The effect of mismatched CCs is reduced with a larger CD:CC
ratio.
Figure 43. Differential Shield Driver
+V
S
– INPUT
+15V
R
G
2
100Ω
AD620
V
0.1μ F
10μ F
AD548
OUT
R
G
2
REFERENCE
C
C
R
R
+IN
+
+ INPUT
V
OUT
–V
S
C
C
499Ω
–IN
AD620
D
C
–
REF
Figure 44. Common-Mode Shield Driver
GROUNDING
0.1μ F
10μ F
Since the AD620 output voltage is developed with respect to the
potential on the reference terminal, it can solve many
grounding problems by simply tying the REF pin to the
appropriate “local ground.”
–15V
Figure 42. Circuit to Attenuate RF Interference
COMMON-MODE REJECTION
To isolate low level analog signals from a noisy digital
environment, many data-acquisition components have separate
analog and digital ground pins (Figure 45). It would be
convenient to use a single ground line; however, current
through ground wires and PC runs of the circuit card can cause
hundreds of millivolts of error. Therefore, separate ground
returns should be provided to minimize the current flow from
the sensitive points to the system ground. These ground returns
must be tied together at some point, usually best at the ADC
package shown in Figure 45.
Instrumentation amplifiers, such as the AD620, offer high
CMR, which is a measure of the change in output voltage when
both inputs are changed by equal amounts. These specifications
are usually given for a full-range input voltage change and a
specified source imbalance.
For optimal CMR, the reference terminal should be tied to a
low impedance point, and differences in capacitance and
resistance should be kept to a minimum between the two
inputs. In many applications, shielded cables are used to
minimize noise; for best CMR over frequency, the shield
should be properly driven. Figure 43 and Figure 44 show active
data guards that are configured to improve ac common-mode
rejections by “bootstrapping” the capacitances of input cable
shields, thus minimizing the capacitance mismatch between the
inputs.
ANALOG P.S.
+15V –15V
DIGITAL P.S.
+5V
C
C
0.1μF
0.1μF
1μF
1
μ
F
1μ
F
+
AD620
DIGITAL
DATA
OUTPUT
AD585
S/H
AD574A
ADC
Figure 45. Basic Grounding Practice
Rev. H | Page 16 of 20
AD620
+V
S
GROUND RETURNS FOR INPUT BIAS CURRENTS
– INPUT
Input bias currents are those currents necessary to bias the
input transistors of an amplifier. There must be a direct return
path for these currents. Therefore, when amplifying “floating”
input sources, such as transformers or ac-coupled sources, there
must be a dc path from each input to ground, as shown in
Figure 46, Figure 47, and Figure 48. Refer to A Designer’s Guide
to Instrumentation Amplifiers (free from Analog Devices) for
more information regarding in-amp applications.
R
V
G
AD620
OUT
LOAD
REFERENCE
+ INPUT
–V
S
TO POWER
SUPPLY
GROUND
+V
S
– INPUT
Figure 47. Ground Returns for Bias Currents with Thermocouple Inputs
AD620
V
R
G
OUT
+V
S
– INPUT
LOAD
+ INPUT
REFERENCE
–V
S
V
R
G
AD620
OUT
TO POWER
SUPPLY
GROUND
LOAD
+ INPUT
REFERENCE
Figure 46. Ground Returns for Bias Currents with Transformer-Coupled Inputs
–V
S
100k
Ω
100kΩ
TO POWER
SUPPLY
GROUND
Figure 48. Ground Returns for Bias Currents with AC-Coupled Inputs
Rev. H | Page 17 of 20
AD620
AD620ACHIPS INFORMATION
Die size: 1803 μm × 3175 μm
Die thickness: 483 μm
Bond Pad Metal: 1% Copper Doped Aluminum
To minimize gain errors introduced by the bond wires, use Kelvin connections between the chip and the gain resistor, RG, by connecting
Pad 1A and Pad 1B in parallel to one end of RG and Pad 8A and Pad 8B in parallel to the other end of RG. For unity gain applications
where RG is not required, Pad 1A and Pad 1B must be bonded together as well as the Pad 8A and Pad 8B.
1A
8A
LOGO
1B
2
8B
7
3
6
4
5
Figure 49. Bond Pad Diagram
Table 6. Bond Pad Information
Pad Coordinates1
Y (μm)
+1424
+628
Pad No.
Mnemonic
X (μm)
−623
−789
−790
−790
−788
+570
+693
+693
+505
+693
1A
1B
2
3
4
5
6
7
8A
8B
RG
RG
−IN
+IN
−VS
REF
OUTPUT
+VS
RG
+453
−294
−1419
−1429
−1254
+139
+1423
+372
RG
1 The pad coordinates indicate the center of each pad, referenced to the center of the die. The die orientation is indicated by the logo, as shown in Figure 49.
Rev. H | Page 18 of 20
AD620
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
8
1
5
4
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
6.20 (0.2441)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
45°
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
1.75 (0.0688)
1.35 (0.0532)
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.25 (0.0098)
0.10 (0.0040)
8°
0°
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 52. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Figure 50. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body (N-8).
Dimensions shown in millimeters and (inches)
Dimensions shown in inches and (millimeters)
0.005 (0.13)
MIN
0.055 (1.40)
MAX
8
5
0.310 (7.87)
0.220 (5.59)
1
4
0.100 (2.54) BSC
0.405 (10.29) MAX
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
15°
0°
0.070 (1.78)
0.030 (0.76)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 51. 8-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-8)
Dimensions shown in inches and (millimeters)
Rev. H | Page 19 of 20
AD620
ORDERING GUIDE
Model1
AD620AN
AD620ANZ
AD620BN
AD620BNZ
AD620AR
AD620ARZ
AD620AR-REEL
AD620ARZ-REEL
AD620AR-REEL7
AD620ARZ-REEL7
AD620BR
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−55°C to +125°C
Package Description
8-Lead PDIP
8-Lead PDIP
8-Lead PDIP
8-Lead PDIP
Package Option
N-8
N-8
N-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead SOIC_N
AD620BRZ
8-Lead SOIC_N
AD620BR-REEL
AD620BRZ-RL
AD620BR-REEL7
AD620BRZ-R7
AD620ACHIPS
AD620SQ/883B
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 13" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
8-Lead SOIC_N, 7" Tape and Reel
Die Form
8-Lead CERDIP
Q-8
1 Z = RoHS Compliant Part.
© 2003–2011 Analog Devices, Inc. All rights reserved. Trademarks
and registered trademarks are the property of their respective owners.
C00775–0–7/11(H)
Rev. H | Page 20 of 20
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Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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