AD6439-2BS [ADI]
IC SPECIALTY TELECOM CIRCUIT, PQFP128, PLASTIC, MQFP-128, Telecom IC:Other;
| 型号： | AD6439-2BS |
| 厂家： | 
ADI |
| 描述： | IC SPECIALTY TELECOM CIRCUIT, PQFP128, PLASTIC, MQFP-128, Telecom IC:Other 电信 电信集成电路 |
| 文件： | 总12页 (文件大小：113K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Discrete Multitone (DMT) Coprocessor
for ADSL Chipsets
a
AD6439-2
FEATURES
GENERAL DESCRIPTION
Component in Analog Devices’ AD20msp918 ADSL
Chipset
Designed to ANSI T1.413 Issue 2/ETSI TR238/ITU
G.992.1 and G.992.2
Higher Performance
Improved Data Rates or Longer Reach
Suitable for CO (Central Office) or Residence (ATU-R
and ATU-C)
Performs All DMT Functions and Operations
Trellis Coding
The AD6439-2 Discrete Multitone Coprocessor is part of
Analog Devices’ ADSL solution: a series of flexible, standards-
based chipsets for creating high performance ADSL and SDSL
modems that implement a superset of standard Category 2
functionality. See the AD6439-2 Functional Block Diagram below.
A high-performance alternative to the AD6436 DMT Copro-
cessor, the AD6439-2 meets the functionality requirements of
ANSI T1.413 Category 2 (Trellis Coding and Echo Cancella-
tion), but is considerably more versatile. It implements both
transmit and receive paths (Trellis Coding/Decoding, IFFT/FFT,
filtering, and Echo Cancellation). Symmetric transforms allow
flexible allocation of upstream and downstream bandwidths,
including symmetric data rates. Improved digital filters exceed the
requirements of T1.413 and deliver strict spectral masks
(e.g., for VDSL compatibility).
Echo Cancellation
Symmetric Transforms (512 Point)
Flexible Allocation of Tones Upstream/Downstream
Supports Symmetric Services (SDSL)
Increased Upstream (e.g., 1 Mbps)
Supports ADSL Over ISDN (Shifted U/S, Program-
mable Pilot Tone)
Strict Filters for Spectral Compatibility
128-Lead MQFP
–40؇C to +85؇C, 3.3 V Operation, 1.1 W
FUNCTIONAL BLOCK DIAGRAM
DIGITAL FILTER
AD6439-2
Tx PATH
FILTERS
IFFT
16
16
512 PT
Tx SERIAL
Rx SERIAL
TRELLIS
DAC
ADC
EC
ENCODE/
DECODE
FFT
512 PT
Rx PATH
FILTERS
CONTROL LOGIC
DSP PORT
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
AD6439-2–SPECIFICATIONS
Parameter
Value
Comments
Transmit DAC Port—Data Width
Transmit DAC Port—Rate
Receive ADC Port—Data Width
Receive ADC Port—Rate
Downstream FFT/IFFT
Upstream FFT/IFFT
Bits/Carrier (Max)
16 Bit
17.664 MHz
16 Bit
8.832 MHz
512 Points
512 Points
15
At Either CO or RT
At Either CO or RT
256 Tones
256 Tones
Interface to AD6438-2
Serial 35.328 MHz
Both Transmit and Receive
Power Supply
VDD
3.0 V to 3.6 V
PDISS
Temperature Range
< 1.5 W Max at 3.6 V
–40°C to +85°C
Specifications subject to change without notice.
ELECTRICAL SPECIFICATIONS
Parameter
Typ Value
Comments
VOH
VOL
VIH
VIL
IIH
VDD – 0.4 V dc
0.4 V dc
2.0 V dc
1.0 V dc
500 nA
At IOH = –0.5 mA
At IOL = +0.5 mA
VIN = VDD = 3.6 V
IIL
500 nA
VIN = 0 V, VDD = 3.6 V
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Tx TIMING
Parameter
Description
Typ
Unit
tTx–SR
tTx–HR
tTx–SF
tTx–HF
Setup Time of Tx_AEC[15:0] from Rising Edge of Tx_CLK
Hold Time of Tx_AEC[15:0] from Rising Edge of Tx_CLK
Setup Time of Tx_AEC[15:0] from Falling Edge of Tx_CLK
Hold Time of Tx_AEC[15:0] from Falling Edge of Tx_CLK
12
6
12
6
ns
ns
ns
ns
Tx_CLK
Tx_AEC[15:0]
VALID DATA
VALID DATA
tTx–SR
tTx–HF
tTx–HR
tTx–SF
Figure 1. Tx Timing Diagram
Rx TIMING
Parameter
Description
Typ
Unit
tRx–S
tRx–H
Setup Time of Rx[15:0] from Rising Edge of Rx_CLK
Hold Time of Rx[15:0] from Rising Edge of Rx_CLK
25
0
ns
ns
R
X
_CLK
[15:0]
RX
VALID DATA
tRx–S
tRx–H
Figure 2. Rx Timing Diagram
REV. 0
–2–
AD6439-2
Tx SERIAL INTERFACE TIMING
Parameter
Description
Typ
Unit
tTFRM–DV
tTFRM–D
tTDREQ–DV
tTDREQ–H
tTBS–S
tTBS–H
tTD–S
tTD–H
Tx_FRM Valid to Falling Edge of Tx_Rx_SCLK
Hold Time of Tx_FRM from Falling Edge of Tx_Rx_SCLK
Tx_DREQ Valid to Rising Edge of Tx_Rx_SCLK
Hold Time of Tx_DREQ from Rising Edge of Tx_Rx_SCLK
Setup Time of Tx_BS from Rising Edge of Tx_Rx_SCLK
Hold Time of Tx_BS from Rising Edge of Tx_Rx_SCLK
Setup Time of Tx_SDATA from Rising Edge of Tx_Rx_SCLK
Hold Time of Tx_SDATA from Rising Edge of Tx_Rx_SCLK
5
10
5
10
10
0
10
0
ns
ns
ns
ns
ns
ns
ns
ns
Tx_Rx_SCLK
Tx_FRM
tTFRM–DV tTFRM–D
Tx_DREQ
tTDREQ–DV tTDREQ–H
Tx_BS
tTBS–S tTBS–H
Tx_SDATA
VALID DATA
tTD–S tTD–H
Figure 3. Tx Serial Interface Timing Diagram
Rx SERIAL INTERFACE TIMING
Parameter
Description
Typ
Unit
tRFRM–DV
tRFRM–H
tRDREQ–S
tRDREQ–H
tRBS–DV
tRBS–H
Rx_FRM Valid to Falling Edge of Tx_Rx_SCLK
5
ns
ns
ns
ns
ns
ns
ns
ns
Hold Time of Rx_FRM from Falling Edge of Tx_Rx_SCLK
Setup Time of Rx_DREQ from Rising Edge of Tx_Rx_SCLK
Hold Time of Rx_DREQ from Rising Edge of Tx_Rx_SCLK
Rx_BS Valid to Rising Edge of Tx_Rx_SCLK
Hold Time of Rx_BS from Rising Edge of Tx_Rx_SCLK
Rx_SDATA Valid to Rising Edge of Tx_Rx_SCLK
Hold Time of Rx_SDATA from Rising Edge of Tx_Rx_SCLK
10
15
0
5
10
5
10
tRD–DV
tRD–H
Tx_Rx_SCLK
Rx_FRM
tRFRM–H
tRFRM–DV
Rx_DREQ
Rx_BS
tRDREQ–S tRDREQ–H
tRBS–DV tRBS–H
VALID DATA
tRD–DV
Rx_SDATA
tRD–H
Figure 4. Rx Serial Interface Timing Diagram
REV. 0
–3–
AD6439-2
READ OPERATION TIMING
Parameter
Description
Min
Max
Unit
tRDD
tAA
tRDH
tRP
tCRD
tASR
tRDA
tRWR
NRD Low to Data Valid
A0–A13, NCS to Data Valid
Data Hold from NRD High
11 + W
18 + W
ns
ns
ns
ns
ns
ns
ns
ns
0
NRD Pulsewidth
14 + W
3
2
5
DSP_CLK High to NRD Low
A0–A13, NCS Setup Before NRD Low
A0–A13, NCS Hold After NRD Deasserted
NRD High to NRD or NWR Low
17
12
NOTES
W = wait state
؋
(DSP_CLK period). AD6439-2 accesses faster than 20 MHz (DSP_CLK); requires one wait state.
DSP_CLK
A[13:0]
DSP_CLK
A[13:0]
NCS
NCS
tRDA
tRWR
tWRA
tWWR
tASR
tRP
tASW
tWP
NRD
NWR
tCRD
tCWR
tRDD
tWDH
tRDV
tWDW
tAA
tRDH
tAW
tRDE
D[15:0]
NWR
D[15:0]
NRD
Figure 5. Read Operation Timing Diagram
Figure 6. Write Operation Timing Diagram
WRITE OPERATION TIMING
Parameter
Description
Min
Max
Unit
tDW
tDH
tWP
tASW
tCWR
tAW
tWRA
tWWR
Data Setup Before NWR High
Data Hold After NWR High
NWR Pulsewidth
A0–A13, NCS Setup Before NWR Low
DSP_CLK High to NWR Low
A0–A13, NCS Setup Before NWR Deasserted
A0–A13, NCS Hold After NWR Deasserted
NWR High to NRD or NWR Low
10 + W
6
12 + W
2
ns
ns
ns
ns
ns
ns
ns
ns
3
17
19 + W
5
12
NOTES
W = wait state
؋
(DSP_CLK period). AD6439-2 accesses faster than 20 MHz (DSP_CLK); requires one wait state.
REV. 0
–4–
AD6439-2
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +4.6 V
Input Voltage . . . . . . . . . . . . . . . . . . . . . –0.5 V to VDD +0.5 V
Output Voltage Swing . . . . . . . . . . . . . . –0.5 V to VDD +0.5 V
Operating Temperature Range (Ambient) . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (5 sec) MQFP . . . . . . . . . . . . . . . . . 280°C
ORDERING GUIDE
Model
Temperature Range
Package Description
128-Lead Plastic MQFP
Package Option
AD6439-2BS
–40°C to +85°C
S-128B
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD6439-2 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
Pin Descriptions
The AD6439-2 carries 79 signal pins (24 output pins, 39 input pins, 16 bidirectional pins) and 43 supply pins. See Figure 7 for details.
Tx_DREQ
TX_AEC[15:0]
Tx_BS
TX
_CLK
Tx_SDATA
Tx_FRM
Tx_Rx_SCLK
Rx_DREQ
Rx_BS
R
X
[15:0]
_CLK
Rx_SDATA
Rx_FRM
R
X
MCLK
NRESET
Figure 7. Functional Pin Diagram
The pin configuration on the chip is shown in the Pin Configuration.
REV. 0
–5–
AD6439-2
PIN CONFIGURATION
VDD
GND
102 D15
101 NC
1
2
3
4
5
6
7
8
9
PIN 1
IDENTIFIER
100
NC
A1
NC
99 VDD
98 GND
A2
A3
Rx0
97
96 Rx1
95
VDD
GND
A4
VDD
94 GND
93 Rx2
A5 10
A6
Rx3
11
A7 12
13
92
91 Rx4
90
DSP_CLK
Rx5
A8 14
89 Rx6
88 Rx7
VDD 15
GND
VDD
16
A9 17
18
87
86 GND
85
A10
Rx8
84 Rx9
AD6439-2
A11 19
A12 20
TOP VIEW
(Not to Scale)
83
82
Rx10
Rx11
A13
21
GND 22
81 Rx12
80
23
24
VDD
Rx13
79 GND
Rx_FRM
78
77
Rx_SDATA 25
Rx_DREQ
VDD
Rx14
26
Rx_BS 27
28
76 Rx15
75
Tx_Rx_SCLK
Rx_CLK
74 NC
GND 29
VDD 30
73
72
GND
VDD
Tx_FRM
31
Tx_SDATA 32
Tx_BS 33
71 NC
70
69
GND
VDD
GND
34
VDD 35
68 Tx_AEC15
Tx_AEC14
Tx_DREQ
36
37
67
66 GND
GND
65
MCLK 38
VDD
NC = NO CONNECT
REV. 0
–6–
AD6439-2
PIN FUNCTION DESCRIPTIONS
Pin Number
Pin Name
Type
Description
1, 7, 15, 23, 30, 35, 41, 46,
51, 57, 62, 65, 69, 72, 78,
87, 95, 99, 104, 114, 125
VDD
Supply
These pins supply 3.3 V power to the AD6439-2.
2, 8, 16, 22, 29, 34, 37, 42,
47, 52, 56, 61, 66, 70, 73,
79, 86, 94, 98, 105, 115, 124
GND
Ground
These pins supply ground for the AD6439-2.
3, 39, 71, 74, 100, 101
NC
No Connection
Input
Output
Output
Input
Output
Output
Output
Input
Input
Output
Input
Output
Outputs
13
24
25
26
27
28
31
32
33
36
38
40
DSP_CLK
Rx_FRM
Rx_SDATA
Rx_DREQ
Rx_BS
Tx_Rx_SCLK
Tx_FRM
Tx_SDATA
Tx_BS
Tx_DREQ
MCLK
Tx_CLK
Tx_AEC[0:15]
Clock for the DSP interface.
Frame pulse for Rx serial port.
Serial data for Rx serial port.
Data request for Rx serial port.
Byte strobe for Rx serial port.
Serial clock for Tx and Rx serial port.
Frame pulse for Tx serial port.
Serial data for Tx serial port.
Byte strobe for Tx serial port.
Data request for Tx serial port.
Master clock (35.328 MHz).
Output clock used to qualify valid transmit data.
16-bit output for transmit and AEC data stream.
43–45, 48–50, 53–55, 58–60,
63, 64, 67, 68
75
Rx_CLK
Rx(0:15)
D(0:15)
NRESET
NWR
NRD
NCS
A(0:13)
Output
Inputs
I/O
Input
Input
Input
Input
Inputs
Output clock used to qualify valid receive data.
16-bit input for receive data stream.
16-bit data bus from DSP port.
97, 96, 93–88, 85–80, 77, 76
121–116, 113–106, 103, 102
122
123
126
127
Reset pin, active low.
Write strobe from DSP port, active low.
Rad strobe from DSP port, active low.
Chip set from DSP port, active low.
14-bit address bus for DSP port.
128, 4–6, 9–12, 14, 17–21
REV. 0
–7–
AD6439-2
The transmit path starts with serial data received from the
AD6438-2. This data is encoded (QAM or Trellis), modulated
(IFFT), processed by the digital filter section, and output to the
AD6438-2 or AD6437. It is also used by the Echo Canceller
(EC) block to produce an Analog Echo Cancel (AEC) data
stream. The AEC data stream is multiplexed on the same output
pins as the transmit data stream to minimize the number of pins
required by both the AD6439-2 and the integrated AFE (AD6440).
The AD6439-2 can also be connected directly to the AD6437;
however, this does not permit utilization of the analog Echo
Cancel function.
INTRODUCTION
This data sheet describes the functionality and interfacing of the
AD6439-2 Discrete Multitone Coprocessor IC. The AD6439-2 is
part of the Analog Devices AD20msp918 ADSL chipset. Other
components include:
• AD6438-2 ATM Interface and Framer IC
• AD6437 Analog Front-End IC
• AD8016 Driver/Receiver
• ADSP-2183 System Control Processor
Figure 8 illustrates the basic interconnection between system
components.
The receive path begins with data being received by the AD6439-2,
from the AD6440 or AD6437 AFE. The receive data stream is
processed by the receive path filters, demodulated by the FFT,
decoded, and sent to the AD6438-2. The Echo Canceller
provides a digital echo cancel stream used by the receive path
filter section.
An object code license for all modem software is supplied with
the AD20msp918 chipset.
When used as part of the AD20msp918 ADSL chipset, internal
functionality of the AD6439-2 is under control of the firmware
supplied with the ADSP-2183 and its MP (Messaging Protocol).
This protocol supplies a hardware-neutral method of controlling
operation of the ADSL chipset that is compatible with various
hardware implementations.
Encoder/Decoder
The Encode/Decode block handles the QAM or Trellis encod-
ing and decoding of data.
The AD6439-2 is a high-performance version of the earlier
AD6436 DMT Coprocessor IC and can be used in place of the
AD6436 in applications such as the AD20msp910 ADSL chipset.
Enhancements to the AD6439-2 include:
Data received from the AD6438-2 as a 35.328 MHz serial stream
is fed to the encoder buffer. This block handles encoding, bin
allocation, and tone reordering operations. Each subcarrier (from
0 to 255) can handle from 0 to 15 bits, with the density controlled
by the bin allocation. This block also handles the pilot tone
insertion. The bin location of the pilot tone is completely pro-
grammable. Typically, this would be set to Bin 64 in CO mode
and Bin 16 in RT mode.
• Trellis Encoder and Decoder Functions Added
• POTS HPF Block Added
• Mask FIR Added
• Digital Echo Canceller Lengthened
• Analog Echo Canceller Block Added (Requires AD6438-2 Chip)
• Standby Operation Mode Added
• Symmetric FFT and IFFT Operations Performed
• Programmable Pilot Tone
The decoder is very similar, recovering the data from the sub-
carriers and reversing tone ordering and bit allocation operations.
It also operates the same way in CO and RT mode. The receive
serial interface between the decoder and the AD6438-2 operates
at 35.328 MHz.
AD6439-2
AD6438-2
QAM encoding corresponds to the “Tone Ordering” and “Con-
stellation Encoder and Gain Scaling” blocks in the T1.413
reference model.
AD6437
AFIC
DMT/
DATA
INTERFACE/
TO HYBRID Tx
POTS SPLITTER
COPROCESSOR
FRAMER
AD8016
DRIVER
IFFT Block
TO RAM
(INTERLEAVE)
The IFFT block performs a 512-point inverse FFT in CO mode
(transmitting the downstream data) and in RT mode (transmit-
ting the upstream data). It also implements gain scaling at the
same time.
ADSP-2183
PROCESSOR
CONTROL
TO BOOT FLASH
MESSAGES
OR
P FOR IDMA
Figure 8. Block Diagram AD20msp918 Chipset
OPERATION
The AD6439-2 performs encoding and decoding operations,
Frequency Domain Equalization (FDQ), FFT/IFFT operations,
and a number of digital filter functions, including interpolation/
decimation and Time-Domain Equalization (TDQ). It is designed
to Category 1 of the ANSI/ETSI standard and relies on Frequency
Division Multiplexing (FDM) to separate upstream and down-
stream signals of up to 256 tones.
While data is being read out of the IFFT block and into the
digital filter section, the cyclic prefix is added to the transmit
path. The purpose of the cyclic prefix is to make the symbol
appear periodic in nature to the receiver. The IFFT produces
512 real data samples, to which 32 samples are added.
FFT Block
On the receive channel, the FFT block performs a 512-point
FFT in CO mode (receiving the upstream duplex data) and in
RT mode (receiving the downstream simplex data). In addition,
carriers can be scaled up to provide full precision for the FDQ
and QAM or Trellis decode operations. After the transform, the
FFT performs the FDQ decode operation in the output buffer.
In addition to performing the FFT, this block also strips off
cyclic prefixes and removes pilot tones from the symbol. The
bin location from which the pilot tone is extracted is completely
The AD6439-2 consists of six major blocks:
• Serial Interface Block,
• Trellis/QAM Encoder/Decoder Block,
• IFFT Block,
• FFT Block,
• Digital Filter (DFIC) Block,
• DSP Interface and Control Block (See Figure 8.)
REV. 0
–8–
AD6439-2
programmable. Typically this would be Bin 16 in CO mode and
Bin 64 in RT mode.
Figure 9 shows the timing of the Tx interface signals.
This is a byte protocol. The AD6439-2 raises Tx_DREQ on
the falling edge of Tx_Rx_SCLK to request data (ref T0). The
AD6438-2 samples the Tx_DREQ on its rising clock signal and
when seen, outputs a one-clock-byte strobe Tx_BS (ref T1) and
simultaneously places Bit 7 of the byte on the Tx_SDATA pin.
Then, on the next seven rising clock pulses, the AD6438-2 places
Bits 6 through 0 on the Tx_SDATA pin.
Digital Filter Block
This implements a variety of digital filtering operations, includ-
ing Time Domain Equalization (TDQ) and the interpolation/
decimation tasks that connect the digital devices to the analog
stage (AD6437).
The Echo Cancellation filter improves system performance by
easing the task of the FDM separation filter, reducing the effect
of sidelobes in FFT, and reducing the size of the guardband. It
also improves line matching.
On the next rising clock pulse, the Tx_DREQ line is again sampled
(ref T5) and, if it is high and another byte is ready to transmit,
outputs the byte strobe coincident with the MSB of the next byte,
then proceeds to output the rest of the byte in successive clock
cycles. If Tx_DREQ were low, or another byte was not available
yet, the byte strobe would not be output, and Tx_DREQ would
continue to be sampled on successive rising clock pulse edges
while waiting for available data. The AD6438-2 is free to place
Bit 7 of a byte on the Tx_SDATA pin even if the AD6439-2 will
not be taking it, as long as the byte strobe is not pulsed. Once
the byte strobe is pulsed for Bit 7, the Tx_DREQ line is ignored
until all eight bits are sent.
The AD6439-2 includes logic for a parallel transmit path to
generate an echo-cancellation signal, which operates with a
second DAC in the AD6437 codec in the analog domain to imple-
ment Category 2 overlapping spectra.
NB Data Width
The AD6439-2 uses 16-bit datapaths internally. As such, it can
take full advantage of high resolution analog stages with up to
16-bit resolution. Note: The AD6437 (companion part in the
AD20msp918 chipset) is only specified to 12-bit linearity.
Once Tx_DREQ is raised, the AD6439-2 leaves Tx_DREQ high
and samples Tx_BS on successive rising edges of the clock. Once
Tx_BS is seen high (ref T2), the AD6439-2 knows that Bit 7 can
be sampled, followed by the remaining seven bits on the next
seven rising clocks edges (ref T3). If desired, the Tx_DREQ can
be dropped at this time.
INTERFACE TIMING
The AD6439-2 contains a transmit serial port that accepts a bit
stream from an AD6438-2, a receive serial port that sends a bit
stream to an AD6437, ADC and DAC interfaces, and a DSP
host port to allow a DSP to monitor signals and control the data
through the device. The analog echo canceller interface is iden-
tical to the DAC interface.
On the falling edge after Bit 1 has been sampled (ref T4), the
AD6439-2 must raise or lower the Tx_DREQ line, depending
on whether it knows it wants another byte immediately following
the current byte. This timing is needed to ensure the AD6438-2
can detect the Tx_DREQ signal as it outputs the last bit.
Tx Serial Interface
The Tx serial interface between the AD6439-2 and the AD6438-2
uses five signals:
Tx_Rx_SCLK: Serial clock provided by AD6439-2
The Tx_FRAME signal, which is not shown, is output by the
AD6439-2 on the rising edge of Tx_Rx_SCLK to signify the start
of a frame. The AD6438-2 does not respond to the Tx_DREQ
line before the start of a frame, or after the number of data bytes
programmed by the DSP has been transferred within a frame.
Tx_DREQ:
Tx_FRAME:
Tx_BS:
Data request provided by AD6439-2
Frame strobe provided by AD6439-2
Byte strobe provided by AD6438-2
Serial data provided by AD6438-2
Tx_SDATA:
AD6439-2 VIEW
TX_RX_SCLK
TX_DREQ
TX_BS
TX
_SDATA
B7
T2
B6
T3
B5
B2
B1
B0
T5
B7
T0
T1
T4
AD6435/AD6438-2 VIEW
TX_RX_SCLK
TX_DREQ
TX_BS
B7
B6
B5
B2
B1
B0
B7
TX_SDATA
NOTE: DATA IS PASSED MSB FIRST
Figure 9. Tx Serial Port Timing
REV. 0
–9–
AD6439-2
AD6439-2 VIEW
TX_RX_SCLK
RX_DREQ
RX_BS
RX
_SDATA
B7
T2
B6
T3
B5
B2
B1
B0
B7
T0
T1
T4
T5
INTERFACE FRAMER VIEW
TX_RX_SCLK
RX_DREQ
RX_BS
B7
B6
B5
B2
B1
B0
B7
RX_SDATA
NOTE: DATA IS PASSED MSB FIRST
Figure 10. Rx Serial Port Timing
Rx Serial Interface
The Rx serial interface between the AD6439-2 and AD6438-2
uses five signals:
whether it knows it wants another byte immediately following the
current byte. This timing is needed to ensure the AD6439-2 can
detect the Rx_DREQ signal on the rising edge after the last bit.
Tx_Rx_SCLK: Serial Clock Provided by AD6439-2
Because of the direction of the clock skew, this protocol allows
up to one full cycle of skew less some period for settling round-
trip timing (AD6439-2 to AD6438-2 and back, or vice-versa).
The main difference from the Tx path is that the data and Rx_BS
are sampled by the AD6438-2 on the falling clock edge because
of the known direction of clock skew. The time from data request
to Bit 7 being received is only one clock cycle (assuming the
AD6439-2 has data ready), so even for the worst case of nine
clock cycles per byte, the time to transmit a full frame is less
than 97 ms, which should be within the safe window for the
AD6439-2.
Rx_FRAME:
Rx_BS:
Tx_SDATA:
Rx_DREQ:
Frame Strobe Provided by AD6439-2
Byte Strobe Provided by AD6439-2
Serial Data Provided by AD6439-2
Data Request Provided by AD6438-2
Figure 10 shows the timing of the Rx interface port signals.
This is a byte protocol. The AD6438-2 raises Rx_DREQ on
the rising edge of Tx_Rx_SCLK to request data (ref T0). The
AD6439-2 samples the Rx_DREQ on its rising clock and, when
seen, outputs a one-clock-byte strobe Rx_BS (ref T1), and at the
same time places Bit 7 of the byte on the Rx_SDATA pin. On
the next seven rising clock pulses, the AD6439-2 places Bit 6
through Bit 0 on the Rx_SDATA pin. As the last bit is output,
the Rx_DREQ line is again sampled (ref T5) and, if high, and
another byte is ready to transmit, outputs the byte strobe coinci-
dent with the MSB of the next byte, then proceeds to output
the remainder of the byte in successive clock cycles.
The Rx_FRAME signal, which is not shown, is output by the
AD6439-2 on the rising edge of Tx_Rx_SCLK to indicate the
start of a frame. The AD6438-2 does not raise the Rx_DREQ
line before the start of a frame, or after the number of data bytes
programmed by the DSP has been received within a frame.
DAC Interface
The AD6439-2 provides 16 bits (Tx[15:0]) to a Tx A/D converter
and 16 bits (AEC[15:0]) to the AEC A/D. These two buses are
MUXed onto one 16-bit output bus provided to the analog
front end (AD6437, AD6440). The Tx_CLK signal accompa-
nying the 16-bit data bus qualifies Tx and AEC data.
If Rx_DREQ is low, or another byte not yet available, the byte
strobe would not be output, and Rx_DREQ will continue to be
sampled on successive rising clock edges while waiting for avail-
able data. The AD6439-2 is free to place Bit 7 of the next byte on
the pin even if Rx_DREQ is low, as long the byte strobe is not
pulsed. Once the byte strobe is pulsed for Bit 7, the Rx_DREQ line
is ignored until all eight bits are sent.
The output bus always provides valid Tx sample data on the ris-
ing edge of Tx_CLK and valid AEC sample data on the falling
edge of Tx_CLK. During normal operation, the Tx and AEC
output sample rates are 17.664 MHz; therefore, on the output
data bus, the rate is 35.328 MHz and Tx_CLK is 17.664 MHz.
Tx and AEC data can be down-sampled to 8.832 MHz, in which
case the output data bus has a rate of 17.664 MHz and the
Tx_CLK signal is 8.832 MHz. The Tx Int8 and AEC Int8 blocks
can also be bypassed, making the Tx and AEC data rate only
Once Rx_DREQ is raised, The AD6438-2 leaves Rx_DREQ high
and samples Rx_BS on successive falling edges of the clock.
Once Rx_BS is seen high (ref T2), the AD6438-2 samples Bit 0
and knows that the data bits can be sampled on the next seven
falling clock edges (ref T3). If desired, the Rx_DREQ can be
dropped at this time. When Bit 1 is being sampled (ref T4), the
AD6438-2 must raise or lower the Rx_DREQ line depending on
REV. 0
–10–
AD6439-2
35.328MH
Z
TX_CLK
AEC0
T
X
0
AEC1
T
X
1
AEC2
T
X
2
AEC3
TX3
TX_AEC[15:0]
Figure 11. Tx_AEC MUX Bus in Normal Operation
DSP Port
2.208 MHz, the output bus rate 4.416 MHz and the Tx_CLK
signal 2.208 MHz. Data sent out is unsigned; however, the
AD6439-2 can be programmed to send out twos complement
binary data.
The AD6439-2 includes a DSP port consisting of a 14-bit address
bus A[13:0], a 16-bit data bus D[15:0], three bus control pins,
NRD, NWR, NCS, and a clock, DSP_CLK. The DSP port allows
a 2183 DSP to access the AD6439-2.
Note that Tx and AEC paths must always be in the same mode.
They are either both in normal mode, both in downsample mode,
or both in bypass mode.
ADDR[13:0]
DATA[15:0]
ADDR[13:0]
DATA[15:0]
ADC Interface
ADSP-2183
AD6439-2
The AD6439-2 includes an interface that accepts 16 bits
(Rx[15:0]) from an A/D converter. The sample rate is 8.832 MHz,
but if the Dec4 block is bypassed, the rate is only 2.208 MHz.
Signal Rx_CLK qualifies when the A/D converter needs to pro-
vide valid data. The AD6439-2 normally assumes that input data
is in unsigned binary format; however, it can also be programmed
to received twos complement binary data.
DSP_CLK
IOMSN
RDN
DSP_CLK
CSN
RDN
WRN
WRN
Figure 12. ADSP-2183 to AD6439-2 Interface
REV. 0
–11–
AD6439-2
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
128-Lead MQFP Plastic Quad Flatpack
(S-128B)
0.685 (17.40)
0.677 (17.20)
0.669 (17.00)
0.555 (14.10)
0.551 (14.00)
0.547 (13.90)
0.093 (2.35)
MAX
0.041 (1.03)
0.035 (0.88)
0.031 (0.78)
128
1
103
102
SEATING
PLANE
0.791 (20.10)
0.787 (20.00)
0.783 (19.90)
TOP VIEW
(PINS DOWN)
0.921 (23.40)
0.913 (23.20)
0.906 (23.00)
0.003 (0.08)
MAX
38
39
65
64
0.010 (0.25)
MAX
0.020 (0.50)
BSC*
0.011 (0.27)
0.009 (0.22)
0.007 (0.17)
0.083 (2.10)
0.079 (2.00)
0.075 (1.90)
REV. 0
–12–
相关型号：
AD644JH
DUAL OP-AMP, 3500uV OFFSET-MAX, 2MHz BAND WIDTH, MBCY8, HERMETIC SEALED, METAL CAN, TO-99, 8 PIN
ROCHESTER
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