AD648SQ [ADI]

Dual Precision, Low Power BiFET Op Amp; 双路精密，低功耗BiFET运算放大器


型号：	AD648SQ
厂家：	ADI
描述：	Dual Precision, Low Power BiFET Op Amp 双路精密，低功耗BiFET运算放大器运算放大器放大器电路
文件：	总12页 (文件大小：337K)
中文：	中文翻译
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Dual Precision,

Low Power BiFET Op Amp

AD648

CO NNECTIO N D IAGRAMS

FEATURES

DC Perform ance

400 ␮A m ax Quiescent Current

10 pA m ax Bias Current, Warm ed Up (AD648C)

300 ␮V m ax Offset Voltage (AD648C)

3 ␮V/ ؇C m ax Drift (AD648C)

2 ␮V p-p Noise, 0.1 Hz to 10 Hz

AC Perform ance

1.8 V/ ␮s Slew Rate

1 MHz Unity Gain Bandw idth

Available in Plastic Mini-DIP, Cerdip, Plastic SOIC

and Herm etic Metal Can Packages

MIL-STD-883B Parts Available

Surface Mount (SOIC) Package Available in Tape and

Reel in Accordance w ith EIA-481A Standard

Single Version: AD548

P RO D UCT D ESCRIP TIO N

T he AD648S and AD648T are rated over the military tempera-

ture range of –55°C to +125°C and are available processed to

MIL-ST D-883B, Rev. C.

T he AD648 is a matched pair of low power, precision mono-

lithic operational amplifiers. It offers both low bias current

(10 pA max, warmed up) and low quiescent current (400 µA

max) and is fabricated with ion-implanted FET and laser wafer

trimming technologies. Input bias current is guaranteed over the

AD648’s entire common-mode voltage range.

T he AD648 is available in an 8-pin plastic mini-DIP, cerdip,

SOIC, T O-99 metal can, or in chip form.

P RO D UCT H IGH LIGH TS

T he economical J grade has a maximum guaranteed offset volt-

age of less than 2 mV and an offset voltage drift of less than

20 µV/°C. T he C grade reduces offset voltage to less than

0.30 mV and offset voltage drift to less than 3 µV/°C. T his level

of dc precision is achieved utilizing Analog’s laser wafer drift

trimming process. T he combination of low quiescent current

and low offset voltage drift minimizes changes in input offset

voltage due to self-heating effects. Five additional grades are

offered over the commercial, industrial and military temperature

ranges.

1. A combination of low supply current, excellent dc and ac

performance and low drift makes the AD648 the ideal op

amp for high performance, low power applications.

2. T he AD648 is pin compatible with industry standard dual op

amps such as the LF442, T L062, and AD642, enabling

designers to improve performance while achieving a reduc-

tion in power dissipation of up to 85%.

3. Guaranteed low input offset voltage (2 mV max) and drift

(20 µV/°C max) for the AD648J are achieved utilizing Analog

Devices’ laser drift trimming technology.

T he AD648 is recommended for any dual supply op amp appli-

cation requiring low power and excellent dc and ac perfor-

mance. In applications such as battery-powered, precision

instrument front ends and CMOS DAC buffers, the AD648’s

excellent combination of low input offset voltage and drift, low

bias current and low 1/f noise reduces output errors. High

common-mode rejection (86 dB, min on the “C” grade) and

high open-loop gain ensures better than 12-bit linearity in high

impedance, buffer applications.

4. Analog Devices specifies each device in the warmed-up con-

dition, insuring that the device will meet its published specifi-

cations in actual use.

5. Matching characteristics are excellent for all grades. T he

input offset voltage matching between amplifiers in the

AD648J is within 2 mV, for the C grade matching is within

0.4 mV.

6. Crosstalk between amplifiers is less than –120 dB at 1 kHz.

7. T he AD648 is available in chip form.

T he AD648 is pinned out in a standard dual op amp configura-

tion and is available in seven performance grades. T he AD648J

and AD648K are rated over the commercial temperature range

of 0°C to +70°C. T he AD648A, AD648B and AD648C are

rated over the industrial temperature range of –40°C to +85°C.

REV. C

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 617/ 329-4700

Fax: 617/ 326-8703

(@ + 25؇C and V = ؎15 V dc, unless otherwise noted)

AD648–SPECIFICATIONS

Model

AD 648J/A/S

Typ

AD 648K/B/T

Typ

AD 648C

Typ

Min

Max

Min

Max

Min

Max

Units

INPUT OFFSET VOLT AGE¹

Initial Offset

T _MINto T _MAX

vs. T emperature

vs. Supply

0.75

2.0

3.0/3.0/3.0

0.3

1.0

1.5/1.5/2.0

0.10

0.3

0.5

3.0

µV/°C

76/76/76

vs. Supply, T _MINto T _MAX

Long-T erm Offset Stability

µV/month

INPUT BIAS CURRENT

Either Input,²V_CM= 0

0.65

Either Input²at T _MAX, V_CM= 0

Max Input Bias Current Over

Common-Mode Voltage Range

Offset Current, V_CM= 0

0.45/1.3/20

0.25/0.65/10

0.35

Offset Current at T _MAX

0.25/0.7/10

0.15/0.35/5

MAT CHING CHARACT ERIST ICS³

Input Offset Voltage

Input Offset Voltage T _MINto T _MAX

Input Offset Voltage vs. T emperature

Input Bias Current

1.0

2.0

3.0/3.0/3.0

0.5

1.0

1.5/1.5/2.0

0.2

0.4

0.5

µV/°C

2.5

Crosstalk

–120

INPUT IMPEDANCE

Differential

Common Mode

1 × 10^{1 2}ʈ3

3 × 10¹²ʈ3

1 × 10¹²ʈ3

3 × 10¹²ʈ3

1 × 10¹²ʈ3

3 × 10¹²ʈ3

ΩʈpF

INPUT VOLT AGE RANGE

Differential⁴

Common Mode

Common-Mode Rejection

V_CM= ±10 V

±20

±12

±20

±12

±20

±12

±11

76/76/76

T _MINto T _MAX

V_CM= ±11 V

T _MINto T _MAX

70/70/70

INPUT VOLT AGE NOISE

Voltage 0.1 Hz to 10 Hz

f = 10 Hz

4.0

µV p-p

nV/√Hz

f = 100 Hz

f = 1 kHz

f = 10 kHz

INPUT CURRENT NOISE

f = 1 kHz

1.8

fA/√Hz

FREQUENCY RESPONSE

Unity Gain, Small Signal

Full Power Response

Slew Rate, Unity Gain

Settling T ime to ±0.01%

0.8

1.0

1.8

0.8

1.0

1.8

0.8

1.0

1.8

MHz

kHz

V/µs

µs

OPEN-LOOP GAIN

V_O= ±10 V, R_L≥ 10 kΩ

T _MINto T _MAX, R_L≥ 10 kΩ

V_O= ±10 V, R_L≥ 5 kΩ

T _MINto T _MAX, R_L≥ 5 kΩ

300

300/300/300

150

1000

700

500

300

150

1000

700

500

300

150

1000

700

500

300

V/mV

150/150/150

OUT PUT CHARACT ERIST ICS

Voltage @ R_L≥ 10 kΩ,

T _MINto T _MAX

Voltage @ R_L≥ 5 kΩ,

T _MINto T _MAX

±12/±12/±12 ±13

±12

±11

±13

±12

±11

±13

±11/±11/±11 ±12

±12

Short Circuit Current

POWER SUPPLY

Rated Performance

±15

Operating Range

±4.5

±18

±4.5

±18

±4.5

±18

Quiescent Current (Both Amplifiers)

340

400

340

400

340

400

µA

T EMPERAT URE RANGE

Operating, Rated Performance

Commercial (0°C to +70°C)

Industrial (–40°C to +85°C)

Military (–55°C to +125°C)

AD648J

AD648A

AD648S

AD648K

AD648B

AD648T

AD648C

PACKAGE OPT IONS

SOIC (R-8)

Plastic (N-8)

AD648JR

AD648JN

AD648KR

AD648KN

Cerdip (Q-8)

AD648AQ, AD648SQ, AD648SQ/883B

AD648AH

AD648JR-REEL, AD648JR-REEL7

AD648JChips, AD648SChips

AD648BQ, AD648T Q/883B

AD648BH, AD648T H/883B

AD648KR-REEL, AD648KR-REEL7

AD648CQ

Metal Can (H-08A)

T ape and Reel

Chips Available

REV. C

–2–

AD648

NOT ES

¹Input Offset Voltage specifications are guaranteed after 5 minutes of operation at T _A= +25°C.

²Bias Current specifications are guaranteed maximum at either input after 5 minutes of operation at T = +25°C. For higher temperature, the current doubles

every 10°C.

³Matching is defined as the difference between parameters of the two amplifiers.

⁴Defined as voltages between inputs, such that neither exceeds ±10 V from ground.

Specifications subject to change without notice.

ABSO LUTE MAXIMUM RATINGS¹

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V

Internal Power Dissipation². . . . . . . . . . . . . . . . . . . . 500 mW

Input Voltage³. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V

Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite

Differential Input Voltage . . . . . . . . . . . . . . . . . . +V_Sand –V_S

Storage T emperature Range (Q, H) . . . . . . . . –65°C to +150°C

Storage T emperature Range (N, R) . . . . . . . . –65°C to +125°C

Operating T emperature Range

AD648J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

AD648A/B/C . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

AD648S/T . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

Lead T emperature Range (Soldering 60 sec) . . . . . . . . +300°C

NOT ES

¹Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. T his is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the

operational section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

²T hermal Characteristics:

8-Pin Plastic Package: θ_JA= 165°C/Watt

8-Pin Cerdip Package: θ_JC= 22°C/Watt; θ_JA= 110°C/Watt

8-Pin Metal Package: θ_JC= 65°C/Watt; θ_JA= 150°C/Watt

8-Pin SOIC Package: θ_JC= 42°C/Wat; θ_JA= 160°C/Watt

³For supply voltages less than ±18 V, the absolute maximum input voltage is equal

to the supply voltage.

METALIZATIO N P H O TO GRAP H

Contact factory for latest dimensions.

D imensions shown in inches and (mm).

CAUTIO N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD648 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. C

–3–

AD648—Typical Characteristics

–4–

REV. C

AD648

REV. C

–5–

AD648

AP P LICATIO N NO TES

T he AD648 is a pair of JFET -input op amps with a guaranteed

maximum I_Bof less than 10 pA, and offset and drift laser-

trimmed to 0.3 mV and 3 µV/°C, respectively (AD648C). AC

specs include 1 MHz bandwidth, 1.8 V/µs typical slew rate and

8 µs settling time for a 20 V step to ±0.01%—all at a supply

current less than 400 µA. T o capitalize on the device’s perfor-

mance, a number of error sources should be considered.

T he minimal power drain and low offset drift of the AD648 re-

duce self-heating or “warm-up” effects on input offset voltage,

making the AD648 ideal for on/off battery powered applica-

tions. T he power dissipation due to the AD648’s 400 µA supply

current has a negligible effect on input current, but heavy out-

put loading will raise the chip temperature. Since a JFET ’s

input current doubles for every 10°C rise in chip temperature,

this can be a noticeable effect.

Figure 22. Board Layout for Guarding Inputs

INP UT P RO TECTIO N

T he AD648 is guaranteed to withstand input voltages equal to

the power supply potential. Exceeding the negative supply volt-

age on either input will forward bias the substrate junction of

the chip. T he induced current may destroy the amplifier due to

excess heat.

T he amplifier is designed to be functional with power supply

voltages as low as ±4.5 V. It will exhibit a higher input offset

voltage than at the rated supply voltage of ±15 V, due to power

supply rejection effects. Common-mode range extends from 3 V

more positive than the negative supply to 1 V more negative

than the positive supply. Designed to cleanly drive up to 10 kΩ

and 100 pF loads, the AD648 will drive a 2 kΩ load with re-

duced open-loop gain.

Input protection is required in applications such as a flame de-

tector in a gas chromatograph, where a very high potential may

be applied to the input terminals during a sensor fault condi-

tion. Figures 23a and 23b show simple current limiting schemes

that can be used. R_{PROT ECT}should be chosen such that the

maximum overload current is 1.0 mA (for example 100 kΩ for a

100 V overload).

Figure 21 shows the recommended crosstalk test circuit. A typi-

cal value for crosstalk is –120 dB at 1 kHz.

Figure 23a. Input Protection of l-to-V Converter

Figure 21. Crosstalk Test Circuit

LAYO UT

T o take full advantage of the AD648’s 10 pA max input current,

parasitic leakages must be kept below an acceptable level. T he

practical limit of the resistance of epoxy or phenolic circuit

board material is between 1 × 10¹²Ω and 3 × 10¹²Ω. T his can

result in an additional leakage of 5 pA between an input of 0 V

and a –15 V supply line. T eflon or a similar low leakage material

(with a resistance exceeding 10¹⁷Ω) should be used to isolate

high impedance input lines from adjacent lines carrying high

voltages. T he insulator should be kept clean, since contaminants

will degrade the surface resistance.

Figure 23b. Voltage Follower Input Protection Method

Figure 23b shows the recommended method for protecting a

voltage follower from excessive currents due to high voltage

breakdown. T he protection resistor, R_P, limits the input current.

A nominal value of 100 kΩ will limit the input current to less

than 1 mA with a 100 volt input voltage applied.

A metal guard completely surrounding the high impedance

nodes and driven by a voltage near the common-mode input

potential can also be used to reduce some parasitic leakages.

T he guarding pattern in Figure 22 will reduce parasitic leakage

due to finite board surface resistance; but it will not compensate

for a low volume resistivity board.

T he stray capacitance between the summing junction and

ground will produce a high frequency roll-off with a corner

frequency equal to:

f_corner

2 π R_PC_stray

Accordingly, a 100 kΩ value for R_Pwith a 3 pF C_straywill cause

a 3 dB corner frequency to occur at 531 kHz.

–6–

REV. C

AD648

Figure 23c shows a diode clamp protection scheme for an I-to-V

converter using low leakage diodes. Because the diodes are con-

nected to the op amp’s summing junction, which is a virtual

ground, their leakage contribution is minimal.

CMOS DAC’s output current to a voltage and provides the

necessary level shifting to achieve a bipolar voltage output. T he

circuit operates with a 12-bit plus sign input code. T he transfer

function is shown in Figure 25.

T he AD7592 is a fully protected dual CMOS SPDT switch with

data latches. R4 and R5 should match to within 0.01% to main-

tain the accuracy of the converter. A mismatch between R4 and

R5 introduces a gain error. Overall gain is trimmed by adjusting

_IN. T he AD648’s low input offset voltage, low drift over tem-

perature, and excellent dynamics make it an attractive low

power output buffer.

T he input offset voltage of the AD648 output amplifier results

in an output error voltage. T his error voltage equals the input

offset voltage of the op amp times the noise gain of the amplifier.

Figure 23c. I-to-V Converter with Diode Input Protection

Exceeding the negative common-mode range on either input

terminal causes a phase reversal at the output, forcing the ampli-

fier output to the corresponding high or low state. Exceeding

the negative common mode on both inputs simultaneously

forces the output high. Exceeding the positive common-mode

range on a single input doesn’t cause a phase reversal; but if

both inputs exceed the limit, the output will be forced high. In

all cases, normal amplifier operation is resumed when input

voltages are brought back within the common-mode range.

T hat is:

R_FB

V_OSOutput = V_OSInput 1 +

R_O

R_FBis the feedback resistor for the op amp, which is internal to

the DAC. R_Ois the DAC’s R-2R ladder output resistance. T he

value of R_Ois code dependent. T his has the effect of changing

the offset error voltage at the amplifier’s output. An output am-

plifier with a sub millivolt input offset voltage is needed to pre-

serve the linearity of the DAC’s transfer function.

D /A CO NVERTER BIP O LAR O UTP UT BUFFER

T he circuit in Figure 24 provides 4 quadrant multiplication with

a resolution of 12 bits. The AD648 is used to convert the AD7545

Figure 24. 12-Bit Plus Sign Magnitude D/A Converter

SIGN BIT BINARY NUMBER IN DAC REGISTER ANALOG OUTPUT

1111 1111 1111

0000 0000 0000

1111 1111 1111

+V_IN

(4095/ 4096)

0 VOLTS

–V_IN

(4095/ 4096)

NOTE: SIGN BIT AT "0" CONNECTS THE NONINVERTING INPUT OF

A2 TO ANALOG COMMON

Figure 25. Sign Magnitude Code Table

REV. C

–7–

AD648

D UAL P H O TO D IO D E P REAMP

T he AD648 in this configuration provides a 700 kHz small sig-

nal bandwidth and 1.8 V/µs typical slew rate. T he 33 pF capaci-

tor across the feedback resistor optimizes the circuit’s response.

T he oscilloscope photos in Figures 26a and 26b show small and

large signal outputs of the circuit in Figure 24. Upper traces

show the input signal V_IN. Lower traces are the resulting output

voltage with the DAC’s digital input set to all 1s. T he circuit

settles to ±0.01% for a 20 V input step in 14 µs.

T he performance of the dual photodiode preamp shown in Fig-

ure 27 is enhanced by the AD648’s low input current, input

voltage offset, and offset voltage drift. Each photodiode sources

a current proportional to the incident light power on its surface.

R_Fconverts the photodiode current to an output voltage equal

to R_F× I_S.

An error budget illustrating the importance of low amplifier in-

put current, voltage offset, and offset voltage drift to minimize

output voltage errors can be developed by considering the

equivalent circuit for the small (0.2 mm²area) photodiode

shown in Figure 27. T he input current results in an error pro-

portional to the feedback resistance used. T he amplifier’s offset

will produce an error proportional to the preamp’s noise gain

(1+R_F/R_SH), where R_SHis the photodiode shunt resistance. T he

amplifier’s input current will double with every 10°C rise in

temperature, and the photodiode’s shunt resistance halves with

every 10°C rise. T he error budget in Figure 28 assumes a room

temperature photodiode R_SHof 500 MΩ, and the maximum in-

put current and input offset voltage specs of an AD648C.

T he capacitance at the amplifier’s negative input (the sum of the

photodiode’s shunt capacitance, the op amp’s differential input

capacitance, stray capacitance due to wiring, etc.) will cause a

rise in the preamp’s noise gain over frequency. T his can result in

excess noise over the bandwidth of interest. C_Freduces the

noise gain “peaking” at the expense of signal bandwidth.

Figure 26a. Response to ±20 V p-p Reference Square

Wave

Figure 26b. Response to ±100 m V p-p Reference Square

Wave

Figure 27. A Dual Photodiode Pre-Am p

TEMP

R_SH

V_OS

I_B

؇C

(M⍀)

(␮V)

(1 + R_F/ R_SH) V_OS

(pA)

I_BR_F

TOTAL

–25

+25

+50

+75

+85

15,970 150

151 ␮V

233 ␮V

360 ␮V

800 ␮V

3.33 m V

6.63 m V

0.30

2.26

10.00

56.6

320

30 ␮V

181 ␮V

2,830

500

225

300

375

450

480

262 ␮V 495 ␮V

1.0 m V 1.36 m V

5.6 m V 6.40 m V

32 m V

64 m V

88.5

15.6

7.8

35.3 m V

70.6 m V

640

Figure 28. Photodiode Pre-Am p Errors Over Tem perature

–8–

REV. C

AD648

INSTRUMENTATIO N AMP LIFIER

Gains of 1 to 100 can be accommodated with gain nonlinearities

of less than 0.01%. T he maximum input current is 30 pA over

the common-mode range, with a common-mode impedance of

over 1 × 10¹²Ω. T he capacitors C1, C2, C3 and C4 compensate

for peaking in the gain over frequency which is caused by input

capacitance.

T he AD648J’s maximum input current of 20 pA per amplifier

makes it an excellent building block for the high input imped-

ance instrumentation amplifier shown in Figure 29. T otal cur-

rent drain for this circuit is under 600 µA. T his configuration is

optimal for conditioning differential voltages from high imped-

ance sources.

T o calibrate this circuit, first adjust trimmer R1 for common-

mode rejection with +10 volts dc applied to the input pins.

Next, adjust R2 for zero offset at V_OUTwith both inputs

grounded. T rim the circuit a second time for optimal

performance.

T he overall gain of the circuit is controlled by R_G, resulting in

the following transfer function:

V_OUT

V_IN

(R3 + R4)

= 1 +

R_G

T he –3 dB small signal bandwidth for this low power instru-

mentation amplifier is 700 kHz for a gain of 1 and 10 kHz for a

gain of 100. T he typical output slew rate is 1.8 V/µs.

Figure 29. Low Power Instrum entation Am plifier

REV. C

–9–

AD648

LO G RATIO AMP LIFIER

which have a positive 3500 ppm/°C temperature coefficient.

Log ratio amplifiers are useful for a variety of signal condition-

ing applications, such as linearizing exponential transducer out-

puts and compressing analog signals having a wide dynamic

range. T he AD648’s picoamp level input current and low input

offset voltage make it a good choice for the front-end amplifier

of the log ratio circuit shown in Figure 30. T his circuit produces

an output voltage equal to the log base 10 of the ratio of the in-

put currents I₁and I₂. Resistive inputs R1 and R2 are provided

for voltage inputs.

T he transfer function for the output voltage is:

V_OUT= 1 V log₁₀(I₂/I₁)

Frequency compensation is provided by R11, R12, C1, and C2.

Small signal bandwidth is approximately 300 kHz at input cur-

rents above 100 µA and will proportionally decrease with lower

signal levels. D1, D2, R13, and R14 compensate for the effects

of the two logging transistors’ ohmic emitter resistance.

T o trim this circuit, set the two input currents to 10 µA and ad-

just V_OUTto zero by adjusting the potentiometer on A3. T hen

set I₂to 1 µA and adjust the scale factor such that the output

voltage is 1 V by trimming potentiometer R10. Offset adjust-

ment for A1 and A2 is provided to increase the accuracy of the

voltage inputs.

Input currents I₁and I₂set the collector currents of Q1 and Q2,

a matched pair of logging transistors. Voltages at points A and B

are developed according to the following familiar diode equation:

V_BE= (kT/q) ln (I_C/I_ES

)

In this equation, k is Boltzmann’s constant, T is absolute tem-

perature, q is an electron charge, and I_ESis the reverse satura-

tion current of the logging transistors. T he difference of these

two voltages is taken by the subtractor section and scaled by a

factor of approximately 16 by resistors R9, R10 and R8. T em-

perature compensation is provided by resistors R8 and R15,

T his circuit ensures a 1% log conformance error over an input

current range of 300 pA to l mA, with low level accuracy limited

by the AD648’s input current. T he low level input voltage accu-

racy of this circuit is limited by the input offset voltage and drift

of the AD648.

Figure 30. Precision Log Ratio Am plifier

–10–

REV. C

AD648

O UTLINE D IMENSIO NS

D imensions shown in inches and (mm).

REV. C

–11–

–12–

AD648SQ [ADI]

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