AD648TH [ADI]

IC DUAL OP-AMP, 1000 uV OFFSET-MAX, 1 MHz BAND WIDTH, MBCY8, HERMETIC SEALED, METAL CAN, TO-99, 8 PIN, Operational Amplifier;


型号：	AD648TH
厂家：	ADI
描述：	IC DUAL OP-AMP, 1000 uV OFFSET-MAX, 1 MHz BAND WIDTH, MBCY8, HERMETIC SEALED, METAL CAN, TO-99, 8 PIN, Operational Amplifier 放大器
文件：	总12页 (文件大小：202K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Dual Precision,

Low Power BiFET Op Amp

AD648

CONNECTION DIAGRAM

FEATURES

DC Performance

Plastic Mini-Dip (N) Package,

Plastic SOIC (R) Package

and

400 ␮A max Quiescent Current

10 pA max Bias Current, Warmed Up (AD648B)

1 ␮V max Offset Voltage (AD648B)

10 ␮V/؇C max Drift (AD648B)

2 ␮V p-p Noise, 0.1 Hz to 10 Hz

AC Performance

CERDIP (Q) Package

1.8 V/␮s Slew Rate

1 MHz Unity Gain Bandwidth

Available in Plastic Mini-DIP, CERDIP, and Plastic SOIC

Packages

MIL-STD-883B Parts Available

Surface Mount (SOIC) Package Available in Tape and

Reel in Accordance with EIA-481A Standard

Single Version: AD548

PRODUCT DESCRIPTION

–55°C to +125°C and the AD648T* grade is available pro-

The AD648 is a matched pair of low power, precision mono-

lithic operational amplifiers. It offers both low bias current

(10 pA max, warmed up) and low quiescent current (400 µA

max) and is fabricated with ion-implanted FET and laser wafer

trimming technologies. Input bias current is guaranteed over the

AD648’s entire common-mode voltage range.

cessed to MIL-STD-883B, Rev. C.

The AD648 is available in an 8-lead plastic mini-DIP,

CERDIP, and SOIC.

*Not for new design, obsolete April 2002.

PRODUCT HIGHLIGHTS

The economical J grade has a maximum guaranteed offset

voltage of less than 2 mV and an offset voltage drift of less than

20 µV/°C. This level of dc precision is achieved using Analog’s

laser wafer drift trimming process. The combination of low

quiescent current and low offset voltage drift minimizes changes

in input offset voltage due to self-heating effects. Five grades are

offered over the commercial, industrial and military temperature

ranges.

1. A combination of low supply current, excellent dc and ac

performance and low drift makes the AD648 the ideal op

amp for high performance, low power applications.

2. The AD648 is pin compatible with industry standard dual

op amps such as the LF442, TL062, and AD642, enabling

designers to improve performance while achieving a reduc-

tion in power dissipation of up to 85%.

3. Guaranteed low input offset voltage (2 mV max) and drift

(20 µV/°C max) for the AD648J are achieved using Analog

Devices’ laser drift trimming technology.

The AD648 is recommended for any dual supply op amp

application requiring low power and excellent dc and ac per-

formance. In applications such as battery-powered, precision

instrument front ends and CMOS DAC buffers, the AD648’s

excellent combination of low input offset voltage and drift, low

bias current, and low 1/f noise reduces output errors. High

common-mode rejection (82 dB, min on the “B” grade) and

high open-loop gain ensures better than 12-bit linearity in high

impedance, buffer applications.

4. Analog Devices specifies each device in the warmed-up

condition, insuring that the device will meet its published

specifications in actual use.

5. Matching characteristics are excellent for all grades. The

input offset voltage matching between amplifiers in the

AD648J is within 2 mV.

The AD648 is pinned out in a standard dual op amp configura-

tion and is available in seven performance grades. The AD648J

and AD648K are rated over the commercial temperature range

of 0°C to 70°C. The AD648 and AD648B are rated over the

industrial temperature range of –40°C to +85°C. The AD648S

and AD648T are rated over the military temperature range of

6. Crosstalk between amplifiers is less than –120 dB at 1 kHz.

REV. E

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

(@ + 25؇C and V = ؎15 V dc, unless otherwise noted.)

AD648–SPECIFICATIONS

AD648J/A/S

Typ

AD648K/B/T

Typ

Model

Min

Max

Min

Max

Unit

INPUT OFFSET VOLTAGE¹

Initial Offset

0.75

2.0

0.3

1.0

_MINto T_MAX

vs. Temperature

vs. Supply

3.0/3.0/3.0

1.5/1.5/2.0

µV/°C

76/76/76

vs. Supply, T_MINto T_MAX

Long-Term Offset Stability

µV/month

INPUT BIAS CURREN

Either Input,²V_CM= 0

Either Input²at T_MAX, V_CM= 0

Max Input Bias Current Over

Common-Mode Voltage Range

Offset Current, V_CM= 0

0.45/1.3/20

0.25/0.65/10

Offset Current at T_MAX

0.25/0.7/10

0.15/0.35/5

MATCHING CHARACTERISTICS³

Input Offset Voltage

Input Offset Voltage T_MINto T_MAX

Input Offset Voltage vs. Temperature

Input Bias Current

1.0

2.0

3.0/3.0/3.0

0.5

1.0

1.5/1.5/2.0

µV/°C

Crosstalk

–120

INPUT IMPEDANCE

Differential

Common Mode

1 × 10^{1 2}ʈ3

3 × 10¹²ʈ3

1 × 10¹²ʈ3

3 × 10¹²ʈ3

ΩʈpF

INPUT VOLTAGE RANGE

Differential⁴

Common Mode

Common-Mode Rejection

V_CM

_MINto T_MAX

V_CM11 V

10 V

76/76/76

T_MINto T_MAX

70/70/70

INPUT VOLTAGE NOISE

Voltage 0.1 Hz to 10 Hz

f = 10 Hz

µV p-p

nV/√Hz

f = 100 Hz

f = 1 kHz

f = 10 kHz

INPUT CURRENT NOISE

f = 1 kHz

1.8

fA/√Hz

FREQUENCY RESPONSE

Unity Gain, Small Signal

Full Power Response

Slew Rate, Unity Gain

Settling Time to 0.01%

0.8

1.0

1.8

0.8

1.0

1.8

MHz

kHz

V/µs

µs

OPEN-LOOP GAIN

V_O

_MINto T_MAX, R_L≥ 10 kΩ

V_O10 V, R_L≥ 5 kΩ

T_MINto T_MAX, R_L≥ 5 kΩ

10 V, R_L≥ 10 kΩ

300

1000

300

150

1000

700

500

300

V/mV

300/300/300 700

150 500

150/150/150 300

REV. E

–2–

AD648

SPECIFICATIONS (Continued)

AD648J/A/S

Typ

AD648K/B/T

Typ

Model

Min

Max

Min

Max

Unit

OUTPUT CHARACTERISTICS

Voltage @ R_L≥ 10 kΩ,

T_MINto T_MAX

Voltage @ R_L≥ 5 kΩ,

T_MINto T_MAX

12/ 12/ 12

11/ 11/ 11

Short Circuit Current

POWER SUPPLY

Rated Performance

Operating Range

4.5

Quiescent Current (Both Amplifiers)

340

400

340

400

µA

TEMPERATURE RANGE

Operating, Rated Performance

Commercial (0°C to 70°C)

Industrial (–40°C to +85°C)

Military (–55°C to +125°C)

AD648J

AD648A

AD648S

AD648K

AD648B

AD648T

PACKAGE OPTIONS

SOIC (R-8)

Plastic (N-8)

CERDIP (Q-8)

Tape and Reel

AD648JR

AD648JN

AD648KR

AD648KN

AD648AQ⁵, AD648SQ⁵

AD648BQ⁵, AD648TQ/883B⁵

AD648JR-REEL, AD648JR-REEL7 AD648KR-REEL, AD648KR-REEL7

NOTES

¹Input Offset Voltage specifications are guaranteed after five minutes of operation at T_A= 25°C.

²Bias Current specifications are guaranteed maximum at either input after five minutes of operation at T_A= 25°C. For higher temperature, the current doubles

every 10°C.

³Matching is defined as the difference between parameters of the two amplifiers.

⁴Defined as voltages between inputs, such that neither exceeds 10 V from ground.

⁵Not for new design. Obsolete April 2002.

Specifications subject to change without notice.

REV. E

–3–

AD648

ABSOLUTE MAXIMUM RATINGS¹

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V

Internal Power Dissipation². . . . . . . . . . . . . . . . . . . . 500 mW

Input Voltage³. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V

Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite

Differential Input Voltage . . . . . . . . . . . . . . . . . . +V_Sand –V_S

Storage Temperature Range (Q, H) . . . . . . . –65°C to +150°C

Storage Temperature Range (N, R) . . . . . . . . –65°C to +125°C

Operating Temperature Range

AD648J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C

AD648A/B . . . . . . . . . . . . . . . . . . . . . . . . . .–40°C to +85°C

AD648S/T . . . . . . . . . . . . . . . . . . . . . . . . .–55°C to +125°C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C

NOTES

¹Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

²Thermal Characteristics:

8-Pin Plastic Package: θ_JA= 165°C/Watt

8-Pin CERDIP Package: θ_JC= 22°C/Watt; θ_JA= 110°C/Watt

8-Pin SOIC Package: θ_JC= 42°C/Wat; θ_JA= 160°C/Watt

³For supply voltages less than 18 V, the absolute maximum input voltage is equal

to the supply voltage.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD648 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–4–

REV. E

Typical Performance Characteristics—AD648

REV. E

–5–

AD648

–6–

REV. E

AD648

APPLICATION NOTES

The AD648 is a pair of JFET-input op amps with a guaranteed

maximum I_Bof less than 10 pA, and offset and drift laser-

trimmed to 1.0 mV and 10 µV/°C, respectively (AD648B). AC

specs include 1 MHz bandwidth, 1.8 V/µs typical slew rate and

8 µs settling time for a 20 V step to 0.01%—all at a supply

current less than 400 µA. To capitalize on the device’s perfor-

mance, a number of error sources should be considered.

Figure 22. Board Layout for Guarding Inputs

INPUT PROTECTION

The AD648 is guaranteed to withstand input voltages equal to

the power supply potential. Exceeding the negative supply volt-

age on either input will forward bias the substrate junction of

the chip. The induced current may destroy the amplifier due to

excess heat.

The minimal power drain and low offset drift of the AD648

reduce self-heating or “warm-up” effects on input offset voltage,

making the AD648 ideal for on/off battery powered applica-

tions. The power dissipation due to the AD648’s 400 µA supply

current has a negligible effect on input current, but heavy out-

put loading will raise the chip temperature. Since a JFET’s

input current doubles for every 10°C rise in chip temperature,

this can be a noticeable effect.

Input protection is required in applications such as a flame

detector in a gas chromatograph, where a very high potential

may be applied to the input terminals during a sensor fault

condition. Figures 23a and 23b show simple current limiting

schemes that can be used. R_PROTECTshould be chosen such that

the maximum overload current is 1.0 mA (for example 100 kΩ

for a 100 V overload).

The amplifier is designed to be functional with power supply

voltages as low as 4.5 V. It will exhibit a higher input offset

voltage than at the rated supply voltage of 15 V, due to power

supply rejection effects. Common-mode range extends from 3 V

more positive than the negative supply to 1 V more negative

than the positive supply. Designed to cleanly drive up to 10 kΩ

and 100 pF loads, the AD648 will drive a 2 kΩ load with reduced

open-loop gain.

Figure 21 shows the recommended crosstalk test circuit. A

typical value for crosstalk is –120 dB at 1 kHz.

Figure 23a. Input Protection of l-to-V Converter

Figure 21. Crosstalk Test Circuit

LAYOUT

To take full advantage of the AD648’s 10 pA max input current,

parasitic leakages must be kept below an acceptable level. The

practical limit of the resistance of epoxy or phenolic circuit

board material is between 1 × 10¹²Ω and 3 × 10¹²Ω. This can

result in an additional leakage of 5 pA between an input of 0 V

and a –15 V supply line. Teflon or a similar low leakage material

(with a resistance exceeding 10¹⁷Ω) should be used to isolate

high impedance input lines from adjacent lines carrying high

voltages. The insulator should be kept clean, since contaminants

will degrade the surface resistance.

Figure 23b. Voltage Follower Input Protection Method

Figure 23b shows the recommended method for protecting a

voltage follower from excessive currents due to high voltage

breakdown. The protection resistor, R_P, limits the input current.

A nominal value of 100 kΩ will limit the input current to less

than 1 mA with a 100 volt input voltage applied.

The stray capacitance between the summing junction and

ground will produce a high-frequency roll-off with a corner

frequency equal to:

A metal guard completely surrounding the high impedance

nodes and driven by a voltage near the common-mode input

potential can also be used to reduce some parasitic leakages.

The guarding pattern in Figure 22 will reduce parasitic leakage

due to finite board surface resistance; but it will not compensate

for a low volume resistivity board.

f_corner

2 π R_PC_stray

Accordingly, a 100 kΩ value for R_Pwith a 3 pF C_straywill cause

a 3 dB corner frequency to occur at 531 kHz.

REV. E

–7–

AD648

Figure 23c shows a diode clamp protection scheme for an I-to-V

converter using low leakage diodes. Because the diodes are

connected to the op amp’s summing junction, which is a virtual

ground, their leakage contribution is minimal.

CMOS DAC’s output current to a voltage and provides the

necessary level shifting to achieve a bipolar voltage output. The

circuit operates with a 12-bit plus sign input code. The transfer

function is shown in Figure 25.

The AD7592 is a fully protected dual CMOS SPDT switch with

data latches. R4 and R5 should match to within 0.01% to main-

tain the accuracy of the converter. A mismatch between R4 and

R5 introduces a gain error. Overall gain is trimmed by adjusting

R_IN. The AD648’s low input offset voltage, low drift over tem-

perature, and excellent dynamics make it an attractive low

power output buffer.

The input offset voltage of the AD648 output amplifier results

in an output error voltage. This error voltage equals the input

offset voltage of the op amp times the noise gain of the amplifier.

Figure 23c. I-to-V Converter with Diode Input Protection

Exceeding the negative common-mode range on either input

terminal causes a phase reversal at the output, forcing the ampli-

fier output to the corresponding high or low state. Exceeding

the negative common mode on both inputs simultaneously

forces the output high. Exceeding the positive common-mode

range on a single input does not cause a phase reversal; but if

both inputs exceed the limit, the output will be forced high. In

all cases, normal amplifier operation is resumed when input

voltages are brought back within the common-mode range.

That is:

R_O



_FB

V_OSOutput = V_OSInput 1+





R_FBis the feedback resistor for the op amp, which is internal to

the DAC. R_Ois the DAC’s R-2R ladder output resistance. The

value of R_Ois code dependent. This has the effect of changing

the offset error voltage at the amplifier’s output. An output

amplifier with a sub millivolt input offset voltage is needed to

preserve the linearity of the DAC’s transfer function.

D/A CONVERTER BIPOLAR OUTPUT BUFFER

The circuit in Figure 24 provides 4 quadrant multiplication with

a resolution of 12 bits. The AD648 is used to convert the AD7545

Figure 24. 12-Bit Plus Sign Magnitude D/A Converter

SIGN BIT BINARY NUMBER IN DAC REGISTER ANALOG OUTPUT

1111 1111 1111

0000 0000 0000

1111 1111 1111

+V_IN

(4095/4096)

0 V

–V_IN

(4095/4096)

NOTE

SIGN BIT AT “0“ CONNECTS THE NONINVERTING INPUT OF

A2 TO ANALOG COMMON

Figure 25. Sign Magnitude Code Table

–8–

REV. E

AD648

DUAL PHOTODIODE PREAMP

The AD648 in this configuration provides a 700 kHz small signal

bandwidth and 1.8 V/µs typical slew rate. The 33 pF capacitor

across the feedback resistor optimizes the circuit’s response. The

oscilloscope photos in Figures 26a and 26b show small and

large signal outputs of the circuit in Figure 24. Upper traces

show the input signal V_IN. Lower traces are the resulting output

voltage with the DAC’s digital input set to all 1s. The circuit

settles to 0.01% for a 20 V input step in 14 µs.

The performance of the dual photodiode preamp shown in

Figure 27 is enhanced by the AD648’s low input current, input

voltage offset, and offset voltage drift. Each photodiode sources

a current proportional to the incident light power on its surface.

R_Fconverts the photodiode current to an output voltage equal

to R_F× I_S.

An error budget illustrating the importance of low amplifier

input current, voltage offset, and offset voltage drift to minimize

output voltage errors can be developed by considering the

equivalent circuit for the small (0.2 mm²area) photodiode

shown in Figure 27. The input current results in an error pro-

portional to the feedback resistance used. The amplifier’s offset

will produce an error proportional to the preamp’s noise gain

(1+R_F/R_SH), where R_SHis the photodiode shunt resistance. The

amplifier’s input current will double with every 10°C rise in

temperature, and the photodiode’s shunt resistance halves with

every 10°C rise. The error budget in Figure 28 assumes a room

temperature photodiode R_SHof 500 MΩ, and the maximum

input current and input offset voltage specs of an AD648C.

The capacitance at the amplifier’s negative input (the sum of the

photodiode’s shunt capacitance, the op amp’s differential input

capacitance, stray capacitance due to wiring, etc.) will cause a

rise in the preamp’s noise gain over frequency. This can result in

excess noise over the bandwidth of interest. C_Freduces the

noise gain “peaking” at the expense of signal bandwidth.

Figure 26a. Response to 20 V p-p Reference Square

Wave

Figure 26b. Response to 100 mV p-p Reference Square

Wave

Figure 27. A Dual Photodiode Pre-Amp

TEMP

؇C

R_SH

(M⍀)

V_OS

(␮V)

I_B

(pA)

(1 + R_F/R_SH) V_OS

I_BR_F

TOTAL

–25

+25

+50

+75

+85

15,970 150

151 ␮V

233 ␮V

360 ␮V

800 ␮V

3.33 mV

6.63 mV

0.30

2.26

10.00

56.6

320

30 ␮V

181 ␮V

2,830

500

225

300

375

450

480

262 ␮V 495 ␮V

1.0 mV 1.36 mV

5.6 mV 6.40 mV

32 mV

64 mV

88.5

15.6

7.8

35.3 mV

70.6 mV

640

Figure 28. Photodiode Pre-Amp Errors Over Temperature

REV. E

–9–

AD648

INSTRUMENTATION AMPLIFIER

the common-mode range, with a common-mode impedance of

over 1 × 10¹²Ω. The capacitors C1, C2, C3 and C4 compensate

for peaking in the gain over frequency which is caused by input

capacitance.

The AD648J’s maximum input current of 20 pA per amplifier

makes it an excellent building block for the high input impedance

instrumentation amplifier shown in Figure 29. Total current

drain for this circuit is under 600 µA. This configuration is

optimal for conditioning differential voltages from high imped-

ance sources.

To calibrate this circuit, first adjust trimmer R1 for common-

mode rejection with 10 V dc applied to the input pins. Next,

adjust R2 for zero offset at V_OUTwith both inputs grounded.

Trim the circuit a second time for optimal

The overall gain of the circuit is controlled by R_G, resulting in

the following transfer function:

performance.

The –3 dB small signal bandwidth for this low power instru-

mentation amplifier is 700 kHz for a gain of 1 and 10 kHz for a

gain of 100. The typical output slew rate is 1.8 V/µs.

V_OUT

V_IN

(R3 + R4)

= 1+

R_G

Gains of 1 to 100 can be accommodated with gain nonlinearities

of less than 0.01%. The maximum input current is 30 pA over

Figure 29. Low Power Instrumentation Amplifier

–10–

REV. E

AD648

LOG RATIO AMPLIFIER

which have a positive 3500 ppm/°C temperature coefficient.

Log ratio amplifiers are useful for a variety of signal conditioning

applications, such as linearizing exponential transducer outputs

and compressing analog signals having a wide dynamic range.

The AD648’s picoamp level input current and low input offset

voltage make it a good choice for the front end amplifier of the

log ratio circuit shown in Figure 30. This circuit produces an

output voltage equal to the log base 10 of the ratio of the input

currents I₁and I₂. Resistive inputs R1 and R2 are provided

for voltage inputs.

The transfer function for the output voltage is:

V_OUT= 1 V log₁₀(I₂/I₁)

Frequency compensation is provided by R11, R12, C1, and C2.

Small signal bandwidth is approximately 300 kHz at input cur-

rents above 100 µA and will proportionally decrease with lower

signal levels. D1, D2, R13, and R14 compensate for the effects

of the two logging transistors’ ohmic emitter resistance.

To trim this circuit, set the two input currents to 10 µA and

adjust V_OUTto zero by adjusting the potentiometer on A3. Then

set I₂to 1 µA and adjust the scale factor such that the output

voltage is 1 V by trimming potentiometer R10. Offset adjust-

ment for A1 and A2 is provided to increase the accuracy of the

voltage inputs.

Input currents I₁and I₂set the collector currents of Q1 and Q2,

a matched pair of logging transistors. Voltages at points A and B

are developed according to the following familiar diode equation:

V_BE= (kT/q) ln (I_C/I_ES)

In this equation, k is Boltzmann’s constant, T is absolute

temperature, q is an electron charge, and I_ESis the reverse

saturation current of the logging transistors. The difference of

these two voltages is taken by the subtractor section and scaled

by a factor of approximately 16 by resistors R9, R10, and R8.

Temperature compensation is provided by resistors R8 and

R15,

This circuit ensures a 1% log conformance error over an input

current range of 300 pA to l mA, with low level accuracy limited

by the AD648’s input current. The low level input voltage accu-

racy of this circuit is limited by the input offset voltage and drift

of the AD648.

Figure 30. Precision Log Ratio Amplifier

REV. E

–11–

AD648

OUTLINE DIMENSIONS

Mini-DIP (N) Package

Dimensions shown in inches and (millimeters)

CERDIP (Q) Package

Dimensions shown in inches and (millimeters)

8-Lead SOIC (R) Package

Dimensions shown in millimeters and (inches)

5.00 (0.1968)

4.80 (0.1890)

6.20 (0.2440)

5.80 (0.2284)

0.1574 (4.00)

0.1497 (3.80)

PIN 1

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

BSC

45؇

1.75 (0.0688)

1.35 (0.0532)

COPLANARITY

0.25 (0.0098)

0.10 (0.0040)

8؇

0؇ 1.27 (0.0500)

0.51 (0.0201)

0.33 (0.0130)

0.25 (0.0098)

0.19 (0.0075)

SEATING

PLANE

0.41 (0.0160)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-012 AA

Revision History

Location

Page

Data Sheet changed from REV. C to REV. E.

Change to SOIC (R-8) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Deleted Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Deleted AD648C column from SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Deleted METALIZATION PHOTOGRAPH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Deleted Metal Can from Figure 22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Deleted TO-99 (H) from OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

–12–

REV. E

AD648TH [ADI]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E