AD652SE/883B2_技术文档

Monolithic Synchronous

Voltage-to-Frequency Converter

AD652

The AD652 is available in five performance grades. The 20-lead

PLCC-packaged JP and KP grades are specified for operation

over the 0°C to +70°C commercial temperature range. The

16-lead CERDIP-packaged AQ and BQ grades are specified for

operation over the −40°C to +85°C industrial temperature

range. The AD652SQ is available for operation over the full

−55°C to +125°C extended temperature range.

FEATURES

Full-scale frequency (up to 2 MHz) set by external system

clock

Extremely low linearity error (0.005% max at 1 MHz FS,

0.02% max at 2 MHz FS)

No critical external components required

Accurate 5 V reference voltage

Low drift (25 ppm/°C max)

Dual- or single-supply operation

Voltage or current input

MIL-STD-883 compliant versions available

PRODUCT HIGHLIGHTS

1. The use of an external clock to set the full-scale frequency

allows the AD652 to achieve linearity and stability far

superior to other monolithic VFCs. By using the same clock

to drive the AD652 and set the counting period (through a

suitable divider), conversion accuracy is maintained

independent of variations in clock frequency.

PRODUCT DESCRIPTION

The AD652 synchronous voltage-to-frequency converter

(SVFC) is a powerful building block for precision analog-to-

digital conversion, offering typical nonlinearity of 0.002%

(0.005% maximum) at a 100 kHz output frequency. The inher-

ent monotonicity of the transfer function and wide range of

clock frequencies allow the conversion time and resolution to

be optimized for specific applications.

2. The AD652 synchronous VFC requires only one external

component (a noncritical integrator capacitor) for

operation.

3. The AD652 includes a buffered, accurate 5 V reference.

4. The AD652’s clock input is TTL and CMOS compatible and

can also be driven by sources referred to the negative power

supply. The flexible open-collector output stage provides

sufficient current sinking capability for TTL and CMOS

logic, as well as for optical couplers and pulse transformers.

A capacitor-programmable one-shot is provided for selec-

tion of optimum output pulse width for power reduction.

The AD652 uses a variation of the charge-balancing technique

to perform the conversion function. The AD652 uses an

external clock to define the full-scale output frequency, rather

than relying on the stability of an external capacitor. The result

is a more stable, more linear transfer function, with significant

application benefits in both single- and multichannel systems.

Gain drift is minimized using a precision low drift reference

and low TC, on-chip, thin-film scaling resistors. Furthermore,

initial gain error is reduced to less than 0.5% by the use of laser-

wafer-trimming.

5. The AD652 can also be configured for use as a synchronous

F/V converter for isolated analog signal transmission.

6. The AD652 is available in versions compliant with

MILSTD-883. Refer to the Analog Devices Military

Products Databook or current AD652/883B data sheet for

detailed specifications.

The analog and digital sections of the AD652 have been

designed to allow operation from a single-ended power source,

simplifying its use with isolated power supplies.

FUNCTIONAL BLOCK DIAGRAM

CLOCK IN

R

IN

COMPARATOR

C

INT

D FLOP

LATCH

V

IN

ONE

SHOT

CK

Q

G

Q

D

AND

INTEGRATOR

C

OS

5V

H

L

1mA

–V

S

Figure 1.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

AD652

TABLE OF CONTENTS

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Definitions of Specifications....................................................... 5

Theory of Operation ........................................................................ 6

Overrange...................................................................................... 8

SVFC Connection for Dual Supply, Positive Input Voltages .. 9

SVFC Connections for Negative Input Voltages ...................... 9

SVFC Connection for Bipolar Input Voltages ........................ 10

PLCC Connections..................................................................... 11

Gain and Offset Calibration...................................................... 11

Gain Performance ...................................................................... 12

Reference Noise .......................................................................... 12

Digital Interfacing Considerations........................................... 12

Component Selection ................................................................ 12

Digital Ground............................................................................ 13

Single-Supply Operation ........................................................... 14

Frequency-to-Voltage Converter ............................................. 15

Decoupling and Grounding...................................................... 16

Frequency Output Multiplier.................................................... 17

Single-Line Multiplexed Data Transmission .......................... 18

Isolated Front End...................................................................... 22

A-to-D Conversion .................................................................... 22

Delta Modulator ......................................................................... 23

Bridge Transducer Interface...................................................... 24

Outline Dimensions....................................................................... 25

Ordering Guide............................................................................... 26

REVISION HISTORY

5/04—Data Sheet Changed from Rev. B to Rev. C

Updated Format..............................................................Universal

Changes to Gain and Offset Calibration section.................... 11

Updated Outline Dimensions................................................... 25

Changes to Ordering Guide ...................................................... 26

2/00—Data Sheet Changed from Rev. A to Rev. B

Rev. C | Page 2 of 28

AD652

SPECIFICATIONS

Typical @ T_A= 25°C, V_S= 15 V, unless otherwise noted. Specifications in boldface are 100% tested at final test and are used to measure

outgoing quality levels.

Table 1.

AD652JP/AQ/SQ

AD652KP/BQ

Parameter

Min

Typ

Max

Min

Typ

Max

Unit

VOLTAGE-TO-FREQUENCY MODE

Gain Error

f_CLOCK= 200 kHz

f_CLOCK= ± MHz

f_CLOCK= 4 MHz

±0.ꢀ

±±

1

1.5

±0.2ꢀ

±0.ꢀ

0.5

0.75

%

Gain Temperature Coefficient

f_CLOCK= 200 kHz

f_CLOCK= ± MHz

±2ꢀ

±±0

±2ꢀ

0.00±

±ꢀ0

50

75

0.01

±±ꢀ

±±0

±±ꢀ

0.00±

±2ꢀ

25

30

50

0.01

ppm/°C

ppm/°C^±

ppm/°C

%/V

f_CLOCK= 4 MHz

Power Supply Rejection Ratio

Linearity Error

f_CLOCK= 200 kHz

f_CLOCK= ± MHz

f_CLOCK= 2 MHz

f_CLOCK= 4 MHz

Offset (Transfer Function, RTI)

Offset Temperature Coefficient

Response Time

±0.002

±0.0±

±0.02

± ±

±0.02

0.02

±0.02

0.05

3

±0.002

±0.0±

±±

±0.00ꢀ

0.005

±0.00ꢀ

0.02

2

%

mV

µV/°C

±±0

50

25

One Period of New Output Frequency Plus One Clock Period.

FREQUENCY-TO-VOLTAGE MODE

Gain Error, f_IN= ±00 kHz FS

Linearity Error, f_IN= ±00 kHz FS

INPUT RESISTORS

±0.ꢀ

±0.002

±±

±0.02

±0.2ꢀ

±0.002

±0.ꢀ

±0.0±

%

CERDIP (Figure 2)(0 to ±0 V FS Range)

PLCC (Figure 3)

±9.8

20

20.2

±9.8

20

20.2

kΩ

Pin 8 to Pin 7

9.9

±9.8

±ꢀ.8

±9.8

±0

20

±6

20

±ꢀ0

±0.±

20.2

±6.2

20.2

100

9.9

±9.8

±ꢀ.8

±9.8

±0

20

±6

20

±ꢀ0

±0.±

20.2

±6.2

20.2

100

kΩ

ppm/°C

Pin 7 to Pin ꢀ (0 V to ꢀ V FS Range)

Pin 8 to Pin ꢀ (0 V to ±0 V FS Range)

Pin 9 to Pin ꢀ (0 V to 8 V FS Range)

Pin ±0 to Pin ꢀ (Auxiliary Input)

Temperature Coefficient (All)

INTEGRATOR OP AMP

Input Bias Current

Inverting Input (Pin ꢀ)

Noninverting Input (Pin 6)

Input Offset Current

Input Offset Current Drift

Input Offset Voltage

±ꢀ

20

±

±±

±±0

86

±ꢀ

20

±

±±

±±0

86

nA

nA/°C

mV

µV/°C

dB

20

50

70

3

±2ꢀ

20

50

70

2

±±ꢀ

Input Offset Voltage Drift

Open-Loop Gain

Common-Mode Input Range

CMRR

–V_S+ ꢀ

80

+V_S– ꢀ

–V_S+ ꢀ

80

+V_S– ꢀ

V

dB

Bandwidth

Output Voltage Range

(Referred to Pin 6, R± > = ꢀ kΩ)

±4

−1

9ꢀ

±4

9ꢀ

(+V_S− 4)

MHz

V

(+V_S− 4)

−1

Rev. C | Page 3 of 28

AD652

AD652JP/AQ/SQ

AD652KP/BQ

Parameter

Min

Typ

Max

Min

Typ

Max

Unit

COMPARATOR

Input Bias Current

Common-Mode Voltage

CLOCK INPUT

Maximum Frequency

Threshold Voltage (Referred to Pin ±2)

T_MINto T_MAX

0.ꢀ

ꢀ

0.ꢀ

ꢀ

µA

V

−V_S+ 4

4

+ V_S− 4

−V_S+ 4

4

+V_S− 4

ꢀ

±.2

ꢀ

±.2

MHz

V

0.8

2.0

0.8

2.0

Input Current

(−V_S< V_CLK< +V_S)

Voltage Range

Rise Time

ꢀ

µA

V

µs

20

+V_S

2

20

+V_S

2

−V_S

OUTPUT STAGE

V_OL(I_OUT= ±0 mA)

I_OL

V

0.4

V_OL< 0.8 V

mA

µA

ns

pF

15

8

10

250

15

8

10

250

V_OL< 0.4 V, T_MINto T_MAX

I_OH(Off Leakage)

Delay Time, Positive Clock Edge to Output Pulse

Fall Time (Load = ꢀ00 pF and I_SINK= ꢀ mA)

Output Capacitance

OUTPUT ONE-SHOT

Pulse Width, t_OS

0.0±

200

±00

ꢀ

0.0±

200

±00

ꢀ

150

C_OS= 300 pF

C_OS= ±000 pF

±.ꢀ

ꢀ

±

4

±.ꢀ

ꢀ

µs

1

4

2

6

2

6

REFERENCE OUTPUT

Voltage

Drift

ꢀ.0

V

4.950

5.050

100

4.975

5.025

50

ppm/°C

Output Current

Source T_MINto T_MAX

Sink

mA

µA

10

±00

10

±00

ꢀ00

Power Supply Rejection

Supply Range = ±±2.ꢀ V to ±±7.ꢀ V

Output Impedance (Sourcing Current)

POWER SUPPLY

0.0±ꢀ

2

0.0±ꢀ

2

%/V

Ω

0.3

Rated Voltage

Operating Range

Dual Supply

Single Supply (−V_S= 0)

Quiescent Current

Digital Common

Analog Common

TEMPERATURE RANGE

Specified Performance

JP, KP Grade

±±ꢀ

±±±

±±ꢀ

±±±

V

±6

+±2

±±8

+36

15

+V_S− 4

+V_S

±6

+±2

±±8

+36

15

+V_S− 4

+V_S

V

mA

V

−V_S

–V_S

−V_S

0

−40

−ꢀꢀ

+70

+8ꢀ

+±2ꢀ

0

−40

+70

+8ꢀ

°C

AQ, BQ Grade

SQ Grade

^±Referred to internal V_REF. In PLCC package, tested on ±0 V input range only.

Rev. C | Page 4 of 28

AD652

ABSOLUTE MAXIMUM RATINGS

Table 2.

Stresses above those listed under Absolute Maximum Ratings

Parameter

Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Total Supply Voltage +V_Sto −V_S

Maximum Input Voltage (Figure 6)

36 V

Maximum Output Current

(Open Collector Output)

ꢀ0 mA

Amplifier Short-Circuit to Ground

Storage Temperature Range: CERDIP

Storage Temperature Range: PLCC

Indefinite

−6ꢀ°C to +±ꢀ0°C

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Table 3. Pin Configurations

DEFINITIONS OF SPECIFICATIONS

Pin No.

Q-16 Package

P-20A Package

NC

Gain Error

±

+V_S

2

3

4

ꢀ

6

7

8

9

±0

±±

±2

±3

±4

±ꢀ

±6

±7

±8

±9

20

TRIM

+V_S

NC

The gain of a voltage-to-frequency converter is the scale factor

setting that provides the nominal conversion relationship, e.g.,

1 MHz full scale. The gain error is the difference in slope

between the actual and ideal transfer functions for the V-F

converter.

OP AMP OUT

OP AMP “−“

OP AMP “+”

±0 VOLT INPUT

−V_S

OP AMP OUT

OP AMP “−“

OP AMP “+”

ꢀ VOLT INPUT

±0 VOLT INPUT

8 VOLT INPUT

OPTIONAL ±0 V INPUT

−V_S

Linearity Error

C_OS

The linearity error of a V-F is the deviation of the actual

transfer function from a straight line passing through the

endpoints of the transfer function.

CLOCK INPUT

FREQ OUT

DIGITAL GND

ANALOG GND

COMP “−“

COMP “+”

COMP REF

C_OS

CLOCK INPUT

FREQ OUT

DIGITAL GND

ANALOG GND

COMP “−“

COMP “+”

NC

Gain Temperature Coefficient

The gain temperature coefficient is the rate of change in full-

scale frequency as a function of the temperature from +25°C to

T_MINor T_MAX

.

COMP REF

Rev. C | Page ꢀ of 28

AD652

THEORY OF OPERATION

A synchronous VFC is similar to other voltage-to-frequency

converters in that an integrator is used to perform a charge-

balance of the input signal with an internal reference current.

However, rather than using a one-shot as the primary timing

element, which requires a high quality and low drift capacitor, a

synchronous voltage-to-frequency converter (SVFC) uses an

external clock. This allows the designer to determine the system

stability and drift based upon the external clock selected. A

crystal oscillator may also be used if desired.

3

2

1

20

19

AD652

SYNCHRONOUS

VOLTAGE-TO-FREQUENCY

CONVERTER

5V

REFERENCE

OP AMP OUT

OP AMP "–"

OP AMP "+"

5V INPUT

4

5

6

7

8

18 COMP "+"

17 COMP "–"

"D"

FLOP

Q

D

16 ANALOG GND

15 DIGITAL GND

14 FREQ OUT

AND

The SVFC architecture provides other system advantages

besides low drift. If the output frequency is measured by

counting pulses gated to a signal that is derived from the clock,

the clock stability is unimportant and the device simply

performs as a voltage-controlled frequency divider, producing a

high resolution A/D. If a large number of inputs must be

monitored simultaneously in a system, the controlled timing

relationship between the frequency output pulses and the user-

supplied clock greatly simplifies this signal acquisition. Also, if

the clock signal is provided by a VFC, the output frequency of

the SVFC is proportional to the product of the two input

voltages. Therefore, multiplication and A-to-D conversion on

two signals are performed simultaneously.

10kΩ

Q

CK

10kΩ

ONE

SHOT

1mA

16kΩ

10V INPUT

4kΩ

9

10

11

12

13

NC = NO CONNECT

Figure 3. PLCC Pin Configuration

Figure 4 shows the typical up-and-down ramp integrator output

of a charge-balance VFC. After the integrator output has

crossed the comparator threshold and the output of the AND

gate has gone high, nothing happens until a negative edge of the

clock comes along to transfer the information to the output of

the D FLOP. At this point, the clock level is low, so the latch does

not change state. When the clock returns high, the latch output

goes high and drives the switch to reset the integrator; at the

same time, the latch drives the AND gate to a low output state.

On the very next negative edge of the clock, the low output state

of the AND gate is transferred to the output of the D FLOP.

When the clock returns high, the latch output goes low and

drives the switch back into the Integrate mode. At the same

time, the latch drives the AND gate to a mode where it

truthfully relays the information presented to it by the

comparator.

AD652

SYNCHRONOUS

VOLTAGE-TO-

5V

+V

1

2

3

4

5

6

7

8

FREQUENCY

CONVERTER

16 COMP REF

15 COMP "+"

S

REFERENCE

TRIM

14 COMP "–"

OP AMP OUT

OP AMP "–"

OP AMP "+"

10 VOLT INPUT

13 ANALOG GND

12 DIGITAL GND

11 FREQ OUT

10 CLOCK INPUT

ONE

SHOT

20kΩ

1mA

Q

CK

–V

S

9

C

OS

D

AND

"D"

Q

FLOP

Figure 2. CERDIP Pin Configuration

The pinouts of the AD652 SVFC are shown in Figure 2 and

Figure 3. A block diagram of the device configured as an SVFC,

along with various system waveforms, is shown in Figure 4.

Because the reset pulses applied to the integrator are exactly one

clock period long, the only place where drift can occur is in a

variation of the symmetry of the switching speed with

temperature.

Since each reset pulse is identical, the AD652 SVFC produces a

very linear voltage-to-frequency transfer relation. Also, because

all reset pulses are gated by the clock, there are no problems

with dielectric absorption causing the duration of a reset pulse

to be influenced by the length of time since the last reset.

Rev. C | Page 6 of 28

AD652

CLOCK IN

D FLOP

R

IN

COMPARATOR

C

INT

LATCH

V

IN

ONE

SHOT

CK

Q

G

Q

D

AND

INTEGRATOR

C

OS

5V

H

L

1mA

–V

S

INTEGRATOR

OUTPUT

THRESHOLD

CLOCK

COMPARATOR

OUT

AND

OUT

D FLOP

OUT

LATCH

OUT

FREQ

OUT

t_OS

Figure 4. Block Diagram and System Waveforms

Figure 4 shows that the period between output pulses is

constrained to be an exact multiple of the clock period.

Consider an input current of exactly one quarter the value of

the reference current. In order to achieve a charge balance, the

output frequency equals the clock frequency divided by four:

one clock period for reset and three clock periods of integrate.

This is shown in Figure 5. If the input current is increased by a

very small amount, the output frequency should also increase

by a very small amount. Initially, however, no output change is

observed for a very small increase in the input current. The

output frequency continues to run at one quarter of the clock,

delivering an average of 250 µA to the summing junction. Since

the input current is slightly larger than this, charge accumulates

in the integrator and the sawtooth signal starts to drift down-

ward. As the integrator sawtooth drifts down, the comparator

threshold is crossed earlier and earlier in each successive cycle,

until finally, a whole cycle is lost. When the cycle is lost, the

integrate phase lasts for two periods of the clock instead of the

usual three periods. Thus, among a long string of divide-by-

fours, an occasional divide-by-three occurs; the average of the

output frequency is very close to one quarter of the clock, but

the instantaneous frequency can be very different.

INTEGRATOR

OUT

THRESHOLD

CLOCK

Figure 5. Integrator Output for I_IN= 250 µA

Because of this, it is very difficult to observe the waveform on

an oscilloscope. During all of this time, the signal at the output

of the integrator is a sawtooth wave with an envelope that is also

a sawtooth. See Figure 6.

200µs/BOX

C

INT

100µs/BOX

FREQ OUT

10µs/BOX

CLOCK IN

10µs/BOX

Figure 6. Integrator Output for I_INSlightly Greater than 250 µs

Rev. C | Page 7 of 28

AD652

Another way to view this is that the output is a frequency of

approximately one-quarter of the clock that has been phase

modulated. A constant frequency can be thought of as

The result of this synchronism is that the rate at which data may

be extracted from the series bit stream produced by the SVFC is

limited. The output pulses are typically counted during a fixed

gate interval and the result is interpreted as an average

frequency. The resolution of such a measurement is determined

by the clock frequency and the gate time. For example, if the

clock frequency is 4 MHz and the gate time is 4.096 ms, a

maximum count of 8,192 is produced by a full-scale frequency

of 2 MHz. Thus, the resolution is 13 bits.

accumulating phase linearly with time at a rate equal to 2πf

radians per second. Therefore, the average output frequency,

which is slightly in excess of a quarter of the clock, requires

phase accumulation at a certain rate. However, since the SVFC

is running at exactly one-quarter of the clock, it does not

accumulate enough phase (see Figure 7). When the difference

between the required phase (average frequency) and the actual

phase equals 2π, a step-in phase is taken where the deficit is

made up instantaneously. The output frequency is then a steady

carrier that has been phase modulated by a sawtooth signal (see

Figure 7). The period of the sawtooth phase modulation is the

time required to accumulate a 2π difference in phase between

the required average frequency and one quarter of the clock

frequency. The sawtooth phase modulation amplitude is 2π.

OVERRANGE

Since each reset pulse is only one clock period in length, the

full-scale output frequency is equal to one-half the clock

frequency. At full scale, the current steering switch spends half

of the time on the summing junction; thus, an input current of

0.5 mA can be balanced. In the case of an overrange, the output

of the integrator op amp drifts in the negative direction and the

output of the comparator remains high. The logic circuits

simply settle into a divide-by-two of the clock state.

PHASE

2

π

EXPECTED

PHASE

2

ACTUAL PHASE

TIME

φ

MOD (t)

2π

V

(t) = COS (2π × f_AVE× t + φMOD (t))

OUT

AVERAGE

CARRIER FREQUENCY

PHASE

MODULATION

Figure 7. Phase Modulation

Rev. C | Page 8 of 28

AD652

the AD652 is specified for a 0 V to 10 V input range using the

SVFC CONNECTION FOR DUAL SUPPLY, POSITIVE

INPUT VOLTAGES

internal 20 kΩ resistor. If a current input is used, the gain drift is

degraded by a maximum of 100 ppm/°C (the TC of the 20 kΩ

resistor). If an external resistor is connected to Pin 5 to establish

a different input voltage range, drift is induced to the extent that

the external resistor’s TC differs from the TC of the internal

resistor. The external resistor used to establish a different input

voltage range should be selected to provide a full-scale current

of 0.5 mA (i.e., 10 kΩ for 0 V to 5 V).

Figure 8 shows the AD652 connection scheme for the

traditional dual supply, positive input mode of operation. The

V_Srange is from 6 V to 18 V. When +V_Sis lower than 9.0 V,

As shown in Figure 8, three additional connections are required

The first connection is to short Pin 13 to Pin 8 (Analog Ground

to −V_S) and add a pull-up resistor to +V_S(as shown in

Figure 21). The pull-up resistor is determined by the following

equation:

SVFC CONNECTIONS FOR NEGATIVE INPUT

VOLTAGES

2V_S−5 V

R_PULLUP

=

Voltages that are negative with respect to ground may be used

as the input to the AD652 SVFC. In this case, Pin 7 is grounded

and the input voltage is applied to Pin 6 (see Figure 9). In this

mode, the input voltage can go as low as 4 V above −V_S. In this

configuration, the input is a high impedance, and only the

20 nA (typical) input bias current of the op amp must be

supplied by the input signal. This is contrasted with the more

usual positive input voltage configuration, which has a 20 kΩ

input impedance and requires 0.5 mA from the signal source.

500µA

These connections ensure proper operation of the 5 V reference.

Tie Pin 16 to Pin 6 (as shown in Figure 21) to ensure that the

integrator output ramps down far enough to trip the

comparator.

The CERDIP-packaged AD652 accepts either a 0 V to 10 V or

0 mA to 0.5 mA full-scale input signal. The temperature drift of

+V

S

AD652

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

5V

1

2

3

4

5

6

7

8

16

15

14

REFERENCE

13

12

11

10

9

ANALOG

GND

C

INT

–

DIGITAL

GND

ONE

SHOT

R

L

5V

FREQ

OUT

V

+

IN

20kΩ

1mA

CLOCK

Q

CK

"D"

+V

–V

S

D

AND

Q FLOP

Figure 8. Standard V/F Connection for Positive Input Voltage with Dual Supply

+V

S

AD652

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

5V

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

REFERENCE

ANALOG

GND

C

INT

DIGITAL

GND

ONE

SHOT

R

L

5V

–

FREQ

OUT

V

IN

20kΩ

+

1mA

CLOCK

Q

CK

+V

S

D

AND

"D"

FLOP

–V

Q

S

Figure 9. Negative Voltage Input

Rev. C | Page 9 of 28

AD652

+V

S

AD652

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

5V

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

REFERENCE

20kΩ

ANALOG

GND

C

INT

DIGITAL

GND

ONE

SHOT

R

L

5V

V

IN

FREQ

OUT

20kΩ

±5V

1mA

CLOCK

Q

CK

D

AND

C

"D"

FLOP

OS

–V

Q

S

Figure 10. Bipolar Offset

SVFC CONNECTION FOR BIPOLAR INPUT VOLTAGES

V

REF

A bipolar input voltage of ±± V can be accommodated by

injecting a 2±0 µA current into Pin ± (see Figure 10). A −± V

signal provides a zero sum current at the integrator summing

junction, which results in a zero-output frequency; a +± V signal

provides a 0.± mA (full-scale) sum current, which results in the

full-scale output frequency.

F

OUT

R

OS

R

IN

V

IN

IDEAL

TRANSFER

RELATION

F

ZERO

V

IN

–5V

+5V

Using an external resistor to inject the offset current has some

effect on the bipolar offset temperature coefficient. The ideal

transfer curve with bipolar inputs is shown in Figure 11. The

user actually has four options to use in injecting the bipolar

offset current into the inverting input of the op amp:

V

ZERO

Figure 11. Ideal Bipolar Input Transfer Curve over Temperature

F

OUT

CASE 1

R

∼

OS

INTERNAL

EXTERNAL

IN

∼

IDEAL

1. Use an external resistor for R_OSand the internal 20 kΩ

resistor for R_IN(as shown in Figure 10).

TEMPERATURE

PERTURBED

TRANSFER

F

ZERO

V

IN

2. Use the internal 20 kΩ resistor as R_OSand an external R_IN.

3. Use two external resistors.

–5V

V

ZERO

F

OUT

IDEAL

CASE 2

4. Use two internal resistors for R_INand R_OS(available on

PLCC version only).

R

∼

OS

EXTERNAL

INTERNAL

IN

∼

TEMPERATURE

PERTURBED

F

ZERO

Option 4 provides the closest to the ideal transfer function as

diagrammed in Figure 11. Figure 12 shows the effects of the

transfer relation on the other three options. In the first case, the

slope of the transfer function is unchanged with temperature.

However, V_ZERO(the input voltage required to produce an output

frequency of 0 Hz) and F_ZERO(the output frequency when

V_IN= 0 V) changes as the transfer function is displaced parallel

to the voltage axis with temperature. In the second case, F_ZERO

remains constant, but V_ZEROchanges as the transfer function

rotates about F_ZEROwith temperature changes. In the third case,

with two external resistors, the V_ZEROpoint remains invariant

while the slope and offset of the transfer function change with

temperature. If selecting this third option, the user should select

low drift, matched resistors.

V

ZERO

F

OUT

CASE 3

R

∼

OS

EXTERNAL

IN

∼

IDEAL

TEMPERATURE

PERTURBED

F

ZERO

V

ZERO

Figure 12. Actual Bipolar Input Transfer over Temperature

Rev. C | Page 10 of 28

AD652

5

6

7

8

5

6

7

8

AD652

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

AD652

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

10kΩ

16kΩ

NC

4kΩ

+

–

9

10

9

10

V

IN

+

–

NC NC

NC

V

IN

A. PLCC 0V TO 10V INPUT

B. PLCC 0V TO 8V INPUT

5

6

7

8

5

6

7

8

AD652

10kΩ

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

10kΩ

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

16kΩ

NC

+

–

V

IN

NC

5V REF

20

4kΩ

V

9

10

IN

9

10

±5V

NC NC

NC

NC = NO CONNECT

D. PLCC ±5V INPUT

C. PLCC 0V TO 5V INPUT

Figure 13.

PLCC CONNECTIONS

AD652

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

+V

S

The PLCC packaged AD652 offers additional input resistors not

found on the CERDIP-packaged device. These resistors provide

the user with additional input voltage ranges. Besides the 10 V

range available using the on-chip resistor in the CERDIP the

PLCC also offers 8 V and 5 V ranges. Figure 13A to Figure 13C

show the proper connections for these ranges with positive

input voltages. For negative input voltages, the appropriate

resistor should be tied to analog ground and the input voltage

should be applied to Pin 6, the + input of the op amp.

5V

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

REFERENCE

250kΩ

20kΩ

0.02µF

ONE

SHOT

2MΩ

500Ω

20kΩ

V

1mA

IN

Q

CK

D

AND

"D"

FLOP

Q

Bipolar input voltages can be accommodated by injecting

250 µA into Pin 5 with the use of the 5 V reference and the

input resistors. For the 5 V or 2.5 V range, the reference

output, Pin 20, should be tied to Pin 10. The input signal should

then be applied to Pin 8 for a 5 V signal and to Pin 7 for a

2.5 V signal. The input connections for a 5 V range are

shown in Figure 13D. For a 4 V range, the input signal should

be applied to Pin 9, and Pin 20 should be connected to Pin 8.

Figure 14. CERDIP Gain and Offset Trim

350kΩ

3

2

1

20

19

±

3.5mV

500Ω

AD652

OFFSET

TRIM

20kΩ

SYNCHRONOUS

5V

REFERENCE

VOLTAGE-TO-FREQUENCY

CONVERTER

4

5

6

7

8

18

17

16

15

14

0.02µF

GAIN AND OFFSET CALIBRATION

The gain error of the AD652 is laser trimmed to within 0.5%.

If higher accuracy is required, the internal 20 kΩ resistor must

be shunted with a 2 MΩ resistor to produce a parallel equivalent

that is 1% lower in value than the nominal 20 kΩ. Full-scale

adjustment is then accomplished using a 500 Ω series trimmer.

See Figure 14 and Figure 15. When negative input voltages are

used, this 500 Ω trimmer is tied to ground and Pin 6 is the

input pin.

"D"

FLOP

Q

D

AND

10kΩ

Q

CK

2MΩ

10kΩ

ONE

1mA

500Ω

16kΩ

SHOT

V

IN

4kΩ

9

10

11

12

13

Figure 15. PLCC Gain and Offset Trim

Rev. C | Page ±± of 28

AD652

This gain trim should be done with an input voltage of 9 V, and

the output frequency should be adjusted to exactly 45% of the

clock frequency. Since the device settles into a divide-by-2 mode

for an input overrange condition, adjusting the gain with a 10 V

input is impractical; the output frequency is exactly one-half the

clock frequency if the gain is too high and does not change with

adjustment until the exact proper scale factor was achieved.

Thus, the gain adjustment should be done with a 9 V input.

REFERENCE NOISE

The AD652 has an on-board, precision buffered 5 V reference

available to the user. Besides being used to offset the nonin-

verting comparator input in the voltage-to-frequency mode, this

reference can be used for other applications such as offsetting

the input to handle bipolar signals and providing bridge excita-

tion. It can source 10 mA and sink 100 µA, and is short-circuit

protected. Heavy loading of the reference does not change the

gain of the VFC, though it does affect the external reference

voltage. For example, a 10 mA load interacting with a 0.3 Ω typ-

ical output impedance changes the reference voltage by 0.06%.

The offset of the op amp may be trimmed to zero with the trim

scheme shown in Figure 14 for the CERDIP package and

Figure 15 for the PLCC package. One way of trimming the

offset is by grounding Pin 7 (8) of the CERDIP (PLCC) device

and observing the waveform at Pin 4. If the offset voltage of the

op amp is positive, the integrator has saturated and the voltage

is at the positive rail. If the offset voltage is negative, there is a

small effective input current that causes the AD652 to oscillate;

a sawtooth waveform is observed at Pin 4. The potentiometer

should be adjusted until the downward slope of this sawtooth

becomes very slow, down to a frequency of 1 Hz or less. In an

analog-to-digital conversion application, an easier way to trim

the offset is to apply a small input voltage, such as 0.01% of the

full-scale voltage, and adjust the potentiometer until the correct

digital output is reached.

DIGITAL INTERFACING CONSIDERATIONS

The AD652 clock input has a high impedance input with a

threshold voltage of two diode voltages with respect to Digital

Ground at Pin 12 (approximately 1.2 V at room temperature).

When the clock input is low, 5 µA to 10 µA flows out of this pin.

When the clock input is high, no current flows.

The frequency output is an open collector pull-down capable of

sinking 10 mA with a maximum voltage of 0.4 V. This drives

6 standard TTL inputs. The open collector pull-up voltage can

be as high as 36 V above digital ground.

COMPONENT SELECTION

GAIN PERFORMANCE

The AD652 integrating capacitor should be 0.02 µF. If a large

amount of normal mode interference is expected (more than

0.1 V) and the clock frequency is less than 500 kHz, an

integrating capacitor of 0.1 µF should be used. Mylar,

polypropylene, or polystyrene capacitors should be used.

The AD652 gain error is specified as the difference in slope

between the actual and the ideal transfer function over the full-

scale frequency range. Figure 16 shows a plot of the typical gain

error changes versus the clock input frequency, normalized to

100 kHz. Figure 16 shows the typical gain changes normalized

to the original 100 kHz gain if, after using the AD652 with a

full-scale clock frequency of 100 kHz, the necessary gating time

is reduced by increasing the clock frequency.

The open collector pull-up resistor should be chosen to give

adequately fast rise times. At low clock frequencies (100 kHz),

larger resistor values (several kΩ) and slower rise times may be

tolerated. However, at higher clock frequencies (1 MHz), a lower

value resistor should be used. The loading of the logic input that

is being driven must also be taken into consideration.

5

4

3

For example, if two standard TTL loads are to be driven, a

3.2 mA current must be sunk, leaving 6.8 mA for the pull-up

resistor if the maximum low level voltage is to be maintained at

0.4 V. A 680 Ω resistor would therefore be selected

((5 V – 0.4 V)/6.8 mA) = 680 Ω.

2

1

0

–1

–2

–3

–4

–5

0

500 1000 1500 2000 2500 3000 3500 4000 4500 5000

CLOCK FREQUENCY (kHz)

Figure 16. Gain vs. Clock Input

Rev. C | Page ±2 of 28

AD652

The one-shot capacitor controls the pulse width of the

frequency output. The pulse is initiated by the rising edge of the

clock signal. The delay time between the rising edge of the clock

and the falling edge of the frequency output is typically 200 ns.

The width of the pulse is 5 ns/pF, and the minimum width is

about 200 ns with Pin 9 floating. If the one-shot period is

accidentally chosen longer than the clock period, the width of

the pulse defaults to equal the clock period. The one-shot can be

disabled by connecting Pin 9 to +V_S(Figure 17); the output

pulse width is then equal to the clock period. The one-shot is

activated (Figure 18) by connecting a capacitor from Pin 9 to

+V_S, −V_S,or Digital Ground (+V_Sis preferred).

DIGITAL GROUND

Digital Ground can be at any potential between −V_Sand

(+V_S– 4 V). This can be very useful in systems with derived

grounds rather than stiff supplies. For example, in a small

isolated power circuit, often only a single supply is generated

and the ground is set by a divider tap. Such a ground cannot

handle the large currents associated with digital signals. With

the AD652 SVFC, it is possible to connect the Digital Ground to

–V_Sfor a solid logic reference, as shown in Figure 19.

+V

S

AD652

+V

S

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

5V

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

REFERENCE

AD652

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

5V

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

REFERENCE

C

INT

ONE

SHOT

R

L

5V

–

IN

+

FREQ

OUT

V

20kΩ

1mA

Q

CK

"D"

CLOCK

ONE

SHOT

D

AND

20kΩ

Q FLOP

C

OS

1mA

Q

CK

"D"

D

AND

Q FLOP

–V

S

Figure 19. Digital GND at −V_S

Figure 17. One-Shot Disabled

AD652

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

5V

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

REFERENCE

ONE

SHOT

20kΩ

1mA

Q

CK

"D"

D

AND

C

OS

Q FLOP

ANY AC GND

(+V , –V , OR DIGITAL GND)

S

Figure 18. One-Shot Enabled

Rev. C | Page ±3 of 28

AD652

SINGLE-SUPPLY OPERATION

output. This resistor should be selected such that a current of

approximately 500 µA flows during operation. For example,

with a power supply voltage of +15 V, a 20 kΩ resistor is selected

((15 V–5 V)/500 µA = 20 kΩ).

In addition to the Digital Ground being connected to –V_S, it is

also possible to connect Analog Ground to –V_Sof the AD652.

Thus, the device is truly operating from a single-supply voltage

that can range from 12 V to 36 V. This is shown in Figure 21 for

a positive voltage input, and in Figure 20 for a negative voltage

input.

Figure 20 shows the negative voltage input configuration for

using the AD652 in single-supply mode. In this mode, the signal

source is driving the + input of the op amp, which requires only

20 nA (typical) compared to the 0.5 mA required in the positive

input voltage configuration. The voltage at Pin 6 may go as low

as 4 V above ground (−V_SPin 8). Since the input reference is 5.0

V above ground, this leaves a 1 V window for the input signal.

To drive the integrating capacitor with a 0.5 mA full-scale

current, it is necessary to provide an external 2 kΩ resistor. This

results in a 2 kΩ resistor and a 1 V input range. The external

2 kΩ resistor should be a low TC metal-film type for lowest

drift degradation.

In Figure 21, the comparator reference is used as a derived

ground; the input voltage is referred to this point as well as to

the op amp common mode (Pin 6 is tied to Pin 16). Since the

input signal source must drive 0.5 mA of full-scale signal

current into Pin 7, it must also draw the exact same current

from the input reference potential. This current is therefore

provided by the 5 V reference.

In single-supply operation, an external resistor, R_PULLUP, is

necessary between the power supply, +V_S, and the 5 V reference

+V

S

R

PULLUP

AD652

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

5V

REFERENCE

1

2

3

4

5

6

7

8

16

INPUT

15

14

13

12

11

10

9

REFERENCE

ANALOG

GND

+

–

C

INT

2kΩ

DIGITAL

GND

ONE

SHOT

5V

R

L

SIGNAL

20kΩ

SOURCE

1mA

CLOCK

1V FULL SCALE

Q

CK

"D"

D

AND

C

OS

Q FLOP

Figure 20. Single-Supply Mode Negative Voltage Input

+V

S

R

PULLUP

AD652

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

5V

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

REFERENCE

I

SIGNAL

INPUT

REFERENCE

ANALOG

GND

C

INT

DIGITAL

GND

ONE

SHOT

R

L

5V

–

+

FREQ

OUT

20kΩ

1mA

CLOCK

C

Q

CK

I

SIGNAL

0.5mA

FULL SCALE

SIGNAL

SOURCE

D

AND

"D"

FLOP

OS

Q

ANALOG

GND

Figure 21. Single-Supply Mode Positive Voltage Input

Rev. C | Page ±4 of 28

AD652

as shown. Because the 50 Ω resistor is 0.25% of the full scale,

and the specified gain error with the 20 kΩ resistor is 0.5%, this

extra resistor only increases the total gain error to 0.75% max.

FREQUENCY-TO-VOLTAGE CONVERTER

The AD652 SVFC also works as a frequency-to-voltage

converter. Figure 22 shows the connection diagram for F/V

conversion. In this case, the negative input of the comparator is

fed the input pulses. Either comparator input may be used so

that an input pulse of either polarity may be applied to the F/V.

The circuit shown is unipolar and only a 0 V to +10 V output is

allowed. The integrator op amp is not a general-purpose op

amp. Instead, it has been optimized for simplicity and high

speed. The most significant difference between this amplifier

and a general-purpose op amp is the lack of an integrator (or

level shift) stage.

In Figure 22, the + input is tied to a 1.2 V reference and low-

level TTL pulses are used as the frequency input. The pulse

must be low on the falling edge of the clock. On the subsequent

rising edge, the 1 mA current source is switched to the

integrator summing junction and ramps up the voltage at Pin 4.

Due to the action of the AND gate, the 1 mA current is switched

off after only one clock period. The average current delivered to

the summing junction varies from 0 mA to 0.5 mA; using the

internal 20 kΩ resistor, this results in a full-scale output voltage

of 10 V at Pin 4.

Consequently, the voltage on the output (Pin 4) must always be

more positive than 1 V below the inputs (Pins 6 and 7). For

example, in the F-to-V conversion mode, the noninverting input

of the op amp (Pin 6) is grounded, which means the output

(Pin 4) cannot go below −1 V. Normal operation of the circuit as

shown never calls for a negative voltage at the output.

A second difference between this op amp and a general-purpose

amplifier is that the output only sinks 1.5 mA to the negative

supply. The only pull-down other than the 1 mA current used

for voltage-to-frequency conversion is a 0.5 mA source. The op

amp sources a great deal of current from the positive supply,

and is internally protected by current limiting. The op amp

output may be driven to within 4 V of the positive supply when

not sourcing external current. When sourcing 10 mA, the out-

put voltage may be driven to within 6 V of the positive supply.

The frequency response of the circuit is determined by the

capacitor; the −3 dB frequency is simply the RC time constant.

A tradeoff exists between ripple and response. If low ripple is

desired, a large value capacitor must be used (1 µF); if fast

response is needed, a small capacitor is used (1 nF minimum).

The op amp can drive a 5 kΩ resistor load to 10 V, using a 15 V

positive power supply. If a large load capacitance (0.01 µF) must

be driven, it is necessary to isolate the load with a 50 Ω resistor

FREQ

IN

+V

S

5V

AD652

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

5kΩ

5V

1

2

3

4

5

6

7

8

16

15

14

13

12

REFERENCE

1N4148

50Ω

+

V

C

OUT

–

0.01µF

5kΩ

DIGITAL

GND

ONE

SHOT

11 NC

10

CLOCK

20kΩ

1mA

Q

CK

9

NC

D

AND

"D"

Q

FLOP

–V

S

CLOCK

FREQ

IN

VOLTS

OUT

LOADS ON FALLING EDGE OF CK

SHIFTS OUT ON RISING EDGE OF CL

FREQUENCY TO VOLTS CONVERTER

Figure 22. Frequency-to-Voltage Converter

Rev. C | Page ±ꢀ of 28

AD652

DECOUPLING AND GROUNDING

It is good engineering practice to use bypass capacitors on the

supply-voltage pins, and to insert small valued resistors (10 Ω to

100 Ω) in the supply lines to provide a measure of decoupling

between the various circuits in a system. Ceramic capacitors of

0.1 µF to 1.0 µF should be applied between the supply voltage

pins and analog signal ground for proper bypassing on the

AD652.

A problem remains from interference caused by radiation of

electromagnetic energy from these fast transients. Typically, a

voltage spike is produced by inductive switching transients;

these spikes can capacitively couple into other sections of the

circuit. Another problem is ringing of ground lines and power

supply lines due to the distributed capacitance and inductance

of the wires. Such ringing can also couple interference into

sensitive analog circuits. The best solution to these problems is

proper bypassing of the logic supply at the AD652 package. A

1 µF to 10 µF tantalum capacitor should be connected directly

to the supply side of the pull-up resistor and to the digital

ground, Pin 12. The pull-up resistor should be connected

directly to the frequency output, Pin 11. The lead lengths on the

bypass capacitor and the pull-up resistor should be as short as

possible. The capacitor supplies (or absorbs) the current

transients, and large ac signals flow in a physically small loop

through the capacitor, pull-up resistor, and frequency output

transistor. It is important that the loop be physically small for

two reasons: first, there is less inductance if the wires are short,

and second, the loop does not radiate RFI efficiently.

Additionally, a larger board-level decoupling capacitor of 1 µF

to 10 µF should be located relatively close to the AD652 on each

power supply line. Such precautions are imperative in high

resolution data acquisition applications where one expects to

exploit the full linearity and dynamic range of the AD652.

Separate digital and analog grounds are provided on the AD652.

Only the emitter of the open-collector frequency output

transistor and the clock input threshold are returned to the

digital ground. Only the 5 V reference is connected to analog

ground. The purpose of the two separate grounds is to allow

isolation between the high precision analog signals and the

digital section of the circuitry. Much noise can be tolerated on

the digital ground without affecting the accuracy of the VFC.

Such ground noise is inevitable when switching the large

currents associated with the frequency output signal.

The digital ground (Pin 12) should be separately connected to

the power supply ground. Note that the leads to the digital

power supply are only carrying dc current. There may be a dc

ground drop due to the difference in currents returned on the

analog and digital grounds. This does not cause a problem;

these features greatly ease power distribution and ground

manage-ment in large systems. The proper technique for

grounding requires separate digital and analog ground returns

to the power supply. Also, the signal ground must be referred

directly to the analog ground (Pin 6) at the package. More

information on proper grounding and reduction of interference

can be found in Noise Reduction Techniques in Electronic

Systems, by H.W. Ort, (John Wiley, 1976).

At high full-scale frequencies, it is necessary to use a pull-up

resistor of about 500 Ω in order to get the rise time fast enough

to provide well-defined output pulses. This means that from a

5 V logic supply, for example, the open collector output draws

10 mA. This much current being switched causes ringing on

long ground runs due to the self-inductance of the wires. For

instance, 20-gauge wire has an inductance of about 20 nH per

inch; a current of 10 mA being switched in 50 ns at the end of

12 inches of 20-gauge wire produces a voltage spike of 50 mV.

The separate digital ground of the AD652 easily handles these

types of switching transients.

Rev. C | Page ±6 of 28

AD652

+5V

R

PU

2.87kΩ

8

1

2

AD654

R1

R2

A

B

8.06kΩ 2kΩ

OSC/DRIVER

C

4

3

1kΩ

R3

1kΩ

V1

74LS86

0V–10V

C1

500pF

5

6

7

f_C

R

T

1kΩ

C

T

200pF

+15V

AD652

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

5V

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

REFERENCE

0.02µF

ONE

SHOT

+5V

–

V2

20kΩ

0V–10V

+

1mA

Q

CK

"D"

D

f_OUT

AND

Q FLOP

200pF

–15V

+15V

+5V

AD652

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

5V

2kΩ

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

REFERENCE

V

OUT

400pF

ONE

SHOT

1MHz

CLOCK

INPUT

20kΩ

1mA

Q

CK

"D"

D

AND

Q FLOP

–15V

Figure 23. Frequency Output Multiplier

FREQUENCY OUTPUT MULTIPLIER

The AD652 can serve as a frequency output multiplier when

used in conjunction with a standard voltage-to-frequency

converter. Figure 23 shows the low cost AD654 VFC being used

as the clock input to the AD652. Also shown is a second AD652

in the F/V mode. The AD654 is set up to produce an output

frequency of 0 kHz to 500 kHz for an input voltage (V₁) range

of 0 V to 10 V. The use of R4, C1, and the XOR gate doubles this

output frequency from 0 kHz–500 kHz to 0 MHz–1 MHz.

This 1 MHz full-scale frequency is then used as the clock input

to the AD652 SVFC. Because the AD652 full-scale output

frequency is one-half the clock frequency, the 1 MHz FS clock

frequency establishes a 500 kHz maximum output frequency for

the AD652 when its input voltage (V₂) is 10 V. The user there-

fore has an output frequency range from 0 kHz to 500 kHz,

which is proportional to the product of V₁and V₂.

Rev. C | Page ±7 of 28

AD652

This can be shown in equation form, where f_Cis the AD654

output frequency and f_OUTis the AD652 output frequency:

system with high noise immunity. Figure 26, Figure 27, and

Figure 30 show the SVFC multiplexer, a representative means of

data transmission, and an SVFC demultiplexer respectively.

1MHz

f_C=V₁

Multiplexer

10 V

Figure 30 shows the SVFC multiplexer. The clock inputs for the

several SVFC channels are generated by a TIM9904A 4-phase

clock driver, and the frequency outputs are combined by

strapping all the frequency output pins together (a wire OR

connection). The one-shot in the AD652 sets the pulse width of

the frequency output pulses to be slightly shorter than one

quarter of the clock period. Synchronization is achieved by

applying one of the four available phases to a fixed TTL one-

shot (’121) and combining the output with external transistor.

f_C

2

10 V

⎛

⎜

⎞

⎟

⎜

⎟

f_OUT=V₂

⎜

⎝

⎟

⎠

⎛

⎞

⎟

⎠

1 MHz

10 V)(10 V

)

⎜

⎝

f_OUT= V₁V₂

2

(

f

_OUT= V₁× V₂× 5 kHz/V²

The width of this sync pulse is shorter than the width of the

frequency output pulses to facilitate decoding the signal. The

RC lag network on the input of the one-shot provides a slight

delay between the rising edge of the clock and the sync pulse in

order to match the 150 ns delay of the AD652 between the

rising edge of the clock and the output pulse.

The scope photo in Figure 24 shows V₁and V₂(top two traces)

and the output of the F-V (bottom trace).

V

1

Transmitter

V

2

The multiplex signal can be transmitted in any manner suitable

to the task at hand. A pulse transformer or an opto-isolator can

provide galvanic isolation; extremely high voltage isolation or

transmission through severe RF environments can be accomp-

lished with a fiber optic link; telemetry can be achieved with a

radio link. The circuit shown in Figure 27 uses an EIA RS-422

standard for digital data transmission over a balanced line.

Figure 24 shows the waveforms of the four clock phases and the

multiplex output signal. Note that the sync pulse is present

every clock cycle, but the data pulses are no more frequent than

every other clock cycle since the maximum output frequency

from the SVFC is half the clock frequency. The clock frequency

used in this circuit is 819.2 kHz, which provides more than

16 bits of resolution if 100 ms gate time is allowed for counting

pulses of the decoded output frequencies.

V

OUT

Figure 24. Multiplier Waveforms

SINGLE-LINE MULTIPLEXED DATA TRANSMISSION

It is often necessary to measure several different signals and

relay the information to some remote location using a mini-

mum amount of cable. Multiple AD652 SVFC devices may be

used with a multiphase clock to combine these measurements

for serial transmission and demultiplexing. Figure 25 shows a

block diagram of a single-line multiplexed data transmission

CLK

f1

f2

f3

SVFC MULTIPLEXER

(SEE FIGURE 26)

GENERATOR

SVFC DEMULTIPLEXER

(SEE FIGURE 30)

SVFC

DEMUX

φ

1

φ

2

φ

3

φ4

AD652 AD652 AD652

φ₂

φ₃

φ₄

ONE

SHOT

TRANSMISSION

LINK

AD652 AD652 AD652

TRANSMISSION

LINK

(SEE FIGURE 27)

V

OUT3

V

IN3

OUT1

OUT2

IN1

IN2

DEMULTIPLEXER FREQUENCY TO

VOLTAGE CONVERSION

(SEE FIGURE 31)

Figure 25. Single-Line Multiplexed Data Transmission Block Diagram

Rev. C | Page ±8 of 28

AD652

+V

S

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

AD652

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

0.02µF

V

φ

2

V

φ

3

V

φ4

IN2

IN3

IN4

15pF

–V

S

TIM 9904A

TANK 1

MULTIPLEX

OUT

+5V

V

1

2

20

19

18

17

16

15

14

13

12

11

ONE SHOT

'121

CC

+5V

V

TANK 2

GND 1

FFQ

FFD

XTAL 2

CC

3.2768MHz

CRYSTAL

1

2

3

4

5

6

14

13

3

XTAL 4

OSCIN

+5V

NC

A1

NC

1kΩ

7.4µH

2kΩ

+5V

4

φ

1

L = 41 TURNS

T50–7 CORE

MICROMETALS

C = 300pF

12 NC

R

/C

500Ω

A2

5

EXT EXT

OSCOUT

11

10

9

150Ω

50pF

EXT

C

R

6

φ

4 TTL

φ

2 TTL

1 TTL

Q

7

3 TTL

1500pF

INT

Q

GND

φ

3

4

3

4

V

+5V

8

7

8

NC

DD

10kΩ

φ

2

φ1

φ

1

2

9

2N2222

10

GND 2

18pF

Figure 26. SVFC Multiplexer

AM26LS31

QUAD HIGH SPEED DIFFERENTIAL LINE RECEIVER

+5V

FROM

INPUTS A

ENCODER

MPX

1

2

3

4

5

6

7

8

16

INPUT

15 INPUTS D

14

A OUTPUTS

ENABLE

D OUTPUTS

13

12 ENABLE

11

B OUTPUTS

C OUTPUTS

10

9

INPUT B

GND

INPUT C

QUAD DIFFERENTIAL LINE RECEIVER

AM26LS33

+5V

75Ω

1

2

3

4

5

6

7

8

16

15

14

13

INPUTS A

500 FEET

BELDEN 9272

78Ω SHIELDED PAIR

INPUTS B

OUTPUT B

OUTPUT A

ENABLE

12 ENABLE

11 INPUT D

10

OUTPUT C

INPUTS C

INPUTS D

9

MPX OUTPUT

TO DECODER

Figure 27. RS-422 Standard Data Transmission

Rev. C | Page ±9 of 28

AD652

SVFC Demultiplexer

The demultiplexer needed to separate the combined signals is

shown in Figure 30. A phase-locked loop drives another 4-phase

clock chip to lock onto the reconstructed clock signal. The sync

pulses are distinguished from the data pulses by their shorter

duration. Each falling edge on the multiplex input signal

triggers the one-shot; at the end of this one-shot pulse, the

multiplex input signal is sampled by a D-type flip-flop. If the

φ

1

2

φ

3

4

1MULTIPLEX

OUTPUT

Q

signal is high, the pulse was short (a sync pulse) and the

output of the D-flop goes low. The D-flop is cleared a short time

(two gate delays) later, and the clock is reconstructed as a

stream of short, low-going pulses. If the multiplex input is a data

pulse, then the signal will still be low and no pulse will appear at

the reconstructed clock output when the D-flop samples at the

end of the one-shot period. See Figure 29.

φ

1

φ

2

φ

3

φ4

SYNC

DATA

Figure 28. Multiplexer Waveforms

If it is desired to recover the individual frequency signals, the

multiplex input is sampled with a D-flop at the appropriate

time, as determined by the rising edge of the various phases

generated by the clock chip. These frequency signals can be

counted as a ratio relative to the reconstructed clock, so it is not

even necessary for the transmitter to be crystal-controlled as

shown in Figure 30.

MULTIPLEX

INPUT

ONE SHOT

RECONSTRUCTED

CLOCK

φ

1

(PHASE LOCKED TO

RECONSTRUCTED

CLOCK)

Figure 29. Demultiplexer Waveforms

+5V

14

RECONSTRUCTED

CLOCK OUTPUT

13

4

5

10

MPX

INPUT

3.01kΩ

1

3

+5V

D

1/2 '74

Q

PHASE LOCK LOOP

MC4044

9

CLOCK CLEAR

719Ω

0.1µF

3

6

16 15 11

4

2

11

8

'00

4

5

VCO

'LS629

2

50pF

1kΩ

'00

8

9

7

+5V

150Ω

390pF

+5V

TIM 9904A

4 PHASE CLOCK

ONE SHOT

'121

130Ω

V

1

2

3

4

5

6

7

8

9

TANK 1

20

CC

V

Q

CC

1

2

3

4

5

6

7

14

13

19

18

17

16

15

14

13

12

11

TANK 2

GND 1

FFQ

XTAL 2

XTAL 1

NC

A1

NC

2kΩ

12 NC

R

OSCIN

/C

A2

EXT EXT

11

10

9

50pF

EXT

FFD

OSCOUT

C

+5V

φ

4 TTL

φ

2 TTL

1 TTL

R

Q

GND

INT

Q

3 TTL

8

NC

V

φ

3

4

3

4

DD

φ

1

2

φ

1

2

'74 (1/2)

10 GND 2

φ

D

φ

2

φ

3

φ4

CLOCK

Q

CLOCK

Q

CLOCK

Q

f2

f3

RECONSTRUCTED

FREQUENCY OUTPUTS

f4

NC = NO CONNECT

Figure 30. SVFC Demultiplexers

Rev. C | Page 20 of 28

AD652

+5V

4kΩ

MPX INPUT

1N4148

+V

S

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1

2

3

4

5

6

7

8

16

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

VOLTS

OUT

VOLTS

OUT

VOLTS

OUT

15

14

13

12

11

10

9

V

2

3

4

AD652

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

0.02µF

φ

2

φ

3

φ4

–V

S

φ2, φ3, φ4 ARE PINS 15, 7, 6 OF TIM9904A FROM DEMUX FIGURE 30

Figure 31. Demultiplexer Frequency-to-Voltage Conversion

+5V

FREQUENCY

OUTPUT

CK

Q

D

Q

CK

Q

D

'74

1.5kΩ

1.2kΩ

DRIVER

OSC

1

2

3

4

8

7

6

5

6

4

2N6659

3

2

1

100Ω

200pF

10kΩ

500Ω

7

MYLAR

0.01µF

6.8kΩ

1.65kΩ

6N137

V

8

+5V

OPTO-

AD654

ISOLATOR

AD589

1.2V

+5V

24 TURNS

T50- MICROMETALS

TRANSFORMER

PICO 31080

10µH

3

1

2

ISOLATION BARRIER

7

6 5

4

1N4148

+15V

AD652

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

47µF

5V

1

2

3

4

5

6

7

8

16

REFERENCE

15

14

13

12

11

10

9

–15V

REG

+15V

7915

7815

REG

47µF

0.02µF

ONE

–15V

+15V

3kΩ

SHOT

LO

V

IN

20kΩ

HI

1mA

Q

CK

1kΩ

D

AND

"D"

FLOP

1nF

Q

10kΩ

1nF

–15V

Figure 32. Isolated Synchronous VFC

Analog Signal Reconstruction

ϕ

driven by the outputs of the clock chip. Remember that data

at the comparator input of the SVFC is loaded on the falling

edge of the clock signal and shifted out on the next rising edge.

Note that the frequency signals for each data channel are

available at the frequency output pin of each FVC.

If it is desired to reconstruct the analog voltages from the

multiplex signal, three more AD652 SVFC devices are used as

frequency-to-voltage converters, as shown in Figure 31. The

comparator inputs of all the devices are strapped together, the

“+” inputs are held at a 1.2 V TTL threshold, and the “−” inputs

are driven by the multiplex input. The three clock inputs are

Rev. C | Page 21 of 28

AD652

The resolution of the A-to-D conversion measurement is

determined by the clock frequency and the gate time. If, for

instance, a resolution of 12 bits is desired and the clock

frequency is 1 MHz (resulting in an AD652 FS frequency of

500 kHz) the gate time is:

ISOLATED FRONT END

In some applications, it may be necessary to have complete

galvanic isolation between the analog signals being measured

and the digital portions of the circuit. The circuit shown in

Figure 32 runs off a single 5 V power supply and provides a self-

contained, completely isolated analog measurement system. The

power for the AD652 SVFC is provided by a chopper and a

transformer, and is regulated to 15 V.

−1

–1

FS Freq

Clock Freq

N

1 MHz

⎛

⎞

⎛

⎞

⎛

⎞

1

2

⎜

⎟

⎜

⎟

⎜

⎟

=

N

2 4096

( )

⎝

⎠

⎝

⎠

⎝

⎠

8192

1×10⁶

=

sec = 8.192 ms

Both the chopper frequency and the AD652 clock frequency are

125 kHz, with the clock signal being relayed to the SVFC

through the transformer. The frequency output signal is relayed

through an opto-isolator and latched into a D flop. The chopper

frequency is generated from an AD654 VFC, and is frequency

divided by two to develop differential drive for the chopper

transistors, and to ensure an accurate 50% duty cycle. The pull-

up resistors on the D flop outputs provide a well-defined high

level voltage to the choppers to equalize the drive in each

direction. The 10 µH inductor in the 5 V lead of the transformer

primary is necessary to equalize any residual imbalance in the

drive on each half cycle, and thus prevent saturation of the core.

The capacitor across the primary resonates the system so that

under light loading conditions on the secondary, the wave shape

is sinusoidal and the clock frequency is relayed to the SVFC. To

adjust the chopper frequency, disconnect any load on the

secondary and tune the AD654 for a minimum in the supply

current drawn from the 5 V supply.

Where N is the total number of codes for a given resolution.

Figure 33 shows the AD652 SVFC as an A-to-D converter in

block diagram form.

f_OUT

INPUT

V

AD652

COUNTER

GATE

TO µP

IN

CLOCK

÷2N

Figure 33. Block Diagram of SVFC A-to-D Converter

To provide the ÷2N block, a single-chip counter such as the

4020B can be used. The 4020B is a 14-stage binary ripple

counter that has a clock and master reset for inputs, and

buffered outputs from the first stage and the last 11 stages. The

output of the first stage is f_CLOCK÷ 2¹= f_CLOCK/2, while the output

of the last stage is f_CLOCK÷ 2¹⁴= f_CLOCK/16384. Therefore, using

this single chip counter as the ÷2N block, 13-bit resolution can

be achieved. Higher resolution can be achieved by cascading D-

type flip flops or another 4020B with the counter.

A-TO-D CONVERSION

In performing an A-to-D conversion, the output pulses of a

VFC are counted for a fixed-gate interval. To achieve maximum

performance with the AD652, the fixed-gate interval should be

generated using a multiple of the SVFC clock input. Counting

in this manner eliminates any errors due to the clock (whether

it be jitter, drift with time or temperature, and so on) since it is

the ratio of the clock and output frequencies that is being

measured.

Table 4 shows the relationship between clock frequency and gate

time for various degrees of resolution. Note that if the variables

are chosen such that the gate times are multiples of 50 Hz,

60 Hz, or 400 Hz, normal mode rejection (NMR) of those line

frequencies occur.

Table 4.

Resolution

N

Clock

Conversion or Gate Time (ms)

Typical Linearity (%)

Comments

12 Bits

4 Digits

14 Bits

4½ Digits

16 Bits

4096

10000

16384

20000

65536

81.92 kHz

2 MHz

4 MHz

200 kHz

327.68 kHz

1.966 MHz

1.638 MHz

400 kHz

655.36 kHz

4 MHz

100

0.002

0.01

0.02

0.002

0.01

50 Hz, 60 Hz,400 Hz NMR

4.096

2.048

100

16.66

20

100

200

32.77

50 Hz, 60 Hz, 400 Hz NMR

60 Hz NMR

50 Hz NMR

50 Hz, 60 Hz, 400 Hz NMR

0.01

0.002

0.02

Rev. C | Page 22 of 28

AD652

The choice of an integrating capacitor is primarily dictated by

DELTA MODULATOR

the input signal bandwidth. Figure 37 shows this relationship.

Note that as the value of C_INTis lowered, the ramp size of the

integrator approximation becomes larger. This can be

compensated for by increasing the clock frequency. The effect of

the clock frequency on the ramp size is demonstrated in

Figure 35 and Figure 36.

The circuit of Figure 34 shows the AD652 configured as a delta

modulator. A reference voltage is applied to the input of the

integrator (Pin 7), which sets the steady state output frequency

at one-half of the AD652 full-scale frequency (1/4 of the clock

frequency). As a 0 V to 10 V input signal is applied to the

comparator (Pin 15), the output of the integrator attempts to

track this signal. For an input in an idling condition (dc), the

output frequency is one-half full scale. For positive-going

signals, the output frequency is between one-half full scale and

full scale; for negative-going signals, the output frequency is

between zero and one-half full scale. The output frequency

corresponds to the slope of the comparator input signal.

AD652

SYNCHRONOUS

VOLTAGE-TO-

5V

1

2

3

4

5

6

7

8

FREQUENCY

CONVERTER

16

15

14

13

12

11

10

9

+15V

REFERENCE

V

(0V TO 10V)

IN

Figure 35. Delta Modulator Input Signal and Ramp-Wise Approximation

+5V

1kΩ

360pF

ONE

SHOT

0.01µF

CLOCK

F

20kΩ

OUT

1mA

Q

CK

–15V

D

AND

"D"

FLOP

Q

0.0047µF

Figure 34. Delta Modulator

Since the output frequency corresponds to the slope of the input

signal, the delta modulator acts as a differentiator. A delta

modulator is thus a direct way of finding the derivative of a

signal. This is useful in systems where, for example, a signal

corresponding to velocity exists, and it is desired to determine

acceleration.

Figure 36. Delta Modulator Input Signal Ramp-Wise Approximation and

Output Frequency

Figure 35 is a scope photo showing a 20 kHz, 0 V to 10 V sine

wave used as the input to the comparator and its ramp-wise

approximation at the integrator output. The clock frequency

used as 2 MHz and the integrating capacitor was 360 pF.

Figure 36 shows the same input signal and its ramp-wise

approximation, along with the output frequency corresponding

to the derivative of the input signal. In this case, the clock

frequency was 50 kHz.

10k

1k

100

1k

10k

INPUT SIGNAL BANDWIDTH (Hz)

Figure 37. Maximum Integrating Cap Value vs. Input Signal Bandwidth

Rev. C | Page 23 of 28

AD652

These resistors should be selected such that the following

equation holds:

BRIDGE TRANSDUCER INTERFACE

The circuit of Figure 38 illustrates a simple interface between

the AD652 and a bridge-type transducer. The AD652 is an ideal

choice because its buffered 5 V reference can be used as the

bridge excitation, thereby ratiometrically eliminating the gain

drift related errors. This reference provides a minimum of

10 mA of external current, which is adequate for bridge

resistance of 600 Ω and above. If, for example, the bridge

resistance is 120 Ω or 350 Ω, an external pull-up resistor (R_PU) is

required. R_PUand can be calculated using the following formula:

⎛

⎜

⎝

⎞

⎟

⎠

2R_F

R_G

10 V =V_BRIDGE

+1

where 10 kΩ ≤ R_F≤ 20 kΩ, and V_BRIDGEis the maximum output

voltage of the bridge.

The bridge output may be unipolar, as is the case for most

pressure transducers, or it may be bipolar as in some strain

measurements. If the signal is unipolar, the reference input of

the AD625 (Pin 7) is simply grounded. If the bridge has a

bipolar output, however, the AD652 reference can be tied to

Pin 7, thereby, converting a 5 V signal (after gain) into a 0 V to

+10 V input for the SVFC.

+V_S−5 V

R_PU(max) =

5 V

−10 mA

R_BRIDGE

An instrumentation amplifier is used to condition the bridge

signal before presenting it to the SVFC. With its high CMRR,

the AD652 minimizes common-mode errors and can be set to

arbitrary gains between 1 and 10,000 via three resistors,

simplifying the scaling for the part’s calibrated 10 V input range.

+15V

R

PU

AD652

+15V

SYNCHRONOUS

VOLTAGE-TO-

FREQUENCY

CONVERTER

R

–

BRIDGE

+

5V

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

1

5

2

REFERENCE

9

V

BRIDGE

R

F

11

7

R

G

AD625

10

V

LOGIC

15

12

16

R

F

C

INT

R

L

ONE

SHOT

2

8

FREQ

OUT

1

S1

20kΩ

CLOCK IN

1mA

–15V

Q

CK

"D"

D

AND

Q FLOP

–15V

+15V

NOTES

1. R SHOULD BE BETWEEN 10kΩ AND 20kΩ.

F

2R

F

2

F

CLOCK

10V

F

= V

BRIDGE

2. R NEEDED IF R

600Ω

+ 1

OUT

PU

BRIDGE

R

G

3. S1 IN POSITION 1 FOR UNIPOLAR SIGNALS

AND POSITION 2 FOR BIPOLAR SIGNALS.

Figure 38. Bridge Transducer Interface

Rev. C | Page 24 of 28

AD652

OUTLINE DIMENSIONS

0.005

(0.13)

MIN

0.098 (2.49)

MAX

0.310 (7.87)

0.220 (5.59)

16

9

PIN 1

1

8

0.060 (1.52)

0.015 (0.38)

0.320 (8.13)

0.290 (7.37)

0.200 (5.08)

0.840 (21.34) MAX

MAX

0.150 (3.81)

MIN

0.015 (0.38)

0.008 (0.20)

0.200 (5.08)

0.125 (3.18)

15°

0°

SEATING

PLANE

0.100

(2.54)

BSC

0.070 (1.78)

0.030 (0.76)

0.023 (0.58)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

Figure 39. 16-Lead Ceramic Dual In-Line Package [CERDIP]

(Q-16)

Dimensions shown in inches and (millimeters)

0.180 (4.57)

0.048 (1.21)

0.165 (4.19)

0.042 (1.07)

0.056 (1.42)

0.042 (1.07)

0.020 (0.50)

R

0.20 (0.51)

MIN

3

4

19

0.021 (0.53)

0.013 (0.33)

0.048 (1.21)

0.042 (1.07)

18

14

0.050

(1.27)

BSC

0.330 (8.38)

0.290 (7.37)

BOTTOM

VIEW

(PINS UP)

TOP VIEW

(PINS DOWN)

0.032 (0.81)

0.026 (0.66)

8

9

13

0.020

(0.50)

R

0.025 (0.64) MIN

0.356 (9.04)

0.350 (8.89)

SQ

0.120 (3.04)

0.090 (2.29)

0.395 (10.02)

0.385 (9.78)

SQ

COMPLIANT TO JEDEC STANDARDS MO-047AA

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

Figure 40. 20-Lead Plastic Leaded Chip Carrier [PLCC]

(P-20A)

Dimensions shown in inches and (mm)

0.200 (5.08)

0.075 (1.91)

REF

0.100 (2.54)

0.064 (1.63)

0.100 (2.54) REF

0.095 (2.41)

0.015 (0.38)

MIN

0.075 (1.90)

3

19

18

20

4

8

0.028 (0.71)

0.022 (0.56)

1

0.358 (9.09)

0.342 (8.69)

SQ

0.358

0.011 (0.28)

0.007 (0.18)

R TYP

(9.09)

MAX

SQ

BOTTOM

VIEW

0.050 (1.27)

BSC

14

0.075 (1.91)

13

9

REF

45° TYP

0.088 (2.24)

0.054 (1.37)

0.055 (1.40)

0.045 (1.14)

0.150 (3.81)

BSC

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

Figure 41. 20-Terminal Leadless Chip Carrier [LCC]

(E-20A)

Dimensions shown in inches and (mm)

Rev. C | Page 2ꢀ of 28

AD652

ORDERING GUIDE

Model

Gain Drift, 100 kHz

1 MHz Linearity (%)

0.02 max

Specified Temperature Range

0°C to +70°C

Package Options ¹

PLCC (P-20A)

CERDIP (Q-±6)

LCC (E-20A)

AD6ꢀ2JP

ꢀ0 ppm/°C max

2ꢀ ppm/°C max

ꢀ0 ppm/°C max

2ꢀ ppm/°C max

ꢀ0 ppm/°C max

AD6ꢀ2JP-REEL

AD6ꢀ2JP-REEL7

AD6ꢀ2KP

0.02 max

0.00ꢀ max

0.02 max

0.00ꢀ max

0.02 max

AD6ꢀ2KP-REEL

AD6ꢀ2AQ²

0°C to +70°C

−40°C to +8ꢀ°C

−ꢀꢀ°C to +±2ꢀ°C

AD6ꢀ2BQ²

AD6ꢀ2SE/883B²

AD6ꢀ2SQ²

0.02 max

CERDIP (Q-±6)

AD6ꢀ2SQ/883B²

^±P = Plastic Leaded Chip Carrier; Q = CERDIP, E = Leadless Chip Carrier.

²For details on grade and package offerings screened in accordance with MILSTD-883, refer to the Analog Devices Military Products Databook or current AD6ꢀ2/883

data sheet.

Rev. C | Page 26 of 28

AD652

NOTES

Rev. C | Page 27 of 28

AD652

NOTES

©

registered trademarks are the property of their respective owners.

C00798–0–5/04(C)

Rev. C | Page 28 of 28


型号：	AD652SE/883B2
厂家：	ADI
描述：	Monolithic Synchronous Voltage-to-Frequency Converter 单片同步电压频率转换器转换器
文件：	总28页 (文件大小：786K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD652SE/883B2 [ADI]

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