AD654JNZ_技术文档

Low Cost Monolithic

a

Voltage-to-Frequency Converter

AD654

FUNCTIONAL BLOCK DIAGRAM

FEATURES

Low Cost

Single or Dual Supply, 5 V to 36 V, ؎5 V to ؎18 V

Full-Scale Frequency Up to 500 kHz

Minimum Number of External Components Needed

Versatile Input Amplifier

Positive or Negative Voltage Modes

Negative Current Mode

C

–V

S

+V

8

C

S

T

7

6

5

DRIVER

OSC

High Input Impedance, Low Drift

Low Power: 2.0 mA Quiescent Current

Low Offset: 1 mV

AD654

1

2

3

4

LOGIC

COMMON

+V

F

R

IN

OUT

T

PRODUCT DESCRIPTION

2. A minimum number of low cost external components are

necessary. A single RC network is all that is required to set

up any full scale frequency up to 500 kHz and any full-scale

input voltage up to ±30 V.

The AD654 is a monolithic V/F converter consisting of an input

amplifier, a precision oscillator system, and a high current output

stage. A single RC network is all that is required to set up any

full scale (FS) frequency up to 500 kHz and any FS input voltage

up to ± 30 V. Linearity error is only 0.03% for a 250 kHz FS,

and operation is guaranteed over an 80 dB dynamic range. The

overall temperature coefficient (excluding the effects of external

components) is typically ±50 ppm/°C. The AD654 operates from

a single supply of 5 V to 36 V and consumes only 2.0 mA quies-

cent current.

3. Plastic packaging allows low cost implementation of the

standard VFC applications: A/D conversion, isolated signal

transmission, F/V conversion, phase-locked loops, and tuning

switched-capacitor filters.

4. Power supply requirements are minimal; only 2.0 mA of

quiescent current is drawn from the single positive supply

from 4.5 volts to 36 volts. In this mode, positive inputs can

vary from 0 volts (ground) to (+V_S–4) volts. Negative inputs

can easily be connected for below ground operation.

The low drift (4 µV/°C typ) input amplifier allows operation

directly from small signals such as thermocouples or strain gauges

while offering a high (250 MΩ) input resistance. Unlike most

V/F converters, the AD654 provides a square-wave output, and

can drive up to 12 TTL loads, optocouplers, long cables, or

similar loads.

5. The versatile open-collector output stage can sink more than

10 mA with a saturation voltage less than 0.4 volts. The Logic

Common terminal can be connected to any level between

ground (or –V_S) and 4 volts below +V_S. This allows easy

direct interface to any logic family with either positive or

negative logic levels.

PRODUCT HIGHLIGHTS

1. Packaged in both an 8-lead mini-DIP and an 8-lead SOIC

package, the AD654 is a complete V/F converter requiring

only an RC timing network to set the desired full-scale fre-

quency and a selectable pull-up resistor for the open-collector

output stage. Any full scale input voltage range from 100 mV

to 10 volts (or greater, depending on +V_S) can be accommo-

dated by proper selection of the timing resistor. The full-

scale frequency is then set by the timing capacitor from the

simple relationship, f = V/10 RC.

C

REV.

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

World Wide Web Site: http://www.analog.com

2013

Fax:781/461.3113

(T_A= +25؇C and V_S(total) = 5 V to 16.5 V, unless otherwise noted. All testing done

@ V_S= +5 V.)

AD654–SPECIFICATIONS

AD654JN/JR

Model

Min

Typ

Max

Units

CURRENT-TO-FREQUENCY CONVERTER

Frequency Range

0

500

kHz

Nonlinearity¹

f_MAX= 250 kHz

0.06

0.20

0.1

0.4

%

f

_MAX= 500 kHz

Full-Scale Calibration Error

C = 390 pF, I_IN= 1.000 mA

vs. Supply (f_MAX≤ 250 kHz)

V_S= +4.75 V to +5.25 V

V_S= +5.25 V to +16.5 V

vs. Temp (0°C to +70°C)

–10

+10

%

0.20

0.05

50

0.40

0.10

%/V

ppm/°C

ANALOG INPUT AMPLIFIER

(Voltage-to-Current Converter)

Voltage Input Range

Single Supply

0

–V_S

(+V_S– 4)

V

Dual Supply

Input Bias Current

(Either Input)

Input Offset Current

Input Resistance (Noninverting)

Input Offset Voltage

vs. Supply

30

5

250

0.5

50

nA

MΩ

mV

1.0

V_S= +4.75 V to +5.25 V

V_S= +5.25 V to +16.5 V

vs. Temp (0°C to +70°C)

0.1

0.03

4

0.25

0.1

mV/V

µV/°C

OUTPUT INTERFACE (Open Collector Output)

(Symmetrical Square Wave)

Output Sink Current in Logic “0”²

V_OUT= 0.4 V max, +25°C

V_OUT= 0.4 V max, 0°C to +70°C

Output Leakage Current in Logic “1”

0°C to +70°C

Logic Common Level Range

Rise/Fall Times (C_T= 0.01 µF)

I_IN= 1 mA

10

5

20

10

50

mA

nA

V

100

500

(+V_S– 4)

–V_S

0.2

1

µs

I_IN= 1 µA

POWER SUPPLY

Voltage, Rated Performance

Voltage, Operating Range

Single Supply

4.5

16.5

V

4.5

±5

36

±18

V

Dual Supply

Quiescent Current

V_S(Total) = 5 V

V_S(Total) = 30 V

1.5

2.0

2.5

3.0

mA

TEMPERATURE RANGE

Operating Range

–40

+85

°C

NOTES

¹At f_MAX= 250 kHz; R_T= 1 kΩ, C_T= 390 pF, I_IN= 0 mA–1 mA.

¹At f_MAX= 500 kHz; R_T= 1 kΩ, C_T= 200 pF, I_IN= 0 mA–1 mA.

²The sink current is the amount of current that can flow into Pin 1 of the AD654 while maintaining a maximum voltage of 0.4 V between Pin 1 and Logic Common.

Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min

and max specifications are guaranteed, although only those shown in boldface are tested on all production units.

Specifications subject to change without notice.

C

REV.

–2–

AD654

ABSOLUTE MAXIMUM RATINGS

Stresses above those listed under Absolute Maximum Ratings

Parameter

Rating

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Total Supply Voltage +V_Sto −V_S

Maximum Input Voltage

(Pins 3, 4) to −V_S

Maximum Output Current

Instantaneous

36 V

−300 mV to +V_S

50 mA

25 mA

Sustained

Logic Common to −V_S

Storage Temperature Range

−500 mV to (+V_S–4)

−65°C to +150°C

ESD CAUTION

Rev. C | Page 3

AD654

CIRCUIT OPERATION

V/F CONNECTIONS FOR NEGATIVE INPUT VOLTAGE

OR CURRENT

The AD654’s block diagram appears in Figure 1. A versatile

operational amplifier serves as the input stage; its purpose is to

convert and scale the input voltage signal to a drive current in the

NPN follower. Optimum performance is achieved when, at the

full-scale input voltage, a 1 mA drive current is delivered to the

current-to-frequency converter (an astable multivibrator). The

drive current provides both the bias levels and the charging current

to the externally connected timing capacitor. This “adaptive” bias

scheme allows the oscillator to provide low nonlinearity over

the entire current input range of 100 nA to 2 mA. The square

wave oscillator output goes to the output driver which provides

a floating base drive to the NPN power transistor. This floating

drive allows the logic interface to be referenced to a level other

than –V_S.

The AD654 can accommodate a wide range of negative input

voltages with proper selection of the scaling resistor, as indicated

in Figure 2. This connection, unlike the buffered positive con-

nection, is not high impedance because the signal source must

supply the 1 mA FS drive current. However, large negative volt-

ages beyond the supply can be handled easily by modifying the

scaling resistors appropriately. If the input is a true current source,

R1 and R2 are not used. Again, diode CR1 prevents latch-up by

insuring Logic Common does not drop more than 500 mV below

–V_S. The clamp diode (MBD101) protects the AD654 input

from “below –V_S” inputs.

+V

S

+V

LOGIC

(+5V TO –V +30)

C

S

T

+V

S

R

PU

+V

LOGIC

(+5V TO –V +30)

C

S

T

F

OUT

OPTIONAL

OSC/

DRIVER

R

COMP

R

PU

V

F

IN

OUT

OPTIONAL

F

=

OUT

OSC/

DRIVER

R

COMP

(10V) (R1 + R2) C

T

AD654

R1

R2

V

IN

V

IN

V

IN

F

=

OUT

(10V) (R1 + R2) C

T

AD654

CLAMP

DIODE

CR1

R1

R2

–V

S

(0V TO –15V)

CR1

Figure 2. V-F Connections for Negative Input Voltages or

Current

–V

S

(0V TO –15V)

Figure 1. Standard V-F Connection for Positive Input

Voltages

OFFSET CALIBRATION

In theory, two adjustments calibrate a V/F: scale and offset. In

practice, most applications find the AD654’s 1 mV max voltage

offset sufficiently low to forgo offset calibration. However, the

input amplifier’s 30 nA (typ) bias currents will generate an offset

due to the difference in dc sound resistance between the input

terminals. This offset can be substantial for large values of R_T=

R1 + R2 and will vary as the bias currents drift over temperature.

Therefore, to maintain the AD654’s low offset, the application may

require balancing the dc source resistances at the inputs (Pins

3 and 4).

V/F CONNECTION FOR POSITIVE INPUT VOLTAGES

In the connection scheme of Figure 1, the input amplifier presents

a very high (250 MΩ) impedance to the input voltage, which

is converted into the proper drive current by the scaling resistors

at Pin 3. Resistors R1 and R2 are selected to provide a 1 mA

full-scale current with enough trim range to accommodate the

AD654’s 10% FS error and the components’ tolerances. Full-

scale currents other than 1 mA can be chosen, but linearity will

be reduced; 2 mA is the maximum allowable drive. The AD654’s

positive input voltage range spans from –V_S(ground in sink supply

operation) to four volts below the positive supply. Power sup-

ply rejection degrades as the input exceeds (+V_S– 3.75 V) and at

(+V_S– 3.5 V) the output frequency goes to zero.

For positive inputs, this is accomplished by adding a compensation

resistor nominally equal to R_Tin series with the input as shown

in Figure 3a. This limits the offset to the product of the 30 nA

bias current and the mismatch between the source resistance R_T

and R_COMP. A second, smaller offset arises from the inputs’ 5 nA

As indicated by the scaling relationship in Figure 1, a 0.01 µF

timing capacitor will give a 10 kHz full-scale frequency, and

0.001 µF will give 100 kHz with a 1 mA drive current. Good V/F

linearity requires the use of a capacitor with low dielectric

absorption (DA), while the most stable operation over tempera-

ture calls for a component having a small tempco. Polystyrene,

polypropylene, or Teflon* capacitors are preferred for tempco and

dielectric absorption; other types will degrade linearity. The

capacitor should be wired very close to the AD654. In Figure 1,

Schottky diode CR1 (MBD101) prevents logic common from

dropping more than 500 mV below –V_S. This diode is not

required if –V_Sis equal to logic common.

offset current flowing through the source resistance R_Tor R_COMP

.

For negative input voltage and current connections, the compensa-

tion resistor is added at Pin 4 as shown in Figure 3b in lieu of

grounding the pin directly. For both positive and negative inputs,

the use of R_COMPmay lead to noise coupling at Pin 4 and should

therefore be bypassed for lowest noise operation.

(OPTIONAL)

C

AD654

V

IN

R

COMP

R1

R2

Figure 3a. Bias Current Compensation—Positive Inputs

*Teflon is a trademark of E.I. Du Pont de Nemours & Co.

C

REV.

–4–

AD654

(OPTIONAL)

C

linearity, it is unnecessary for the end-user to perform this tedious

and time consuming test on a routine basis.

AD654

Sufficient FS calibration trim range must be provided to accom-

modate the worst-case sum of all major scaling errors. This

includes the AD654’s 10% full-scale error, the tolerance of the

fixed scaling resistor, and the tolerance of the timing capacitor.

Therefore, with a resistor tolerance of 1% and a capacitor tolerance

of 5%, the fixed part of the scaling resistor should be a maximum

of 84% of nominal, with the variable portion selected to allow

116% of the nominal.

R

COMP

R1

R2

V

IN

Figure 3b. Bias Current Compensation—Negative Inputs

If the AD654’s 1 mV offset voltage must be trimmed, the trim

must be performed external to the device. Figure 3c shows an

optional connection for positive inputs in which R_OFF1and

R_OFF2add a variable resistance in series with R_T. A variable

source of ±0.6 V applied to R_OFF1then adjusts the offset ±1 mV.

Similarly, a ±0.6 V variable source is applied to R_OFFin Fig-

ure 3d to trim offset for negative inputs. The ±0.6 V bipolar

source could simply be an AD589 reference connected as shown

in Figure 3e.

If the input is in the form of a negative current source, the scaling

resistor is no longer required, eliminating the capability of trim-

ming FS frequency in this fashion. Since it is usually not practical

to smoothly vary the capacitance for trimming purposes, an

alternative scheme such as the one shown in Figure 4 is needed.

Designed for a FS of 1 mA, this circuit divides the input into two

R2

100⍀

AD654

R4

10k⍀

V

392⍀

IN

R3

1k⍀

I

S

R

OFF2

20⍀ 5k⍀ 8.25k⍀

R1

100⍀

R

10k⍀

OFF1

I

R

1mA

FS

R

OFF

I

S

*

f =

100k⍀

(20V) C

T

؎0.6V

–V

؎0.6V

*OPTIONAL

Figure 3c. Offset Trim Positive Input (10 V FS)

OFFSET TRIM

؎0.6V

Figure 4. Current Source FS Trim

R

OFF

and flowing into Pin 3; it constitutes the signal current I_Tto be

converted. The second path, through another 100 Ω resistor R2,

carries the same nominal current. Two equal valued resistors

offer the best overall stability, and should be either 1% discrete

film units, or a pair from a common array.

5.6M⍀

AD654

10k⍀

8.25k⍀ 5k⍀

V

IN

Since the 1 mA FS input current is divided into two 500 µA legs

(one to ground and one to Pin 3), the total input signal current

(I_S) is divided by a factor of two in this network. To achieve the

same conversion scale factor, C_Tmust be reduced by a factor of

two. This results in a transfer unique to this hookup:

Figure 3d. Offset Trim Negative Input (–10 V FS)

R1

10k⍀

+5V

I_S

R3

10k⍀

f =

+

–

(20 V ) C_T

R5

100k⍀

؎0.6V

AD589

For calibration purposes, resistors R3 and R4 are added to the

network, allowing a ± 15% trim of scale factor with the values

shown. By varying R4’s value the trim range can be modified to

accommodate wider tolerance components or perhaps the cali-

bration tolerance on a current output transducer such as the

AD592 temperature sensor. Although the values of R1–R4 shown

are valid for 1 mA FS signals only, they can be scaled upward

proportionately for lower FS currents. For instance, they should

be increased by a factor of ten for a FS current of 100 µA.

R4

10k⍀

R2

10k⍀

–5V

Figure 3e. Offset Trim Bias Network

FULL-SCALE CALIBRATION

Full-scale trim is the calibration of the circuit to produce the

desired output frequency with a full-scale input applied. In most

cases this is accomplished by adjusting the scaling resistor R_T.

Precise calibration of the AD654 requires the use of an accurate

voltage standard set to the desired FS value and an accurate

frequency meter. A scope is handy for monitoring output wave-

shape. Verification of converter linearity requires the use of a

switchable voltage source or DAC having a linearity error below

±0.005%, and the use of long measurement intervals to mini-

mize count uncertainties. Since each AD654 is factory tested for

In addition to the offsets generated by the input amplifier’s bias

and offset currents, an offset voltage induced parasitic current

arises from the current fork input network. These effects are

minimized by using the bias current compensation resistor R_OFF

and offset trim scheme shown in Figure 3e.

Although device warm-up drifts are small, it is good practice to

allow the devices operating environment to stabilize before trim,

C

REV.

–5–

AD654

and insure the supply, source and load are appropriate. If provision

is made to trim offset, begin by setting the input to 1/10,000 of

full scale. Adjust the offset pot until the output is 1/10,000 of

full scale (for example, 25 Hz for a FS of 250 kHz). This is most

easily accomplished using a frequency meter connected to the

output. The FS input should then be applied and the gain pot

should be adjusted until the desired FS frequency is indicated.

between the various circuits in the system. Ceramic capacitors

of 0.1 µF to 1.0 µF should be applied between the supply-

voltage pins and analog signal ground for proper bypassing on

the AD654. A proper ground scheme appears in Figure 6.

10⍀

C

T

0.1␮F

8

1

7

6

5

4

INPUT PROTECTION

The AD654 was designed to be used with a minimum of additional

hardware. However, the successful application of a precision IC

involves a good understanding of possible pitfalls and the use of

suitable precautions. Thus +V_INand R_Tpins should not be driven

more than 300 mV below –V_S. Likewise, Logic Common should

not drop more than 500 mV below –V_S. This would cause inter-

nal junctions to conduct, possibly damaging the IC. In addition

to the diode shown in Figures 1 and 2 protecting Logic Common,

a second Schottky diode (MBD101) can protect the AD654’s

inputs from “below –V_S’’ inputs as shown in Figure 5. It is also

desirable not to drive +V_INand R_Tabove +V_S. In operation, the

converter will exhibit a zero output for inputs above (+V_S– 3.5 V).

Also, control currents above 2 mA will increase nonlinearity.

+5V

DIGITAL

P.S.

R

AD654

PU

GND

2

3

f

OUT

R

T

AGND

V

IN

Figure 6. Proper Ground Scheme

OUTPUT INTERFACING CONSIDERATION

The output stage’s design allows easy interfacing to all digital logic

families. The output NPN transistor’s emitter and collector are

both uncommitted. The emitter can be tied to any voltage between

–V_Sand 4 volts below +V_S, and the open collector can be pulled

up to a voltage 36 volts above the emitter regardless of +V_S. The

high power output stage can sink over 10 mA at a maximum

saturation voltage of 0.4 V. The stage limits the output current

at 25 mA and can handle this limit indefinitely without damag-

ing the device.

The AD654’s 80 dB dynamic range guarantees operation from a

control current of 1 mA (nominal FS) down to 100 nA (equiva-

lent to 1 mV to 10 V FS). Below 100 nA improper operation of

the oscillator may result, causing a false indication of input

amplitude. In many cases this might be due to short-lived noise

spikes which become added to input. For example, when scaled

to accept an FS input of 1 V, the –80 dB level is only 100 µV, so

when the mean input is only 60 dB below FS (1 mV), noise spikes

of 0.9 mV are sufficient to cause momentary malfunction.

NONLINEARITY SPECIFICATION

The preferred method of specifying nonlinearity error is in terms

of maximum deviation from the ideal relationship after calibrat-

ing the converter at full scale. This error will vary with the full

scale frequency and the mode of operation. The AD654 operates

best at a 150 kHz full-scale frequency with a negative voltage input;

the linearity is typically within 0.05%. Operating at higher fre-

quencies or with positive inputs will degrade the linearity as

indicated in the Specifications Table. Typical linearity at various

temperatures is shown in Figure 7.

This effect can be minimized by using a simple low-pass filter

ahead of the converter or a guard ring around the R_Tpin. The

filter can be assembled using the bias current compensation

resistor discussed in the previous section. For an FS of 10 kHz,

a single-pole filter with a time constant of 100 ms will be suitable,

but the optimum configuration will depend on the application

and the type of signal processing. Noise spikes are only likely to

be a cause of error when the input current remains near its mini-

mum value for long periods of time; above 100 nA full integration

of additive input noise occurs. Like the inputs, the capacitor

terminals are sensitive to interference from other signals. The

timing capacitor should be located as close as possible to the

AD654 to minimize signal pickup in the leads. In some cases,

guard rings or shielding may be required.

10

5

f

= –40؇C

AMB

1

0.5

AD654

f

= 0؇C TO +85؇C

AMB

I

IN

0.10

0.05

MBD101

0.01

10

150

250

350

500

FULL-SCALE FREQUENCY – kHz

Figure 5. Input Protection

Figure 7. Typical Nonlinearities at Different Full-Scale

Frequencies

DECOUPLING

It is good engineering practice to use bypass capacitors on the

supply-voltage pins and to insert small-valued resistors (10 to

100 Ω) in the supply lines to provide a measure of decoupling

C

REV.

–6–

AD654

1N4148

1␮F

R1

R2

R3

R4

R

T

V

S

(10V TO 15V)

+

–

AD654

AD589

140⍀

OSC/

DRIVER

Q1

2N3906

CMOS

OUTPUT

R

S

AD592

1␮A/k⍀

TTL

OUTPUT

(1 LOAD)

C

T

0.01␮F

R6

220⍀

R5

I

T

f =

(10V) C

T

Figure 8. Two-Wire Temperature-to-Frequency Converter

TWO-WIRE TEMPERATURE-TO-FREQUENCY

CONVERSION

Figure 8 shows the AD654 in a two-wire temperature-to-frequency

conversion scheme. The twisted pair transmission line serves the

dual purpose of supplying power to the device and also carrying

frequency data in the form of current modulation.

values shown in Table II. Since temperature is the parameter of

interest, an NPO ceramic capacitor is used as the timing capaci-

tor for low V/F TC.

When scaling per K, resistors R1–R3 and the AD589 voltage

reference are not used. The AD592 produces a 1 µA/K current

output which drives Pin 3 of the AD654. With the timing

capacitor of 0.01 µF this produces an output frequency scaled to

10 Hz/K. When scaling per °C and °F, the AD589 and resistors

R1–R3 offset the drive current at Pin 3 by 273.2 µA for scaling

per °C and 255.42 µA for scaling per °F. This will result in fre-

quencies sealed at 10 Hz/°C and 5.55 Hz/°F, respectively.

The positive supply line is fed to the remote V/F through a

140 Ω resistor. This resistor is selected such that the quiescent

current of the AD654 will cause less than one V_BEto be dropped.

As the V/F oscillates, additional switched current is drawn through

R_Lwhen Pin 1 goes low. The peak level of this additional cur-

rent causes Q1 to saturate, and thus regenerates the AD654’s

output square wave at the collector. The supply voltage to the

AD654 then consists of a dc level, less the resistive line drop, plus a

one V_BEp-p square wave at the output frequency of the AD654.

This ripple is reduced by the diode/capacitor combination.

OPTOISOLATOR COUPLING

A popular method of isolated signal coupling is via optoelec-

tronic isolators, or optocouplers. In this type of device, the signal is

coupled from an input LED to an output photo-transistor, with

light as the connecting medium. This technique allows dc to be

transmitted, is extremely useful in overcoming ground loop

problems between equipment, and is applicable over a wide

range of speeds and power.

To set up the receiver circuit for a given voltage, the R_Sand R_L

resistances are selected as shown in Table I. CMOS logic stages

can be driven directly from the collector of Q1, and a single TTL

load can be driven from the junction of R_Sand R6.

Figure 9 shows a general purpose isolated V/F circuit using a

low cost 4N37 optoisolator. A +5 V power supply is assumed for

both the isolated (+5 V isolated) and local (+5 V local) supplies.

The input LED of the isolator is driven from the collector out-

put of the AD654, with a 9 mA current level established by R1

for high speed, as well as for a 100% current transfer ratio.

Table I.

+V_S

R_S(⍀)

R_L(⍀)

10 V

15 V

270

680

1.8k

2.7k

5V

(LOCAL)

(ISOLATED)

4N37

OPTO-ISOLATOR

Table II.

R1

390⍀

R3

270⍀

(+V_S) R1 (⍀) R2 (⍀) R3 (⍀) R4 (⍀) R5 (⍀)

GRN

LED

10 V

15 V

–

100k

127k

74LS14

K

F = 10 Hz/K

F = 10 Hz/°C

F = 5.55 Hz/°F

AD654

OSC/

DRIVER

Q1

2N3904

V/F OUTPUT

FS = 100kHz

TTL

10 V 6.49k 4.02k 1k

15 V 12.7k 4.02k 1k

95.3k 22.6k

78.7k 36.5k

R2

120⍀

°C

°F

V

IN

(0V TO 1V)

R

1k⍀

10 V 6.49k 4.42k 1k

15 V 12.7k 4.42k 1k

154k

105k

22.6k

36.5k

T

C

T

1000pF

At the V/F end, the AD592C temperature transducer is inter-

faced with the AD654 in such a manner that the AD654 output

frequency is proportional to temperature. The output frequency

can be sealed and offset from K to °C or °F using the resistor

ISOLATED

LOCAL

Figure 9. Optoisolator Interface

C

REV.

–7–

AD654

At the receiver side, the output transistor is operated in the

photo-transistor mode; that is with the base lead (Pin 6) open.

This allows the highest possible output current. For reasonable

speed in this mode, it is imperative that the load impedance be

as low as possible. This is provided by the single transistor stage

current-to-voltage converter, which has a dynamic load imped-

ance of less than 10 ohms and interfaces with TTL at the output.

Longer count periods not only result in the count having more

resolution, they also serve as an integration of noisy analog signals.

For example, a normal-mode 60 Hz sine wave riding on the input

of the AD654 will result in the output frequency increasing on

the positive half of the sine wave and decreasing on the negative

half of the sine wave. This effect is cancelled by selecting a count

period equal to an integral number of noise signal periods. A

100 ms count period is effective because it not only has an inte-

gral number of 60 Hz cycles (6), it also has an integral number

of 50 Hz cycles (5). This is also true of the 1 second and 10 sec-

ond count period.

USING A STAND-ALONE FREQUENCY COUNTER/LED

DISPLAY DRIVER FOR VOLTMETER APPLICATIONS

Figure 10 shows the AD654 used with a stand-alone frequency

counter/LED display driver. With C_T= 1000 pF and R_T= 1 kΩ

the AD654 produces an FS frequency of 100 kHz when V_IN

=

AD654-BASED ANALOG-TO-DIGITAL CONVERSION

USING A SINGLE CHIP MICROCOMPUTER

+1 V. This signal is fed into the ICM7226A, a universal counter

system that drives common anode LEDs. With the FUNCTION

pin tied to D1 through a 10 kΩ resistor the ICM7226A counts the

frequency of the signal at A_IN. This count period is selected by

the user and can be 10 ms, 100 ms, 1s, or 10 seconds, as shown on

Pin 21. The longer the period selected, the more resolution the

count will have. The ICM7226A then displays the frequency on

the LEDs, driving them directly as shown. Refreshing of the LEDs

is handled automatically by the ICM7226. The entire circuit op-

erates on a single +5 V supply and gives a meter with 3, 4, or 5

digit resolution.

The AD654 can serve as an analog-to-digital converter when

used with a single component microcomputer that has an inter-

val timer/event counter such as the 8048. Figure 11 shows the

AD654, with a full-scale input voltage of +1 V and a full-scale

output frequency of 100 kHz, connected to the timer/counter

input Pin T1 of the 8048. Such a system can also operate on a

single +5 V supply.

The 8748 counter is negative edge triggered; after the STRT

CNT instruction is executed subsequent high to low transitions

on T1 increment the counter. The maximum rate at which the

counter may be incremented is once per three instruction cycles;

using a 6 MHz crystal, this corresponds to once every 7.5 µs, or

a maximum frequency of 133 kHz. Because the counter overflows

every 256 counts (8 bits), the timer interrupt is enabled. Each

overflow then causes a jump to a subroutine where a register is

incremented. After the STOP TCNT instruction is executed, the

number of overflows that have occurred will be the number in

this register. The number in this register multiplied by 256 plus

the number in the counter will be the total number of negative

edges counted during the count period. The count period is

handled simply by decrementing a register the number of times

necessary to correspond to the desired count time. After the

register has been decremented the required number of times the

STOP TCNT instruction is executed.

5V

1k⍀

1

2

3

4

8

7

6

5

825⍀

500⍀

1000pF

AD654

+

V

1k⍀

IN

(0V TO 1V)

–

40

AIN

1

2

30k⍀

39

38

37

HOLD

3

10MHz

CRYSTAL

10k⍀

DI PIN 30

4

FUNCTION

NC

5V

OSL JN 36

5

6

OSL OUT ³⁵

NC ³⁴

22M⍀

7

5V

dp

e

33

8

39pF

ICM7226A

The total number of negative edges counted during the count

period is proportional to the input voltage. For example, if a 1 V

full-scale input voltage produces a 100 kHz signal and the count

period is 100 ms, then the total count will be 10,000. Scaling

from this maximum is then used to determine the input voltage,

i.e., a count of 5000 corresponds to an input voltage of 0.5 V.

As with the ICM7226, longer count times result in counts hav-

ing more resolution; and they result in the integration of noisy

analog signals.

32

31

30

9

g

10

11

12

13

14

15

16

17

18

19

20

5V

D1

a

D2 ²⁹

GND

28

d

b

c

D3

27

D4

26

D5

V+ ²⁵

f

5V

24

D6

23

22

21

D1 (10ms)

D2 (100ms)

D7

D8

4

10k⍀

RANGE

D3 (1s)

8

D4 (10s)

8

D.P.

g

f

e

d

c

b

a

LED

OVERFLOW

INDICATOR

D8

D7

D6

D5

D4

D3

D2

D1

NC = NO CONNECT

Figure 10. AD654 With Stand-Alone Frequency Counter/

LED Display Driver

C

REV.

–8–

AD654

5V

GND

FREQUENCY DOUBLING

Since the AD654’s output is a square-wave rather than a pulse

train, information about the input signal is carried on both

halves of the output waveform. The circuit in Figure 12 converts

the output into a pulse train, effectively doubling the output

frequency, while preserving the better low frequency linearity of

the AD654. This circuit also accommodates an input voltage

that is greater than the AD654 supply voltage.

V

20pF

CC

DD

SS

P10

XTAL1

PORT 1

PORT 2

6MHz

1␮F

P17

P20

XTAL2

RESET

EA

8048

Resistors R1–R3 are used to scale the 0 V to +10 V input voltage

down to 0 V to +1 V as seen at Pin 4 of the AD654. Recall that

V_INmust be less than V_SUPPLY–4 V, or in this case less than 1 V.

The timing resistor and capacitor are selected such that this 0 V

to +1 V signal seen at Pin 4 results in a 0 kHz to 200 kHz output

frequency.

NC

SS

P27

INT

T0

DB0

BUS

PORT

DB7

T1

ALE PSEN PROG WR RD

NC

The use of R4, C1 and the XOR gate doubles this 200 kHz

output frequency to 400 kHz. The AD654 output transistor is

basically used as a switch, switching capacitor C1 between a

charging mode and a discharging mode of operation. The voltages

seen at the input of the 74LS86 are shown in the waveform dia-

gram. Due to the difference in the charge and discharge time

constants, the output pulse widths of the 74LS86 are not equal.

The output pulse is wider when the capacitor is charging due to

its longer rise time than fall time. The pulses should therefore be

counted on their rising, rather than falling, edges.

NC = NO CONNECT

5V

10k⍀

1

2

3

4

8

7

6

5

AD654

1000pF

1k⍀

+

825⍀

1%

V

IN

(0V TO 1V)

500⍀

–

D

A

Figure 11. AD654 VFC as an ADC

5V

R

PU

74LS86

2.87k⍀

A

B

C

AD654

R1

R2

OSC/

DRIVER

R4

1k⍀

8.06k⍀ 2k⍀

C1

1000pF

V/F OUTPUT

FS = 400MHz

R3

1k⍀

V

IN

(0V TO 10V)

R

T

1k⍀

C

T

500pF

OFF

TRANSISTOR

ON

V

0

A

B

C

V

0

5

0

WAVEFORM DIAGRAM

Figure 12. Frequency Doubler

C

REV.

–9–

AD654

+15V

10␮F

+5V

+15V

A3 = 74LS86

A3-d

MINIMUM

DISTANCE

0.1␮F

D

V4

0.1␮F

R7

8.2⍀

68k⍀ 68k⍀

10␮F

+

V1

Q1

Q2

V3

1

2

3

4

8

7

6

5

J270

A3-c

A3-b

V2

C

A2

LM360

T

AD654

100pF

10␮F

1k⍀

+

18⍀

J270

A3-a

V

5.9k⍀

1%

(

؋

2)

IN

R

= 1k⍀

0.1␮F

MINIMUM

DISTANCE

T

470pF

(0V TO 1V)

–

0.1␮F

10␮F

A

D

–5V

Figure 13. 2 MHz, Frequency Doubling V/F

OPERATION AT HIGHER OUTPUT FREQUENCIES

Operation of the AD654 via the conventional output (Pins 1 and

2) is speed limited to approximately 500 kHz for reasons of TTL

logic compatibility. Although the output stage may become

speed limited, the multivibrator core itself is able to oscillate to

1 MHz or more. The designer may take advantage of this feature in

order to operate the device at frequencies in excess of 500 kHz.

The output of the comparator is a complementary square wave

at 1 MHz FS. Unlike pulse train output V/F converters, each

half-cycle of the AD654 output conveys information about the

input. Thus it is possible to count edges, rather than full cycles

of the output, and double the effective output frequency. The

XOR gate following A2 acts as an edge detector producing a short

pulse for each input state transition. This effectively doubles the

V/F FS frequency to 2 MHz. The final result is a 1 V full-scale

input V/F with a 2 MHz full-scale output capability; typical

nonlinearity is 0.5%.

Figure 13 illustrates this with a circuit offering 2 MHz full scale.

In this circuit the AD654 is operated at a full scale (FS) of 1 mA,

with a C_Tof 100 pF. This achieves a basic device FS frequency

of 1 MHz across C_T. The P channel JFETs, Q1 and Q2, buffer

the differential timing capacitor waveforms to a low impedance

level where the push-pull signal is then ac coupled to the high speed

comparator A2. Hysteresis is used, via R7, for nonambiguous

switching and to eliminate the oscillations which would other-

wise occur at low frequencies.

2V

5V

500ns

2V

0

100

90

V1

2V

0

V2

V3

V4

The net result of this is a very high speed circuit which does not

compromise the AD654 dynamic range. This is a result of the FET

buffers typically having only a few pA of bias current. The high

end dynamic range is limited, however, by parasitic package and

layout capacitances in shunt with C_T, as well as those from each node

to ac ground. Minimizing the lead length between A2–6/A2–7 and

Q1/Q2 in PC layout will help. A ground plane will also help

stability. Figure 14 shows the waveforms V1–V4 found at the

respective points shown in Figure 13.

5V

0

10

0%

5V

0

2V

5V

Figure 14. Waveforms of 2 MHz Frequency Doubler

C

REV.

–10–

AD654

OUTLINE DIMENSIONS

0.400 (10.16)

0.365 (9.27)

0.355 (9.02)

8

1

5

4

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.100 (2.54)

BSC

0.060 (1.52)

MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.210 (5.33)

MAX

0.015

(0.38)

MIN

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.015 (0.38)

GAUGE

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

PLANE

SEATING

PLANE

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

0.430 (10.92)

MAX

0.005 (0.13)

MIN

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 15. 8-Lead Plastic Dual In-Line Package [PDIP]

Narrow Body

(N-8)

Dimensions shown in inches and (millimeters)

5.00 (0.1968)

4.80 (0.1890)

8

1

5

4

6.20 (0.2441)

5.80 (0.2284)

4.00 (0.1574)

3.80 (0.1497)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

BSC

45°

1.75 (0.0688)

1.35 (0.0532)

0.25 (0.0098)

0.10 (0.0040)

8°

0°

0.51 (0.0201)

0.31 (0.0122)

COPLANARITY

0.10

1.27 (0.0500)

0.40 (0.0157)

0.25 (0.0098)

0.17 (0.0067)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-AA

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 16. 8-Lead Standard Small Outline Package [SOIC_N]

(Narrow Body)

(R-8)

Dimensions shown in millimeters and (inches)

Rev. C | Page 11

AD654

ORDERING GUIDE

Model¹

AD654JN

AD654JNZ

AD654JNZ/+

AD654JR

AD654JR-REEL

AD654JR-REEL7

AD654JRZ

AD654JRZ-REEL

AD654JRZ-REEL7

Temperature Range

–40°C to +85°C

Package Description

8-Lead PDIP

Package Option

N-8

R-8

8-Lead PDIP

8-Lead SOIC_N

¹Z = RoHS Compliant Part.

REVISION HISTORY

7/13—Rev. B to Rev. C

Added ESD Caution and Stresses Paragraph................................ 3

Updated Outline Dimensions....................................................... 11

Changes to Ordering Guide .......................................................... 11

12/99—Rev. A to Rev. B

registered trademarks are the property of their respective owners.

D11523-0-7/13(C)

Rev. C | Page 12


型号：	AD654JNZ
厂家：	ADI
描述：	Low Cost Monolithic Voltage-to-Frequency Converter 低成本的单芯片电压频率转换器转换器
文件：	总12页 (文件大小：359K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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