AD6684 [ADI]
135 MHz Quad IF Receiver;
ADI 
135 MHz Quad IF Receiver
AD6684
4 integrated wideband digital downconverters (DDCs)
48-bit numerically controlled oscillator (NCO), up to
4 cascaded half-band filters
1.4 GHz analog input full power bandwidth
Amplitude detect bits for efficient automatic gain control
(AGC) implementation
Differential clock input
Integer clock divide by 1, 2, 4, or 8
Data Sheet
FEATURES
JESD204B (Subclass 1) coded serial digital outputs
Lane rates up to 15 Gbps
1.68 W total power at 500 MSPS
420 mW per analog-to-digital converter (ADC) channel
SFDR = 82 dBFS at 305 MHz (1.8 V p-p input range)
SNR = 66.8 dBFS at 305 MHz (1.8 V p-p input range)
Noise density = −151.5 dBFS/Hz (1.8 V p-p input range)
Analog input buffer
On-chip dithering to improve small signal linearity
Flexible differential input range
1.44 V p-p to 2.16 V p-p (1.80 V p-p nominal)
82 dB channel isolation/crosstalk
0.975 V, 1.8 V, and 2.5 V dc supply operation
Noise shaping requantizer (NSR) option for main receiver
Variable dynamic range (VDR) option for digital
predistortion (DPD)
On-chip temperature diode
Flexible JESD204B lane configurations
APPLICATIONS
Communications
Diversity multiband, multimode digital receivers
3G/4G, W-CDMA, GSM, LTE, LTE-A
HFC digital reverse path receivers
Digital predistortion observation paths
General-purpose software radios
FUNCTIONAL BLOCK DIAGRAM
AVDD2
(1.8V)
AVDD3
(2.5V)
AVDD1 AVDD1_SR
DVDD
DRVDD1 DRVDD2
SPIVDD
(1.8V)
(0.975V)
(0.975V)
(0.975V) (0.975V)
(1.8V)
SIGNAL PROCESSING
BUFFER
14
VIN+A
ADC
CORE
DIGITAL DOWNCONVERTER
(×2)
VIN–A
VCM_AB
FD_A
2
JESD204B
HIGH SPEED
SERIALIZER
SERDOUTAB0±
SERDOUTAB1±
Tx
OUTPUTS
NOISE SHAPED REQUANTIZER
(×2)
FAST
DETECT
SIGNAL
MONITOR
FD_B
BUFFER
VARIABLE DYNAMIC RANGE
(×2)
14
VIN+B
VIN–B
ADC
CORE
SIGNAL MONITOR
AND FAST DETECT
SYSREF±
JESD204B
SUBCLASS 1
CONTROL
CLOCK
GENERATION
SYNCINB±AB
SYNCINB±CD
CLK+
CLK–
÷2
÷4
÷8
SIGNAL PROCESSING
BUFFER
14
VIN+C
ADC
CORE
DIGITAL DOWNCONVERTER
(×2)
VIN–C
VCM_CD
FD_C
2
JESD204B
HIGH SPEED
SERIALIZER
SERDOUTCD0±
SERDOUTCD1±
Tx
NOISE SHAPED REQUANTIZER
(×2)
OUTPUTS
FAST
DETECT
SIGNAL
MONITOR
FD_D
VARIABLE DYNAMIC RANGE
(×2)
BUFFER
14
VIN+D
VIN–D
ADC
CORE
SPI CONTROL
PDWN/STBY
AD6684
AGND DRGND
SDIO
SCLK CSB
Figure 1.
Rev. 0
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AD6684
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
DDC Gain Stage ......................................................................... 44
DDC Complex to Real Conversion ......................................... 44
DDC Example Configurations ................................................. 45
Noise Shaping Requantizer (NSR) ............................................... 49
Decimating Half-Band Filter .................................................... 49
NSR Overview ............................................................................ 50
Variable Dynamic Range (VDR).................................................. 51
VDR Real Mode.......................................................................... 52
VDR Complex Mode ................................................................. 52
Digital Outputs ............................................................................... 54
Introduction to the JESD204B Interface ................................. 54
JESD204B Overview .................................................................. 54
Functional Overview ................................................................. 56
JESD204B Link Establishment ................................................. 56
Physical Layer (Driver) Outputs .............................................. 57
JESD204B Tx Converter Mapping........................................... 59
Setting Up the AD6684 Digital Interface................................ 60
Latency............................................................................................. 64
End-To-End Total Latency........................................................ 64
Multichip Synchronization............................................................ 65
SYSREF Setup/Hold Window Monitor................................. 67
Test Modes....................................................................................... 69
ADC Test Modes ........................................................................ 69
JESD204B Block Test Modes .................................................... 70
Serial Port Interface........................................................................ 72
Configuration Using the SPI..................................................... 72
Hardware Interface..................................................................... 72
SPI Accessible Features.............................................................. 72
Memory Map .................................................................................. 73
Reading the Memory Map Register Table............................... 73
Memory Map .................................................................................. 74
Memory Map Summary ............................................................ 74
Memory Map Details................................................................. 82
Applications Information............................................................ 106
Power Supply Recommendations........................................... 106
Exposed Pad Thermal Heat Slug Recommendations.......... 106
AVDD1_SR (Pin 64) and AGND_SR (Pin 63 and Pin 67). 106
Outline Dimensions..................................................................... 107
Ordering Guide ........................................................................ 107
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description......................................................................... 4
Product Highlights ........................................................................... 4
Specifications..................................................................................... 5
DC Specifications ......................................................................... 5
AC Specifications.......................................................................... 6
Digital Specifications ................................................................... 8
Switching Specifications .............................................................. 9
Timing Specifications .................................................................. 9
Absolute Maximum Ratings.......................................................... 11
Thermal Characteristics ............................................................ 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Typical Performance Characteristics ........................................... 14
Equivalent Circuits......................................................................... 21
Theory of Operation ...................................................................... 23
ADC Architecture ...................................................................... 23
Analog Input Considerations.................................................... 23
Voltage Reference ....................................................................... 25
Clock Input Considerations...................................................... 26
Temperature Diode .................................................................... 27
ADC Overrange and Fast Detect.................................................. 28
ADC Overrange.......................................................................... 28
Fast Threshold Detection (FD_A, FD_B, FD_C and FD_D).... 28
Signal Monitor ................................................................................ 29
SPORT Over JESD204B............................................................. 29
Digital Downconverter (DDC)..................................................... 32
DDC I/Q Input Selection .......................................................... 32
DDC I/Q Output Selection ....................................................... 32
DDC General Description ........................................................ 32
Frequency Translation ................................................................... 38
General Description................................................................... 38
DDC NCO + Mixer Loss and SFDR........................................ 39
Numerically Controlled Oscillator........................................... 39
FIR Filters ........................................................................................ 41
General Description................................................................... 41
Half-Band Filters ........................................................................ 42
Rev. 0 | Page 2 of 107
Data Sheet
AD6684
REVISION HISTORY
10/2016—Revision 0: Initial Version
Rev. 0 | Page 3 of 107
AD6684
Data Sheet
GENERAL DESCRIPTION
is truncated. This mask is based on DPD applications and
supports tunable real IF sampling, and zero IF or complex IF
receive architectures.
The AD6684 is a 135 MHz bandwidth, quad intermediate
frequency (IF) receiver. It consists of four 14-bit, 500 MSPS
ADCs and various digital processing blocks consisting of four
wideband DDCs, an NSR, and VDR monitoring. The device has
an on-chip buffer and a sample-and-hold circuit designed for low
power, small size, and ease of use. This device is designed to
support communications applications. The analog full power
bandwidth of the device is 1.4 GHz.
Operation of the AD6684 in the DDC, NSR, and VDR modes is
selectable via SPI-programmable profiles (the default mode is
NSR at startup).
In addition to the DDC blocks, the AD6684 has several functions
that simplify the AGC function in the communications receiver.
The programmable threshold detector allows monitoring of the
incoming signal power using the fast detect output bits of the
ADC. If the input signal level exceeds the programmable threshold,
the fast detect indicator goes high. Because this threshold
indicator has low latency, the user can quickly turn down the
system gain to avoid an overrange condition at the ADC input.
The quad ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations. The AD6684 is optimized for wide
input bandwidth, excellent linearity, and low power in a small
package.
Users can configure each pair of IF receiver outputs onto either
one or two lanes of Subclass 1 JESD204B-based high speed
serialized outputs, depending on the decimation ratio and the
acceptable lane rate of the receiving logic device. Multiple device
synchronization is supported through the SYSREF ,
The analog inputs and clock signal input are differential. Each
pair of ADC data outputs are internally connected to two DDCs
through a crossbar mux. Each DDC consists of up to five cascaded
signal processing stages: a 48-bit frequency translator, NCO, and
up to four half-band decimation filters.
SYNCINB AB, and SYNCINB CD input pins.
Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows improved SNR performance in
a smaller frequency band within the Nyquist bandwidth. The
device supports two different output modes selectable via the
serial port interface (SPI). With the NSR feature enabled, the
outputs of the ADCs are processed such that the AD6684
supports enhanced SNR performance within a limited portion
of the Nyquist bandwidth while maintaining a 9-bit output
resolution.
The AD6684 has flexible power-down options that allow
significant power savings when desired. All of these features can
be programmed using the 1.8 V capable, 3-wire SPI.
The AD6684 is available in a Pb-free, 72-lead LFCSP and is
specified over the −40°C to +105°C junction temperature range.
This product may be protected by one or more U.S. or international
patents
PRODUCT HIGHLIGHTS
Each ADC output is also connected internally to a VDR block.
This optional mode allows full dynamic range for defined input
signals. Inputs that are within a defined mask (based on DPD
applications) are passed unaltered. Inputs that violate this
defined mask result in the reduction of the output resolution.
1. Low power consumption per channel.
2. JESD204B lane rate support up to 15 Gbps.
3. Wide full power bandwidth supports IF sampling of signals
up to 1.4 GHz.
4. Buffered inputs ease filter design and implementation.
5. Four integrated wideband decimation filters and NCO
blocks supporting multiband receivers.
With VDR, the dynamic range of the observation receiver is
determined by a defined input frequency mask. For signals
falling within the mask, the outputs are presented at the
maximum resolution allowed. For signals exceeding defined
power levels within this frequency mask, the output resolution
6. Programmable fast overrange detection.
7. On-chip temperature diode for system thermal management.
Rev. 0 | Page 4 of 107
Data Sheet
AD6684
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V,
SPIVDD = 1.8 V, specified maximum sampling rate, clock divider = 4, 1.8 V p-p full-scale differential input, 0.5 V internal reference, AIN =
−1.0 dBFS, default SPI settings, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating
junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 50°C (TA = 25°C).
Table 1.
Parameter
Min
Typ
Max
Unit
RESOLUTION
14
Bits
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Guaranteed
0
0
% FSR
% FSR
% FSR
% FSR
LSB
−5.0
+5.0
1.0
0.4
1.0
−0.7
−5.1
+0.7
+5.1
LSB
8
ppm/°C
ppm/°C
Gain Error
214
INTERNAL VOLTAGE REFERENCE
Voltage
0.5
2.6
V
INPUT REFERRED NOISE
ANALOG INPUTS
LSB rms
Differential Input Voltage Range (Programmable)
1.44
1.80
1.34
1.75
200
1.4
2.16
V p-p
V
pF
Ω
GHz
Common-Mode Voltage (VCM
)
Differential Input Capacitance
Differential Input Resistance
Analog Input Full Power Bandwidth
POWER SUPPLY1
AVDD1
AVDD1_SR
AVDD2
AVDD3
DVDD
DRVDD1
DRVDD2
SPIVDD
IAVDD1
0.95
0.95
1.71
2.44
0.95
0.95
1.71
1.71
0.975
0.975
1.8
1.00
1.00
1.89
2.56
1.00
1.00
1.89
1.89
482
53
473
103
198
207
29
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
2.5
0.975
0.975
1.8
1.8
319
21
438
87
145
162
23
IAVDD1_SR
IAVDD2
IAVDD3
2
IDVDD
IDRVDD1
IDRVDD2
ISPIVDD
1
1.6
POWER CONSUMPTION
Total Power Dissipation (Including Output Drivers)2
Power-Down Dissipation
Standby3
1.68
325
1.20
1.94
W
mW
W
1 Power is measured at NSR, 28% bandwidth, L, M, and F = 222.
2 Default mode, no decimation enabled. For each link, L = 2, M = 2, and F = 2.
3 Standby mode is controlled by the SPI.
Rev. 0 | Page 5 of 107
AD6684
Data Sheet
AC SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V,
SPIVDD = 1.8 V, specified maximum sampling rate, clock divider = 4, 1.8 V p-p full-scale differential input, 0.5 V internal reference, AIN =
−1.0 dBFS, default SPI settings, VDR mode (input mask not triggered), unless otherwise noted. Minimum and maximum specifications are
guaranteed for the full operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 50°C
(TA = 25°C).
Table 2.
Analog Input Full Scale =
1.44 V p-p
Analog Input Full Scale =
1.80 V p-p
Analog Input Full Scale =
2.16 V p-p
Parameter1
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
ANALOG INPUT FULL SCALE
NOISE DENSITY2
SIGNAL-TO-NOISE RATIO (SNR)3
VDR Mode
1.44
1.80
2.16
V p-p
−149.7
−151.5
−153.0
dBFS/Hz
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
65.4
65.3
65.2
65.0
64.8
64.5
67.1
67.0
66.8
66.6
66.5
66.0
68.4
68.3
68.0
67.8
67.5
66.9
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
64.8
21% Bandwidth (BW) Mode
(>105 MHz at 500 MSPS)
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
72.1
71.8
71.9
71.6
71.0
70.6
73.8
73.5
73.5
73.2
72.7
72.1
75.1
74.8
74.7
74.4
73.7
73.0
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
28% BW Mode (>135 MHz at
500 MSPS)
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
69.6
69.1
69.1
69.4
68.5
68.5
71.3
70.8
70.7
71.0
70.2
70.0
72.6
72.1
71.9
72.2
71.2
70.9
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
SIGNAL-TO-NOISE-AND-DISTORTION
RATIO (SINAD)3
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
EFFECTIVE NUMBER OF BITS (ENOB)3
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
65.3
65.2
65.1
65.0
64.7
64.2
67.0
66.8
66.6
66.4
66.1
65.5
68.2
67.9
67.6
67.3
66.9
66.2
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
64.5
10.4
10.5
10.5
10.5
10.5
10.4
10.3
10.8
10.8
10.7
10.7
10.6
10.6
11.0
10.9
10.9
10.8
10.8
10.7
Bits
Bits
Bits
Bits
Bits
Bits
Rev. 0 | Page 6 of 107
Data Sheet
AD6684
Analog Input Full Scale =
1.44 V p-p
Analog Input Full Scale =
1.80 V p-p
Analog Input Full Scale =
2.16 V p-p
Parameter1
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
SPURIOUS-FREE DYNAMIC RANGE
(SFDR)3
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
89
89
82
82
77
82
90
85
82
83
75
79
80
77
78
77
72
76
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
75
SPURIOUS-FREE DYNAMIC RANGE
(SFDR) AT −3 dBFS3
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
94
94
89
87
82
85
94
90
90
86
80
82
86
82
83
84
77
79
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
WORST HARMONIC, SECOND OR
THIRD3
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
−89
−89
−82
−82
−77
−82
−90
−85
−82
−83
−75
−79
−80
−77
−78
−77
−72
−76
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
−75
WORST HARMONIC, SECOND OR
THIRD AT −3 dBFS3
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
−94
−94
−89
−87
−82
−85
−94
−90
−90
−86
−80
−82
−86
−82
−83
−84
−77
−79
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
WORST OTHER, EXCLUDING SECOND
OR THIRD HARMONIC3
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
−96
−97
−97
−95
−92
−90
−98
−97
−98
−96
−91
−89
−99
−97
−97
−96
−88
−86
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
−86
TWO TONE INTERMODULATION
DISTORTION (IMD), AIN1 AND
AIN2 = −7 dBFS
fIN1 = 154 MHz, fIN2 = 157 MHz
fIN1 = 302 MHz, fIN2 = 305 MHz
CROSSTALK4
−93
−90
82
−90
−90
82
−84
−84
82
dBFS
dBFS
dB
FULL POWER BANDWIDTH5
1.4
1.4
1.4
GHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
2 Noise density is measured with no analog input signal.
3 See Table 9 for recommended settings for full-scale voltage and buffer current setting.
4 Crosstalk is measured at 155 MHz with a −1.0 dBFS analog input on one channel and no input on the adjacent channel.
5 Measured with circuit shown in Figure 58.
Rev. 0 | Page 7 of 107
AD6684
Data Sheet
DIGITAL SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V,
SPIVDD = 1.8 V, specified maximum sampling rate, clock divider = 4, 1.8 V p-p full-scale differential input, 0.5 V internal reference, AIN =
−1.0 dBFS, default SPI settings, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction
temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 50°C (TA = 25°C).
Table 3.
Parameter
Min
Typ
Max
1600
0.9
Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LVDS/LVPECL
400
800
0.69
32
mV p-p
V
kΩ
pF
SYSREF INPUTS (SYSREF+, SYSREF−)1
Logic Compliance
LVDS/LVPECL
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance (Single-Ended per Pin)
LOGIC INPUTS (PDWN/STBY)
Logic Compliance
400
0.6
18
800
0.69
22
1800
2.2
mV p-p
V
kΩ
pF
0.7
CMOS
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
0.65 × SPIVDD
0
V
V
MΩ
0.35 × SPIVDD
0.35 × SPIVDD
0.45
10
LOGIC INPUTS (SDIO, SCLK, CSB)
Logic Compliance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
CMOS
0.65 × SPIVDD
0
V
V
kΩ
56
LOGIC OUTPUT (SDIO)
Logic Compliance
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
SYNCIN INPUT (SYNCINB+AB, SYNCINB−AB, SYNCINB+CD, SYNCINB−CD)
Logic Compliance
CMOS
SPIVDD − 0.45 V
0
V
V
LVDS/LVPECL/CMOS
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance (Single-Ended per Pin)
LOGIC OUTPUTS (FD_A, FD_B)
Logic Compliance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
400
0.6
18
800
0.69
22
1800
2.2
mV p-p
V
kΩ
pF
0.7
CMOS
56
0.8 × SPIVDD
0
V
V
kΩ
0.5
DIGITAL OUTPUTS (SERDOUTx , x = AB0, AB1, CD0, and CD1)
Logic Compliance
Differential Output Voltage
CML
455.8
15
mV p-p
mA
Short-Circuit Current (ID SHORT
)
Differential Termination Impedance
100
Ω
1 DC-coupled input only.
Rev. 0 | Page 8 of 107
Data Sheet
AD6684
SWITCHING SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V,
SPIVDD = 1.8 V, specified maximum sampling rate, clock divider = 4, 1.8 V p-p full-scale differential input, 0.5 V internal reference, AIN =
−1.0 dBFS, default SPI settings, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction
temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 50°C (TA = 25°C).
Table 4.
Parameter
Min
Typ
Max
Unit
CLOCK
Clock Rate at CLK+/CLK− Pins
Maximum Sample Rate1
Minimum Sample Rate2
Clock Pulse Width High
Clock Pulse Width Low
OUTPUT PARAMETERS
Unit Interval (UI)3
Rise Time (tR) (20% to 80% into 100 Ω Load)
Fall Time (tF) (20% to 80% into 100 Ω Load)
Phase-Locked Loop (PLL) Lock Time
Data Rate per Channel (NRZ)4
LATENCY5
0.3
2.4
GHz
MSPS
MSPS
ps
500
240
125
125
ps
62.5
100
31.25
31.37
5
ps
ps
ps
ms
Gbps
1.5625
10
15
30
Pipeline Latency
Fast Detect Latency
54
Sample clock cycles
Sample clock cycles
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tj)
Out-of-Range Recovery Time
160
44
1
ps
fs rms
Sample clock cycles
1 The maximum sample rate is the clock rate after the divider.
2 The minimum sample rate operates at 240 MSPS with L = 2 or L = 1. Refer to SPI Register 0x011A to reduce the threshold of the clock detect circuit.
3 Baud rate = 1/UI. A subset of this range can be supported.
4 Default L = 2. This number can be changed based on the sample rate and decimation ratio.
5 No DDCs used. L = 2, M = 2, F = 2 for each link.
TIMING SPECIFICATIONS
Table 5.
Parameter
Test Conditions/Comments
Min Typ
Max Unit
CLK+ to SYSREF+ TIMING REQUIREMENTS See Figure 3
tSU_SR
tH_SR
Device clock to SYSREF+ setup time
Device clock to SYSREF+ hold time
−44.8
64.4
ps
ps
SPI TIMING REQUIREMENTS
See Figure 4
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tACCESS
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK must be in a logic high state
Minimum period that SCLK must be in a logic low state
Maximum time delay between falling edge of SCLK and output
data valid for a read operation
4
2
40
2
2
ns
ns
ns
ns
ns
ns
ns
10
10
6
10
ns
tDIS_SDIO
Time required for the SDIO pin to switch from an output to an
input relative to the CSB rising edge (not shown in Figure 4)
10
ns
Rev. 0 | Page 9 of 107
AD6684
Data Sheet
Timing Diagrams
APERTURE
DELAY
SAMPLE N
ANALOG
INPUT
SIGNAL
N – 53
N + 1
N – 54
N – 52
N – 1
N – 51
N – 50
CLK–
CLK+
Figure 2. Data Output Timing (NSR Mode, 21%, L, M, F = 222)
CLK–
CLK+
tSU_SR
tH_SR
SYSREF–
SYSREF+
Figure 3. SYSREF Setup and Hold Timing
tDS
tHIGH
tCLK
tACCESS
tH
tS
tDH
tLOW
CSB
SCLK DON’T CARE
SDIO DON’T CARE
DON’T CARE
DON’T CARE
R/W
A14
A13
A12
A11
A10
A9
A8
A7
D7
D6
D3
D2
D1
D0
Figure 4. Serial Port Interface Timing Diagram
Rev. 0 | Page 10 of 107
Data Sheet
AD6684
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 6.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
Rating
Electrical
AVDD1 to AGND
1.05 V
AVDD1_SR to AGND
AVDD2 to AGND
AVDD3 to AGND
1.05 V
2.00 V
2.70 V
1.05 V
1.05 V
2.00 V
2.00 V
−0.3 V to AVDD3 + 0.3 V
−0.3 V to AVDD1 + 0.3 V
−0.3 V to SPIVDD + 0.3 V
−0.3 V to SPIVDD + 0.3 V
0 V to 2.5 V
Table 7. Thermal Resistance
Airflow Velocity
(m/sec)
PCB Type
θJA
θJCB
Unit
°C/W
°C/W
°C/W
°C/W
DVDD to DGND
JEDEC
0.0
1.951, 3
N/A4
N/A4
1.00
21.581, 2
17.941, 2
16.581, 2
9.74
DRVDD1 to DRGND
DRVDD2 to DRGND
SPIVDD to AGND
VIN x to AGND
2s2p Board
1.0
2.5
10-Layer Board 0.0
1 Per JEDEC 51-7, plus JEDEC 51-5 2s2p test board.
CLK to AGND
2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3 Per MIL-STD 883, Method 1012.1.
SCLK, SDIO, CSB to DGND
PDWN/STBY to DGND
SYSREF to AGND_SR
SYNCIN AB/SYNCIN CD to DRGND
Environmental
4 N/A means not applicable.
0 V to 2.5 V
ESD CAUTION
Operating Junction Temperature
Range
−40°C to +105°C
Maximum Junction Temperature
125°C
Storage Temperature Range
(Ambient)
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 11 of 107
AD6684
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AVDD3
VIN–A
VIN+A
AVDD2
AVDD2
AVDD3
VIN+B
VIN–B
AVDD2
AVDD1 10
AVDD1 11
VCM_AB 12
DVDD 13
1
2
3
4
5
6
7
8
9
AVDD3
VIN–C
VIN+C
AVDD2
54
53
52
51
50 AVDD2
49 AVDD3
48 VIN+D
47 VIN–D
46 AVDD2
AD6684
TOP VIEW
(Not to Scale)
45
44
43
AVDD1
AVDD1
VCM_CD/VREF
42 DVDD
41 DGND
40 SPIVDD
39 CSB
DGND 14
DRVDD2 15
PDWN/STBY 16
FD_A 17
38 SCLK
FD_B 18
37 SDIO
NOTES
1. EXPOSED PAD. ANALOG GROUND. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE
PROVIDES THE GROUND REFERENCE FOR AVDDx, SPIVDD, DVDD, DRVDD1, AND DRVDD2.
THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 5. Pin Configuration (Top View)
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Type
Description
0
AGND/EPAD
Ground
Exposed Pad. Analog Ground. The exposed thermal pad on
the bottom of the package provides the ground reference for
AVDDx, SPIVDD, DVDD, DRVDD1, and DRVDD2. This exposed
pad must be connected to ground for proper operation.
1, 6, 49, 54
AVDD3
Supply
Input
Analog Power Supply (2.5 V Nominal).
ADC A Analog Input Complement/True.
Analog Power Supply (1.8 V Nominal).
ADC B Analog Input True/Complement.
Analog Power Supply (0.975 V Nominal).
2, 3
VIN−A, VIN+A
AVDD2
4, 5, 9, 46, 50, 51, 55, 72
7, 8
Supply
Input
VIN+B, VIN−B
AVDD1
10, 11, 44, 45, 56, 57, 58, 59,
62, 68, 69, 70, 71
Supply
12
VCM_AB
Output
Common-Mode Level Bias Output for Analog Input Channel A
and Channel B
13, 42
14, 41
15
DVDD
Supply
Ground
Supply
Input
Digital Power Supply (0.975 V Nominal).
DGND
Ground Reference for DVDD and SPIVDD.
Digital Power Supply for JESD204B PLL (1.8 V Nominal).
DRVDD2
PDWN/STBY
16
Power-Down Input (Active High). The operation of this pin
depends on the SPI mode and can be configured as power-
down or standby. Requires external 10 kΩ pull-down resistor.
17, 18, 36, 35
FD_A, FD_B, FD_C, FD_D
SYNCINB−AB
Output
Input
Fast Detect Outputs for Channel A, Channel B, Channel C, and
Channel D.
Active Low JESD204B LVDS Sync Input Complement for
Channel A and Channel B.
Active Low JESD204B LVDS/CMOS Sync Input True for Channel A
and Channel B.
19
20
SYNCINB+AB
Input
21, 32
22, 31
DRGND
DRVDD1
Ground
Supply
Ground Reference for DRVDD1 and DRVDD2.
Digital Power Supply for SERDOUT Pins (0.975 V Nominal).
Rev. 0 | Page 12 of 107
Data Sheet
AD6684
Pin No.
Mnemonic
Type
Description
23, 24
SERDOUTAB0−,
SERDOUTAB0+
Output
Lane 0 Output Data Complement/True for Channel A and
Channel B.
25, 26
27, 28
29, 30
33
SERDOUTAB1−,
SERDOUTAB1+
SERDOUTCD1+,
SERDOUTCD1−
SERDOUTCD0+,
SERDOUTCD0−
SYNCINB+CD
Output
Output
Output
Input
Lane 1 Output Data Complement/True for Channel A and
Channel B.
Lane 1 Output Data True/Complement for Channel C and
Channel D.
Lane 0 Output Data True/Complement for Channel C and
Channel D.
Active Low JESD204B LVDS/CMOS Sync Input True for Channel C
and Channel D.
34
SYNCINB−CD
Input
Active Low JESD204B LVDS Sync Input Complement for
Channel C and Channel D.
37
38
39
40
43
SDIO
Input/output
Input
SPI Serial Data Input/Output.
SPI Serial Clock.
SCLK
CSB
Input
SPI Chip Select (Active Low).
Digital Power Supply for SPI (1.8 V Nominal).
SPIVDD
VCM_CD/VREF
Supply
Output/input Common-Mode Level Bias Output for Analog Input Channel C
and Channel D/0.5 V Reference Voltage Input. This pin is
configurable through the SPI as an output or an input. Use
this pin as the common-mode level bias output if using the
internal reference. This pin requires a 0.5 V reference voltage
input if using an external voltage reference source.
47, 48
52, 53
60, 61
63, 67
64
VIN−D, VIN+D
VIN+C, VIN−C
CLK+, CLK−
AGND_SR
AVDD1_SR
Input
Input
Input
Ground
Supply
Input
ADC D Analog Input Complement/True.
ADC C Analog Input True/Complement.
Clock Input True/Complement.
Ground Reference for SYSREF .
Analog Power Supply for SYSREF (0.975 V Nominal).
65, 66
SYSREF+, SYSREF−
Active Low JESD204B LVDS System Reference (SYSREF) Input
True/Complement. DC-coupled input only.
Rev. 0 | Page 13 of 107
AD6684
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V,
SPIVDD = 1.8 V, specified maximum sampling rate, clock divider = 4, 1.5 V p-p full-scale differential input, AIN = −1.0 dBFS, default SPI
settings, VDR mode (input mask not triggered), unless otherwise noted. Minimum and maximum specifications are guaranteed for the full
operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 50°C (TA = 25°C).
0
0
A
= –1dBFS
A
= –1dBFS
IN
IN
SNR = 67.10dB
SFDR = 90dBFS
ENOB = 10.8 BITS
SNR = 66.6dB
SFDR = 83dBFS
ENOB = 10.7 BITS
–20
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–100
–120
–140
0
50
100
150
250
0
50
100
150
250
200
200
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 6. Single-Tone FFT with fIN = 10.3 MHz
Figure 9. Single-Tone FFT with fIN = 453 MHz
0
–20
0
–20
A
= –1dBFS
A
= –1dBFS
IN
IN
SNR = 67.0dB
SFDR = 85dBFS
ENOB = 10.8 BITS
SNR = 66.5dB
SFDR = 75dBFS
ENOB = 10.6 BITS
–40
–40
–60
–60
–80
–80
–100
–120
–140
–100
–120
–140
0
50
100
150
250
0
50
100
150
250
200
200
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 7. Single-Tone FFT with fIN = 155 MHz
Figure 10. Single-Tone FFT with fIN = 765 MHz
0
–20
0
–20
A
= –1dBFS
A
= –1dBFS
IN
IN
SNR = 66.8dB
SFDR = 82dBFS
ENOB = 10.7 BITS
SNR = 66.0dB
SFDR = 79dBFS
ENOB = 10.6 BITS
–40
–40
–60
–60
–80
–80
–100
–120
–140
–100
–120
–140
0
50
100
150
250
200
0
50
100
150
250
200
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 8. Single-Tone FFT with fIN = 305 MHz
Figure 11. Single-Tone FFT with fIN = 985 MHz
Rev. 0 | Page 14 of 107
Data Sheet
AD6684
90
85
80
75
70
65
60
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
SFDR
SNR
ANALOG INPUT FREQUENCY (MHz)
SAMPLE RATE (MHz)
Figure 12. SNR/SFDR vs. Sample Rate (fS), fIN = 155 MHz
Figure 15. SFDR vs. Analog Input Frequency (fIN), First and Second Nyquist
Zones; AIN at −3 dBFS
95
90
85
80
75
70
65
60
67.5
67.0
66.5
SFDR (dBFS), –40°C
SFDR (dBFS), +50°C
SFDR (dBFS), +105°C
SNRFS, –40°C
SNRFS, +50°C
SNRFS, +105°C
66.0
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Figure 13. SNR/SFDR vs. Analog Input Frequency (fIN
)
Figure 16. SNR vs. Analog Input Frequency (fIN), Third Nyquist Zone
AIN at −3 dBFS
67.5
67.4
67.3
67.2
67.1
67.0
66.9
66.8
66.7
66.6
66.5
66.4
66.3
66.2
66.1
66.0
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Figure 14. SNR vs. Analog Input Frequency (fIN), First and Second Nyquist
Zones; AIN at −3 dBFS
Figure 17. SFDR vs. Analog Input Frequency (fIN), Third Nyquist Zone; AIN
at −3 dBFS
Rev. 0 | Page 15 of 107
AD6684
Data Sheet
120
110
100
90
0
SFDR (dBFS)
A
AND A
= –7dBFS
IN2
IN1
–20
–40
SFDR = 86.4dBFS
80
SNRFS
70
60
–60
50
SFDR (dBc)
40
–80
30
20
–100
–120
–140
–160
SNR
10
0
–10
–20
–30
–40
0
50
100
150
250
200
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
ANALOG INPUT FREQUENCY (MHz)
0
FREQUENCY (MHz)
Figure 18. Two Tone FFT; fIN1 = 153.5 MHz, fIN2 = 156.5 MHz
Figure 21. SNR/SFDR vs. Analog Input Frequency, fIN = 155 MHz
120
0
SFDR (dBFS)
110
A
AND A
= –7dBFS
IN2
IN1
100
90
–20
–40
SFDR = 85.9dBFS
80
SNRFS
70
60
–60
50
40
SFDR (dBc)
–80
30
SNR
20
–100
–120
–140
–160
10
0
–10
–20
–30
–40
0
50
100
150
250
200
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
ANALOG INPUT FREQUENCY (MHz)
0
FREQUENCY (MHz)
Figure 19. Two Tone FFT; fIN1 = 303.5 MHz, fIN2 = 306.5 MHz
Figure 22. SNR/SFDR vs. Analog Input Frequency, fIN = 305 MHz
0
90
SFDR
–20
85
SFDR (dBc)
–40
–60
80
75
IMD3 (dBc)
–80
SFDR (dBFS)
70
SNR
–100
65
60
–120
–140
IMD3 (dBFS)
–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12
0
ANALOG INPUT AMPLITUDE (dBFS)
JUNCTION TEMPERATURE (°C)
Figure 20. Two Tone SFDR/IMD3 vs. Analog Input Amplitude (AIN) with
fIN1 = 303.5 MHz and fIN2 = 306.5 MHz
Figure 23. SNR/SFDR vs. Junction Temperature, fIN = 155 MHz
Rev. 0 | Page 16 of 107
Data Sheet
AD6684
2.1
2.0
1.9
1.8
1.7
1.6
1.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–38 –21
8
20
43
49
59
81
100 115
TEMPERATURE (°C)
OUTPUT CODE
Figure 27. NSR Mode Power Dissipation vs. Junction Temperature
Figure 24. INL, fIN = 10.3 MHz
1.85
1.80
1.75
1.70
1.0
0.8
0.6
0.4
0.2
NSR
1.65
0
1.60
1.55
1.50
1.45
1.40
–0.2
–0.4
–0.6
–0.8
–1.0
250
300
350
400
450
500
550
600
650
SAMPLE RATE (MSPS)
OUTPUT CODE
Figure 28. Power Dissipation vs. Sample Rate (fS)
Figure 25. DNL, fIN = 10.3 MHz
0
–20
6000
5000
4000
3000
2000
1000
0
A
= –1dBFS
IN
SNRFS = 65.94dB
SFDR = 89.01dBFS
–40
–60
–80
–100
–120
–140
–160
–125
–75
–25
25
75
125
FREQUENCY (MHz)
CODE
Figure 26. Input-Referred Noise Histogram
Figure 29. DDC Mode (4 DDCs, DCM2, L, M, and F = 244) with fIN = 305 MHz
Rev. 0 | Page 17 of 107
AD6684
Data Sheet
0
0
–20
A
= –1dBFS
A
= –1dBFS
IN
IN
SNRFS = 71.80dB
SFDR = 98.27dBFS
SNRFS = 74.50dB
SFDR = 100.68dBFS
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–160
5
25
45
65
85
105
125
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 30. DDC Mode (4 DDCs, Decimate by 4, L, M, and F = 148) with
IN = 305 MHz
Figure 33. NSR Mode (Decimate by 2, L, M, and F = 124) with fIN = 305 MHz
f
0
–20
0
A
= –1dBFS
IN
A
= –1dBFS
IN
SNRFS = 71.80dB
SFDR = 98.27dBFS
SNRFS = 70.7dB
SFDR = 82dBFS
–20
–40
–40
–60
–60
–80
–80
–100
–120
–140
–160
–100
–120
–140
–31.25
–21.25
–11.25
–1.25
8.75
18.75
28.75
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 34. NSR Mode (LMF = 222) with fIN = 305 MHz
Figure 31. DDC Mode (4 DDCs, Decimate by 8, L, M, and F = 148) with
IN = 305 MHz
f
0
–20
67.0
66.9
66.8
66.7
66.6
66.5
66.4
66.3
66.2
66.1
66.0
65.9
65.8
65.7
65.6
65.5
A
= –1dBFS
IN
SNRFS = 74.50dB
SFDR = 100.68dBFS
–40
–60
–80
–100
–120
–140
–160
–15.625 –10.625
–5.625
–0.625
4.375
9.375
14.375
FREQUENCY (MHz)
DIFFERENTIAL VOLTAGE (V)
Figure 35. SNR vs. Clock Amplitude (Differential Voltage), fIN = 155.3 MHz
Figure 32. DDC Mode (4 DDCs, Decimate by 16, L, M, and F = 148) with
fIN = 305 MHz
Rev. 0 | Page 18 of 107
Data Sheet
AD6684
–95
–94
–93
–92
–91
–90
–89
–88
–87
–86
–85
–84
–83
–82
–81
–80
–79
–78
–77
–76
–75
69
68
67
66
65
64
BUFFER CURRENT = 160µA
BUFFER CURRENT = 200µA
BUFFER CURRENT = 240µA
BUFFER CURRENT = 280µA
INPUT FULL SCALE = 2.16V
INPUT FULL SCALE = 1.44V
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Figure 36. SFDR vs. Analog Input Frequency with Different Buffer Current
Settings (First and Second Nyquist Zones)
Figure 39. SNR vs. Analog Input Frequency with Different Analog Input
Full Scales (First and Second Nyquist Zones)
–85
–84
–83
–82
–81
–80
–79
–78
–77
–76
–75
–74
69.0
68.8
68.6
68.4
INPUT FULL SCALE = 2.16V
68.2
68.0
67.8
67.6
67.4
67.2
67.0
66.8
66.6
66.4
66.2
66.0
65.8
65.6
65.4
65.2
65.0
64.8
64.6
64.4
64.2
64.0
–73
BUFFER CURRENT = 200µA
–72
–71
–70
–69
–68
–67
–66
–65
BUFFER CURRENT = 240µA
BUFFER CURRENT = 280µA
BUFFER CURRENT = 320µA
INPUT FULL SCALE = 1.44V
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Figure 37. SFDR vs. Analog Input Frequency with Different Buffer Current
Settings (Third Nyquist Zone)
Figure 40. SNR vs. Analog Input Frequency with Different Analog Input
Full Scales (Third Nyquist Zone)
–80
–78
–76
–74
–72
–70
–68
–66
–64
–62
–60
68
67
INPUT FULL SCALE = 2.16V
66
65
INPUT FULL SCALE = 1.44V
–58
BUFFER CURRENT = 320µA
–56
–54
–52
–50
–48
–46
–44
–42
–40
BUFFER CURRENT = 360µA
BUFFER CURRENT = 400µA
BUFFER CURRENT = 440µA
64
63
62
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Figure 41. SNR vs. Analog Input Frequency with Different Analog Input
Full Scales (Fourth Nyquist Zone)
Figure 38. SFDR vs. Analog Input Frequency with Different Buffer Current
Settings (Fourth Nyquist Zone)
Rev. 0 | Page 19 of 107
AD6684
Data Sheet
–90
–89
–88
–87
–86
–85
–84
–83
–82
–81
–80
–79
–78
–77
–76
–75
–74
–73
–72
–71
–70
–81
INPUT FULL SCALE = 1.44V
–79
–77
–75
–73
–71
–69
–67
–65
–63
–61
–59
–57
–55
INPUT FULL SCALE = 1.44V
INPUT FULL SCALE = 2.16V
INPUT FULL SCALE = 2.16V
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Figure 44. SFDR vs. Analog Input Frequency with Different Analog Input
Full Scales (Fourth Nyquist Zone)
Figure 42. SFDR vs. Analog Input Frequency with Different Analog Input
Full Scales (First and Second Nyquist Zones)
–90
–89
–88
–87
–86
–85
–84
–83
–82
–81
–80
–79
–78
–77
–76
–75
–74
–73
–72
–71
–70
INPUT FULL SCALE = 1.44V
INPUT FULL SCALE = 2.16V
ANALOG INPUT FREQUENCY (MHz)
Figure 43. SFDR vs. Analog Input Frequency with Different Analog Input
Full Scales (Third Nyquist Zone)
Rev. 0 | Page 20 of 107
Data Sheet
AD6684
EQUIVALENT CIRCUITS
AVDD3
EMPHASIS/SWING
CONTROL (SPI)
AVDD3
DRVDD
VIN+x
SERDOUTABx+/
DATA+
DATA–
SERDOUTCDx+
x = 0, 1
3.5pF
AVDD3
100Ω
100ꢀ
DRGND
DRVDD
OUTPUT
DRIVER
400ꢀ
V
CM
SERDOUTABx–/
SERDOUTCDx–
x = 0, 1
BUFFER
10pF
AVDD3
DRGND
AVDD3
Figure 48. Digital Outputs
VIN–x
DRVDD
3.5pF
A
IN
CONTROL
(SPI)
CMOS
PATH
SYNCINB PIN
CONTROL (SPI)
DRGND
Figure 45. Analog Inputs
2.5kꢀ
DRVDD
100ꢀ
10kꢀ
SYNCINB+AB/
SYNCINB+CD
AVDD1
25ꢀ
1.9pF
DRGND
130kꢀ
CLK+
LEVEL
TRANSLATOR
DRGND
130kꢀ
DRVDD
16kꢀ
100ꢀ
10kꢀ
SYNCINB–AB/
SYNCINB–CD
AVDD1
1.9pF
25ꢀ
DRGND
CLK–
16kꢀ
DRGND
V
= 0.69V
CM
Figure 49. SYNCINB AB, SYNCINB CD Inputs
Figure 46. Clock Inputs
SPIVDD
ESD
100ꢀ
10kꢀ
PROTECTED
SPIVDD
DGND
SYSREF+
SCLK
1.9pF
130kꢀ
56kꢀ
DGND
ESD
PROTECTED
LEVEL
TRANSLATOR
130kꢀ
100ꢀ
10kꢀ
SYSREF–
Figure 50. SCLK Input
1.9pF
SPIVDD
ESD
PROTECTED
56kꢀ
Figure 47. SYSREF Inputs
CSB
ESD
PROTECTED
DGND
DGND
Figure 51. CSB Input
Rev. 0 | Page 21 of 107
AD6684
Data Sheet
SPIVDD
SPIVDD
SPIVDD
SDI
ESD
PROTECTED
ESD
PROTECTED
PDWN/
STBY
DGND
SDIO
56kꢀ
DGND
SPIVDD
ESD
PROTECTED
ESD
PROTECTED
PDWN
CONTROL (SPI)
SDO
DGND
DGND
DGND
DGND
Figure 52. SDIO Input
Figure 54. PDWN/STBY Input
SPIVDD
ESD
TEMPERATURE
AVDD2
AGND
DIODE VOLTAGE
PROTECTED
EXTERNAL REFERENCE
VOLTAGE INPUT
SPIVDD
FD
VREF
FD_A/FD_B/
FD_C/FD_D
JESD204B LMFC
JESD204B SYNC
VREF PIN
CONTROL (SPI)
56kꢀ
DGND DGND
ESD
PROTECTED
Figure 55. VREF Input/Output
FD_x PIN CONTROL (SPI)
DGND
Figure 53. FD_A/FD_B/FD_C/FD_D Outputs
Rev. 0 | Page 22 of 107
Data Sheet
AD6684
THEORY OF OPERATION
the dither can slightly improve the SNR (by about 0.2 dB) at the
expense of the small signal SFDR.
ADC ARCHITECTURE
The architecture of the AD6684 consists of an input buffered
pipelined ADC. The input buffer is designed to provide a 200 Ω
termination impedance to the analog input signal. The equivalent
circuit diagram of the analog input termination is shown in
Figure 45.
Differential Input Configurations
There are several ways to drive the AD6684, either actively or
passively. However, optimum performance is achieved by
driving the analog input differentially.
The input buffer provides a linear high input impedance (for
ease of drive) and reduces kickback from the ADC. The buffer
is optimized for high linearity, low noise, and low power. The
quantized outputs from each stage are combined into a final
14-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate with a new input
sample while, at the same time, the remaining stages operate
with the preceding samples. Sampling occurs on the rising edge
of the clock.
For applications where SNR and SFDR are key parameters,
differential transformer coupling is the recommended input
configuration (see Figure 57 and Figure 58) because the noise
performance of most amplifiers is not adequate to achieve the
true performance of the AD6684.
For low to midrange frequencies, a double balun or double
transformer network (see Figure 57) is recommended for
optimum performance of the AD6684. For higher frequencies
in the second or third Nyquist zones, it is recommended to
remove some of the front-end passive components to ensure
wideband operation (see Figure 58).
ANALOG INPUT CONSIDERATIONS
The analog input to the AD6684 is a differential buffer with an
internal common-mode voltage of 1.34 V. The clock signal
alternately switches the input circuit between sample mode and
hold mode. Either a differential capacitor or two single-ended
capacitors can be placed on the inputs to provide a matching
passive network. This configuration ultimately creates a low-pass
filter at the input, which limits unwanted broadband noise. See
Figure 57 and Figure 58 for details on input network recom-
mendations. For more information, see the Analog Dialogue
article “Transformer-Coupled Front-End for Wideband A/D
Converters” (Volume 39, April 2005). In general, the precise
values depend on the application.
Input Common Mode
The analog inputs of the AD6684 are internally biased to the
common mode as shown in Figure 56.
For dc-coupled applications, the recommended operation
procedure is to export the common-mode voltage to the
VCM_CD/VREF pin using the SPI writes listed in this section.
The common-mode voltage must be set by the exported value
to ensure proper ADC operation. Disconnect the internal
common-mode buffer from the analog input using
Register 0x1908.
When performing SPI writes for dc coupling operation, use the
following register settings in order:
For best dynamic performance, the source impedances driving
VIN+x and VIN−x must be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC. An internal reference
buffer creates a differential reference that defines the span of the
ADC core.
1. Set Register 0x1908, Bit 2 to 1; this setting disconnects the
internal common-mode buffer from the analog input.
2. Set Register 0x18A6 to 0x00; this setting turns off the
voltage reference.
3. Set Register 0x18E6 to 0x00; this setting turns off the
temperature diode export.
4. Set Register 0x18E0 to 0x04.
5. Set Register 0x18E1 to 0x1C.
6. Set Register 0x18E2 to 0x14.
7. Set Register 0x18E3, Bit 6 to 0x01; this setting turns on the
VCM export.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the
AD6684, the available span is programmable through the SPI
port from 1.44 V p-p to 2.16 V p-p differential with 1.80 V p-p
differential being the default.
Dither
The AD6684 has internal on-chip dither circuitry that improves
the ADC linearity and SFDR, particularly at smaller signal levels. A
known but random amount of white noise is injected into the
input of the AD6684. This dither improves the small signal linearity
within the ADC transfer function and is precisely subtracted
out digitally. The dither is turned on by default and does not
reduce the ADC input dynamic range. The data sheet specifications
and limits are obtained with the dither turned on. The dither
can be disabled using SPI writes to Register 0x0922. Disabling
8. Set Register 0x18E3, Bits[5:0] to the buffer current setting
(copy the buffer current setting from Register 0x1A4C and
Register 0x1A4D to improve the accuracy of the common-
mode export).
Rev. 0 | Page 23 of 107
AD6684
Data Sheet
Analog Input Controls and SFDR Optimization
Using Register 0x1A4C and Register 0x1A4D, the buffer
currents on each channel can be scaled to optimize the SFDR
over various input frequencies and bandwidths of interest. As the
input buffer currents are set, the amount of current required by
the AVDD3 supply changes. This relationship is shown in
Figure 59. For a complete list of buffer current settings, see
Table 46.
The AD6684 offers flexible controls for the analog inputs, such
as buffer current and input full-scale adjustment. All of the
available controls are shown in Figure 56.
AVDD3
AVDD3
VIN+x
3.5pF
AVDD3
100ꢀ
400ꢀ
V
CM
BUFFER
10pF
AVDD3
100ꢀ
AVDD3
VIN–x
3.5pF
A
IN
CONTROL
(SPI)
Figure 56. Analog Input Controls
AGND
0ꢀ
2pF
10ꢀ
0.1µF
10ꢀ
VIN+x
50ꢀ
10ꢀ
0.1µF
BALUN
2pF
AGND
50ꢀ
0ꢀ
10ꢀ
0.1µF
10ꢀ
10ꢀ
2pF
AGND
VIN–x
Figure 57. Differential Transformer Coupled Configuration for First and Second Nyquist Frequencies
AGND
DNI
0.1µF
10ꢀ
0ꢀ
10ꢀ
VIN+x
50ꢀ
DNI
0.1µF
BALUN
DNI
DNI
AGND
50ꢀ
0ꢀ
0.1µF
10ꢀ
10ꢀ
DNI
AGND
VIN–x
Figure 58. Differential Transformer Coupled Configuration for Third and Fourth Nyquist Zones
Rev. 0 | Page 24 of 107
Data Sheet
AD6684
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
VIN+A/
VIN+B
VIN–A/
VIN–B
ADC
INTERNAL
VREF
GENERATOR
CORE
FULL-SCALE
VOLTAGE
ADJUST
INPUT FULL-SCALE
RANGE ADJUST
SPI REGISTER
(0x1910)
VREF
VREF PIN
CONTROL SPI
REGISTER
(0x18A6)
Figure 60. Internal Reference Configuration and Controls
100 150 200 250 300 350 400 450 500 550 600
BUFFER CURRENT SETTING (µA)
The SPI Register 0x18A6 enables the user to either use this
internal 0.5 V reference, or to provide an external 0.5 V
reference. When using an external voltage reference, provide a
0.5 V reference. The full-scale adjustment is made using the SPI,
irrespective of the reference voltage. For more information on
adjusting the full-scale level of the AD6684, refer to the
Memory Map section.
Figure 59. AVDD3 Power vs. Buffer Current Setting
In certain high frequency applications, the SFDR can be
improved by reducing the full-scale setting.
Table 9 shows the recommended buffer current settings for the
different analog input frequency ranges.
Table 9. SFDR Optimization for Input Frequencies
The SPI writes required to use the external voltage reference, in
order, are as follows:
Input Buffer Current Control
Setting, Register 0x1A4C and
Nyquist Zone
Register 0x1A4D
1. Set Register 0x18E3 to 0x00 to turn off VCM export.
2. Set Register 0x18E6 to 0x00 to turn off temperature diode
export.
3. Set Register 0x18A6 to 0x01 to turn on the external voltage
reference.
First, Second, and Third
Nyquist
Fourth Nyquist
240 (Register 0x1A4C, Bits[5:0] =
Register 0x1A4D, Bits[5:0] = 01100)
400 (Register 0x1A4C, Bits[5:0] =
Register 0x1A4D, Bits[5:0] = 10100)
The use of an external reference may be necessary, in some
applications, to enhance the gain accuracy of the ADC or to
improve thermal drift characteristics.
Absolute Maximum Input Swing
The absolute maximum input swing allowed at the inputs of the
AD6684 is 4.3 V p-p differential. Signals operating near or at
this level can cause permanent damage to the ADC.
The external reference has to be a stable 0.5 V reference. The
ADR130 is a good option for providing the 0.5 V reference.
Figure 61 shows how the ADR130 can be used to provide the
external 0.5 V reference to the AD6684. The grayed out areas
show unused blocks within the AD6684 while using the
ADR130 to provide the external reference.
VOLTAGE REFERENCE
A stable and accurate 0.5 V voltage reference is built into the
AD6684. This internal 0.5 V reference is used to set the full-
scale input range of the ADC. The full-scale input range can be
adjusted via the ADC function register (Register 0x1910). For
more information on adjusting the input swing, see Table 46.
Figure 60 shows the block diagram of the internal 0.5 V
reference controls.
INTERNAL
VREF
GENERATOR
FULL-SCALE
VOLTAGE
ADJUST
ADR130
1
2
3
6
5
4
NC
NC
GND SET
VREF
INPUT
V
V
OUT
IN
0.1µF
0.1µF
VREF PIN AND
FULL-SCALE
VOLTAGE
CONTROL
Figure 61. External Reference Using ADR130
Rev. 0 | Page 25 of 107
AD6684
Data Sheet
Input Clock Divider
CLOCK INPUT CONSIDERATIONS
The AD6684 contains an input clock divider with the ability to
divide the input clock by 1, 2, 4, and 8. The divider ratios can be
selected using Register 0x0108 (see Figure 65).
For optimum performance, drive the AD6684 sample clock
inputs (CLK+ and CLK−) with a differential signal. This signal
is typically ac-coupled to the CLK+ and CLK− pins via a
transformer or clock drivers. These pins are biased internally
and require no additional biasing.
In applications where the clock input is a multiple of the sample
clock, care must be taken to program the appropriate divider
ratio into the clock divider before applying the clock signal.
This ratio ensures that the current transients during device
startup are controlled.
Figure 62 shows a preferred method for clocking the AD6684. The
low jitter clock source is converted from a single-ended signal to
a differential signal using an RF transformer.
CLK+
0.1µF
1:1Z
CLK–
÷2
÷4
÷8
CLK+
ADC
CLK–
CLOCK
INPUT
100ꢀ
50ꢀ
0.1µF
Figure 62. Transformer-Coupled Differential Clock
REG 0x0108
Another option is to ac couple a differential CML or LVDS
Figure 65. Clock Divider Circuit
signal to the sample clock input pins, as shown in Figure 63 and
Figure 64.
The AD6684 clock divider can be synchronized using the external
SYSREF input. A valid SYSREF causes the clock divider to
reset to a programmable state. This synchronization feature
allows multiple devices to have their clock dividers aligned to
guarantee simultaneous input sampling.
3.3V
71ꢀ
33ꢀ
10pF
33ꢀ
0.1µF
Z0 = 50ꢀ
Clock Jitter Considerations
CLK+
ADC
CLK–
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input
frequency (fA) due only to aperture jitter (tJ) can be calculated by
0.1µF
Z0 = 50ꢀ
Figure 63. Differential CML Sample Clock
SNR = −20 × log (2 × π × fA × tJ)
0.1µF
0.1µF
0.1µF
100ꢀ
0.1µF
In this equation, the rms aperture jitter represents the root
mean square of all jitter sources, including the clock input,
analog input signal, and ADC aperture jitter specifications. IF
undersampling applications are particularly sensitive to jitter
(see Figure 66).
CLOCK INPUT
CLOCK INPUT
CLK+
LVDS
CLK+
ADC
DRIVER
CLK–
CLK–
1
1
50ꢀ
50ꢀ
130
12.5fS
25fS
50fS
100fS
200fS
400fS
800fS
1
50ꢀ RESISTORS ARE OPTIONAL.
120
110
100
90
Figure 64. Differential LVDS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. The AD6684 contains an
internal clock divider and a duty cycle stabilizer (DCS). In
applications where the clock duty cycle cannot be guaranteed to
be 50%, a higher multiple frequency clock along with the usage
of the clock divider is recommended. When it is not possible to
provide a higher frequency clock, it is recommended to turn on
the DCS using Register 0x011C. The output of the divider offers
a 50% duty cycle, high slew rate (fast edge) clock signal to the
internal ADC. See the Memory Map section for more details on
using this feature.
80
70
60
50
40
30
10
100
1000
10000
ANALOG INPUT FREQUENCY (MHz)
Figure 66. Ideal SNR vs. Analog Input Frequency and Jitter
Rev. 0 | Page 26 of 107
Data Sheet
AD6684
Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD6684. Separate the
power supplies for clock drivers from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
If the clock is generated from another type of source (by gating,
dividing, or other methods), retime the clock by the original clock
at the last step. Refer to the AN-501 Application Note and the
AN-756 Application Note for more in-depth information about
jitter performance as it relates to ADCs.
that other voltages may be exported to the same pin at the same
time, which may result in undefined behavior. Thus, to ensure a
proper readout, switch off all other voltage exporting circuits as
detailed in this section.
The SPI writes required to export the temperature diode are as
follows (see Table 46 for more information):
1. Set Register 0x0009 to 0x03 to select both cores.
2. Set Register 0x18E3 to 0x00 to turn off VCM export.
3. Set Register 0x18A6 to 0x00 to turn off the voltage
reference.
4. Set Register 0x18E6 to 0x01 to turn on temperature diode
export. The typical voltage response of the temperature
diode is shown in Figure 67. However, it is recommended
to take measurements from a pair of diodes into account
when introducing another step.
Figure 66 shows the estimated SNR of the AD6684 across input
frequency for different clock induced jitter values. The SNR can
be estimated by using the following equation:
SNR
SNR
JITTER
ADC
10
10
SNR(dBFS) 10log 10
10
5. Set Register 0x18E6 to 0x02 to turn on the second
temperature diode (that is, 20× the size) of the pair.
Power-Down/Standby Mode
The AD6684 has a PDWN/STBY pin that can be used to
configure the device in power-down or standby mode. The
default operation is power-down. The PDWN/STBY pin is a
logic high pin. When in power-down mode, the JESD204B link
is disrupted. The power-down option can also be set via
Register 0x003F and Register 0x0040.
For the method utilizing two diodes simultaneously giving a more
accurate result, see the AN-1432 Application Note, Practical
Thermal Modeling and Measurements in High Power ICs.
0.80
0.75
0.70
0.65
0.60
0.55
0.50
In standby mode, the JESD204B link is not disrupted and
transmits zeros for all converter samples. This setting can be
changed using Register 0x0571, Bit 7 to select /K/ characters.
TEMPERATURE DIODE
The AD6684 contains a diode-based temperature sensor for
measuring the temperature of the die. The diode can output a
voltage and serve as a coarse temperature sensor to monitor the
internal die temperature.
The temperature diode voltage can be output to the VCM_CD/
VREF pin using the SPI. Use Register 0x18E6 to enable or disable
the diode. Register 0x18E6 is a local register. Both cores must be
selected in the core index register (Register 0x0009 = 0x03) to
enable the temperature diode readout. It is important to note
–40
–20
0
20
40
60
80
100
JUNCTION TEMPERATURE (°C)
Figure 67. Temperature Diode Voltage vs. Junction Temperature
Rev. 0 | Page 27 of 107
AD6684
Data Sheet
ADC OVERRANGE AND FAST DETECT
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overrange bit in the JESD204B outputs provides
information on the state of the analog input that is of limited
usefulness. Therefore, it is helpful to have a programmable
threshold below full scale that allows time to reduce the gain
before the clip actually occurs. In addition, because input signals
can have significant slew rates, the latency of this function is of
major concern. Highly pipelined converters can have significant
latency. The AD6684 contains fast detect circuitry for individual
channels to monitor the threshold and to assert the FD_A,
FD_B, FD_C, and FD_D pins.
The FD indicator is asserted if the input magnitude exceeds the
value programmed in the fast detect upper threshold registers,
located at Register 0x0247 and Register 0x0248. The selected
threshold register is compared with the signal magnitude at the
output of the ADC. The fast upper threshold detection has a
latency of 30 clock cycles (maximum). The approximate upper
threshold magnitude is defined by
Upper Threshold Magnitude (dBFS) = 20log (Threshold
Magnitude/213)
The FD indicators are not cleared until the signal drops below
the lower threshold for the programmed dwell time. The lower
threshold is programmed in the fast detect lower threshold
registers, located at Register 0x0249 and Register 0x024A. The
fast detect lower threshold register is a 13-bit register that is
compared with the signal magnitude at the output of the ADC.
This comparison is subject to the ADC pipeline latency, but is
accurate in terms of converter resolution. The lower threshold
magnitude is defined by
ADC OVERRANGE
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange indicator can
be embedded within the JESD204B link as a control bit. The
latency of this overrange indicator matches the sample latency.
FAST THRESHOLD DETECTION (FD_A, FD_B, FD_C
AND FD_D)
Lower Threshold Magnitude (dBFS) = 20log (Threshold
Magnitude/213)
The FD bits (Register 0x0040, Bits[5:0]) are immediately set
whenever the absolute value of the input signal exceeds the
programmable upper threshold level. The FD bits are only
cleared when the absolute value of the input signal drops below
the lower threshold level for greater than the programmable
dwell time. This feature provides hysteresis and prevents the
FD bits from excessively toggling.
For example, to set an upper threshold of −6 dBFS, write 0xFFF
to Register 0x0247 and Register 0x0248. To set a lower threshold of
−10 dBFS, write 0xA1D to Register 0x0249 and Register 0x024A.
The dwell time can be programmed from 1 to 65,535 sample
clock cycles by placing the desired value in the fast detect dwell
time registers, located at Register 0x024B and Register 0x024C.
See the Memory Map section (Register 0x040, and Register 0x245
to Register 0x24C in Table 45) for more details.
The operation of the upper threshold and lower threshold
registers, along with the dwell time registers, is shown in
Figure 68.
UPPER THRESHOLD
DWELL TIME
TIMER RESET BY
RISE ABOVE
LOWER
THRESHOLD
LOWER THRESHOLD
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE
LOWER THRESHOLD
DWELL TIME
FD_A OR FD_B
Figure 68. Threshold Settings for the FD_A and FD_B Signals
Rev. 0 | Page 28 of 107
Data Sheet
AD6684
SIGNAL MONITOR
The signal monitor block provides additional information about
the signal being digitized by the ADC. The signal monitor
computes the peak magnitude of the digitized signal. This
information can be used to drive an AGC loop to optimize the
range of the ADC in the presence of real-world signals.
decimated clock rate. The magnitude of the input signal is
compared with the value in the internal magnitude storage
register (not accessible to the user), and the greater of the two
is updated as the current peak level. The initial value of the
magnitude storage register is set to the current ADC input signal
magnitude. This comparison continues until the monitor period
timer reaches a count of 1.
The results of the signal monitor block can be obtained either
by reading back the internal values from the SPI port or by
embedding the signal monitoring information into the
JESD204B interface as special control bits. A global, 24-bit
programmable period controls the duration of the measurement.
Figure 69 shows the simplified block diagram of the signal
monitor block.
When the monitor period timer reaches a count of 1, the 13-bit
peak level value is transferred to the signal monitor holding
register, which can be read through the memory map or output
through the SPORT over the JESD204B interface. The monitor
period timer is reloaded with the value in the SMPR, and the
countdown restarts. In addition, the magnitude of the first
input sample is updated in the magnitude storage register, and
the comparison and update procedure, as explained previously,
continues.
SIGNAL MONITOR
FROM
MEMORY
MAP
PERIOD REGISTER
(SMPR)
DOWN
COUNTER
IS
COUNT = 1?
0x0271, 0x0272, 0x0273
LOAD
CLEAR
LOAD
SPORT OVER JESD204B
MAGNITUDE
STORAGE
REGISTER
SIGNAL
MONITOR
HOLDING
REGISTER
TO SPORT OVER
JESD204B AND
MEMORY MAP
FROM
INPUT
The signal monitor data can also be serialized and sent over the
JESD204B interface as control bits. These control bits must be
deserialized from the samples to reconstruct the statistical data.
The signal control monitor function is enabled by setting Bits[1:0]
of Register 0x0279 and Bit 1 of Register 0x027A. Figure 70
shows two different example configurations for the signal monitor
control bit locations inside the JESD204B samples. A maximum of
three control bits can be inserted into the JESD204B samples;
however, only one control bit is required for the signal monitor.
Control bits are inserted from MSB to LSB. If only one control bit
is to be inserted (CS = 1), only the most significant control bit is
used (see Example Configuration 1 and Example Configuration 2
in Figure 70). To select the SPORT over JESD204B option,
program Register 0x0559, Register 0x055A, and Register 0x058F.
See Table 46 for more information on setting these bits.
LOAD
COMPARE
A > B
Figure 69. Signal Monitor Block
The peak detector captures the largest signal within the
observation period. The detector only observes the magnitude
of the signal. The resolution of the peak detector is a 13-bit
value, and the observation period is 24 bits and represents
converter output samples. The peak magnitude can be derived
by using the following equation:
Peak Magnitude (dBFS) = 20log(Peak Detector Value/213)
The magnitude of the input port signal is monitored over a
programmable time period, which is determined by the signal
monitor period register (SMPR). The peak detector function is
enabled by setting Bit 1 of Register 0x0270 in the signal monitor
control register. The 24-bit SMPR must be programmed before
activating this mode.
Figure 71 shows the 25-bit frame data that encapsulates the
peak detector value. The frame data is transmitted MSB first
with five 5-bit subframes. Each subframe contains a start bit
that can be used by a receiver to validate the deserialized data.
Figure 72 shows the SPORT over JESD204B signal monitor data
with a monitor period timer set to 80 samples.
After enabling peak detection mode, the value in the SMPR is
loaded into a monitor period timer, which decrements at the
Rev. 0 | Page 29 of 107
AD6684
Data Sheet
16-BIT JESD204B SAMPLE SIZE (N' = 16)
15-BIT CONVERTER RESOLUTION (N = 15)
1-BIT
CONTROL
BIT
(CS = 1)
EXAMPLE
CONFIGURATION 1
(N' = 16, N = 15, CS = 1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CTRL
[BIT 2]
X
S[14] S[13] S[12] S[11] S[10]
S[9]
X
S[8]
X
S[7]
X
S[6]
X
S[5]
X
S[4]
X
S[3]
X
S[2]
X
S[1]
X
S[0]
X
X
X
X
X
X
SERIALIZED SIGNAL MONITOR
FRAME DATA
16-BIT JESD204B SAMPLE SIZE (N' = 16)
14-BIT CONVERTER RESOLUTION (N = 14)
1
CONTROL
BIT
(CS = 1)
1 TAIL
BIT
EXAMPLE
CONFIGURATION 2
(N' = 16, N = 14, CS = 1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CTRL
[BIT 2]
X
S[13] S[12] S[11] S[10]
S[9]
X
S[8]
X
S[7]
X
S[6]
X
S[5]
X
S[4]
X
S[3]
X
S[2]
X
S[1]
X
S[0]
X
TAIL
X
X
X
X
X
SERIALIZED SIGNAL MONITOR
FRAME DATA
Figure 70. Signal Monitor Control Bit Locations
5-BIT SUBFRAMES
5-BIT IDLE
SUBFRAME
(OPTIONAL)
IDLE IDLE IDLE IDLE IDLE
1
1
1
1
1
5-BIT IDENTIFIER START ID[3]
ID[2]
0
ID[1]
0
ID[0]
1
0
0
SUBFRAME
5-BIT DATA
MSB
START
0
P[12]
P[11]
P[7]
P[10]
P[6]
P[9]
P5]
SUBFRAME
25-BIT
FRAME
5-BIT DATA
SUBFRAME
START
0
P[8]
P[4]
P[0]
5-BIT DATA
SUBFRAME
START
0
P[3]
0
P[2]
0
P[1]
0
5-BIT DATA
LSB
SUBFRAME
START
0
P[ ] = PEAK MAGNITUDE VALUE
Figure 71. SPORT over JESD204B Signal Monitor Frame Data
Rev. 0 | Page 30 of 107
Data Sheet
AD6684
SMPR = 80 SAMPLES (0x0271 = 0x50; 0x0272 = 0x00; 0x0273 = 0x00)
80 SAMPLE PERIOD
PAYLOAD 3
25-BIT FRAME (N)
IDENT- DATA
DATA
LSB
DATA DATA
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IFIER
MSB
80 SAMPLE PERIOD
PAYLOAD 3
25-BIT FRAME (N + 1)
DATA
DATA
LSB
IDENT-
IFIER
DATA DATA
MSB
IDLE
IDLE
IDLE
IDLE
80 SAMPLE PERIOD
PAYLOAD 3
25-BIT FRAME (N + 2)
IDENT- DATA
IFIER MSB
DATA
LSB
DATA DATA
IDLE
IDLE
IDLE
IDLE
Figure 72. SPORT over JESD204B Signal Monitor Example with Period = 80 Samples
Rev. 0 | Page 31 of 107
AD6684
Data Sheet
DIGITAL DOWNCONVERTER (DDC)
The AD6684 includes four DDCs that provide filtering and reduce
the output data rate. This digital processing section includes an
NCO, a half-band decimating filter, a finite impulse response
(FIR) filter, a gain stage, and a complex to real conversion stage.
Each of these processing blocks has control lines that allow it to be
independently enabled and disabled to provide the desired
processing function. Each pair of ADC channels has two DDCs
(DDC0 and DDC1) for a total of four DDCs. The digital down-
converter can be configured to output either real data or
complex output data.
The Chip Q ignore bit in the chip mode register (Register 0x0200,
Bit 5) controls the chip output muxing of all the DDC channels.
When all DDC channels use real outputs, set this bit high to
ignore all DDC Q output ports. When any of the DDC channels
are set to use complex I/Q outputs, the user must clear this bit
to use both DDC Output Port I and DDC Output Port Q. For
more information, see Figure 81.
DDC GENERAL DESCRIPTION
The four DDC blocks are used to extract a portion of the full
digital spectrum captured by the ADC(s). The DDC blocks are
intended for IF sampling or oversampled baseband radios
requiring wide bandwidth input signals.
The DDCs output a 16-bit stream. To enable this operation, the
converter number of bits, N, is set to a default value of 16, even
though the analog core only outputs 14 bits. In full bandwidth
operation, the ADC outputs are 9-bit words followed by seven
zeros, unless the tail bits are enabled.
Each DDC block contains the following signal processing stages:
Frequency translation stage (optional)
Filtering stage
Gain stage (optional)
DDC I/Q INPUT SELECTION
The AD6684 has four ADC channels and four DDC channels.
Each DDC channel has two input ports that can be paired to
support both real and complex inputs through the I/Q crossbar
mux. For real signals, both DDC input ports must select the
same ADC channel (that is, DDC Input Port I = ADC Channel A
and DDC Input Port Q = ADC Channel A). For complex
signals, each DDC input port must select different ADC
channels (that is, DDC Input Port I = ADC Channel A and
DDC Input Port Q = ADC Channel B, or DDC Input Port I =
ADC Channel C and DDC Input Port Q = ADC Channel D).
Complex to real conversion stage (optional)
Frequency Translation Stage (Optional)
This stage consists of a 48-bit complex NCO and quadrature
mixers that can be used for frequency translation of both real
and complex input signals. This stage shifts a portion of the
available digital spectrum down to baseband.
Filtering Stage
After shifting down to baseband, this stage decimates the
frequency spectrum using a chain of up to four half-band, low-
pass filters for rate conversion. The decimation process lowers the
output data rate, which in turn reduces the output interface rate.
The inputs to each DDC are controlled by the DDC input selec-
tion registers (Register 0x0311 and Register 0x0331) in conjunction
with the pair index register (Register 0x0009). See Table 45 and
Table 46 for information on how to configure the DDCs.
Gain Stage (Optional)
To compensate for losses associated with mixing a real input
signal down to baseband, this stage adds an additional 0 dB or
6 dB of gain.
DDC I/Q OUTPUT SELECTION
Each DDC channel has two output ports that can be paired to
support both real and complex outputs. For real output signals,
only the DDC Output Port I is used (the DDC Output Port Q is
invalid). For complex I/Q output signals, both DDC Output
Port I and DDC Output Port Q are used.
Complex to Real Conversion Stage (Optional)
When real outputs are necessary, this stage converts the complex
outputs back to real by performing an fS/4 mixing operation
plus a filter to remove the complex component of the signal.
The I/Q outputs to each DDC channel are controlled by the
DDC complex to real enable bit, Bit 3 in the DDC control
registers (Register 0x0310 and Register 0x0330) in conjunction
with the pair index register (Register 0x0009).
Figure 73 shows the detailed block diagram of the DDCs
implemented in the AD6684.
Rev. 0 | Page 32 of 107
Data Sheet
AD6684
DDC 0
DDC 1
DDC 0
DDC 1
REAL/I
I
REAL/I
CONVERTER 0
NCO
+
ADC
REAL/I
REAL/Q
REAL/I
SAMPLING
AT fS
MIXER
(OPTIONAL)
REAL/Q
Q
Q CONVERTER 1
L
JESD204B
LANES
SYSREF±
I
AT UP TO
15Gbps
REAL/I
REAL/I
CONVERTER 2
NCO
ADC
SAMPLING
AT fS
+
MIXER
(OPTIONAL)
REAL/Q
Q
Q CONVERTER 3
SYSREF±
I
REAL/I
REAL/I
CONVERTER 0
NCO
ADC
SAMPLING
AT fS
+
MIXER
(OPTIONAL)
REAL/Q
Q
Q CONVERTER 1
L
JESD204B
LANES
SYSREF±
I
AT UP TO
15Gbps
REAL/I
REAL/I
CONVERTER 2
NCO
ADC
SAMPLING
AT fS
REAL/Q
+
MIXER
(OPTIONAL)
REAL/Q
Q
Q CONVERTER 3
SYSREF±
SYSREF
SYNCHRONIZATION
CONTROL CIRCUITS
Figure 73. DDC Detailed Block Diagram
Figure 74 shows an example usage of one of the four DDC
blocks with a real input signal and four half-band filters (HB4 +
HB3 + HB2 + HB1). It shows both complex (decimate by 16)
and real (decimate by 8) output options.
issued. If the DDC soft reset is not issued, the output may
potentially show amplitude variations.
Table 10, Table 11, Table 12, Table 13, and Table 14 show the
DDC samples when the chip decimation ratio is set to 1, 2, 4, 8,
or 16, respectively. When DDCs have different decimation
ratios, the chip decimation ratio must be set to the lowest
decimation ratio of all the DDC channels in the respective
channel pair (Channel A/Channel B or Channel C/Channel D).
In this scenario, samples of higher decimation ratio DDCs are
repeated to match the chip decimation ratio sample rate.
When DDCs have different decimation ratios, the chip
decimation ratio (Register 0x0201) must be set to the lowest
decimation ratio of all the DDC blocks on a per pair basis in
conjunction with the pair index (Register 0x0009). In this
scenario, samples of higher decimation ratio DDCs are repeated
to match the chip decimation ratio sample rate. Whenever the
NCO frequency is set or changed, the DDC soft reset must be
Rev. 0 | Page 33 of 107
AD6684
Data Sheet
ADC
SAMPLING
AT fS
ADC
REAL
REAL
REAL INPUT—SAMPLED AT fS
BANDWIDTH OF
INTEREST
BANDWIDTH OF
INTEREST IMAGE
–
fS/32
fS/32
fS/16
–
fS/2
–fS/3
–
fS/4
–
fS/8
–
fS/16
fS/8
fS/4
fS/3
fS/2
DC
FREQUENCY TRANSLATION STAGE (OPTIONAL)
DIGITAL MIXER + NCO FOR fS/3 TUNING, THE FREQUENCY TUNING
WORD = ROUND ((fS/3)/fS × 2 ) = +9.3825 (0x555555555555)
I
48
13
NCO TUNES CENTER OF
BANDWIDTH OF INTEREST
TO BASEBAND
cos(ωt)
REAL
48-BIT
NCO
90°
0°
–sin(ωt)
Q
BANDWIDTH OF
INTEREST IMAGE
(–6dB LOSS DUE TO
NCO + MIXER)
DIGITAL FILTER
RESPONSE
BANDWIDTH OF INTEREST
(–6dB LOSS DUE TO
NCO + MIXER)
–
fS/32
fS/32
DC
–
fS/2
–fS/3
–
fS/4
–
fS/8
–
fS/16
fS/16
fS/8
fS/4
fS/3
fS/2
FILTERING STAGE
4 DIGITAL HALF-BAND FILTERS
(HB4 + HB3 + HB2 + HB1)
HB4 FIR
HB3 FIR
HB2 FIR
HB1 FIR
HALF-
HALF-
HALF-
HALF-
BAND
BAND
BAND
BAND
I
I
FILTER
FILTER
FILTER
FILTER
2
2
2
2
2
2
2
HB4 FIR
HB3 FIR
HB2 FIR
HB1 FIR
HALF-
BAND
FILTER
HALF-
BAND
FILTER
HALF-
BAND
FILTER
HALF-
BAND
FILTER
Q
Q
2
6dB GAIN TO
COMPENSATE FOR
NCO + MIXER LOSS
COMPLEX (I/Q) OUTPUTS
DECIMATE BY 16
GAIN STAGE (OPTIONAL)
0dB OR 6dB GAIN
DIGITAL FILTER
RESPONSE
I
I
2
+6dB
GAIN STAGE (OPTIONAL)
0dB OR 6dB GAIN
Q
Q
2
+6dB
–
fS/32
fS/32
–
fS/32
fS/32
DC
COMPLEX TO REAL
DC
–
fS/8
–
fS/16
fS/16
fS/8
–
fS/16
fS/16
CONVERSION STAGE (OPTIONAL)
DOWNSAMPLE BY 2
fS/4 MIXING + COMPLEX FILTER TO REMOVE Q
I
I
+6dB
+6dB
REAL (I) OUTPUTS
DECIMATE BY 8
COMPLEX
TO
REAL
REAL/I
Q
Q
6dB GAIN TO
COMPENSATE FOR
NCO + MIXER LOSS
–
fS/32
fS/32
DC
–
fS/8
–
fS/16
fS/16
fS/8
Figure 74. DDC Theory of Operation Example (Real Input, Decimate by 16)
Rev. 0 | Page 34 of 107
Data Sheet
AD6684
Table 10. DDC Samples in Each JESD204B Link When Chip Decimation Ratio = 1
Real (I) Output (Complex to Real Enabled)
Complex (I/Q) Outputs (Complex to Real Disabled)
HB2 FIR +
HB1 FIR
HB3 FIR + HB2
FIR + HB1 FIR
(DCM1 = 4)
HB4 FIR + HB3 FIR +
HB2 FIR + HB1 FIR
(DCM1 = 8)
HB2 FIR +
HB1 FIR
HB3 FIR + HB2
FIR + HB1 FIR
(DCM1 = 8)
HB4 FIR + HB3 FIR +
HB2 FIR + HB1 FIR
(DCM1 = 16)
HB1 FIR
HB1 FIR
(DCM1 = 1) (DCM1 = 2)
(DCM1 = 2) (DCM1 = 4)
N
N
N
N
N
N
N
N
N + 1
N
N
N
N
N
N
N
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
N + 8
N + 9
N + 1
N + 1
N + 2
N + 2
N + 3
N + 3
N + 4
N + 4
N + 5
N + 5
N + 6
N + 6
N + 7
N + 7
N + 8
N + 8
N + 9
N + 9
N + 10
N + 10
N + 11
N + 11
N + 12
N + 12
N + 13
N + 13
N + 14
N + 14
N + 15
N + 15
N
N
N
N
N
N
N
N
N + 1
N + 1
N + 2
N + 2
N + 3
N + 3
N + 4
N + 4
N + 5
N + 5
N + 6
N + 6
N + 7
N + 7
N + 8
N + 8
N + 9
N + 9
N + 10
N + 10
N + 11
N + 11
N + 12
N + 12
N + 13
N + 13
N + 14
N + 14
N + 15
N + 15
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 2
N + 2
N + 2
N + 2
N + 3
N + 3
N + 3
N + 3
N + 4
N + 4
N + 4
N + 4
N + 5
N + 5
N + 5
N + 5
N + 6
N + 6
N + 6
N + 6
N + 7
N + 7
N + 7
N + 7
N + 1
N + 1
N + 1
N + 1
N + 2
N + 2
N + 2
N + 2
N + 3
N + 3
N + 3
N + 3
N + 4
N + 4
N + 4
N + 4
N + 5
N + 5
N + 5
N + 5
N + 6
N + 6
N + 6
N + 6
N + 7
N + 7
N + 7
N + 7
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 2
N + 2
N + 2
N + 2
N + 2
N + 2
N + 2
N + 2
N + 3
N + 3
N + 3
N + 3
N + 3
N + 3
N + 3
N + 3
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 2
N + 2
N + 2
N + 2
N + 2
N + 2
N + 2
N + 2
N + 3
N + 3
N + 3
N + 3
N + 3
N + 3
N + 3
N + 3
N + 10
N + 11
N + 12
N + 13
N + 14
N + 15
N + 16
N + 17
N + 18
N + 19
N + 20
N + 21
N + 22
N + 23
N + 24
N + 25
N + 26
N + 27
N + 28
N + 29
N + 30
N + 31
1 DCM means decimation.
Table 11. DDC Samples in Each JESD204B Link When Chip Decimation Ratio = 2
Real (I) Output (Complex to Real Enabled)
Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR +
HB4 FIR +
HB3 FIR +
HB2 FIR +
HB1 FIR
HB3 FIR +
HB2 FIR +
HB1 FIR
HB3 FIR +
HB2 FIR +
HB1 FIR
HB3 FIR +
HB2 FIR +
HB1 FIR
HB2 FIR +
HB1 FIR
HB2 FIR +
HB1 FIR
HB1 FIR
(DCM1 = 2)
(DCM1 = 4)
(DCM1 = 8)
(DCM1 = 2)
(DCM1 = 4)
(DCM1 = 8)
(DCM1 = 16)
N
N
N
N
N
N
N
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
N + 8
N + 9
N
N
N
N
N + 1
N + 1
N + 1
N + 1
N + 2
N + 2
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
N + 8
N + 9
N
N
N
N
N + 1
N + 1
N + 1
N + 1
N + 2
N + 2
N
N
N
N
N
N
N
N + 1
N + 1
N + 1
N + 1
N + 2
N + 2
N + 3
N + 3
N + 4
N + 4
N + 1
N + 1
N + 2
N + 2
N + 3
N + 3
N + 4
N + 4
Rev. 0 | Page 35 of 107
AD6684
Data Sheet
Real (I) Output (Complex to Real Enabled)
Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR +
HB3 FIR +
HB2 FIR +
HB1 FIR
HB4 FIR +
HB3 FIR +
HB2 FIR +
HB1 FIR
HB3 FIR +
HB2 FIR +
HB1 FIR
HB3 FIR +
HB2 FIR +
HB1 FIR
HB2 FIR +
HB1 FIR
HB2 FIR +
HB1 FIR
HB1 FIR
(DCM1 = 2)
(DCM1 = 4)
(DCM1 = 8)
(DCM1 = 2)
(DCM1 = 4)
(DCM1 = 8)
(DCM1 = 16)
N + 10
N + 11
N + 12
N + 13
N + 14
N + 15
N + 5
N + 5
N + 6
N + 6
N + 7
N + 7
N + 2
N + 2
N + 3
N + 3
N + 3
N + 3
N + 10
N + 11
N + 12
N + 13
N + 14
N + 15
N + 5
N + 5
N + 6
N + 6
N + 7
N + 7
N + 2
N + 2
N + 3
N + 3
N + 3
N + 3
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
1 DCM means decimation.
Table 12. DDC Samples in Each JESD204B Link When Chip Decimation Ratio = 4
Real (I) Output (Complex to Real Enabled)
Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR + HB3 FIR +
HB2 FIR + HB1 FIR
(DCM1 = 8)
HB4 FIR + HB3 FIR +
HB2 FIR + HB1 FIR
(DCM1 = 16)
HB3 FIR + HB2 FIR +
HB2 FIR + HB1 FIR
(DCM1 = 4)
HB3 FIR + HB2 FIR +
HB1 FIR (DCM1 = 8)
HB1 FIR (DCM1 = 4)
N
N
N
N
N
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
N
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
N
N
N
N
N + 1
N + 1
N + 1
N + 1
N + 1
N + 1
N + 2
N + 2
N + 3
N + 3
N + 1
N + 1
N + 2
N + 2
N + 3
N + 3
1 DCM means decimation.
Table 13. DDC Samples in Each JESD204B Link When Chip Decimation Ratio = 8
Real (I) Output (Complex to Real Enabled)
Complex (I/Q) Outputs (Complex to Real Disabled)
HB3 FIR + HB2 FIR + HB1 FIR
HB4 FIR + HB3 FIR + HB2 FIR +
HB1 FIR (DCM1 = 16)
HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 8)
(DCM1 = 8)
N
N
N
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
N
N + 1
N + 1
N + 2
N + 2
N + 3
N + 3
1 DCM means decimation.
Table 14. DDC Samples in Each JESD204B Link When Chip Decimation Ratio = 16
Real (I) Output (Complex to Real Enabled)
HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16)
Not applicable
Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16)
N
Not applicable
Not applicable
Not applicable
N + 1
N + 2
N + 3
1 DCM means decimation.
Rev. 0 | Page 36 of 107
Data Sheet
AD6684
For example, if the chip decimation ratio is set to decimate by 4,
DDC 0 is set to use HB2 + HB1 filters (complex outputs, decimate
by 4) and DDC 1 is set to use HB4 + HB3 + HB2 + HB1 filters
(real outputs, decimate by 8). DDC 1 repeats its output data two
times for every one DDC 0 output. The resulting output samples
are shown in Table 15.
Table 15. DDC Output Samples in Each JESD204B Link When Chip DCM1 = 4, DDC 0 DCM1 = 4 (Complex), and DDC 1 DCM1 = 8 (Real)
DDC 0 DDC 1
Output Port Q Output Port Q
Not applicable
DDC Input Samples
N
Output Port I
Output Port I
I0 (N)
Q0 (N)
I1 (N)
N + 1
N + 2
N + 3
N + 4
N + 5
N + 6
N + 7
I0 (N + 1)
I0 (N + 2)
I0 (N + 3)
Q0 (N + 1)
Q0 (N + 2)
Q0 (N + 3)
N + 8
N + 9
I1 (N + 1)
Not applicable
N + 10
N + 11
N + 12
N + 13
N + 14
N + 15
1 DCM means decimation.
Rev. 0 | Page 37 of 107
AD6684
Data Sheet
FREQUENCY TRANSLATION
Variable IF Mode
GENERAL DESCRIPTION
NCO and mixers are enabled. NCO output frequency can be
used to digitally tune the IF frequency.
Frequency translation is accomplished by using a 48-bit
complex NCO with a digital quadrature mixer. This stage
translates either a real or complex input signal from an IF to a
baseband complex digital output (carrier frequency = 0 Hz).
0 Hz IF (ZIF) Mode
The mixers are bypassed, and the NCO is disabled.
fS/4 Hz IF Mode
The frequency translation stage of each DDC can be controlled
individually and supports four different IF modes using Bits[5:4]
of the DDC control registers (Register 0x0310 and Register 0x0330)
in conjunction with the pair index register (Register 0x0009).
These IF modes are
The mixers and the NCO are enabled in special downmixing by
fS/4 mode to save power.
Test Mode
Input samples are forced to 0.9599 to positive full scale. The
NCO is enabled. This test mode allows the NCOs to directly
drive the decimation filters.
Variable IF mode
0 Hz IF or zero IF (ZIF) mode
fS/4 Hz IF mode
Test mode
Figure 75 and Figure 76 show examples of the frequency
translation stage for both real and complex inputs.
NCO FREQUENCY TUNING WORD (FTW) SELECTION
48-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 2
48
I
cos(ωt)
ADC
SAMPLING
AT fS
ADC + DIGITAL MIXER + NCO
REAL INPUT—SAMPLED AT fS
REAL
REAL
48-BIT
NCO
90°
0°
COMPLEX
–sin(ωt)
Q
BANDWIDTH OF
INTEREST
BANDWIDTH OF
INTEREST IMAGE
–
fS/32
fS/32
DC
–
fS/2
–
fS/3
–
fS/4
–
fS/8
–
fS/16
fS/16
fS/8
fS/4
fS/3
fS/2
–6dB LOSS DUE TO
NCO + MIXER
48-BIT NCO FTW =
48
ROUND ((fS/3)/fS × 2 ) =
POSITIVE FTW VALUES
13
+9.3825 (0x555555555555)
–
fS/32
fS/32
DC
48-BIT NCO FTW =
NEGATIVE FTW VALUES
48
ROUND ((–fS/3)/fS × 2 ) =
13
–9.3825 (0xFFFF000000000000)
–
fS/32
fS/32
DC
Figure 75. DDC NCO Frequency Tuning Word Selection—Real Inputs
Rev. 0 | Page 38 of 107
Data Sheet
AD6684
NCO FREQUENCY TUNING WORD (FTW) SELECTION
48-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 2
48
QUADRATURE MIXER
ADC
SAMPLING
AT fS
I
+
I
I
I
–
I
Q
QUADRATURE ANALOG MIXER +
Q
2 ADCs + QUADRATURE DIGITAL
MIXER + NCO
48-BIT
NCO
REAL
90°
PHASE
90°
0°
COMPLEX
Q
COMPLEX INPUT—SAMPLED AT fS
I
I
+
ADC
SAMPLING
AT fS
Q
Q
Q
Q
+
BANDWIDTH OF
INTEREST
IMAGE DUE TO
ANALOG I/Q
MISMATCH
–
fS/32
fS/32
fS/16
–
fS/2
–
fS/3
–
fS/4
–
fS/8
–
fS/16
fS/8
fS/4
fS/3
fS/2
DC
48-BIT NCO FTW =
48
ROUND ((fS/3)/fS × 2 ) =
POSITIVE FTW VALUES
13
+9.3825 (0x555555555555)
–
fS/32
fS/32
DC
Figure 76. DDC NCO Frequency Tuning Word Selection—Complex Inputs
Setting Up the NCO FTW and POW
DDC NCO + MIXER LOSS AND SFDR
The NCO frequency value is given by the 48-bit twos
complement number entered in the NCO FTW. Frequencies
between −fS/2 and +fS/2 (fS/2 excluded) are represented using
the following frequency words:
When mixing a real input signal down to baseband, 6 dB of loss
is introduced in the signal due to filtering of the negative image.
An additional 0.05 dB of loss is introduced by the NCO. The
total loss of a real input signal mixed down to baseband is
6.05 dB. For this reason, it is recommended that the user
compensate for this loss by enabling the 6 dB of gain in the gain
stage of the DDC to recenter the dynamic range of the signal
within the full scale of the output bits.
0x8000 0000 0000 represents a frequency of −fS/2.
0x0000 0000 0000 represents dc (frequency is 0 Hz).
0x7FFF FFFF FFFF represents a frequency of +fS/2 − fS/248.
The NCO frequency tuning word can be calculated using the
following equation:
When mixing a complex input signal down to baseband, the
maximum value that each I/Q sample can reach is 1.414 × full
scale after it passes through the complex mixer. To avoid over-
range of the I/Q samples and to keep the data bit widths aligned
with real mixing, 3.06 dB of loss is introduced in the mixer for
complex signals. An additional 0.05 dB of loss is introduced by
the NCO. The total loss of a complex input signal mixed down
to baseband is −3.11 dB.
mod
fC , fS
fS
48
NCO _ FTW round 2
where:
NCO_FTW is a 48-bit twos complement number representing
the NCO FTW.
fC is the desired carrier frequency in Hz.
fS is the AD6684 sampling frequency (clock rate) in Hz.
mod( ) is a remainder function. For example, mod(110,100) =
10 and for negative numbers, mod(–32,10) = −2.
round( ) is a rounding function. For example, round(3.6) = 4
and for negative numbers, round(–3.4) = −3.
The worst case spurious signal from the NCO is greater than
102 dBc SFDR for all output frequencies.
NUMERICALLY CONTROLLED OSCILLATOR
The AD6684 has a 48-bit NCO for each DDC that enables the
frequency translation process. The NCO allows the input
spectrum to be tuned to dc, where it can be effectively filtered
by the subsequent filter blocks to prevent aliasing. The NCO
can be set up by providing a frequency tuning word (FTW) and
a phase offset word (POW).
Note that this equation applies to the aliasing of signals in the
digital domain (that is, aliasing introduced when digitizing
analog signals).
Rev. 0 | Page 39 of 107
AD6684
Data Sheet
For example, if the ADC sampling frequency (fS) is 500 MSPS
and the carrier frequency (fC) is 140.312 MHz, then
of the NCO. See the Setting Up the NCO FTW and POW section
for more information.
Use the following two methods to synchronize multiple PAWs
within the chip.
48 mod 140.312,500
2
NCO_FTW = round
=
500
7.89886 × 1013 Hz
Using the SPI. Use the DDC NCO soft reset bit in the DDC
synchronization control register (Register 0x0300, Bit 4) to
reset all the PAWs in the chip. This is accomplished by
setting the DDC NCO soft reset bit high and then setting
this bit low. Note that this method can only be used to
synchronize DDC channels within the same pair (A/B or
C/D) of a AD6684 chip.
This, in turn, converts to 0x47D in the 48-bit twos complement
representation for NCO_FTW. The actual carrier frequency,
C_ACTUAL, is calculated based on the following equation:
f
NCO _ FTW fS
fC_ACTUAL
=
= 140.312 MHz
248
Using the SYSREF pin. When the SYSREF pin is enabled
in the SYSREF control registers (Register 0x0120 and
Register 0x0121) and the DDC synchronization is enabled
in the DDC synchronization control register (Register 0x0300,
Bits[1:0]), any subsequent SYSREF event resets all the
PAWs in the chip. Note that this method can be used to
synchronize DDC channels within the same AD6684 chip
or DDC channels within separate AD6684 chips.
A 48-bit POW is available for each NCO to create a known phase
relationship between multiple AD6684 chips or individual DDC
channels inside one AD6684 chip.
The POW registers can be updated in the NCO at any time
without disrupting the phase accumulators, allowing phase
adjustments to occur during normal operation. However, the
following procedure must be followed to update the FTW
registers to ensure proper operation of the NCO:
Mixer
1. Write to the FTW registers for all the DDCs.
2. Synchronize the NCOs either through the DDC NCO soft
reset bit (Register 0x0300, Bit 4), which is accessible
through the SPI, or through the assertion of the SYSREF
pin.
The NCO is accompanied by a mixer. Its operation is similar to
an analog quadrature mixer. It performs the downconversion of
input signals (real or complex) by using the NCO frequency as a
local oscillator. For real input signals, this mixer performs a real
mixer operation (with two multipliers). For complex input
signals, the mixer performs a complex mixer operation (with
four multipliers and two adders). The mixer adjusts its operation
based on the input signal (real or complex) provided to each
individual channel. The selection of real or complex inputs can
be controlled individually for each DDC block using Bit 7 of the
DDC control registers (Register 0x0310 and Register 0x0330) in
conjunction with the pair index register (Register 0x0009).
It is important to note that the NCOs must be synchronized
either through the SPI or through the SYSREF pin after all
writes to the FTW or POW registers are complete. This step
is necessary to ensure the proper operation of the NCO.
NCO Synchronization
Each NCO contains a separate phase accumulator word (PAW).
The initial reset value of each PAW is set to zero, and the phase
increment value of each PAW is determined by the FTW. The
POW is added to the PAW to produce the instantaneous phase
Rev. 0 | Page 40 of 107
Data Sheet
AD6684
FIR FILTERS
Table 16 shows the different bandwidths selectable by including
different half-band filters. In all cases, the DDC filtering stage
on the AD6684 provides <−0.001 dB of pass-band ripple and
>100 dB of stop-band alias rejection.
GENERAL DESCRIPTION
There are four sets of decimate by 2, low-pass, half-band, FIR
filters (labeled HB1 FIR, HB2 FIR, HB3 FIR, and HB4 FIR in
Figure 73) following the frequency translation stage. After the
carrier of interest is tuned down to dc (carrier frequency = 0 Hz),
these filters efficiently lower the sample rate, while providing
sufficient alias rejection from unwanted adjacent carriers
around the bandwidth of interest.
Table 17 shows the amount of stop-band alias rejection for
multiple pass-band ripple/cutoff points. The decimation ratio of
the filtering stage of each DDC can be controlled individually
through Bits[1:0] of the DDC control registers (Register 0x0310
and Register 0x0330) in conjunction with the pair index register
(Register 0x0009).
HB1 FIR is always enabled and cannot be bypassed. The HB2,
HB3, and HB4 FIR filters are optional and can be bypassed for
higher output sample rates.
Table 16. DDC Filter Characteristics
Real Output
Output
Sample
Decimation Rate
Complex (I/Q) Output
Output
Sample
Decimation Rate
Alias
Half Band
Filter
Selection
Protected
Bandwidth
(MHz)
Ideal SNR
Improvement1
(dB)
Alias
Rejection
Ripple (dB) (dB)
Pass-Band
Ratio
(MSPS)
Ratio
(MSPS)
HB1
1
500
2
250 (I) +
250 (Q)
200
100
50
1
<−0.0001 >100
HB1 + HB2
2
4
8
250
125
62.5
4
125 (I) +
125 (Q)
4
HB1 + HB2 +
HB3
8
62.5 (I) +
62.5 (Q)
7
HB1 + HB2 +
HB3 + HB4
16
31.25 (I) +
31.25 (Q)
25
10
1 Ideal SNR improvement due to oversampling and filtering = 10log(bandwidth/(fS/2)).
Table 17. DDC Filter Alias Rejection
Alias Rejection
(dB)
Pass-Band Ripple/Cutoff
Point (dB)
Alias Protected Bandwidth for Real
(I) Outputs1
Alias Protected Bandwidth for Complex
(I/Q) Outputs
>100
95
90
85
80
25.07
19.3
10.7
<−0.0001
<−0.0002
<−0.0003
<−0.0005
<−0.0009
−0.5
<40% × fOUT
<80% × fOUT
<40.12% × fOUT
<40.23% × fOUT
<40.36% × fOUT
<40.53% × fOUT
45.17% × fOUT
46.2% × fOUT
<80.12% × fOUT
<80.46% × fOUT
<80.72% × fOUT
<81.06% × fOUT
90.34% × fOUT
92.4% × fOUT
−1.0
−3.0
48.29% × fOUT
96.58% × fOUT
1 fOUT = ADC input sample rate ÷ DDC decimation.
Rev. 0 | Page 41 of 107
AD6684
Data Sheet
Table 19. HB3 Filter Coefficients
HALF-BAND FILTERS
HB3 Coefficient
Number
Decimal
Coefficient
Quantized
Coefficient (17-Bit)
The AD6684 offers four half-band filters to enable digital signal
processing of the ADC converted data. These half-band filters
are bypassable and can be individually selected.
C1, C11
C2, C10
C3, C9
C4, C8
C5, C7
C6
0.006638
0
−0.051055
0
0.294418
0.500000
435
0
−3,346
0
19,295
32,768
HB4 Filter
The first decimate by 2, half-band, low-pass, FIR filter (HB4)
uses an 11-tap, symmetrical, fixed coefficient filter implementa-
tion that is optimized for low power consumption. The HB4
filter is only used when complex outputs (decimate by 16) or
real outputs (decimate by 8) are enabled; otherwise, it is
bypassed. Table 18 and Figure 77 show the coefficients and
response of the HB4 filter.
–20
–40
Table 18. HB4 Filter Coefficients
–60
HB4 Coefficient
Number
Decimal
Coefficient
Quantized
Coefficient (15-Bit)
–80
–100
–120
–140
–160
–180
C1, C11
C2, C10
C3, C9
C4, C8
C5, C7
C6
0.006042
0
−0.049377
0
0.293334
0.500000
99
0
−809
0
4806
8192
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
NORMALIZED FREQUENCY (× RAD/SAMPLE)
Figure 78. HB3 Filter Response
HB2 Filter
–50
–100
–150
–200
–250
The third decimate by 2, half-band, low-pass, FIR filter (HB2)
uses a 19-tap, symmetrical, fixed coefficient filter implementa-
tion that is optimized for low power consumption.
The HB2 filter is only used when complex or real outputs
(decimate by 4, 8, or 16) is enabled; otherwise, it is bypassed.
Table 20 and Figure 79 show the coefficients and response of
the HB2 filter.
Table 20. HB2 Filter Coefficients
HB2 Coefficient
Number
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Decimal
Coefficient
Quantized
Coefficient (18-Bit)
NORMALIZED FREQUENCY (× RAD/SAMPLE)
Figure 77. HB4 Filter Response
C1, C19
C2, C18
C3, C17
C4, C16
C5, C15
C6, C14
C7, C13
C8, C12
C9, C11
C10
0.000671
0
−0.005325
0
0.022743
0
−0.074181
0
0.306091
0.500000
88
0
−698
0
2,981
0
−9,723
0
40,120
65,536
HB3 Filter
The second decimate by 2, half-band, low-pass, FIR filter (HB3)
uses an 11-tap, symmetrical, fixed coefficient filter implementa-
tion that is optimized for low power consumption. The HB3
filter is only used when complex outputs (decimate by 8 or 16)
or real outputs (decimate by 4 or 8) are enabled; otherwise, it is
bypassed. Table 19 and Figure 78 show the coefficients and
response of the HB3 filter.
Rev. 0 | Page 42 of 107
Data Sheet
AD6684
Table 21. HB1 Filter Coefficients
–20
–40
HB1 Coefficient
Number
Decimal
Coefficient
Quantized
Coefficient (20-Bit)
C1, C63
C2, C62
C3, C61
C4, C60
C5, C59
C6, C58
C7, C57
C8, C56
C9, C55
C10, C54
C11, C53
C12, C52
C13, C51
C14, C50
C15, C49
C16, C48
C17, C47
C18, C46
C19, C45
C20, C44
C21, C43
C22, C42
C23, C41
C24, C40
C25, C39
C26, C38
C27, C37
C28, C36
C29, C35
C30, C34
C31, C33
C32
−0.000019
0
0.000072
0
−0.000194
0
0.000442
0
−0.000891
0
0.001644
0
−0.002840
0
0.004653
0
−0.007311
0
0.011121
0
−0.016553
0
0.024420
0
−0.036404
0
0.056866
0
−0.101892
0
0.316883
0.500000
−10
0
38
0
−102
0
232
0
−467
0
862
0
−1,489
0
2,440
0
−3,833
0
5,831
0
−8,679
0
12,803
0
−19,086
0
29,814
0
–60
–80
–100
–120
–140
–160
–180
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
NORMALIZED FREQUENCY (× RAD/SAMPLE)
Figure 79. HB2 Filter Response
HB1 Filter
The fourth and final decimate by 2, half-band, low-pass, FIR
filter (HB1) uses a 63-tap, symmetrical, fixed coefficient filter
implementation that is optimized for low power consumption.
The HB1 filter is always enabled and cannot be bypassed.
Table 21 and Figure 80 show the coefficients and response of
the HB1 filter.
–20
–40
–60
–80
–100
–120
–140
–160
−53,421
0
166,138
262,144
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
NORMALIZED FREQUENCY (× RAD/SAMPLE)
Figure 80. HB1 Filter Response
Rev. 0 | Page 43 of 107
AD6684
Data Sheet
DDC GAIN STAGE
DDC COMPLEX TO REAL CONVERSION
Each DDC contains an independently controlled gain stage.
The gain is selectable as either 0 dB or 6 dB. When mixing a real
input signal down to baseband, it is recommended that the user
enable the 6 dB of gain to recenter the dynamic range of the
signal within the full scale of the output bits.
Each DDC contains an independently controlled complex to
real conversion block. The complex to real conversion block
reuses the last filter (HB1 FIR) in the filtering stage along with
an fS/4 complex mixer to upconvert the signal. After upconvert-
ing the signal, the Q portion of the complex mixer is no longer
needed and is dropped.
When mixing a complex input signal down to baseband, the mixer
has already recentered the dynamic range of the signal within
the full scale of the output bits, and no additional gain is necessary.
However, the optional 6 dB gain compensates for low signal
strengths. The downsample by 2 portion of the HB1 FIR filter is
bypassed when using the complex to real conversion stage.
Figure 81 shows a simplified block diagram of the complex to
real conversion.
HB1 FIR
GAIN STAGE
COMPLEX TO
REAL ENABLE
LOW-PASS
FILTER
I
0dB
OR
I
I
0
2
I/REAL
6dB
1
COMPLEX TO REAL CONVERSION
0dB
OR
6dB
cos(ωt)
+
90°
REAL
fS/4
0°
–
sin(ωt)
0dB
OR
6dB
Q
LOW-PASS
FILTER
Q
0dB
OR
6dB
Q
Q
2
HB1 FIR
Figure 81. Complex to Real Conversion Block
Rev. 0 | Page 44 of 107
Data Sheet
AD6684
DDC EXAMPLE CONFIGURATIONS
Table 22 describes the register settings for multiple DDC example configurations.
Table 22. DDC Example Configurations (Per ADC Channel Pair)
No. of
Virtual
Chip
Chip
DDC
Application Decimation DDC Input Output
Bandwidth Converters
Layer
Ratio
Type
Type
Per DDC1
Required
Register Settings2
One DDC
2
Complex
Complex 40% × fS
2
0x0009 = 0x01, 0x02, or 0x03 (pair selection)
0x0200 = 0x01 (one DDC; I/Q selected)
0x0201 = 0x01 (chip decimate by 2)
0x0310 = 0x83 (complex mixer; 0 dB gain; variable
IF; complex outputs; HB1 filter)
0x0311 = 0x04 (DDC I input = ADC Channel A/
Channel C; DDC Q input = ADC Channel B/
Channel D)
0x0314, 0x0315, 0x0316, 0x0317, 0x0318, 0x031A,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for
DDC 0
One DDC
4
Complex
Complex 20% × fS
2
0x0009 = 0x01, 0x02, or 0x03 (pair selection)
0x0200 = 0x01 (one DDC; I/Q selected)
0x0201 = 0x02 (chip decimate by 4)
0x0310= 0x80 (complex mixer; 0 dB gain; variable
IF; complex outputs; HB2 + HB1 filters)
0x0311= 0x04 (DDC I input = ADC Channel A/
Channel C; DDC Q input = ADC Channel B/
Channel D)
0x0314, 0x0315, 0x0316, 0x0317, 0x0318, 0x031A,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for
DDC 0
Two DDCs
2
Real
Real
20%× fS
2
0x0009 = 0x01, 0x02, or 0x03 (pair selection)
0x0200 = 0x22 (two DDCs; I only selected)
0x0201 = 0x01 (chip decimate by 2)
0x0310, 0x0330 = 0x48 (real mixer; 6 dB gain;
variable IF; real output; HB2 + HB1 filters)
0x0311 = 0x00 (DDC 0 I input = ADC Channel A/
Channel C; DDC 0 Q input = ADC Channel A/
Channel C)
0x0331 = 0x05 (DDC 1 I input = ADC Channel B/
Channel D; DDC 1 Q input = ADC Channel B/
Channel D)
0x0314, 0x0315, 0x0316, 0x0317, 0x0318, 0x031A,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for
DDC 0
0x0334, 0x0335, 0x0336, 0x0337, 0x0338, 0x033A,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 =
FTW and POW set as required by application for
DDC 1
Rev. 0 | Page 45 of 107
AD6684
Data Sheet
No. of
Virtual
Bandwidth Converters
Chip
Chip
DDC
Application Decimation DDC Input Output
Layer
Ratio
Type
Type
Per DDC1
Required
Register Settings2
Two DDCs
2
Complex
Complex 40%× fS
4
0x0009 = 0x01, 0x02, or 0x03 (pair selection)
0x0200 = 0x22 (two DDCs; I only selected)
0x0201 = 0x01 (chip decimate by 2)
0x0310, 0x0330 = 0x4B (complex mixer; 6 dB gain;
variable IF; complex output; HB1 filter)
0x0311, 0x0331 = 0x04 (DDC 0 I input = ADC
Channel A/Channel C; DDC 0 Q input = ADC
Channel B/Channel D)
0x0314, 0x0315, 0x0316, 0x0317, 0x0318, 0x031A,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for
DDC 0
0x0334, 0x0335, 0x0336, 0x0337, 0x0338, 0x033A,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342=
FTW and POW set as required by application for
DDC 1
Two DDCs
4
Complex
Complex 20% × fS
4
0x0009 = 0x01, 0x02, or 0x03 (pair selection)
0x0200 = 0x02 (two DDCs; I/Q selected)
0x0201 = 0x02 (chip decimate by 4)
0x0310, 0x0330 = 0x80 (complex mixer; 0 dB gain;
variable IF; complex outputs; HB2 + HB1 filters)
0x0311, 0x0331 = 0x04 (DDC I input = ADC
Channel A/Channel C; DDC Q input = ADC
Channel B/Channel D)
0x0314, 0x0315, 0x0316, 0x0317, 0x0318, 0x031A,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for
DDC 0
0x0334, 0x0335, 0x0336, 0x0337, 0x0338, 0x033A,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342=
FTW and POW set as required by application for
DDC 1
Two DDCs
4
Complex
Real
10% × fS
2
0x0009 = 0x01, 0x02, or 0x03 (pair selection)
0x0200 = 0x22 (two DDCs; I only selected)
0x0201 = 0x02 (chip decimate by 4)
0x0310, 0x0330 = 0x89 (complex mixer; 0 dB gain;
variable IF; real output; HB3 + HB2 + HB1 filters)
0x0311, 0x0331 = 0x04 (DDC I input = ADC
Channel A/Channel C; DDC Q input = ADC
Channel B/Channel D)
0x0314, 0x0315, 0x0316, 0x0317, 0x0318, 0x031A,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for
DDC 0
0x0334, 0x0335, 0x0336, 0x0337, 0x0338, 0x033A,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342=
FTW and POW set as required by application for
DDC 1
Rev. 0 | Page 46 of 107
Data Sheet
AD6684
No. of
Virtual
Bandwidth Converters
Chip
Chip
DDC
Application Decimation DDC Input Output
Layer
Ratio
Type
Type
Per DDC1
Required
Register Settings2
Two DDCs
4
Real
Real
10% × fS
2
0x0009 = 0x01, 0x02, or 0x03 (pair selection)
0x0200 = 0x22 (two DDCs; I only selected)
0x0201 = 0x02 (chip decimate by 4)
0x0310, 0x0330 = 0x49 (real mixer; 6 dB gain;
variable IF; real output; HB3 + HB2 + HB1 filters)
0x0311 = 0x00 (DDC 0 I input = ADC Channel A/
Channel C; DDC 0 Q input = ADC Channel A/
Channel C)
0x0331 = 0x05 (DDC 1 I input = ADC Channel B/
Channel D; DDC 1 Q input = ADC Channel B/
Channel D)
0x0314, 0x0315, 0x0316, 0x0317, 0x0318, 0x031A,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for
DDC 0
0x0334, 0x0335, 0x0336, 0x0337, 0x0338, 0x033A,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342=
FTW and POW set as required by application for
DDC 1
Two DDCs
4
Real
Complex 20% × fS
4
0x0009 = 0x01, 0x02, or 0x03 (pair selection)
0x0200 = 0x02 (two DDCs; I/Q selected)
0x0201 = 0x02 (chip decimate by 4)
0x0310, 0x0330 = 0x40 (real mixer; 6 dB gain;
variable IF; complex output; HB2 + HB1 filters)
0x0311 = 0x00 (DDC 0 I input = ADC Channel A/
Channel C; DDC 0 Q input = ADC Channel A/
Channel C)
0x0331 = 0x05 (DDC 1 I input = ADC Channel B/
Channel D; DDC 1 Q input = ADC Channel B/
Channel D)
0x0314, 0x0315, 0x0316, 0x0317, 0x0318, 0x031A,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for
DDC 0
0x0334, 0x0335, 0x0336, 0x0337, 0x0338, 0x033A,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342=
FTW and POW set as required by application for
DDC 1
Rev. 0 | Page 47 of 107
AD6684
Data Sheet
No. of
Virtual
Bandwidth Converters
Chip
Chip
DDC
Application Decimation DDC Input Output
Layer
Ratio
Type
Type
Per DDC1
Required
Register Settings2
Two DDCs
8
Real
Real
5% × fS
2
0x0009 = 0x01, 0x02, or 0x03 (pair selection)
0x0200 = 0x22 (two DDCs; I only selected)
0x0201 = 0x03 (chip decimate by 8)
0x0310, 0x0330 = 0x4A (real mixer; 6 dB gain;
variable IF; real output; HB4 + HB3 + HB2 + HB1
filters)
0x0311 = 0x00 (DDC 0 I input = ADC Channel A/
Channel C; DDC 0 Q input = ADC Channel A/
Channel C)
0x0331 = 0x05 (DDC 1 I input = ADC Channel B/
Channel D; DDC 1 Q input = ADC Channel B/
Channel D)
0x0314, 0x0315, 0x0316, 0x0317, 0x0318, 0x031A,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for
DDC 0
0x0334, 0x0335, 0x0336, 0x0337, 0x0338, 0x033A,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342=
FTW and POW set as required by application for
DDC 1
1 fS is the ADC sample rate. Bandwidths listed are <−0.001 dB of pass-band ripple and >100 dB of stop-band alias rejection.
2 The NCOs must be synchronized either through the SPI or through the SYSREF pin after all writes to the FTW or POW registers have completed. This is necessary to
ensure the proper operation of the NCO. See the NCO Synchronization section for more information.
Rev. 0 | Page 48 of 107
Data Sheet
AD6684
NOISE SHAPING REQUANTIZER (NSR)
When operating the AD6684 with the NSR enabled, a decimating
half-band filter that is optimized at certain input frequency bands
can also be enabled. This filter offers the user the flexibility in
signal bandwidth processing and image rejection. Careful
frequency planning can offer advantages in analog filtering
preceding the ADC. The filter can function either in high-pass
or low-pass mode. The filter can be optionally enabled on the
AD6684 when the NSR is enabled. When operating with the
NSR enabled, the decimating half-band filter mode (low pass or
high pass) is selected by setting Bit 7 in Register 0x041E. When the
decimating half-band filter is enabled, the chip decimation ratio
register (Register 0x0201) must be set to a decimation rate of 2
(register value = 0x01).
Half-Band Filter Features
The half-band decimating filter provides approximately 39.5%
of the output sample rate in usable bandwidth (19.75% of the
input sample clock). The filter provides >40 dB of rejection. The
normalized response of the half-band filter in low-pass mode is
shown in Figure 82. In low-pass mode, operation is allowed in
the first Nyquist zone, which includes frequencies of up to fS/2,
where fS is the decimated sample rate. For example, with an
input clock of 500 MHz, the output sample rate is 250 MSPS
and fS/2 = 125 MHz.
10
0
–10
–20
–30
–40
–50
–60
–70
–80
DECIMATING HALF-BAND FILTER
The AD6684 optional decimating half-band filter reduces the
input sample rate by a factor of 2 while rejecting aliases that fall
into the band of interest. For an input sample clock of 500 MHz,
this filter reduces the output sample rate to 250 MSPS. This filter is
designed to provide >40 dB of alias protection for 39.5% of the
output sample rate (79% of the Nyquist band). For an ADC sample
rate of 500 MSPS, the filter provides a maximum usable
bandwidth of 98.75 MHz.
0
0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
NORMALIZED FREQUENCY (× RAD/SAMPLE)
Half-Band Filter Coefficients
The 19-tap, symmetrical, fixed coefficient half-band filter has
low power consumption due to its polyphase implementation.
Table 23 lists the coefficients of the half-band filter in low-pass
mode. In high-pass mode, Coefficient C9 is multiplied by −1.
The decimal coefficients used in the implementation and the
decimal equivalent values of the coefficients are listed.
Coefficients not listed in Table 23 are 0s.
Figure 82. Low-Pass, Half-Band Filter Response
The half-band filter can also be used in high-pass mode. The
usable bandwidth remains at 39.5% of the output sample rate
(19.75% of the input sample clock), which is the same as in low-
pass mode). Figure 83 shows the normalized response of the
half-band filter in high-pass mode. In high-pass mode, operation
is allowed in the second and third Nyquist zones, which includes
frequencies from fS/2 to 3fS/2, where fS is the decimated sample
rate. For example, with an input clock of 500 MHz, the output
sample rate is 250 MSPS, fS/2 = 125 MHz, and 3fS/2 = 375 MHz.
10
Table 23. Fixed Coefficients for Half-Band Filter
Coefficient
Number
Decimal
Coefficient
Quantized
Coefficient (12-Bit)
0
0.012207
−0.022949
0.045410
−0.094726
0.314453
0.500000
25
−47
93
−194
644
1024
C2, C16
C4, C14
C6, C12
C8, C10
C9
0
–10
–20
–30
–40
–50
–60
–70
–80
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
NORMALIZED FREQUENCY (× π RAD/SAMPLE)
Figure 83. High-Pass, Half-Band Filter Response
Rev. 0 | Page 49 of 107
AD6684
Data Sheet
mode, the useful frequency range can be set using the 6-bit
NSR OVERVIEW
tuning word in the NSR tuning register (Address 0x0422).
There are 59 possible tuning words (TW), from 0 to 58; each
step is 0.5% of the ADC sample rate. The following three
equations describe the left band edge (f0), the channel center
(fCENTER), and the right band edge (f1), respectively:
The AD6684 features an NSR to allow higher than 9-bit SNR to
be maintained in a subset of the Nyquist band. The harmonic
performance of the receiver is unaffected by the NSR feature.
When enabled, the NSR contributes an additional 3.0 dB of loss
to the input signal, such that a 0 dBFS input is reduced to
−3.0 dBFS at the output pins. This loss does not degrade the SNR
performance of the AD6684.
f0 = fADC × 0.005 × TW
f
CENTER = f0 + 0.105 × fADC
The NSR feature can be independently controlled per channel
via the SPI.
f1 = f0 + 0.21 × fADC
28% BW Mode (>130 MHz at 491.52 MSPS)
Two different bandwidth modes are provided; select the mode
from the SPI port. In each of the two modes, the center frequency
of the band can be tuned such that IFs can be placed anywhere
in the Nyquist band. The NSR feature is enabled by default on
the AD6684. The bandwidth and mode of the NSR operation
are selected by setting the appropriate bits in Register 0x0420
and Register 0x0422. By selecting the appropriate profile and
mode bits in these two registers, the NSR feature can be enabled
for the desired mode of operation.
The second NSR mode offers excellent noise performance
across a bandwidth that is 28% of the ADC output sample rate
(56% of the Nyquist band) and can be centered by setting the
NSR mode bits in the NSR mode register (Address 0x0420) to
001. In this mode, the useful frequency range can be set using
the 6-bit tuning word in the NSR tuning register (Address 0x0422).
There are 44 possible tuning words (TW, from 0 to 43); each step is
0.5% of the ADC sample rate. The following three equations
describe the left band edge (f0), the channel center (fCENTER), and
the right band edge (f1), respectively:
21% BW Mode (>100 MHz at 491.52 MSPS)
The first NSR mode offers excellent noise performance across a
bandwidth that is 21% of the ADC output sample rate (42% of
the Nyquist band) and can be centered by setting the NSR mode
bits in the NSR mode register (Address 0x0420) to 000. In this
f0 = fADC × 0.005 × TW
f
CENTER = f0 + 0.14 × fADC
f1 = f0 + 0.28 × fADC
Rev. 0 | Page 50 of 107
Data Sheet
AD6684
VARIABLE DYNAMIC RANGE (VDR)
The AD6684 features a VDR digital processing block to allow
up to a 14-bit dynamic range to be maintained in a subset of the
Nyquist band. Across the full Nyquist band, a minimum 9-bit
dynamic range is available at all times. This operation is suitable
for applications such as DPD processing. The harmonic perfor-
mance of the receiver is unaffected by this feature. When enabled,
VDR does not contribute loss to the input signal but operates by
effectively changing the output resolution at the output pins.
This feature can be independently controlled per channel via
the SPI.
Table 24. VDR Reduced Output Resolution Values
VDR Punish Bits[1:0]
Output Resolution (Bits)
00
01
10
11
14
13
12 or 11
10 or 9
The frequency zones of the mask are defined by the bandwidth
mode selected in Register 0x0430. The upper amplitude limit
for input signals located in these frequency zones is −30 dBFS.
If the input signal level in the disallowed frequency zones exceeds
an amplitude level of –30 dBFS (into the gray shaded areas), the
VDR block triggers a reduction in the output resolution, as shown
in Figure 84. The VDR block engages and begins limiting output
resolution gradually as the signal amplitudes increase in the
mask regions. As the signal amplitude level increases into the
mask regions, the output resolution is gradually lowered. For
every 6 dB increase in signal level above −30 dBFS, one bit of
output resolution is discarded from the output data by the VDR
block, as shown in Table 25. These zones can be tuned within
the Nyquist band by setting Bits[3:0] in Register 0x0434 to
determine the VDR center frequency (fVDR). The VDR center
frequency in complex mode can be adjusted from 1/16 fS to
15/16 fS in 1/16 fS steps. In real mode, fVDR can be adjusted from
1/8 fS to 3/8 fS in 1/16 fS steps.
The VDR block operates in either complex or real mode. In
complex mode, VDR has selectable bandwidths of 25% and 43%
of the output sample rate. In real mode, the bandwidth of
operation is limited to 25% of the output sample rate. The
bandwidth and mode of the VDR operation are selected by
setting the appropriate bits in Register 0x0430.
When the VDR block is enabled, input signals that violate a
defined mask (signified by the gray shaded areas in Figure 84)
result in the reduction of the output resolution of the AD6684.
The VDR block analyzes the peak value of the aggregate signal
level in the disallowed zones to determine the reduction of the
output resolution. To indicate that the AD6684 is reducing
output, the resolution VDR punish bits and/or a VDR high/low
resolution bit can optionally be inserted into the output data
stream as control bits by programming the appropriate value
into Register 0x0559 and Register 0x055A. Up to two control
bits can be used without the need to change the converter
resolution parameter, N. Up to three control bits can be used,
but if using three, the converter resolution parameter, N, must
be changed to 13. The VDR high/low resolution bit can be
programmed into either of the three available control bits and
indicates if VDR is reducing output resolution (bit value is a 1),
or if full resolution is available (bit value is a 0). Enable the two
punish bits to provide a clearer indication of the available resolution
of the sample. To decode these two bits, see Table 24.
Table 25. VDR Reduced Output Resolution Values
Signal Amplitude Violating Defined
VDR Mask
Output Resolution
(Bits)
Amplitude ≤ −30 dBFS
14
13
12
11
10
9
−30 dBFS < amplitude ≤ −24 dBFS
−24 dBFS < amplitude ≤ −18 dBFS
−18 dBFS < amplitude ≤ −12 dBFS
−12 dBFS < amplitude ≤ −6 dBFS
−6 dBFS < amplitude ≤ 0 dBFS
dBFS
–30
0
0
fS
fS
INTERMODULATION PRODUCTS < –30dBFS
INTERMODULATION PRODUCTS > –30dBFS
Figure 84. VDR Operation—Reduction in Output Resolution
Rev. 0 | Page 51 of 107
AD6684
Data Sheet
VDR REAL MODE
VDR COMPLEX MODE
The real mode of VDR works over a bandwidth of 25% of the
sample rate (50% of the Nyquist band). The output bandwidth
of the AD6684 can be 25% only when operating in real mode.
Figure 85 shows the frequency zones for the 25% bandwidth
real output VDR mode tuned to a center frequency (fVDR) of fS/4
(tuning word = 0x04). The frequency zones where the amplitude
cannot exceed −30 dBFS are the upper and lower portions of
the Nyquist band signified by the gray shaded areas.
dBFS
The complex mode of VDR works with selectable bandwidths
of 25% of the sample rate (50% of the Nyquist band) and 43% of
the sample rate (86% of the Nyquist band). Figure 86 and Figure 87
show the frequency zones for VDR in the complex mode. When
operating VDR in complex mode, place in-phase (I) input signal
data in Channel A and place quadrature (Q) signal data in
Channel B.
Figure 86 shows the frequency zones for the 25% bandwidth
VDR mode with a center frequency of fS/4 (tuning word =
0x04). The frequency zones where the amplitude may not
exceed −30 dBFS are the upper and lower portions of the
Nyquist band extending into the complex domain.
dBFS
–30
–30
0
–1/2 fS
1/8 fS
3/8 fS 1/2 fS
Figure 86. 25% VDR Bandwidth, Complex Mode
0
1/8 fS
3/8 fS
1/2 fS
The center frequency (fVDR) of the VDR function can be tuned
within the Nyquist band from 0 to 15/16 fS in 1/16 fS steps. In
complex mode, Tuning Word 0 (0x00) through Tuning Word 15
(0x0F) are valid. Table 28 and Table 29 show the tuning words
and frequency values for the 25% complex mode. Table 28
shows the relative frequency values, and Table 29 shows the
absolute frequency values based on a sample rate of 491.52 MSPS.
Figure 85. 25% VDR Bandwidth, Real Mode
The center frequency (fVDR) of the VDR function can be tuned
within the Nyquist band from 1/8 fS to 3/8 fS in 1/16 fS steps. In
real mode, Tuning Word 2 (0x02) through Tuning Word 6
(0x06) are valid. Table 26 shows the relative frequency values,
and Table 27 shows the absolute frequency values based on a
sample rate of 491.52 MSPS.
Table 28. VDR Tuning Words and Relative Frequency
Values, 25% BW, Complex Mode
Table 26. VDR Tuning Words and Relative Frequency
Values, 25% BW, Real Mode
Lower
Center
Frequency
Upper Band
Edge
Tuning Word Band Edge
Tuning
Word
Lower Band
Edge
Center
Frequency
Upper Band
Edge
0 (0x00)
1 (0x01)
2 (0x02)
3 (0x03)
4 (0x04)
5 (0x05)
6 (0x06)
7 (0x07)
8 (0x08)
9 (0x09)
10 (0x0A)
11 (0x0B)
12 (0x0C)
13 (0x0D)
14 (0x0E)
15 (0x0F)
−1/8 fS
−1/16 fS
0
1/16 fS
1/8 fS
3/16 fS
1/4 fS
5/16 fS
3/8 fS
7/16 fS
1/2 fS
9/16 fS
5/8 fS
11/16 fS
3/4 fS
13/16 fS
0
1/8 fS
3/16 fS
1/4 fS
5/16 fS
3/8 fS
7/16 fS
1/2 fS
9/16 fS
5/8 fS
11/16 fS
3/4 fS
13/16 fS
7/8 fS
15/16 fS
fS
1/16 fS
1/8 fS
3/16 fS
1/4 fS
5/16 fS
3/8 fS
7/16 fS
1/2 fS
9/16 fS
5/8 fS
11/16 fS
3/4 fS
13/16 fS
7/8 fS
15/16 fS
2 (0x02)
3 (0x03)
4 (0x04)
5 (0x05)
6 (0x06)
0
1/8 fS
3/16 fS
1/4 fS
5/16 fS
3/8 fS
1/4 fS
5/16 fS
3/8 fS
7/16 fS
1/2 fS
1/16 fS
1/8 fS
3/16 fS
1/4 fS
Table 27. VDR Tuning Words and Absolute Frequency
Values, 25% BW, Real Mode (fS = 491.52 MSPS)
Center
Tuning
Word
Lower Band
Edge (MHz)
Frequency
(MHz)
Upper Band
Edge (MHz)
2 (0x02)
3 (0x03)
4 (0x04)
5 (0x05)
6 (0x06)
0
61.44
92.16
122.88
153.6
184.32
122.88
153.6
184.32
215.04
245.76
30.72
61.44
92.16
122.88
17/16 fS
Rev. 0 | Page 52 of 107
Data Sheet
AD6684
Table 29. VDR Tuning Words and Absolute Frequency
Values, 25% BW, Complex Mode (fS = 491.52 MSPS)
Table 30. VDR Tuning Words and Relative Frequency
Values, 43% BW, Complex Mode
Center
Lower
Band Edge Frequency
Center
Tuning
Word
Upper Band
Edge (MHz)
Lower Band
Tuning Word Edge (MHz)
Frequency
(MHz)
Upper Band
Edge (MHz)
(MHz)
−61.44
−30.72
0.00
(MHz)
0 (0x00)
1 (0x01)
2 (0x02)
3 (0x03)
4 (0x04)
5 (0x05)
6 (0x06)
7 (0x07)
8 (0x08)
9 (0x09)
10 (0x0A)
11 (0x0B)
12 (0x0C)
13 (0x0D)
14 (0x0E)
15 (0x0F)
0.00
30.72
61.44
61.44
92.16
122.88
153.6
0 (0x00)
1 (0x01)
2 (0x02)
3 (0x03)
4 (0x04)
5 (0x05)
6 (0x06)
7 (0x07)
8 (0x08)
9 (0x09)
10 (0x0A)
11 (0x0B)
12 (0x0C)
13 (0x0D)
14 (0x0E)
15 (0x0F)
−14/65 fS
−11/72 fS
−1/11 fS
−1/36 fS
1/29 fS
7/72 fS
4/25 fS
2/9 fS
2/7 fS
25/72 fS
34/83 fS
17/36 fS
23/43 fS
43/72 fS
31/47 fS
13/18 fS
0
14/65 fS
5/18 fS
1/16 fS
1/8 fS
3/16 fS
1/4 fS
5/16 fS
3/8 fS
7/16 fS
1/2 fS
9/16 fS
5/8 fS
11/16 fS
3/4 fS
13/16 fS
7/8 fS
15/16 fS
16/47 fS
29/72 fS
20/43 fS
19/36 fS
49/83 fS
47/72 fS
5/7 fS
30.72
92.16
61.44
92.16
122.88
153.6
184.32
215.04
245.76
276.48
307.2
337.92
368.64
399.36
122.88
153.6
184.32
215.04
245.76
276.48
307.2
337.92
368.64
399.36
430.08
460.8
184.32
215.04
245.76
276.48
307.2
337.92
368.64
399.36
430.08
460.8
7/9 fS
21/25 fS
65/72 fS
28/29 fS
37/36 fS
12/11 fS
83/72 fS
491.52
522.24
Table 31. VDR Tuning Words and Absolute Frequency
Values, 43% BW, Complex Mode (fS = 491.52 MSPS)
Center
Table 30 and Table 31 show the tuning words and frequency
values for the 43% complex mode. Table 30 shows the relative
frequency values, and Table 31 shows the absolute frequency
values based on a sample rate of 491.52 MSPS. Figure 87 shows
the frequency zones for the 43% BW VDR mode with a center
frequency (fVDR) of fS/4 (tuning word = 0x04). The frequency
zones where the amplitude may not exceed −30 dBFS are the
upper and lower portions of the Nyquist band extending into
the complex domain.
Lower Band
Tuning Word Edge (MHz)
Frequency
(MHz)
Upper Band
Edge (MHz)
0 (0x00)
1 (0x01)
2 (0x02)
3 (0x03)
4 (0x04)
5 (0x05)
6 (0x06)
7 (0x07)
8 (0x08)
9 (0x09)
10 (0x0A)
11 (0x0B)
12 (0x0C)
13 (0x0D)
14 (0x0E)
15 (0x0F)
−105.37
−75.09
−44.68
−13.65
16.95
0.00
30.72
61.44
92.16
122.88
153.6
184.32
215.04
245.76
276.48
307.2
337.92
368.64
399.36
430.08
460.8
105.87
136.53
167.33
197.97
228.61
259.41
290.17
320.85
351.09
382.29
412.88
443.73
474.57
505.17
536.2
dBFS
47.79
78.64
109.23
140.43
170.67
201.35
232.11
262.91
293.55
324.19
354.99
–30
–1/2 fS
0
1/4 fS
1/2 fS
20/43 fS
1/29 fS
Figure 87. 43% VDR Bandwidth, Complex Mode
566.61
Rev. 0 | Page 53 of 107
AD6684
Data Sheet
DIGITAL OUTPUTS
K = number of frames per multiframe
INTRODUCTION TO THE JESD204B INTERFACE
(AD6684 value = 4, 8, 12, 16, 20, 24, 28, or 32 )
S = samples transmitted per single converter per frame cycle
(AD6684 value = set automatically based on L, M, F, and N΄)
HD = high density mode (AD6684 = set automatically based
on L, M, F, and N΄)
The AD6684 digital outputs are designed to the JEDEC standard
JESD204B, serial interface for data converters. JESD204B is a
protocol to link the AD6684 to a digital processing device over
a serial interface with lane rates of up to 15 Gbps. The benefits
of the JESD204B interface over LVDS include a reduction in
required board area for data interface routing, and an ability to
enable smaller packages for converter and logic devices.
CF = number of control words per frame clock cycle per
converter device (AD6684 value = 0)
Figure 88 shows a simplified block diagram of the AD6684
JESD204B link. By default, the AD6684 is configured to use four
converters and four lanes. The Converter A and Converter B
data is output to SERDOUTAB0 and SERDOUTAB1 , and the
Converter C and Converter D data is output to SERDOUTCD0
and SERDOUTCD1 . The AD6684 allows other configurations,
such as combining the outputs of each pair of converters into a
single lane, or changing the mapping of the digital output paths.
These modes are set up via a quick configuration register in the
SPI register map, along with additional customizable options.
JESD204B OVERVIEW
The JESD204B data transmit blocks assemble the parallel data
from the ADC into frames and uses 8-bit/10-bit encoding as
well as optional scrambling to form serial output data. Lane
synchronization is supported through the use of special control
characters during the initial establishment of the link. Additional
control characters are embedded in the data stream to maintain
synchronization thereafter. A JESD204B receiver is required to
complete the serial link. For additional details on the JESD204B
interface, refer to the JESD204B standard.
By default in the AD6684, the 14-bit converter word from each
converter is broken into two octets (eight bits of data). Bit 13
(MSB) through Bit 6 are in the first octet. The second octet
contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits
can be configured as zeros or a pseudorandom number sequence.
The tail bits can also be replaced with control bits indicating
overrange, SYSREF , VDR punish bits, or fast detect output.
Control bits are filled and inserted MSB first such that enabling
CS = 1 activates Control Bit 2, enabling CS = 2 activates Control
Bit 2 and Control Bit 1, and enabling CS = 3 activates Control Bit 2,
Control Bit 1, and Control Bit 0.
The JESD204B data transmit blocks in the AD6684 map up to
two physical ADCs or up to four virtual converters (when the
DDCs are enabled) over each of the two JESD204B links. Each
link can be configured to use one or two JESD204B lanes for up
to a total of four lanes for the AD6684 chip. The JESD204B
specification refers to a number of parameters to define the
link, and these parameters must match between the JESD204B
transmitter (the AD6684 output) and the JESD204B receiver
(the logic device input). The JESD204B outputs of the AD6684
function effectively as two individual JESD204B links. The two
JESD204B links can be synchronized, if desired, using the
SYSREF input.
The two resulting octets can be scrambled. Scrambling is
optional; however, it is recommended to avoid spectral peaks
when transmitting similar digital data patterns. The scrambler
uses a self synchronizing, polynomial-based algorithm defined
by the equation 1 + x14 + x15. The descrambler in the receiver is
a self synchronizing version of the scrambler polynomial.
Each JESD204B link is described according to the following
parameters:
L = number of lanes per converter device (lanes per link)
(AD6684 value = 1 or 2)
M = number of converters per converter device (virtual
converters per link)
The two octets are then encoded with an 8-bit/10-bit encoder.
The 8-bit/10-bit encoder works by taking eight bits of data (an
octet) and encoding them into a 10-bit symbol. Figure 89 shows
how the 14-bit data is taken from the ADC, the tail bits are
added, the two octets are scrambled, and how the octets are
encoded into two 10-bit symbols. Figure 89 shows the default
data format.
(AD6684 value = 1, 2, or 4)
F = octets per frame (AD6684 value = 1, 2, 4, or 8)
N΄ = number of bits per sample (JESD204B word size)
(AD6684 value = 8 or 16)
N = converter resolution
(AD6684 value = 7 to 16)
CS = number of control bits per sample
(AD6684 value = 0, 1, 2, or 3)
Rev. 0 | Page 54 of 107
Data Sheet
AD6684
CONVERTER A
INPUT
ADC A
LANE MUX
AND MAPPING
(SPI
REGISTERS:
0x05B0,
JESD204B PAIR
A/B LINK
CONTROL
(L, M, F)
(SPI REGISTER
0x0570)
SERDOUTAB0+
SERDOUTAB0–
MUX/
FORMAT
(SPI REGISTERS:
0x0561, 0x0564)
SERDOUTAB1+
SERDOUTAB1–
0x05B2,
0x05B3)
CONVERTER B
INPUT
ADC B
SYSREF±
SYNCINAB±
SYNCINCD±
CONVERTER C
INPUT
ADC C
LANE MUX
AND MAPPING
(SPI
REGISTERS:
0x05B0,
JESD204B PAIR
A/B LINK
CONTROL
(L, M, F)
(SPI REGISTER
0x0570)
MUX/
FORMAT
(SPI REGISTERS:
0x0561, 0x0564)
SERDOUTCD0+
SERDOUTCD0–
SERDOUTCD1+
SERDOUTCD1–
0x05B2,
0x05B3)
CONVERTER D
INPUT
ADC D
Figure 88. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x0200 = 0x00)
JESD204B DATA
JESD204B
INTERFACE TEST
PATTERNS
LINK LAYER TEST
PATTERNS
JESD204B LONG
TRANSPORT TEST
PATTERN
REG 0x0574[2:0]
(REG 0x0573,
REG 0x0551 TO REG 0x0558)
REG 0x0571[5]
SERDOUTAB0±/
SERDOUTCD0±/
SERDOUTAB0±/
SERDOUTCD0±/
SERIALIZER
SCRAMBLER
1 + x14
(OPTIONAL)
8-BIT/10-BIT
ENCODER
x15
ADC TEST PATTERNS
(REG 0x0550,
REG 0x0551 TO REG 0x0558)
+
FRAME
CONSTRUCTION
a
b
. . . .
i
j
a
b
. . . .
i j
A13
MSB
JESD204B SAMPLE
CONSTRUCTION
SYMBOL0
SYMBOL1
A12
A11
A10
A9
a
a
b
b
c
c
d
d
e
e
f
f
g
g
h
h
i
i
j
j
A8
A7
A6
A5
A4
A3
A2
A1
A0
ADC
A13 A5
S7
S6
S5
S4
S3
S2
S1
S0
S7
S6
S5
S4
S3
S2
S1
S0
MSB
LSB
MSB
A12 A4
A11 A3
A10 A2
A9 A1
A8 A0
A7 C2
TAIL BITS
REG 0x0571[6]
A6
T
LSB
LSB
CONTROL BITS
C2
C1
C0
Figure 89. ADC Output Datapath Showing Data Framing
TRANSPORT
LAYER
DATA LINK
LAYER
PHYSICAL
LAYER
PROCESSED
ALIGNMENT
8-BIT/10-BIT
SAMPLE
FRAME
CROSSBAR
MUX
SAMPLES
SCRAMBLER
CHARACTER
GENERATION
SERIALIZER
Tx
OUTPUT
CONSTRUCTION CONSTRUCTION
ENCODER
FROM ADC
SYSREF±
SYNCINB±
Figure 90. Data Flow
Rev. 0 | Page 55 of 107
AD6684
Data Sheet
characters in its input data stream using clock and data recovery
(CDR) techniques.
FUNCTIONAL OVERVIEW
The block diagram in Figure 90 shows the flow of data through
each of the two JESD204B links from the sample input to the
physical output. The processing can be divided into layers that
are derived from the open source initiative (OSI) model widely
used to describe the abstraction layers of communications
systems. These layers are the transport layer, data link layer, and
physical layer (serializer and output driver).
The receiver issues a synchronization request by asserting the
SYNCINB AB and SYNCINB CD pins of the AD6684 low.
The JESD204B Tx then begins sending /K/ characters. After the
receiver synchronizes, it waits for the correct reception of at
least four consecutive /K/ symbols. It then deasserts SYNCINB AB
and SYNCINB CD. The AD6684 then transmits an ILAS on
the following local multiframe clock (LMFC) boundary.
Transport Layer
For more information on the code group synchronization
phase, refer to the JEDEC Standard JESD204B, July 2011,
Section 5.3.3.1.
The transport layer handles packing the data (consisting of
samples and optional control bits) into JESD204B frames that
are mapped to 8-bit octets. These octets are sent to the data link
layer. The transport layer mapping is controlled by rules derived
from the link parameters. Tail bits are added to fill gaps where
required. The following equation can be used to determine the
number of tail bits within a sample (JESD204B word):
The SYNCINB AB and SYNCINB CD pin operation can also
be controlled by the SPI. The SYNCINB AB and SYNCINB CD
signals are differential LVDS mode signals by default, but can
also be driven single-ended. For more information on configuring
the SYNCINB AB and SYNCINB CD pin operation, refer to
Register 0x0572.
T = N΄ – N – CS
Data Link Layer
Initial Lane Alignment Sequence (ILAS)
The data link layer is responsible for the low level functions of
passing data across the link. These functions include optionally
scrambling the data, inserting control characters for multichip
synchronization, lane alignment, or monitoring, and encoding
8-bit octets into 10-bit symbols. The data link layer is also
responsible for sending the initial lane alignment sequence
(ILAS), which contains the link configuration data used by the
receiver to verify the settings in the transport layer.
The ILAS phase follows the CGS phase and begins on the next
LMFC boundary. The ILAS consists of four mulitframes, with
an /R/ character marking the beginning and an /A/ character
marking the end. The ILAS begins by sending an /R/ character
followed by 0 to 255 ramp data for one multiframe. On the
second multiframe, the link configuration data is sent, starting
with the third character. The second character is a /Q/ character
to confirm that the link configuration data follows. All
undefined data slots are filled with ramp data. The ILAS
sequence is never scrambled.
Physical Layer
The physical layer consists of the high speed circuitry clocked at
the serial clock rate. In this layer, parallel data is converted into
one, two, or four lanes of high speed differential serial data.
The ILAS sequence construction is shown in Figure 91. The
four multiframes include the following:
JESD204B LINK ESTABLISHMENT
Multiframe 1. Begins with an /R/ character (/K28.0/) and
ends with an /A/ character (/K28.3/).
The AD6684 JESD204B transmitter (Tx) interface operates in
Subclass 1 as defined in the JEDEC Standard 204B (July 2011
specification). The link establishment process is divided into the
following steps: code group synchronization and SYNCINB AB/
SYNCINB CD, initial lane alignment sequence, and user data
and error correction.
Multiframe 2. Begins with an /R/ character followed by a
/Q/ (/K28.4/) character, followed by link configuration
parameters over 14 configuration octets (see Table 32) and
ends with an /A/ character. Many of the parameter values
are of the value – 1 notation.
Multiframe 3. Begins with an /R/ character (/K28.0/) and
ends with an /A/ character (/K28.3/).
Multiframe 4. Begins with an /R/ character (/K28.0/) and
ends with an /A/ character (/K28.3/).
Code Group Synchronization (CGS) and SYNCINB
The CGS is the process by which the JESD204B receiver finds
the boundaries between the 10-bit symbols in the stream of
data. During the CGS phase, the JESD204B transmit block
transmits /K28.5/ characters. The receiver must locate /K28.5/
K
K
R
D
D
A
R
Q
C
C
D
D
A
R
D
D
A
R
D
D A D
END OF
MULTIFRAME
START OF
ILAS
START OF LINK
CONFIGURATION DATA
START OF
USER DATA
Figure 91. Initial Lane Alignment Sequence
Rev. 0 | Page 56 of 107
Data Sheet
AD6684
User Data and Error Detection
The 8-bit/10-bit interface has options that can be controlled via
the SPI. These operations include bypass and invert. These options
are intended to be troubleshooting tools for the verification of
the digital front end (DFE). Refer to the Memory Map section,
Register 0x0572, Bits[2:1] for information on configuring the 8-bit/
10-bit encoder.
After the initial lane alignment sequence is complete, the user
data is sent. Normally, within a frame, all characters are considered
user data. However, to monitor the frame clock and multiframe
clock synchronization, there is a mechanism for replacing
characters with /F/ or /A/ alignment characters when the data
meets certain conditions. These conditions are different for
unscrambled and scrambled data. The scrambling operation is
enabled by default, but it can be disabled using the SPI.
PHYSICAL LAYER (DRIVER) OUTPUTS
Digital Outputs, Timing, and Controls
The AD6684 physical layer consists of drivers that are defined
in the JEDEC Standard JESD204B, July 2011. The differential
digital outputs are powered up by default. The drivers use a
dynamic 100 Ω internal termination to reduce unwanted
reflections.
For scrambled data, any 0xFC character at the end of a frame is
replaced with an /F/, and any 0xFD character at the end of a multi-
frame is replaced with an /A/. The JESD204B receiver (Rx)
checks for /F/ and /A/ characters in the received data stream
and verifies that they only occur in the expected locations. If an
unexpected /F/ or /A/ character is found, the receiver handles
the situation by using dynamic realignment or asserting the
SYNCINB signal for more than four frames to initiate a
resynchronization. For unscrambled data, if the final character
of two subsequent frames are equal, the second character is
replaced with an /F/ if it is at the end of a frame, and an /A/ if it
is at the end of a multiframe.
Place a 100 ꢀ differential termination resistor at each receiver
input to result in a nominal 300 mV p-p swing at the receiver
(see Figure 92). Alternatively, single-ended 50 ꢀ termination
can be used. When single-ended termination is used, the
termination voltage is DRVDD1/2. Otherwise, 0.1 μF
ac coupling capacitors can be used to terminate to any single-
ended voltage.
V
RXCM
Insertion of alignment characters can be modified using the
SPI. The frame alignment character insertion (FACI) is enabled
by default. More information on the link controls is available in
the Memory Map section, Register 0x0571.
50ꢀ
50ꢀ
DRVDD
100ꢀ
DIFFERENTIAL
TRACE PAIR
0.1µF
0.1µF
SERDOUTx+
RECEIVER
100ꢀ
OR
8-Bit/10-Bit Encoder
SERDOUTx–
The 8-bit/10-bit encoder converts 8-bit octets into 10-bit symbols
and inserts control characters into the stream when needed. The
control characters used in JESD204B are shown in Table 32. The
8-bit/10-bit encoding ensures that the signal is dc balanced by
using the same number of ones and zeros across multiple
symbols.
OUTPUT SWING = 300mV p-p
V
= V
RXCM
CM
Figure 92. AC-Coupled Digital Output Termination Example
Table 32. AD6684 Control Characters used in JESD204B
10-Bit Value,
10-Bit Value,
Abbreviation
Control Symbol
/K28.0/
/K28.3/
/K28.4/
/K28.5/
8-Bit Value
000 11100
011 11100
100 11100
101 11100
111 11100
RD1 = −1
RD1 = +1
Description
/R/
/A/
/Q/
/K/
/F/
001111 0100
001111 0011
001111 0100
001111 1010
001111 1000
110000 1011
110000 1100
110000 1101
110000 0101
110000 0111
Start of multiframe
Lane alignment
Start of link configuration data
Group synchronization
Frame alignment
/K28.7/
1 RD means running disparity.
Rev. 0 | Page 57 of 107
AD6684
Data Sheet
500
400
The AD6684 digital outputs can interface with custom application
specific integrated circuits (ASICs) and field programmable gate
array (FPGA) receivers, providing superior switching performance
in noisy environments. Single point to point network topologies
are recommended with a single differential 100 Ω termination
resistor placed as close to the receiver inputs as possible. The
common mode of the digital output automatically biases itself
to half the DRVDD1 supply of 1.25 V (VCM = 0.6 V). See Figure 93
for an example of dc coupling the outputs to the receiver logic.
300
200
100
0
Tx EYE
MASK
–100
–200
–300
–400
–500
DRVDD
100ꢀ
DIFFERENTIAL
TRACE PAIR
SERDOUTx+
RECEIVER
100ꢀ
–60
–40
–20
0
20
40
60
SERDOUTx–
TIME (ps)
Figure 94. AD6684 Digital Outputs Data Eye Diagram; External 100 Ω
Terminations at 15 Gbps
OUTPUT SWING = 300mV p-p
V
= DRVDD/2
CM
16000
14000
12000
10000
8000
6000
4000
2000
0
Figure 93. DC-Coupled Digital Output Termination Example
If there is no far end receiver termination, or if there is poor
differential trace routing, timing errors may result. To avoid
such timing errors, it is recommended that the trace length be
less than six inches, and that the differential output traces be
close together and at equal lengths.
Figure 94, Figure 95, and Figure 96 show examples of the digital
output data eye, time interval error (TIE) jitter histogram, and
bathtub curve, respectively, for one AD6684 lane running at
15 Gbps. The format of the output data is twos complement by
default. To change the output data format, see the Memory Map
section (Register 0x0561 in Table 45 and Table 46).
–4
–2
0
2
4
6
TIME (ps)
De-Emphasis
Figure 95. AD6684 Digital Outputs Histogram; External 100 Ω Terminations
at 15 Gbps
De-emphasis enables the receiver eye diagram mask to be met
in conditions where the interconnect insertion loss does not
meet the JESD204B specification. Use the preemphasis feature
only when the receiver is unable to recover the clock due to
excessive insertion loss. Under normal conditions, preemphasis
is disabled to conserve power. Additionally, enabling and setting
too high a preemphasis value on a short link can cause the
receiver eye diagram to fail. Use the preemphasis setting with
caution because it can increase electromagnetic interference
(EMI). See the Memory Map section (Registers 0x05C4 and
Register 0x05C6 in Table 45 and Table 46) for more details.
1
–2
1
–4
1
–6
1
–8
1
–10
1
–12
1
–14
1
Phase-Locked Loop
–16
1
The phase-locked loop (PLL) is used to generate the serializer
clock, which operates at the JESD204B lane rate. The status
of the PLL lock can be checked in the PLL lock status bit
(Register 0x056F, Bit 7). This read only bit lets the user know if
the PLL has achieved a lock for the specific setup. The JESD204B
lane rate control bit, Bit 4 of Register 0x056E, must be set to
correspond with the lane rate.
–0.5 –0.4 –0.3 –0.2 –0.1
0
0.1
0.2
0.3
0.4
0.5
UI
Figure 96. AD6684 Digital Outputs Bathtub Curve; External 100 Ω
Terminations at 15 Gbps
Rev. 0 | Page 58 of 107
Data Sheet
AD6684
Figure 97 shows a block diagram of the two scenarios described
for I/Q transport layer mapping.
JESD204B Tx CONVERTER MAPPING
To support the different chip operating modes, the AD6684
design treats each sample stream (real or I/Q) as originating
from separate virtual converters. The I/Q samples are always
mapped in pairs with the I samples mapped to the first virtual
converter and the Q samples mapped to the second virtual
converter. With this transport layer mapping, the number of
virtual converters are the same whether
The JESD204B Tx block for AD6684 supports up to four DDC
blocks. Each DDC block outputs either two sample streams
(I/Q) for the complex data components (real + imaginary), or
one sample stream for real (I) data. The JESD204B interface can
be configured to use up to eight virtual converters depending on
the DDC configuration. Figure 98 shows the virtual converters
and their relationship to the DDC outputs when complex outputs
are used. Table 33 shows the virtual converter mapping for each
chip operating mode when channel swapping is disabled.
A single real converter is used along with a digital
downconverter block producing I/Q outputs, or
An analog downconversion is used with two real
converters producing I/Q outputs.
DIGITAL DOWNCONVERSION
M = 2
I
CONVERTER 0
DIGITAL
DOWNCONVERSION
JESD204B
Tx
REAL
REAL
L LANES
ADC
Q
CONVERTER 1
I/Q ANALOG MIXING
M = 2
I
I
CONVERTER 0
ADC
REAL
90°
PHASE
JESD204B
Tx
L LANES
Σ
Q
Q
CONVERTER 1
ADC
Figure 97. I/Q Transport Layer Mapping
DDC 0
ADC
SAMPLING
AT fS
REAL/I
REAL/Q
REAL/I
REAL/Q
REAL/I
REAL/I
CONVERTER 0
Q
I
I
REAL/Q
Q
Q
I/Q
CROSSBAR
MUX
CONVERTER 1
OUTPUT
INTERFACE
DDC 1
DDC 0
DDC 1
ADC
SAMPLING
AT fS
REAL/I
REAL/I
CONVERTER 2
Q
I
I
REAL/Q
Q
Q
CONVERTER 3
ADC A
SAMPLING
AT fS
REAL/I
REAL/I
CONVERTER 4
Q
I
I
REAL/Q
Q
Q
I/Q
CROSSBAR
MUX
CONVERTER 5
OUTPUT
INTERFACE
ADC
SAMPLING
AT fS
REAL/I
REAL/I
CONVERTER 6
Q
I
I
REAL/Q
Q
Q
CONVERTER 7
Figure 98. DDCs and Virtual Converter Mapping
Rev. 0 | Page 59 of 107
AD6684
Data Sheet
The maximum lane rate allowed by the JESD204B specification
is 15 Gbps. The lane line rate is related to the JESD204B
parameters using the following equation:
SETTING UP THE AD6684 DIGITAL INTERFACE
The following SPI writes are required for the AD6684 at startup
and each time the ADC is reset (datapath reset, soft reset, link
power-down/power-up, or hard reset):
10
8
M N '
f
OUT
1. Write 0x4F to Register 0x1228.
2. Write 0x0F to Register 0x1228.
3. Write 0x04 to Register 0x1222.
4. Write 0x00 to Register 0x1222.
5. Write 0x08 to Register 0x1262.
6. Write 0x00 to Register 0x1262.
Lane Line Rate =
where:
OUT
L
fADC_CLOCK
Decimation Ratio
f
The decimation ratio (DCM) is the parameter programmed in
Register 0x0201.
The AD6684 has two JESD204B links. The device offers an easy
way to set up the JESD204B link through the JESD04B quick
configuration register (Register 0x0570). The serial outputs
(SERDOUTABx and SERDOUTCDx ) are considered to be
part of one JESD204B link. The basic parameters that determine
the link setup are
Use the following steps to configure the output:
1. Power down the link.
2. Select quick configuration options.
3. Configure detailed options
4. Set output lane mapping (optional).
5. Set additional driver configuration options (optional).
6. Power up the link.
Number of lanes per link (L)
Number of converters per link (M)
Number of octets per frame (F)
If the lane line rate calculated is less than 6.25 Gbps, select the
low line rate option by programming a value of 0x10 to
Register 0x056E.
If the internal DDCs are used for on-chip digital processing, M
represents the number of virtual converters. The virtual
converter mapping setup is shown in Figure 98.
Table 34 and Table 35 show the JESD204B output configurations
for both N΄ = 16 and N΄ = 8 for a given number of virtual
converters. Take care to ensure that the serial line rate for given
configuration is within the supported range of 1.5625 Gbps to
15 Gbps.
Table 33. Virtual Converter Mapping (Per Link)
Chip Application Mode
(Register 0x0200,
Bits[3:0])
Chip Q Ignore
(Register 0x0200,
Bit 5)
Virtual Converter Mapping
Number of Virtual
Converters Supported
0
1
2
3
1 to 2
Full bandwidth mode (0x0) Real or complex (0x0)
ADC A/C
samples
ADC B/D
samples
Unused
Unused
1
2
2
4
One DDC mode (0x1)
One DDC mode (0x1)
Two DDC mode (0x2)
Two DDC mode (0x2)
Real (I only) (0x1)
Complex (I/Q) (0x0)
Real (I only) (0x1)
Complex (I/Q) (0x0)
DDC 0
I samples
DDC 0
I samples
DDC 0
I samples
DDC 0
Unused
Unused
Unused
Unused
Unused
Unused
Unused
DDC 0
Q samples
DDC 1
I samples
DDC 0
DDC 1
DDC 1
I samples
Q samples
I samples
Q samples
Rev. 0 | Page 60 of 107
Data Sheet
AD6684
Table 34. JESD204B Output Configurations for N΄= 16
Number of Virtual
JESD204B Transport Layer Settings2
Converters
Supported (Same
Value as M)
JESD204B Quick
Configuration
(0x0570)
JESD204B Serial
Line Rate1
L
1
2
2
1
2
1
2
M
1
1
1
2
2
4
4
F
2
1
2
4
2
8
4
S
1
1
2
1
1
1
1
HD
0
N
N΄ CS
K3
1
0x01
0x40
0x41
0x0A
0x49
0x13
0x52
20 × fOUT
10 × fOUT
10 × fOUT
40 × fOUT
20 × fOUT
80 × fOUT
40 × fOUT
8 to 16 16 0 to 3
8 to 16 16 0 to 3
8 to 16 16 0 to 3
8 to 16 16 0 to 3
8 to 16 16 0 to 3
8 to 16 16 0 to 3
8 to 16 16 0 to 3
Only valid K
values that
are divisible
by 4 are
1
0
2
4
0
supported
0
0
0
1 fOUT = output sample rate = ADC sample rate/chip decimation ratio. The JESD204B serial line rate must be ≥1687.5 Mbps and ≤15,000 Mbps. When the serial line rate is
≤15 Gbps and ≥13.5 Gbps, set Bits[7:4] to 0x3 in Register 0x056E. When the serial line rate is ≤13.5 Gbps and ≥6.75 Gbps, set Bits[7:4] to 0x0 in Register 0x056E. When
the serial line rate is <6.75 Gbps and ≥3.375 Gbps, set Bits[7:4] to 0x1 in Register 0x056E. When the serial line rate is ≤3.375 Gbps and ≥1687.5 Mbps, set Bits[7:4] to 0x5
in Register 0x056E.
2 JESD204B transport layer descriptions are as described in the JESD204B Overview section.
3 For F = 1, K = 20, 24, 28, and 32. For F = 2, K = 12, 16, 20, 24, 28, and 32. For F = 4, K = 8, 12, 16, 20, 24, 28, and 32. For F = 8 and F = 16, K = 4, 8, 12, 16, 20, 24, 28, and 32.
Table 35. JESD204B Output Configurations for N΄= 8
Number of Virtual
JESD204B Quick
JESD204B Transport Layer Settings2
Converters Supported Configuration
(Same Value as M)
(Register 0x0570) Serial Line Rate1
L
1
1
2
2
2
1
2
2
M
1
1
1
1
1
2
2
2
F
1
2
1
2
4
2
1
2
S
1
2
2
4
8
1
1
2
HD
0
0
N
N΄
8
8
CS
0 to 1 Only valid K
K3
1
0x00
0x01
0x40
0x41
0x42
0x09
0x48
0x49
10 × fOUT
10 × fOUT
5 × fOUT
7 to 8
7 to 8
7 to 8
7 to 8
7 to 8
7 to 8
7 to 8
7 to 8
values which
are divisible
by 4 are
0 to 1
0 to 1
0 to 1
0 to 1
0 to 1
0 to 1
0 to 1
0
8
5 × fOUT
0
8
supported
5 × fOUT
0
8
2
20 × fOUT
10 × fOUT
10 × fOUT
0
8
0
8
0
8
1 fOUT = output sample rate = ADC sample rate/chip decimation ratio. The JESD204B serial line rate must be ≥1687.5 Mbps and ≤15,000 Mbps. When the serial line rate is
≤15 Gbps and ≥13.5 Gbps, set Bits[7:4] to 0x3 in Register 0x056E. When the serial line rate is ≤13.5 Gbps and ≥6.75 Gbps, set Bits[7:4] to 0x0 in Register 0x056E. When
the serial line rate is <6.75 Gbps and ≥3.375 Gbps, set Bits[7:4] to 0x1 in Register 0x056E. When the serial line rate is ≤3.375 Gbps and ≥1687.5 Mbps, set Bits[7:4] to 0x5
in Register 0x056E.
2 JESD204B transport layer descriptions are as described in the JESD204B Overview section.
3 For F = 1, K = 20, 24, 28, and 32. For F = 2, K = 12, 16, 20, 24, 28, and 32. For F = 4, K = 8, 12, 16, 20, 24, 28, and 32. For F = 8 and F = 16, K = 4, 8, 12, 16, 20, 24, 28, and 32.
Rev. 0 | Page 61 of 107
AD6684
Data Sheet
Example 1: ADC with DDC Option (Two ADCs Plus Two
DDCs in Each Pair)
N = 16 bits
L = 1, M = 4, and F = 8 (quick configuration = 0x13)
CS = 0 to 1
K = 32
Output serial line rate = 5 Gbps per lane (L = 1) or
2.5 Gbps per lane (L = 2)
The chip application mode is DDC mode (seeFigure 99) with
the following characteristics:
Chip application mode = two DDC mode (see Figure 99)
Two 14-bit converters at 500 MSPS
Two DDC application layer mode with complex outputs (I/Q)
Chip decimation ratio = 4
For L = 1, set Bits[7:4] to 0x1 in Register 0x056E. For L = 2, set
Bits[7:4] to 0x5 in Register 0x056E.
DDC decimation ratio = 4 (see Table 33)
Example 1 shows the flexibility in the digital and lane
configurations for the AD6684. The sample rate is 500 MSPS,
but the outputs are all combined in either one or two lanes,
depending on the I/O speed capability of the receiving device.
The JESD204B output configuration is as follows:
Virtual converters required = 4 (see Table 33)
Output sample rate (fOUT) = 500/4 = 125 MSPS
N΄ = 16 bits
DDC 0
REAL/I
I
REAL/I
CONVERTER 0
NCO
+
ADC
SAMPLING
AT fS
REAL/I
REAL/Q
REAL/I
MIXER
(OPTIONAL)
REAL/Q
Q
Q CONVERTER 1
L
JESD204B
LANES
SYSREF±
I
AT UP TO
15Gbps
DDC 1
DDC 0
DDC 1
REAL/I
REAL/I
CONVERTER 2
NCO
+
ADC
SAMPLING
AT fS
MIXER
(OPTIONAL)
REAL/Q
Q
Q CONVERTER 3
SYSREF±
I
REAL/I
REAL/I
CONVERTER 0
NCO
+
ADC
SAMPLING
AT fS
MIXER
(OPTIONAL)
REAL/Q
Q
Q CONVERTER 1
L
JESD204B
LANES
SYSREF±
I
AT UP TO
15Gbps
REAL/I
REAL/I
CONVERTER 2
NCO
+
ADC
SAMPLING
AT fS
REAL/Q
MIXER
(OPTIONAL)
REAL/Q
Q
Q CONVERTER 3
SYSREF±
SYSREF
SYNCHRONIZATION
CONTROL CIRCUITS
Figure 99. Two ADC + Four DDC Mode in Each Pair
Rev. 0 | Page 62 of 107
Data Sheet
AD6684
The JESD204B output configuration is as follows:
Example 2: ADC with NSR Option (Two ADCs + NSR in
Each Pair)
Virtual converters required = 2 (see Table 33).
Output sample rate (fOUT) = 500 MSPS
N΄ = 16 bits
The chip application mode is NSR mode (see Figure 100) with
the following characteristics:
Two 14-bit converters at 500 MSPS
NSR blocks enabled for each channel
Chip decimation ratio = 1
N = 9 bits
L = 2, M = 2, and F = 2 (quick configuration = 0x49)
CS = 0 to 2
K = 32
Output serial lane rate = 10 Gbps per lane (L = 2)
Set Bits[7:4] to 0x0 in Register 0x056E
NSR
(21% OR 28%
BANDWIDTH)
14-BIT ADC
CORE
AT 500MSPS
CONVERTER 0
AT 500MSPS
REAL
REAL
REAL
JESD204B
1 OR 2 LANES
TRANSMIT
INTERFACE
(JTX)
AT UP TO 15Gbps
NSR
(21% OR 28%
BANDWIDTH)
CONVERTER 1
AT 500MSPS
14-BIT ADC
CORE
AT 500MSPS
NSR
(21% OR 28%
BANDWIDTH)
14-BIT ADC
CORE
AT 500MSPS
CONVERTER 0
AT 500MSPS
JESD204B
TRANSMIT
INTERFACE
(JTX)
1 OR 2 LANES
AT UP TO 15Gbps
NSR
(21% OR 28%
BANDWIDTH)
14-BIT ADC
CORE
CONVERTER 1
AT 500MSPS
REAL
AT 500MSPS
Figure 100. Two ADC + NSR Mode
Rev. 0 | Page 63 of 107
AD6684
Data Sheet
LATENCY
latency must be calculated based on the DSP options selected
and the JESD204B configuration.
END-TO-END TOTAL LATENCY
Total latency in the AD6684 is dependent on the various digital
signal processing (DSP) and JESD204B configuration modes.
Latency is fixed at 28 encode clocks through the ADC itself, but
the latency through the DSP and JESD204B blocks can vary
greatly, depending on the configuration. Therefore, the total
Table 36 shows the combined latency through the ADC, DSP,
and JESD204B blocks for some of the different application
modes supported by the AD6684. Latency is in units of the
encode clock.
Table 36. Latency Through the AD6684
JESD204B Transport Layer Settings
Latency (Number of Encode Clocks)
ADC Application Mode
Full Bandwidth (9-Bit)
DDC (HB1)1
DDC (HB2 + HB1)1
DDC (HB3 +HB2 + HB1)1
DDC (HB4 + HB3 + HB2 + HB1)1
Decimate by 2 + NSR
NSR
L
2
2
1
1
1
1
2
M
2
4
4
4
4
2
2
F
2
4
8
8
8
4
2
ADC + DSP
JESD204B
Total
44
30
92
162
292
548
64
14
17
13
28
39
6
109
175
320
587
70
38
16
54
1 No mixer, complex outputs.
Rev. 0 | Page 64 of 107
Data Sheet
AD6684
MULTICHIP SYNCHRONIZATION
The AD6684 has a SYSREF input that provides flexible options
for synchronizing the internal blocks. The SYSREF input is a
source synchronous system reference signal that enables multichip
synchronization. The input clock divider, DDCs, signal monitor
block, and JESD204B link can be synchronized using the SYSREF
input. For the highest level of timing accuracy, SYSREF must
meet setup and hold requirements relative to the CLK input.
The flowchart in Figure 101 describes the internal mechanism
for multichip synchronization in the AD6684. The AD6684
supports several features that aid users in meeting the requirements
set out for capturing a SYSREF signal. The SYSREF sample
event can be defined as either a synchronous low to high transition,
or a synchronous high to low transition. Additionally, the AD6684
allows the SYSREF signal to be sampled using either the rising
edge or falling edge of the CLK input. The AD6684 also has the
ability to ignore a programmable number (up to 16) of SYSREF
events. The SYSREF control options can be selected using
Register 0x0120 and Register 0x0121.
Rev. 0 | Page 65 of 107
AD6684
Data Sheet
START
INCREMENT
SYSREF± IGNORE
COUNTER
NO
NO
NO
SYSREF±
IGNORE
COUNTER
EXPIRED?
(0x0121)
UPDATE
SETUP/HOLD
DETECTOR STATUS
(0x0128)
RESET
SYSREF± IGNORE
COUNTER
SYSREF±
ENABLED?
(0x0120)
NO
YES
SYSREF±
ASSERTED?
YES
YES
INPUT
CLOCK
CLOCK
DIVIDER
AUTO ADJUST
ENABLED?
(0x0108)
INCREMENT
SYSREF±
COUNTER
(0x012A)
CLOCK
DIVIDER
> 1?
ALIGN CLOCK
DIVIDER
PHASE TO
SYSREF
YES
YES
YES
DIVIDER
ALIGNMENT
REQUIRED?
(0x010B)
NO
NO
NO
TIMESTAMP
MODE
SYSREF±
TIMESTAMP
DELAY
SYSREF±
SYSREF±
YES
CONTROL BITS?
(0x0559, 0x055A,
0x058F)
INSERTED
IN JESD204B
CONTROL BITS
SYNCHRONIZATION
MODE?
(0x0123)
(0x01FF)
NO
RAMP
TEST
SYSREF± RESETS
RAMP TEST
MODE
YES
MODE
NORMAL
MODE
BACK TO START
ENABLED?
(0x0550)
GENERATOR
NO
ALIGN PHASE
JESD204B
LMFC
ALIGNMENT
REQUIRED?
SEND INVALID
NORMAL
OF ALL
YES
YES
SYNC~
ASSERTED
8-BIT/10-BIT
CHARACTERS
(ALL ZEROS)
SEND K28.5
CHARACTERS
JESD204B
INTERNAL CLOCKS
(INCLUDING LMFC)
TO SYSREF±
INITIALIZATION
NO
NO
SIGNAL
MONITOR
ALIGNMENT
ENABLED?
(0x026F)
DDC NCO
ALIGN DDC
NCO PHASE
ACCUMULATOR
ALIGN SIGNAL
YES
YES
ALIGNMENT
ENABLED?
(0x0300)
MONITOR
BACK TO START
COUNTERS
NO
NO
Figure 101. Multichip Synchronization
Rev. 0 | Page 66 of 107
Data Sheet
AD6684
Figure 102 and Figure 103 show the setup and hold status values
for different phases of SYSREF . The setup detector returns the
status of the SYSREF signal before the CLK edge, and the
hold detector returns the status of the SYSREF signal after the
CLK edge. Register 0x0128 stores the status of SYSREF and
lets the user know if the SYSREF signal is captured by the ADC.
SYSREF SETUP/HOLD WINDOW MONITOR
To ensure a valid SYSREF signal capture, the AD6684 has a
SYSREF setup/hold window monitor. This feature allows the
system designer to determine the location of the SYSREF signals
relative to the CLK signals by reading back the amount of
setup/hold margin on the interface through the memory map.
0xF
0xE
0xD
0xC
0xB
0xA
0x9
REG 0x0128[3:0]
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
CLK±
INPUT
SYSREF±
INPUT
VALID
FLIP FLOP
HOLD (MIN)
FLIP FLOP
SETUP (MIN)
FLIP FLOP
HOLD (MIN)
Figure 102. SYSREF Setup Detector
Rev. 0 | Page 67 of 107
AD6684
Data Sheet
0xF
0xE
0xD
0xC
0xB
0xA
0x9
REG 0x0128[7:4] 0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
CLK±
INPUT
SYSREF±
INPUT
VALID
FLIP FLOP
SETUP (MIN)
FLIP FLOP
HOLD (MIN)
FLIP FLOP
HOLD (MIN)
Figure 103. SYSREF Hold Detector
Table 37 shows the description of the contents of Register 0x0128 and how to interpret them.
Table 37. SYSREF Setup/Hold Monitor, Register 0x0128
Register 0x0128, Bits[7:4]
Hold Status
Register 0x0128, Bits[3:0]
Setup Status
Description
0x0
0x0 to 0x8
0x8
0x0 to 0x7
0x8
0x9 to 0xF
0x0
Possible setup error. The smaller this number, the smaller the setup margin.
No setup or hold error (best hold margin).
No setup or hold error (best setup and hold margin).
No setup or hold error (best setup margin).
0x8
0x9 to 0xF
0x0
0x0
0x0
Possible hold error. The larger this number, the smaller the hold margin.
Possible setup or hold error.
Rev. 0 | Page 68 of 107
Data Sheet
AD6684
TEST MODES
present, the analog signal is ignored); however, they do require
an encode clock.
ADC TEST MODES
The AD6684 has various test options that aid in the system level
implementation. The AD6684 has ADC test modes that are
available in Register 0x0550. These test modes are described in
Table 38. When an output test mode is enabled, the analog section
of the ADC is disconnected from the digital back-end blocks,
and the test pattern is run through the output formatting block.
Some of the test patterns are subject to output formatting, and
some are not. The PN generators from the PN sequence tests
can be reset by setting Bit 4 or Bit 5 of Register 0x0550. These
tests can be performed with or without an analog signal (if
If the application mode is set to select a DDC mode of
operation, the test modes must be enabled for each DDC
enabled. The test patterns can be enabled via Bit 2 and Bit 0 of
Register 0x0327, Register 0x0347, depending on which DDC(s)
are selected. The (I) data uses the test patterns selected for
Channel A, and the (Q) data uses the test patterns selected for
Channel B. For more information, see the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI.
Table 38. ADC Test Modes
Output Test Mode
Bit Sequence
Default/
Seed Value
Pattern Name
Off (default)
Midscale short
+Full-scale short
−Full-scale short
Checkerboard
Expression
Sample (N, N + 1, N + 2, …)
0000
0001
0010
0011
0100
0101
0110
Not applicable
00 0000 0000 0000
01 1111 1111 1111
10 0000 0000 0000
10 1010 1010 1010
x23 + x18 + 1
Not applicable Not applicable
Not applicable Not applicable
Not applicable Not applicable
Not applicable Not applicable
Not applicable 0x1555, 0x2AAA, 0x1555, 0x2AAA, 0x1555
0x3AFF
0x0092
PN sequence long
PN sequence short
0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6
0x125B, 0x3C9A, 0x2660, 0x0c65, 0x0697
x9 + x5 + 1
0111
One word/zero word
toggle
11 1111 1111 1111
Not applicable 0x0000, 0x3FFF, 0x0000, 0x3FFF, 0x0000
1000
1111
User input
Register 0x0551 to
Register 0x0558
Not applicable User Pattern 1[15:2], User Pattern 2[15:2],
User Pattern 3[15:2], User Pattern 4[15:2],
User Pattern 1[15:2] … for repeat mode
User Pattern 1[15:2], User Pattern 2[15:2],
User Pattern 3[15:2], User Pattern 4[15:2],
0x0000 … for single mode
Ramp output
(x) % 214
Not applicable (x) % 214, (x +1) % 214, (x +2) % 214, (x +3) % 214
Rev. 0 | Page 69 of 107
AD6684
Data Sheet
These tests indicated by the value of Register 0x0571, Bit 5. The
test pattern is equivalent to the raw samples from the ADC.
JESD204B BLOCK TEST MODES
In addition to the ADC pipeline test modes, the AD6684 also
has flexible test modes in the JESD204B block. These test modes
are listed in Register 0x0573 and Register 0x0574. These test
patterns can be injected at various points along the output data-
path. These test injection points are shown in Figure 89. Table 39
describes the various test modes available in the JESD204B
block. For the AD6684, a transition from test modes
(Register 0x0573 ≠ 0x00) to normal mode (Register 0x0573 =
0x00) requires an SPI soft reset. This is done by writing 0x81 to
Register 0x0000 (self cleared).
Interface Test Modes
The interface test modes are described in Register 0x0573, Bits[3:0].
These test modes are also explained in Table 39. The interface tests
can be injected at various points along the data. See Figure 89
for more information on the test injection points. Register 0x0573,
Bits[5:4] show where these tests are injected.
Table 40, Table 41, and Table 42 show examples of some of the
test modes when injected at the JESD204B sample input, PHY
10-bit input, and scrambler 8-bit input. In Table 40, Table 41,
and Table 42, UPx represent the user pattern control bits from
the customer register map.
Transport Layer Sample Test Mode
The transport layer samples are implemented in the AD6684 as
defined by Section 5.1.6.3 in the JEDEC JESD204B specification.
Table 39. JESD204B Interface Test Modes
Output Test Mode
Bit Sequence
Pattern Name
Expression
Default
0000
Off (default)
Not applicable
Not applicable
0001
0010
0011
0100
0101
0110
0111
1000
Alternating checkerboard
1/0 word toggle
0x5555, 0xAAAA, 0x5555, …
0x0000, 0xFFFF, 0x0000, …
x31 + x28 + 1
Not applicable
Not applicable
0x0003AFFF
0x003AFF
0x03AF
0x092
0x07
Ramp size depends on test injection point
User Pattern 1 to User Pattern 4, then repeat
User Pattern 1 to User Pattern 4, then zeros
31-bit PN sequence
23-bit PN sequence
15-bit PN sequence
9-bit PN sequence
7-bit PN sequence
Ramp output
x23 + x18 + 1
x15 + x14 + 1
x9 + x5 + 1
x7 + x6 + 1
(x) % 216
1110
1111
Continuous/repeat user test
Single user test
Register 0x0551 to Register 0x0558
Register 0x0551 to Register 0x0558
Table 40. JESD204B Sample Input for M = 2, S = 2, N' = 16 (Register 0x0573, Bits[5:4] = 'b00)
Frame
Number
Converter
Number
Sample
Number
Alternating
Checkerboard
1/0 Word
Toggle
9-Bit
PN
23-Bit
PN
Ramp
User Repeat
UP1[15:0]
UP1[15:0]
UP1[15:0]
UP1[15:0]
UP2[15:0]
UP2[15:0]
UP2[15:0]
UP2[15:0]
UP3[15:0]
UP3[15:0]
UP3[15:0]
UP3[15:0]
User Single
UP1[15:0]
UP1[15:0]
UP1[15:0]
UP1[15:0]
UP2[15:0]
UP2[15:0]
UP2[15:0]
UP2[15:0]
UP3[15:0]
UP3[15:0]
UP3[15:0]
UP3[15:0]
UP4[15:0]
UP4[15:0]
UP4[15:0]
UP4[15:0]
0x0000
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0x5555
0x5555
0x5555
0x5555
0xAAAA
0xAAAA
0xAAAA
0xAAAA
0x5555
0x5555
0x5555
0x5555
0xAAAA
0xAAAA
0xAAAA
0xAAAA
0x5555
0x5555
0x5555
0x5555
0x0000
0x0000
0x0000
0x0000
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0x0000
0x0000
0x0000
0x0000
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0x0000
0x0000
0x0000
0x0000
(x) % 216
0x496F
0x496F
0x496F
0x496F
0xC9A9 0x0029
0xC9A9 0x0029
0xC9A9 0x0029
0xC9A9 0x0029
0x980C
0x980C
0x980C
0x980C
0x651A
0x651A
0x651A
0x651A
0x5FD1
0x5FD1
0x5FD1
0x5FD1
0xFF5C
0xFF5C
0xFF5C
0xFF5C
(x) % 216
(x) % 216
(x) % 216
(x +1) % 216
(x +1) % 216
(x +1) % 216
(x +1) % 216
(x +2) % 216
(x +2) % 216
(x +2) % 216
(x +2) % 216
(x +3) % 216
(x +3) % 216
(x +3) % 216
(x +3) % 216
(x +4) % 216
(x +4) % 216
(x +4) % 216
(x +4) % 216
0xB80A
0xB80A
0xB80A
0xB80A
0x3D72 UP4[15:0]
0x3D72 UP4[15:0]
0x3D72 UP4[15:0]
0x3D72 UP4[15:0]
0x9B26
0x9B26
0x9B26
0x9B26
UP1[15:0]
UP1[15:0]
UP1[15:0]
UP1[15:0]
0x0000
0x0000
0x0000
Rev. 0 | Page 70 of 107
Data Sheet
AD6684
Table 41. Physical Layer 10-Bit Input (Register 0x0573, Bits[5:4] = 'b01)
10-Bit Symbol
Number
Alternating
Checkerboard
1/0 Word
Toggle
23-Bit
9-Bit PN PN
Ramp
User Repeat
UP1[15:6]
UP2[15:6]
UP3[15:6]
UP4[15:6]
UP1[15:6]
UP2[15:6]
UP3[15:6]
UP4[15:6]
UP1[15:6]
UP2[15:6]
UP3[15:6]
UP4[15:6]
User Single
0
1
2
3
4
5
6
7
8
9
10
11
0x155
0x2AA
0x155
0x2AA
0x155
0x2AA
0x155
0x2AA
0x155
0x2AA
0x155
0x2AA
0x000
0x3FF
0x000
0x3FF
0x000
0x3FF
0x000
0x3FF
0x000
0x3FF
0x000
0x3FF
(x) % 210
0x125
0x2FC
0x26A
0x198
0x031
0x251
0x297
0x3D1
0x18E
0x2CB
0x0F1
0x3DD
0x3FD
0x1C0
0x00A
0x1B8
0x028
0x3D7
0x0A6
0x326
0x10F
0x3FD
0x31E
0x008
UP1[15:6]
UP2[15:6]
UP3[15:6]
UP4[15:6]
0x000
0x000
0x000
0x000
0x000
(x + 1) % 210
(x + 2) % 210
(x + 3) % 210
(x + 4) % 210
(x + 5) % 210
(x + 6) % 210
(x + 7) % 210
(x + 8) % 210
(x + 9) % 210
(x + 10) % 210
(x + 11) % 210
0x000
0x000
0x000
Table 42. Scrambler 8-Bit Input (Register 0x0573, Bits[5:4] = 'b10)
8-Bit Octet
Number
Alternating
Checkerboard
1/0 Word
Toggle
9-Bit
PN
23-Bit
PN
Ramp
User Repeat
UP1[15:9]
UP2[15:9]
UP3[15:9]
UP4[15:9]
UP1[15:9]
UP2[15:9]
UP3[15:9]
UP4[15:9]
UP1[15:9]
UP2[15:9]
UP3[15:9]
UP4[15:9]
User Single
UP1[15:9]
UP2[15:9]
UP3[15:9]
UP4[15:9]
0x00
0x00
0x00
0x00
0x00
0
1
2
3
4
5
6
7
8
9
10
11
0x55
0xAA
0x55
0xAA
0x55
0xAA
0x55
0xAA
0x55
0xAA
0x55
0xAA
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
(x) % 28
0x49
0x6F
0xC9
0xA9
0x98
0x0C
0x65
0x1A
0x5F
0xD1
0x63
0xAC
0xFF
0x5C
0x00
0x29
0xB8
0x0A
0x3D
0x72
0x9B
0x26
0x43
0xFF
(x + 1) % 28
(x + 2) % 28
(x + 3) % 28
(x + 4) % 28
(x + 5) % 28
(x + 6) % 28
(x + 7) % 28
(x + 8) % 28
(x + 9) % 28
(x + 10) % 28
(x + 11) % 28
0x00
0x00
0x00
Data Link Layer Test Modes
patterns inserted at this point are useful for verifying the
functionality of the data link layer. When the data link layer test
modes are enabled, disable SYNCINB AB/SYNCINB CD by
writing 0xC0 to Register 0x0572.
The data link layer test modes are implemented in the AD6684 as
defined by Section 5.3.3.8.2 in the JEDEC JESD204B specification.
These tests are shown in Register 0x0574, Bits[2:0]. Test
Rev. 0 | Page 71 of 107
AD6684
Data Sheet
SERIAL PORT INTERFACE
The AD6684 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space provided inside the ADC. The SPI gives the user added
flexibility and customization, depending on the application.
Addresses are accessed via the serial port and can be written to
or read from the port. Memory is organized into bytes that can
be further divided into fields. These fields are documented in
the Memory Map section. For detailed operational information,
see the Serial Control Interface Standard (Rev. 1.0).
command is issued. This bit allows the SDIO pin to change
direction from an input to an output.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a
readback operation, performing a readback causes the SDIO pin
to change direction from an input to an output at the appropriate
point in the serial frame.
CONFIGURATION USING THE SPI
Data can be sent in MSB first mode or in LSB first mode. MSB
first mode is the default on power-up and can be changed via
the SPI port configuration register. For more information about
this and other features, see the Serial Control Interface Standard
(Rev. 1.0).
Three pins define the SPI of this ADC: the SCLK pin, the SDIO
pin, and the CSB pin (see Table 43). The SCLK (serial clock) pin
is used to synchronize the read and write data presented from
and to the ADC. The SDIO (serial data input/output) pin is a
dual-purpose pin that allows data to be sent and read from the
internal ADC memory map registers. The CSB (chip select bar)
pin is an active low control that enables or disables the read and
write cycles.
HARDWARE INTERFACE
The pins described in Table 43 comprise the physical interface
between the user programming device and the serial port of the
AD6684. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
Table 43. Serial Port Interface Pins
Pin
Function
SCLK Serial clock. The serial shift clock input, which is used to
synchronize serial interface reads and writes.
SDIO Serial data input/output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note,
Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
CSB
Chip select bar. An active low control that gates the read
and write cycles.
Do not activate the SPI port during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used
for other devices, it may be necessary to provide buffers between
this bus and the AD6684 to prevent these signals from
transitioning at the converter inputs during critical sampling
periods.
The falling edge of CSB, in conjunction with the rising edge of
SCLK, determines the start of the framing. An example of the
serial timing and its definitions can be found in Figure 4 and
Table 5.
Other modes involving the CSB pin are available. The CSB pin
can be held low indefinitely, which permanently enables the
device; this is called streaming. The CSB can stall high between
bytes to allow for additional external timing. When CSB is tied
high, SPI functions are placed in a high impedance mode. This
mode turns on the secondary functions of the SPI pin.
SPI ACCESSIBLE FEATURES
Table 44 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the Serial Control Interface Standard (Rev. 1.0). The AD6684
device specific features are described in the Memory Map section.
All data is composed of 8-bit words. The first bit of each
individual byte of serial data indicates whether a read or write
Table 44. Features Accessible Using the SPI
Feature Name
Description
Mode
Clock
Allows the user to set either power-down mode or standby mode.
Allows the user to access the clock divider via the SPI.
DDC
Allows the user to set up decimation filters for different applications.
Allows the user to set test modes to have known data on output bits.
Allows the user to set up outputs.
Test Input/Output
Output Mode
SERDES Output Setup
Allows the user to vary SERDES settings such as swing and emphasis.
Rev. 0 | Page 72 of 107
Data Sheet
AD6684
MEMORY MAP
Channel-Specific Registers
READING THE MEMORY MAP REGISTER TABLE
Some channel setup functions, such as the fast detect control
(Register 0x0247), can be programmed to a different value for
each channel. In these cases, channel address locations are
internally duplicated for each channel. These registers and bits
are designated in Table 45 as local. These local registers and bits can
be accessed by setting the appropriate Channel A/Channel C or
Channel B/Channel D bits in Register 0x0008. The particular
channel that is addressed is dependent upon the pair selection
written to Register 0x0009. If both bits are set, the subsequent
write affects the registers of both channels. In a read cycle, set
only Channel A/Channel C or Channel B/Channel D to read
one of the two registers. If both bits are set during an SPI read
cycle, the device returns the value for Channel A. If both pairs
and both channels have been selected via Register 0x0009 and
Register 0x0008, then the device returns the value for Channel A.
Each row in the memory map register table has eight bit locations.
The memory map is divided into four sections: the Analog
Devices SPI registers (Register 0x0000 to Register 0x000D and
Register 0x18A6 to Register 0x1A4D), the ADC function registers
(Register 0x003F to Register 0x027A), the DDC, NSR, and VDR
function registers (Register 0x0300 to Register 0x0434), and
the digital outputs and test modes registers (Register 0x0550 to
Register 0x05C6).
Table 45 documents the default hexadecimal value for each
hexadecimal address shown. The column with the heading Bit 7
(MSB) is the start of the default hexadecimal value given. For
example, Address 0x0561, the output mode register, has a
hexadecimal default value of 0x01. This means that Bit 0 = 1,
and the remaining bits are 0s. This setting is the default output
format value, which is twos complement. For more information
on this function and others, see Table 45 and Table 46.
The names of the registers listed in Table 45 and Table 46 are
prefixed with either global map, channel map, JESD204B map,
or pair map. Registers in the pair map and JESD204B map apply
to a pair of channels, either Pair A/B or Pair C/D. To write registers
in the pair map and the JESD204B map, the pair index register
(Register 0x0009) must be written to address the appropriate
pair. The SPI Configuration A (Register 0x0000), SPI Config-
uration B (Register 0x0001), and pair index (Register 0x0009)
registers are the only registers that reside in the global map.
Registers in the channel map are local to each channel, either
Channel A, Channel B, Channel C, or Channel D. To write registers
in the channel map, the pair index register (Register 0x0009) must
be written first to address the desired pair (Pair A/B or Pair C/D),
followed by writing the channel index register (Register 0x0008)
to select the desired channel (Channel A/Channel C or Channel B/
Channel D). For example, to write Channel A to a test mode (set by
Register 0x0550), first write a value of 0x01 to Register 0x0009 to
select Pair A/B, followed by writing 0x01 to Register 0x0008 to
select Channel A. Then, write Register 0x0550 to the value for
the desired test mode. To write all channels to a test mode (set
by Register 0x0550), first write Register 0x0009 to a value of
0x03 to select both Pair A/B and Pair C/D, followed by writing
Register 0x0008 to a value of 0x03 to select Channel A, Channel B,
Channel C, and Channel D. Next, write Register 0x0550 to the
value for the desired test mode.
Open and Reserved Locations
All address and bit locations that are not included in Table 45
are not currently supported for this device. Write unused bits of
a valid address location with 0s unless the default value is set
otherwise. Writing to these locations is required only when part
of an address location is unassigned (for example, Address 0x0561).
If the entire address location is open (for example,
Address 0x0013), do not write to this address location.
Default Values
After the AD6684 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table, Table 45.
Logic Levels
An explanation of logic level terminology follows:
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
X denotes a don’t care bit.
ADC Pair Addressing
The AD6684 functionally operates as two pairs of dual IF
receiver channels. There are two ADCs, two NSR processing
blocks, two VDR processing blocks, and two DDCs in each pair,
resulting in a total of four of each for the AD6684. To access the
SPI registers for each pair, the pair index must be written in
Register 0x0009. The pair index regist must be written prior to
any other SPI write to the AD6684.
SPI Soft Reset
After issuing a soft reset by programming 0x81 to
Register 0x0000, the AD6684 requires 5 ms to recover. When
programming the AD6684 for application setup, ensure that an
adequate delay is programmed into the firmware after asserting
the soft reset and before starting the device setup.
Rev. 0 | Page 73 of 107
AD6684
Data Sheet
MEMORY MAP
MEMORY MAP SUMMARY
All address locations that are not included in Table 45 are not currently supported for this device and must not be written.
Table 45. Memory Map Summary
Reg.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
R/W
0x0000 Global Map
SPI
Soft reset
(self
LSB first Address
Reserved
Address
ascension
LSB first
Soft
reset
(self
0x00
R/W
mirror
ascension
mirror
Configuratio clearing)
n A
clearing)
0x0001 Global Map
Single
instruction
Reserved
Datapath
soft reset
(self
Reserved 0x00
R/W
R/W
SPI Config-
uration B
clearing)
0x0002 Channel map
chip config-
Reserved
Channel power modes 0x00
uration
0x0003 Pair map
chip type
CHIP_TYPE
0x03
0xDC
0x00
R
0x0004 Pair map
chip ID LSB
CHIP_ID[7:0]
R
0x0006 Pair map
chip grade
CHIP_SPEED_GRADE
Reserved
R
0x0008 Pair map
device index
Reserved
Reserved
Channel B/ Channel 0x03
Channel D A/Chan-
nel C
R/W
0x0009 Global map
pair index
Pair C/D
Pair A/B 0x03
R/W
R/W
R
0x000A Pair map
scratch pad
Scratch pad
0x07
0x000B Pair map SPI
revision
SPI_REVISION
0x01
0x000C Pair map
vendor ID
LSB
CHIP_VENDOR_ID[7:0]
CHIP_VENDOR_ID[15:8]
Reserved
0x56
R
0x000D Pair map
vendor ID
0x04
0x00
R
MSB
0x003F Channel map PDWN/
chip power- STBY
R/W
R/W
R/W
R/W
R/W
down pin
disable
0x0040 Pair Map
Chip Pin
PDWN/STBY function
Fast Detect B/Fast Detect D (FD_B/FD_D)
Reserved
Fast Detect A/Fast Detect C (FD_A/FD_C) 0x3F
Control 1
0x0108 Pair map
clock divider
control
Clock divider
0x01
0x00
0x0109 Channel map
clock divider
Reserved
Clock divider phase offset
phase
0x010A Pair map
Clock
Reserved
Reserved
Clock divider negative skew
window
Clock divider positive 0x00
skew window
clock divider divider auto
SYSREF
control
phase
adjust
0x0110 Pair map
clock delay
Clock delay mode select
0x00
0x00
0xC0
R/W
R/W
R/W
control
0x0111 Channel map
clock super
Clock super fine delay adjust
fine delay
0x0112 Channel map
clock fine
Clock fine delay adjust
Rev. 0 | Page 74 of 107
delay
Data Sheet
AD6684
Reg.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reserved
Reset
R/W
0x011A Clock
Reserved
Clock detection threshold
Clock detection
enable
0x00
R/W
detection
control
0x011B Pair map
clock status
Reserved
Input
clock
detect
0x00
0x00
R
0x011C Clock DCS
control
Reserved
Clock DCS
enable
Clock
DCS
R/W
power-
up
0x0120 Pair Map
SYSREF
Reserved
Reserved
SYSREF Reserved
flag
reset
SYSREF transition
select
CLK
edge
select
SYSREF mode select
Reserved 0x00
R/W
R/W
R/W
R
Control 1
0x0121 Pair Map
SYSREF
Reserved
SYSREF N shot ignore counter select 0x00
Control 2
0x0123 Pair Map
SYSREF
SYSREF time stamp delay[6:0]
0x40
Control 4
0x0128 Pair Map
SYSREF
SYSREF hold status[7:4]
Reserved
SYSREF setup status[3:0]
0x00
Status 1
0x0129 Pair Map
SYSREF
Clock divider phase when SYSREF is captured
0x00
0x00
R
Status 2
0x012A Pair Map
SYSREF
SYSREF counter [7:0] (increments when a SYSREF input is captured)
R
Status 3
0x01FF Pair map
chip sync
Reserved
Synchro- 0x00
nization
mode
R/W
0x0200 Pair map
chip mode
Reserved
Chip Q
ignore
Reserved
Reserved
Chip application mode
Chip decimation ratio select
0x07
R/W
R/W
0x0201 Pair map
chip decim-
0x00
0x00
0x00
ation ratio
0x0228 Channel map
custom
Offset adjust in LSBs from +127 to −128
Force
R/W
R/W
offset
0x0245 Channel map
fast detect
Reserved
Force value of
FD_A/FD_B/
Reserved
Enable
fast
FD_A/
FD_B/
FD_C/
control
FD_C/FD_D pins;
if force pins is
detect
output
FD_D pins true, this value is
output on the
FD_x pins
0x0247 Channel map
fast detect
upper
Fast detect upper threshold[7:0]
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
threshold
LSB
0x0248 Channel map
fast detect
upper
Reserved
Fast detect upper threshold[12:8]
threshold
MSB
0x0249 Channel map
fast detect
lower
Fast detect lower threshold[7:0]
threshold
LSB
0x024A Channel map
fast detect
lower
Reserved
Fast detect lower threshold[12:8]
threshold
MSB
Rev. 0 | Page 75 of 107
AD6684
Data Sheet
Reg.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
R/W
0x024B Channel map
fast detect
Fast detect dwell time[7:0]
0x00
R/W
dwell time
LSB
0x024C Channel map
fast detect
Fast detect dwell time[15:8]
Reserved
0x00
0x00
R/W
R/W
dwell time
MSB
0x026F Pair map
signal
Signal
monitor
synchro-
nization
mode
monitor sync
control
0x0270 Channel map
signal
Reserved
Peak
detector
Reserved 0x00
R/W
R/W
R/W
R/W
R/W
monitor
control
0x0271 Channel Map
Signal
Signal monitor period[7:0]
Signal monitor period[15:8]
Signal monitor period[23:16]
0x80
Monitor
Period 0
0x0272 Channel Map
Signal
0x00
Monitor
Period 1
0x0273 Channel Map
Signal
0x00
Monitor
Period 2
0x0274 Channel map
Reserved
Result update
Reserved
Result selection
0x01
signal
monitor
status
control
0x0275 Channel Map
Signal
Signal monitor result[7:0]
Signal monitor result[15:8]
0x00
0x00
0x00
0x00
R
R
R
R
Monitor
Status 0
0x0276 Channel Map
Signal
Monitor
Status 1
0x0277 Channel Map
Signal
Reserved
Signal monitor result[19:16]
Monitor
Status 2
0x0278 Channel map
signal
Period count result, Bits[7:0]
Reserved
monitor
status frame
counter
0x0279 Channel map
signal
Signal
0x00
0x02
0x00
R/W
R/W
R/W
monitor
SPORT
over JES-
D204B
enable
monitor
serial framer
control
0x027A Channel map
signal
Reserved
Signal monitor SPORT over JESD204B peak detector enable
monitor
serial framer
input
selection
0x0300 Pair map
DDC sync
Reserved
DDC NCO soft reset
Reserved
DDC next
sync
DDC
synchro-
nization
mode
control
Rev. 0 | Page 76 of 107
Data Sheet
AD6684
Reg.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
R/W
0x0310 Pair map
DDC 0
DDC 0
mixer select gain
select
DDC 0
DDC 0 IF mode
DDC 0
complex
to real
Reserved
DDC 0 decimation rate 0x00
select
R/W
control
enable
0x0311 Pair Map
Reserved
DDC 0 Q input
select
Reserved
DDC 0
I input
select
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DDC 0 input
select
0x0314 Pair Map
DDC 0 NCO frequency value, twos complement[7:0]
DDC 0 NCO frequency value, twos complement[15:8]
DDC 0 NCO frequency value, twos complement[23:16]
DDC 0 NCO frequency value, twos complement[31:24]
DDC 0 NCO frequency value, twos complement[39:32]
DDC 0 NCO frequency value, twos complement[47:40]
DDC 0 NCO phase value, twos complement[7:0]
DDC 0 NCO phase value, twos complement[15:8]
DDC 0 NCO phase value, twos complement[23:16]
DDC 0 NCO phase value, twos complement[31:24]
DDC 0 NCO phase value, twos complement[39:32]
DDC 0 NCO phase value, twos complement[47:40]
DDC 0 Phase
Increment 0
0x0315 Pair Map
DDC 0 Phase
Increment 1
0x0316 Pair Map
DDC 0 Phase
Increment 2
0x0317 Pair Map
DDC 0 Phase
Increment 3
0x0318 Pair Map
DDC 0 Phase
Increment 4
0x031A Pair Map
DDC 0 Phase
Increment 5
0x031D Pair Map
DDC 0 Phase
Offset 0
0x031E Pair Map
DDC 0 Phase
Offset 1
0x031F Pair Map
DDC 0 Phase
Offset 2
0x0320 Pair Map
DDC 0 Phase
Offset 3
0x0321 Pair Map
DDC 0 Phase
Offset 4
0x0322 Pair Map
DDC 0 Phase
Offset 5
0x0327 Pair map
Reserved
DDC 0 Q output
test mode enable
Reserved
DDC 0 I
output
test
DDC 0 test
enable
mode
enable
0x0330 Pair map
DDC 1
DDC 1
mixer select gain
select
DDC 1
DDC 1 IF mode
DDC 1
complex
to real
Reserved
DDC 1 decimation rate 0x00
select
R/W
control
enable
0x0331 Pair map
DDC 1 input
select
Reserved
DDC 1 Q input
select
Reserved
DDC 1 I
input
select
0x05
0x00
0x00
0x00
R/W
R/W
R/W
R/W
0x0334 Pair Map
DDC 1 Phase
DDC 1 NCO frequency value, twos complement[7:0]
DDC 1 NCO frequency value, twos complement[15:8]
DDC 1 NCO frequency value, twos complement[23:16]
Increment 0
0x0335 Pair Map
DDC 1 Phase
Increment 1
0x0336 Pair Map
DDC 1 Phase
Increment 2
Rev. 0 | Page 77 of 107
AD6684
Data Sheet
Reg.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
R/W
0x0337 Pair Map
DDC 1 NCO frequency value, twos complement[31:24]
DDC 1 NCO frequency value, twos complement[39:32]
DDC 1 NCO frequency value, twos complement[47:40]
DDC 1 NCO phase value, twos complement[7:0]
DDC 1 NCO phase value, twos complement[15:8]
DDC 1 NCO phase value, twos complement[23:16]
DDC 1 NCO phase value, twos complement[31:24]
DDC 1 NCO phase value, twos complement[39:32]
DDC 1 NCO phase value, twos complement[47:40]
0x00
R/W
DDC 1 Phase
Increment 3
0x0338 Pair Map
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DDC 1 Phase
Increment 4
0x033A Pair Map
DDC 1 Phase
Increment 5
0x033D Pair Map
DDC 1 Phase
Offset 0
0x033E Pair Map
DDC 1 Phase
Offset 1
0x033F Pair Map
DDC 1 Phase
Offset 2
0x0340 Pair Map
DDC 1 Phase
Offset 3
0x0341 Pair Map
DDC 1 Phase
Offset 4
0x0342 Pair Map
DDC 1 Phase
Offset 5
0x0347 Pair map
Reserved
DDC 1 Q output
test mode enable
Reserved
DDC 1
I output
test
DDC 1 test
enable
mode
enable
0x041E Channel map High-pass/
Reserved
NSR dec- 0x00
imate by
2 enable
R/W
NSR dec-
imate by 2
control
low-pass
mode
0x0420 NSR mode
Reserved
NSR mode
Reserved 0x00
0x00
R/W
R/W
0x0422 Channel map
NSR tuning
Reserved
NSR tuning word
0x0430 Pair map
VDR control
Reserved
VDR
VDR
0x01
R/W
bandwidth complex
mode
enable
0x0434 Channel map
VDR tuning
Reserved
VDR center frequency
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
frequency
0x0550 Channel map User
Reser-
ved
Reset PN
sequence
Reset PN short
generation
Test mode selection
test mode
control
pattern
selection
0x0551 Pair Map
User
User Pattern 1[7:0]
User Pattern 1[15:8]
Pattern 1 LSB
0x0552 Pair Map
User
Pattern 1
MSB
0x0553 Pair Map
User
User Pattern 2[7:0]
User Pattern 2[15:8]
0x00
0x00
R/W
R/W
Pattern 2 LSB
0x0554 Pair Map
User
Pattern 2
MSB
Rev. 0 | Page 78 of 107
Data Sheet
AD6684
Reg.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
User Pattern 3[7:0]
Bit 2
Bit 1
Bit 0
Reset
R/W
0x0555 Pair Map
User
0x00
R/W
Pattern 3 LSB
0x0556 Pair Map
User Pattern
User Pattern 3[15:8]
User Pattern 4[7:0]
User Pattern 4[15:8]
0x00
0x00
0x00
R/W
R/W
R/W
3 MSB
0x0557 Pair Map
User
Pattern 4 LSB
0x0558 Pair Map
User
Pattern 4
MSB
0x0559 Pair Map
Output
Reserved
Converter control Bit 1 selection
Reserved
Converter control Bit 0 selection
Converter control Bit 2 selection
0x00
0x01
0x01
0x00
R/W
R/W
R/W
R/W
Control
Mode 0
0x055A Pair Map
Output
Reserved
Reserved
Reserved
Control
Mode 1
0x0561 Pair map
output
Sample invert
Data format select
sample
mode
0x0564 Pair map
output
Reserved
Con-
verter
channel
swap
channel
select
control
0x056E JESD204B
map PLL
JESD204B lane rate control
Reserved
0x00
0x00
0x49
R/W
R
control
0x056F JESD204B
map PLL
PLL lock
status
Reserved
status
0x0570 JESD204B
map JTX
Quick Configuration L
Quick Configuration M
Lane synchronization
Quick Configuration F
R/W
quick
configuration
0x0571 JESD204B
map JTX Link mode
Standby
Tail bit
(t) PN
Long
transport
layer test
ILAS sequence mode
FACI
Link
control
0x14
R/W
R/W
Control 1
0x0572 JESD204B
map JTX Link
Control 2
SYNCINB AB/
SYNC-
SYNCINB AB/
Reserved 8-bit/10-bit
bypass
8-bit/10-bit Reserved 0x00
invert
SYNCINB CD pin
control
INB AB/
SYNCINB CD
pin invert
SYNCINB CD pin type
0x0573 JESD204B
map JTX Link
Control 3
Checksum mode
Test injection point
JESD204B test mode patterns
0x00
0x00
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
R/W
R/W
0x0574 JESD204B
map JTX Link
Control 4
ILAS delay
Reserved
Link layer test mode
0x0578 JESD204B
map JTX
Reserved
LMFC phase offset value
LMFC offset
0x0580 JESD204B
map JTX DID
JESD204B Tx serial device identification (DID) value
configuration
0x0581 JESD204B
map JTX BID
Reserved
JESD204B Tx serial bank identification (BID) value
configuration
0x0583 JESD204B
map JTX
Reserved
Lane 0 serial lane identification (LID) value
LID 0
configuration
Rev. 0 | Page 79 of 107
AD6684
Data Sheet
Reg.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
R/W
0x0585 JESD204B
map JTX
Reserved
Lane 1 LID value
0x02
R/W
LID 1
configuration
0x058B JESD204B
map JTX
JESD204B
scrambling
(SCR)
Reserved
JESD204B lanes (L)
0x81
R/W
SCR L
configuration
0x058C JESD204B
map JTX F
Number of octets per frame (F)
0x01
0x1F
0x01
0x0F
R
configuration
0x058D JESD204B
map JTX K
Reserved
Number of frames per multiframe (K)
R/W
R
configuration
0x058E JESD204B
map JTX M
Number of converters per link
configuration
0x058F JESD204B
map JTX
Number of control bits Reserved
(CS) per sample
ADC converter resolution (N)
R/W
CS N
configuration
0x0590 JESD204B
map JTX
Subclass support
Reserved
ADC number of bits per sample (N')
0x2F
R/W
Subclass
Version NP
configuration
0x0591 JESD204B
map JTX JV S
Samples per converter frame cycle (S)
0x20
0x00
R
R
configuration
0x0592 JESD204B
map JTX
HD value
Reserved
Control words per frame clock cycle per link (CF)
HD CF
configuration
0x05A0 JESD204B
map JTX
Checksum 0 checksum value for SERDOUTAB0 /SERDOUTCD0
Checksum 1 checksum value for SERDOUTAB1 /SERDOUTCD1
0xC3
0xC4
0xFA
R
Checksum 0
configuration
0x05A1 JESD204B
map JTX
R
Checksum 1
configuration
0x05B0 JESD204B
map JTX lane
Reserved
JESD204B lane 1 Reserved
power-down
JESD-
204B
R/W
power-down
Lane 0
power-
down
0x05B2 JESD204B
map JTX
Reserved
Reserved
SERDOUTAB0 /SERDOUTCD0 lane
assignment
0x00
0x11
0x11
R/W
R/W
R/W
Lane Assign-
ment 1
0x05B3 JESD204B
map JTX
SERDOUTAB1 /SERDOUTCD1 lane
assignment
Lane Assign-
ment 2
0x05C0 JESD204B
map
Reserved
Swing voltage for SERDOUTAB1 /
SERDOUTCD1
Reserved
Swing voltage for SERDOUTAB0 /
SERDOUTCD0
JESD204B
serializer
drive adjust
0x05C4 JESD204B
serializer
preemph-
asis
Post tab
polarity
Sets post tab level
Pretab
polarty
Sets pretab level
0x0
R/W
selection
register for
Logical
Lane 0
Rev. 0 | Page 80 of 107
Data Sheet
AD6684
Reg.
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
R/W
0x05C6 JESD204B
serializer
Post tab
polarity
Sets post tab level
Pre tab
polarty
Sets pre tab level
0x0
R/W
preempha-
sis selection
register for
Logical
Lane 0
0x0922 Large dither
control
Large dither control
PLL calibration
0x70
0x0
R/W
R/W
R/W
0x1222 PLL
calibration
0x1228 JESD204B
start-up
JESD204B start-up circuit reset
0xF
circuit reset
0x1262 PLL loss of
lock control
PLL loss of lock control
Reserved
0x0
R/W
R/W
R/W
0x18A6 Pair map
VREF control
VREF
control
0x00
0x00
0x18E0 External VCM
Buffer
External VCM Buffer Control 1
Control 1
0x18E1 External VCM
Buffer
External VCM Buffer Control 1
External VCM Buffer Control 1
0x00
0x00
0x00
0x00
R/W
R/W
R/W
R/W
Control 2
0x18E2 External VCM
Buffer
Control 3
0x18E3 External
VCM buffer
control
Reserved External
External VCM buffer current setting
VCM
buffer
0x18E6 Temp-
erature
Reserved
Temp-
erature
diode
diode
export
export
0x1908 Channel map
analog input
Reserved
Analog input dc
coupling
selection
Reserved
0x00
0x0D
0x0C
0x0C
R/W
R/W
R/W
R/W
control
0x1910 Channel map
input full-
Reserved
Input full-scale control
scale range
0x1A4C Channel Map
Buffer
Reserved
Reserved
Buffer Control 1
Control 1
0x1A4D Channel Map
Buffer
Buffer Control 2
Control 2
Rev. 0 | Page 81 of 107
AD6684
Data Sheet
MEMORY MAP DETAILS
All address locations that are not included in Table 46 are not currently supported for this device and must not be written.
Table 46. Memory Map Details
Address Name
Bits Bit Name
Settings
Description
Reset Access
0x0000
Global Map
SPI Config-
uration A
7
Soft reset (self clearing)
When a soft reset is issued, the user must
wait 5 ms before writing to any other
register. This wait provides sufficient time
for the boot loader to complete.
0x0
R/W
0
1
Do nothing.
Reset the SPI and registers (self clearing).
6
5
LSB first mirror
0x0
0x0
R/W
R/W
1
0
LSB shifted first for all SPI operations.
MSB shifted first for all SPI operations.
Address ascension mirror
0
1
Multibyte SPI operations cause addresses
to auto-increment.
Multibyte SPI operations cause addresses
to auto-increment.
[4:3] Reserved
Reserved.
0x0
0x0
R
2
Address ascension
R/W
0
1
Multibyte SPI operations cause addresses
to autoincrement.
Multibyte SPI operations cause addresses
to auto increment.
1
0
LSB first
0x0
0x0
R/W
R/W
1
0
LSB shifted first for all SPI operations.
MSB shifted first for all SPI operations.
Soft reset (self clearing)
When a soft reset is issued, the user must
wait 5 ms before writing to any other
register. This wait provides sufficient time
for the boot loader to complete.
0
1
Do nothing.
Reset the SPI and registers (self clearing).
0x0001
Global Map
SPI Config-
uration B
7
Single instruction
0x0
R/W
0
1
SPI streaming enabled.
Streaming (multibyte read/write) is
disabled. Only one read or write operation
is performed, regardless of the state of the
CSB line.
[6:2] Reserved
Reserved.
0x0
0x0
R
1
Datapath soft reset (self
R/W
clearing)
0
1
Normal operation.
Datapath soft reset (self-clearing).
Reserved.
0
Reserved
0x0
0x0
0x0
R
0x0002
Channel map [7:2] Reserved
Reserved.
R
chip config-
uration
[1:0] Channel power modes
Channel power modes.
Normal mode (power up).
Standby mode. The digital datapath clocks
are disabled, the JESD204B interface is
enabled, and the outputs are enabled.
R/W
00
10
11
Power-down mode. The digital datapath
clocks are disabled, the digital datapath is
held in reset, the JESD204B interface is
disabled, and the outputs are disabled.
Rev. 0 | Page 82 of 107
Data Sheet
AD6684
Address Name
Bits Bit Name
Settings
Description
Chip type.
Reset Access
0x0003
Pair map
[7:0] CHIP_TYPE
0x3
R
chip type
0x3
High speed ADC.
Chip ID.
0x0004
0x0006
Pair map
[7:0] CHIP_ID
0xDC
0x0
R
R
chip ID LSB
Pair map
chip grade
[7:4] CHIP_SPEED_GRADE
Chip speed grade.
500 MHz.
0101
[3:0] Reserved
[7:2] Reserved
Reserved.
0x0
0x0
0x1
R
0x0008
0x0009
0x000A
Pair map
device index
Reserved.
R
1
Channel B/Channel D
R/W
0
1
ADC Core B/ADC Core D does not receive
the next SPI command.
ADC Core B/ADC Core D receives the next
SPI command.
0
Channel A/Channel C
0x1
R/W
0
1
ADC Core A/ADC Core C does not receive
the next SPI command.
ADC Core A/ADC Core C receives the next
SPI command.
Global map
pair index
[7:2] Reserved
Reserved.
0x0
0x1
R
1
Pair C/D
R/W
0
1
ADC Pair C/D does not receive the next read/
write command from the SPI interface.
ADC Pair C/D does not receive the next read/
write command from the SPI interface.
0
Pair A/B
0x1
R/W
0
1
ADC Pair A/B does not receive the next read/
write command from the SPI interface.
ADC Pair A/B receives the next read/write
command from the SPI interface.
Pair map
scratch pad
[7:0] Scratch pad
Chip scratch pad register. This register
provides a consistent memory location for
software debug.
0x07
R/W
0x000B
0x000C
Pair map SPI [7:0] SPI_REVISION
revision
SPI revision register (0x01 = Revision 1.0).
00000001 Revision 1.0.
Vendor ID.
0x1
R
R
Pair map
vendor ID
LSB
[7:0] CHIP_VENDOR_ID[7:0]
0x56
0x000D
0x003F
Pair map
vendor ID
MSB
[7:0] CHIP_VENDOR_ID[15:8]
Vendor ID.
0x4
0x0
R
Channel
map chip
power-
7
PDWN/STBY disable
This bit is used in conjunction with
Register 0x0040.
R/W
0
1
Power-down pin (PDWN/STBY) enabled;
global pin control selection enabled
(default).
Power-down pin (PDWN/STBY) disabled/
ignored; global pin control selection
ignored.
down pin
[6:0] Reserved
Reserved.
0x0
R
Rev. 0 | Page 83 of 107
AD6684
Data Sheet
Address Name
Bits Bit Name
Settings
Description
Reset Access
0x0040
Pair Map
[7:6] PDWN/STBY function
0x0
R/W
Chip Pin
Control 1
00
Power-down pin—assertion of the external
power-down pin (PDWN/STBY) causes the
chip to enter full power-down mode.
01
10
Standby pin—assertion of the external
power-down pin (PDWN/STBY) causes the
chip to enter standby mode.
Pin disabled—assertion of the external
power-down pin (PDWN/STBY) is ignored.
[5:3] Fast Detect B/Fast Detect D
(FD_B/FD_D)
0x7
R/W
000
001
010
Fast Detect B/Fast Detect D output.
JESD204B LMFC output.
JESD204B internal SYNC signal in the ADC
output.
111
Disabled (configured as an input with a
weak pull down).
[2:0] Fast Detect A/Fast Detect C
(FD_A/FD_C)
0x7
R/W
000
001
010
Fast Detect A/Fast Detect C output.
JESD204B LMFC output.
JESD204B internal SYNC signal in the ADC
output.
111
Disabled (configured as an input with a
weak pull down).
0x0108
0x0109
Pair map
clock divider
control
[7:3] Reserved
Reserved.
0x0
0x1
R
[2:0] Clock divider
R/W
000
001
011
111
Divide by 1.
Divide by 2.
Divide by 4.
Divide by 8.
Reserved.
Channel
map clock
divider
[7:4] Reserved
0x0
0x0
R
[3:0] Clock divider phase offset
R/W
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0 input clock cycles delayed.
1/2 input clock cycles delayed (invert clock).
1 input clock cycles delayed.
1 1/2 input clock cycles delayed.
2 input clock cycles delayed.
2 1/2 input clock cycles delayed.
3 input clock cycles delayed.
3 1/2 input clock cycles delayed.
4 input clock cycles delayed.
4 1/2 input clock cycles delayed.
5 input clock cycles delayed.
5 1/2 input clock cycles delayed.
6 input clock cycles delayed.
6 1/2 input clock cycles delayed.
7 input clock cycles delayed.
7 1/2 input clock cycles delayed.
phase
Rev. 0 | Page 84 of 107
Data Sheet
AD6684
Address Name
Bits Bit Name
Clock divider auto phase
adjust
Settings
Description
Reset Access
0x010A
Pair map
7
0x0
R/W
clock divider
SYSREF
control
0
1
Clock divider phase is not changed by
SYSREF (disabled).
Clock divider phase is automatically
adjusted by SYSREF (enabled).
[6:4] Reserved
Reserved.
0x0
0x0
R
[3:2] Clock divider negative
skew window
R/W
00
No negative skew; SYSREF must be captured
accurately.
01
10
11
1/2 device clock of negative skew.
1 device clocks of negative skew.
1 1/2 device clocks of negative skew.
[1:0] Clock divider positive skew
window
0x0
0x0
R/W
00
No positive skew; SYSREF must be captured
accurately.
1/2 device clock of positive skew.
1 device clocks of positive skew.
1 1/2 device clocks of positive skew.
Reserved.
01
10
11
0x0110
Pair map
clock delay
control
[7:3] Reserved
R
[2:0] Clock delay mode select
Clock delay mode select; used in conjunction 0x0
with Register 0x0111 and Register 0x0112.
R/W
000
001
010
No clock delay.
Reserved.
Fine delay; only Delay Step 0 to Delay
Step 16 are valid.
011
Fine delay (lowest jitter); only Delay Step 0 to
Delay Step 16 are valid.
100
101
110
Fine delay; all 192 delay steps are valid.
Reserved (same as 001).
Fine delay enabled; all 192 delay steps are
valid. Super fine delay enabled (all 128
delay steps are valid).
0x0111
Channel map [7:0] Clock super fine delay
This is an unsigned control to adjust the
super fine sample clock delay in 0.25 ps
steps.
0x0
R/W
clock super
adjust
fine delay
0x00
0x08
0x80
0 delay steps.
…
8 delay steps.
…
128 delay steps.
These bits are only used when
Register 0x0110, Bits[2:0] = 0x2 or 0x6.
0x0112
Channel
map clock
fine delay
[7:0] Clock fine delay adjust
Clock fine delay adjust. This is an unsigned 0xC0
control to adjust the fine sample clock
skew in 1.725 ps steps.
R/W
0x00
0x08
0xC0
0 delay steps.
…
8 delay steps.
…
192 delay steps.
These bits are only used when
Register 0x0110, Bits[2:0] = 0x2, 0x3, 0x4,
or 0x6.
Rev. 0 | Page 85 of 107
AD6684
Data Sheet
Address Name
Bits Bit Name
Settings
Description
Reset Access
0x011A
Clock
detection
control
[7:5] Reserved
Reserved.
0x0
0x1
R/W
R/W
[4:3] Clock detection threshold
Clock detection threshold.
200 MHz.
150 MHz.
01
11
2
Clock detection enable
Clock detection enable
Enable.
Disable.
0x1
R/W
1
0
[1:0] Reserved.
[7:1] Reserved
Reserved.
0x2
0x0
0x0
R/W
R
0x011B
0x011C
Pair map
clock status
Reserved.
0
Input clock detect
Clock detection status.
Input clock not detected.
Input clock detected/locked.
Reserved.
R
0
1
Clock DCS
control
[7:3] Reserved
0x1
0x0
R/W
R/W
1
Clock DCS enable
Clock DCS enable.
DCS bypassed.
DCS enabled.
0
1
0
Clock DCS power-up
Clock DCS power-up.
DCS powered down.
DCS powered up. The DCS must be
powered up before being enabled.
0x0
R/W
0
1
0x0120
Pair map
SYSREF
Control 1
7
6
Reserved
Reserved.
0x0
0x0
R
SYSREF flag reset
0
1
Normal flag operation.
SYSREF flags held in reset (setup/hold
error flags cleared).
R/W
5
4
Reserved
Reserved.
0x0
R
SYSREF transition select
0
1
SYSREF is valid on low to high transitions 0x0
using the selected CLK input edge. When
changing this setting, the SYSREF mode
select must be set to disabled.
SYSREF is valid on high to low transitions
using the selected CLK input edge. When
changing this setting, the SYSREF mode
select must be set to disabled.
R/W
3
CLK edge select
0
1
Captured on rising edge of CLK input.
Captured on falling edge of CLK input.
0x0
0x0
R/W
R/W
[2:1] SYSREF mode select
00
01
10
Disabled.
Continuous.
N shot.
0
Reserved
Reserved.
0x0
R
Rev. 0 | Page 86 of 107
Data Sheet
AD6684
Address Name
Bits Bit Name
Settings
Description
Reset Access
0x0121
Pair map
SYSREF
Control 2
[7:4] Reserved
Reserved.
0x0
0x0
R
[3:0] SYSREF N shot ignore
counter select
0000
Next SYSREF only (do not ignore).
R/W
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Ignore the first SYSREF transition.
Ignore the first two SYSREF transitions.
Ignore the first three SYSREF transitions.
Ignore the first four SYSREF transitions.
ignore the first five SYSREF transitions.
ignore the first six SYSREF transitions.
ignore the first seven SYSREF transitions.
ignore the first eight SYSREF transitions.
ignore the first nine SYSREF transitions.
ignore the first 10 SYSREF transitions.
ignore the first 11 SYSREF transitions.
ignore the first 12 SYSREF transitions.
ignore the first 13 SYSREF transitions.
ignore the first 14 SYSREF transitions.
ignore the first 15 SYSREF transitions.
Reserved.
0x0123
Pair map
SYSREF
Control 4
7
Reserved
0x0
R
[6:0] SYSREF time stamp
delay[6:0]
SYSREF timestamp delay (in converter
sample clock cycles)
0x40
R/W
0
1
0 sample clock cycle delay
1 sample clock cycle delay
…
127
127 sample clock cycle delay
0x0128
0x0129
Pair map
SYSREF
Status 1
[7:4] SYSREF hold status[7:4]
[3:0] SYSREF setup status[3:0]
[7:4] Reserved
SYSREF hold status. See Table 37 for
more information.
0x0
0x0
R
R
SYSREF setup status. See Table 37 for
more information.
Pair map
SYSREF
Status 2
Reserved.
0x0
0x0
R
R
[3:0] Clock divider phase when
SYSREF is captured
SYSREF divider phase. These bits
represent the phase of the divider when
SYSREF is captured.
0000
0001
0010
0011
0100
0101
In phase.
SYSREF is ½ cycle delayed from clock.
SYSREF is 1 cycle delayed from clock.
1½ input clock cycles delayed.
2 input clock cycles delayed.
2½ input clock cycles delayed.
…
1111
7½ input clock cycles delayed.
0x012A
Pair map
SYSREF
Status 3
[7:0] SYSREF counter [7:0]
(increments when a
SYSREF count. These bits are a running
counter that increments whenever a
SYSREF event is captured. Thes bits are
reset by Register 0x0120, Bit 6, and wrap
around at 255. Read these bits only while
Register 0x120, Bits[2:1] are disabled.
0x0
R
SYSREF is captured)
Rev. 0 | Page 87 of 107
AD6684
Data Sheet
Address Name
Bits Bit Name
Settings
Description
Reset Access
0x01FF
Pair map
chip sync
[7:1] Reserved
Reserved.
0x0
0x0
R
0
Synchronization mode
R/W
0x0
Sample synchronization mode. The
SYSREF signal resets all internal sample
dividers. Use this mode when synchronizing
multiple chips as specified in the JESD204B
standard. If the phase of any of the dividers
must change, the JESD204B link is
interrupted.
0x1
Partial synchronization/timestamp mode.
The SYSREF signal does not reset sample
internal dividers. In this mode, the JESD204B
link, the signal monitor, and the parallel
interface clocks are not affected by the
SYSREF signal. The SYSREF signal simply
time stamps a sample as it passes through
the ADC.
0x0200
Pair map
chip mode
[7:6] Reserved
Reserved.
0x0
0x0
R/W
R/W
5
Chip Q ignore
Chip real (I) only selection.
Both real (I) and complex (Q) selected.
Only real (I) selected. Complex (Q) is ignored.
Reserved.
0
1
4
Reserved
0x0
0x7
R
[3:0] Chip application mode
R/W
0000
0001
0010
0111
1000
Full bandwidth mode.
One DDC mode (DDC 0 only).
Two DDC mode (DDC 0 and DDC 1 only).
Noise shaped requantizer (NSR) mode.
Variable dynamic range (VDR) mode.
Reserved.
0x0201
Pair map
chip dec-
imation ratio
[7:3] Reserved
0x0
0x0
R
[2:0] Chip decimation ratio
select
Chip decimation ratio.
R/W
000
001
010
011
100
Decimate by 1 (full sample rate).
Decimate by 2.
Decimate by 4.
Decimate by 8.
Decimate by 16.
0x0228
0x0245
Channel map [7:0] Offset adjust in LSBs from
Digital datapath offset. Twos complement
offset adjustment aligned with least
significant converter resolution bit.
0x0
R/W
custom
+127 to −128
offset
Channel
map fast
detect
[7:4] Reserved
Reserved.
0x0
0x0
R
3
2
Force FD_A/FD_B/FD_C/
FD_D pins
R/W
control
0
1
Normal operation of the fast detect pin.
Force a value on the fast detect pin (see
Bit 2 of this register).
Force value of FD_A/FD_B/
FD_C/FD_D pins; if force
pins is true, this value is
output on the fast detect
pins
The fast detect output pin for this channel
is set to this value when the output is
forced.
0x0
R/W
1
0
Reserved
Reserved.
0x0
0x0
R
Enable fast detect output
R/W
0
1
Fine fast detect disabled.
Fine fast detect enabled.
Rev. 0 | Page 88 of 107
Data Sheet
AD6684
Address Name
Bits Bit Name
Settings
Description
Reset Access
0x0247
Channel map [7:0] Fast detect upper
LSBs of fast detect upper threshold. Eight
LSBS of the programmable 13-bit upper
threshold that is compared to the fine
ADC magnitude.
0x0
R/W
fast detect
upper thres-
hold LSB
threshold [7:0]
0x0248
Channel map [7:5] Reserved
Reserved.
0x0
0x0
R
fast detect
upper thres-
hold MSB
[4:0] Fast detect upper
threshold[12:8]
LSBs of fast detect upper threshold. Eight
LSBS of the programmable 13-bit upper
threshold that is compared to the fine
ADC magnitude.
R/W
0x0249
0x024A
Channel map [7:0] Fast detect lower
LSBs of fast detect lower threshold. Eight
LSBS of the programmable 13-bit lower
threshold that is compared to the fine
ADC magnitude
0x0
R/W
fast detect
lower thres-
hold LSB
threshold[7:0]
Channel
map fast
detect lower
threshold
MSB
[7:5] Reserved
Reserved.
0x0
0x0
R
[4:0] Fast detect lower
threshold[12:8]
LSBs of fast detect lower threshold. Eight
LSBS of the programmable 13-bit lower
threshold that is compared to the fine
ADC magnitude
R/W
0x024B
0x024C
0x026F
Channel
[7:0] Fast detect dwell time[7:0]
LSBs of fast detect dwell time counter target. 0x0
This target is a load value for a 16-bit counter
that determines how long the ADC data
must remain below the lower threshold
before the FD_x pins are reset to 0
R/W
R/W
map fast
detect dwell
time LSB
Channel
map fast
detect dwell
time MSB
[7:0] Fast detect dwell
time[15:8]
LSBs of fast detect dwell time counter
target. This target is a load value for a 16-bit
counter that determines how long the ADC
data must remain below the lower threshold
before the FDD_x pins are reset to 0.
0x0
Pair map
signal
monitor
sync control
[7:2] Reserved
Reserved.
Reserved.
0x0
0x0
0x0
R
1
0
Reserved
R/W
R/W
Signal monitor
synchronization mode
0
1
Synchronization disabled.
Only the next valid edge of the SYSREF pin
is used to synchronize the signal monitor
block. Subsequent edges of the SYSREF pin
are ignored. After the next SYSREF is
received, this bit is cleared. Note that the
SYSREF input pin must be enabled to
synchronize the signal monitor blocks.
0x0270
Channel
map signal
monitor
control
[7:2] Reserved
Reserved.
0x0
0x0
R
1
Peak detector
R/W
0
1
Peak detector disabled.
Peak detector enabled.
Reserved.
0
Reserved
0x0
R
0x0271
0x0272
0x0273
Channel
map Signal
Monitor
[7:0] Signal monitor period[7:0]
This 24-bit value sets the number of
output clock cycles over which the signal
monitor performs its operation. Bit 0 is
ignored.
0x80
R/W
Period 0
Channel
map Signal
Monitor
[7:0] Signal monitor period[15:8]
This 24-bit value sets the number of
output clock cycles over which the signal
monitor performs its operation. Bit 0 is
ignored.
0x0
0x0
R/W
R/W
Period 1
Channel
map Signal
Monitor
[7:0] Signal monitor
period[23:16]
This 24-bit value sets the number of
output clock cycles over which the signal
monitor performs its operation. Bit 0 is
ignored.
Period 2
Rev. 0 | Page 89 of 107
AD6684
Data Sheet
Address Name
Bits Bit Name
Settings
Description
Reset Access
0x0274
Channel
map signal
monitor
status
[7:5] Reserved
Reserved.
0x0
0x0
R
4
Result update
R/W
1
Status update based on Bits[2:0] (self
clearing).
control
3
Reserved
Reserved.
0x0
0x1
R
[2:0] Result selection
R/W
001
Peak detector placed on status readback
signals.
0x0275
0x0276
0x0277
Channel
map Signal
Monitor
[7:0] Signal monitor result[7:0]
Signal monitor status result. This 20-bit
value contains the status result calculated
by the signal monitor block. The content is
dependent on the Register 0x0274,
Bits[2:0] bit settings.
0x0
0x0
R
R
Status 0
Channel
map Signal
Monitor
[7:0] Signal monitor result[15:8]
[7:4] Reserved
Signal monitor status result. This 20-bit
value contains the status result calculated
by the signal monitor block. The content is
dependent on the Register 0x0274,
Bits[2:0] bit settings.
Status 1
Channel
map Signal
Monitor
Reserved.
0x0
0x0
R
R
[3:0] Signal monitor
result[19:16]
Signal monitor status result. This 20-bit
value contains the status result calculated
by the signal monitor block. The content is
dependent on the Register 0x0274,
Bits[2:0] bit settings.
Status 2
0x0278
0x0279
Channel map [7:0] Period count result[7:0]
signal
monitor
status frame
counter
Signal monitor frame counter status bits.
The frame counter increments whenever
the period counter expires.
0x0
R
Channel map [7:2] Reserved
Reserved.
Reserved.
0x0
0x0
0x0
R
signal
1
0
Reserved
R/W
R/W
monitor
serial framer
control
Signal monitor SPORT over
JESD204B enable
0
1
Disabled.
Enabled.
Reserved.
0x027A
Channel
map signal
monitor
serial framer
input
[7:6] Reserved
0x0
0x2
R
[5:0] Signal monitor SPORT over
JESD204B peak detector
enable
R/W
1
Peak detector enabled.
selection
Rev. 0 | Page 90 of 107
Data Sheet
AD6684
Address Name
Bits Bit Name
Settings
Description
Reserved.
Reserved.
Reset Access
0x0300
Pair map
[7:6] Reserved
0x0
0x0
0x0
R/W
R
DDC sync
control
5
4
Reserved
DDC NCO soft reset
This bit can be used to synchronize all the
NCOs inside the DDC blocks.
R/W
0
1
Normal operation.
DDC held in reset.
Reserved.
[3:2] Reserved
1 DDC next sync
0x0
0x0
R
The SYSREF pin must be an integer mul-
tiple of the NCO frequency for this function
to operate correctly in continuous mode.
R/W
0
1
Continuous mode.
Only the next valid edge of the SYSREF pin
is used to synchronize the NCO in the DDC
block. Subsequent edges of the SYSREF
pin are ignored. Aftwr the next SYSREF is
found, the DDC synchronization enable bit
is cleared.
0
DDC synchronization
mode
The SYSREF input pin must be enabled to 0x0
synchronize the DDCs.
R/W
0
1
Synchronization disabled.
If the DDC next syncbit = 1, only the next
valid edge of the SYSREF pin is used to
synchronize the NCO in the DDC block.
Subsequent edges of the SYSREF pin are
ignored. After the next SYSREF is
received, this bit is cleared.
0x0310
Pair map
DDC 0
control
7
6
DDC 0 mixer select
DDC 0 gain select
0x0
R/W
R/W
0
1
Real mixer (I and Q inputs must be from
the same real channel).
Complex mixer (I and Q must be from
separate real and imaginary quadrature ADC
receive channels—analog demodulator).
Gain can be used to compensate for the
6 dB loss associated with mixing an input
signal down to baseband and filtering out
its negative component.
0x0
0
1
0 dB gain.
6 dB gain (multiply by 2).
[5:4] DDC 0 IF mode
0x0
0x0
R/W
R/W
00
01
10
11
Variable IF mode.
0 Hz IF mode.
fS/4 Hz IF mode.
Test mode.
3
2
DDC 0 complex to real
enable
0
1
Complex (I and Q) outputs contain valid
data.
Real (I) output only. Complex to real enabled.
Uses extra fS/4 mixing to convert to real.
Reserved
Reserved.
0x0
R
Rev. 0 | Page 91 of 107
AD6684
Data Sheet
Address Name
Bits Bit Name
Settings
Description
Reset Access
[1:0] DDC 0 decimation rate
select
Decimation filter selection. Complex
outputs (complex to real disabled):
0x0
R/W
11
00
01
HB1 filter selection (decimate by 2).
HB2 + HB1 filter selection (decimate by 4).
HB3 + HB2 + HB1 filter selection (decimate
by 8).
10
HB4 + HB3 + HB2 + HB1 filter selection
(decimate by 16).
Real outputs (complex to real enabled):
HB1 filter selection (decimate by 1).
HB2 + HB1 filter selection (decimate by 2).
HB3 + HB2 + HB1 filter selection (decimate
by 4).
11
00
01
10
HB4 + HB3 + HB2 + HB1 filter selection
(decimate by 8).
11
00
HB1 filter selection: decimate by 1 or 2.
HB2 + HB1 filter selection (decimate by 2
or 4).
01
10
HB3 + HB2 + HB1 filter selection (decimate
by 4 or 8)
HB4 + HB3 + HB2 + HB1 filter selection
(decimate by 8 or 16)
0x0311
Pair Map
DDC 0 input
select
[7:3] Reserved
Reserved.
0x0
0x0
R
2
DDC 0 Q input select
R/W
0
1
Channel A.
Channel B.
Reserved.
1
0
Reserved
0x0
0x0
R
DDC 0 I input select
R/W
0
1
Channel A.
Channel B.
0x0314
0x0315
0x0316
0x0317
0x0318
0x031A
0x031D
Pair map
DDC 0 Phase
Increment 0
[7:0] DDC 0 NCO frequency value,
twos complement[7:0]
NCO phase increment value; twos
complement phase increment value for
the NCO. Complex mixing frequency =
(DDC phase increment × fS)/248.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Pair map
DDC 0 Phase
Increment 1
[7:0] DDC 0 NCO frequency value,
twos complement[15:8]
NCO phase increment value; twos
complement phase increment value for
the NCO. Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
Pair map
DDC 0 Phase
Increment 2
[7:0] DDC 0 NCO frequency value,
twos complement[23:16]
NCO phase increment value; twos
complement phase increment value for
the NCO. Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
Pair map
DDC 0 Phase
Increment 3
[7:0] DDC 0 NCO frequency value,
twos complement[31:24]
NCO phase increment value; twos
complement phase increment value for
the NCO. Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
Pair map
DDC 0 Phase
Increment 4
[7:0] DDC 0 NCO frequency value,
twos complement[39:32]
NCO phase increment value; twos
complement phase increment value for
the NCO. Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
Pair map
DDC 0 Phase
Increment 5
[7:0] DDC 0 NCO frequency value,
twos complement[47:40]
NCO phase increment value; twos
complement phase increment value for
the NCO. Complex mixing frequency =
(DDC_PHASE_INC × fS)/248.
Pair map
DDC 0 Phase
Offset 0
[7:0] DDC 0 NCO phase value,
twos complement[7:0]
Twos complement phase offset value for
the NCO.
Rev. 0 | Page 92 of 107
Data Sheet
AD6684
Address Name
Bits Bit Name
Settings
Description
Reset Access
0x031E
0x031F
0x0320
0x0321
0x0322
0x0327
Pair map
DDC 0 Phase
Offset 1
[7:0] DDC 0 NCO phase value,
twos complement[15:8]
Twos complement phase offset value for
the NCO.
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
Pair map
DDC 0 Phase
Offset 2
[7:0] DDC 0 NCO phase value,
twos complement[23:16]
Twos complement phase offset value for
the NCO.
Pair map
DDC 0 Phase
Offset 3
[7:0] DDC 0 NCO phase value,
twos complement[31:24]
Twos complement phase offset value for
the NCO.
Pair Map
DDC 0 Phase
Offset 4
[7:0] DDC 0 NCO phase value,
twos complement[39:32]
Twos complement phase offset value for
the NCO.
Pair map
DDC 0 Phase
Offset 5
[7:0] DDC 0 NCO phase value,
twos complement[47:40]
Twos complement phase offset value for
the NCO.
Pair map
DDC 0 test
enable
[7:3] Reserved
Reserved.
0x0
0x0
R
2
DDC 0 Q output test mode
enable
Q samples always use the Test Mode B/
Test Mode D block.
R/W
0
1
Test mode disabled.
Test mode enabled.
Reserved.
1
0
Reserved
0x0
0x0
R
DDC 0 I output test mode
enable
I Samples always use Test Mode A/ Test
Mode C block.
R/W
0
1
Test mode disabled.
Test mode enabled.
0x0330
Pair map
DDC 1
control
7
6
DDC 1 mixer select
DDC 1 gain select
0x0
0x0
R/W
R/W
0
1
Real mixer (I and Q inputs must be from
the same real channel).
Complex mixer (I and Q must be from
separate, real and imaginary quadrature ADC
receive channels—analog demodulator).
Gain can be used to compensate for the
6 dB loss associated with mixing an input
signal down to baseband and filtering out
its negative component.
0
1
0 dB gain.
6 dB gain (multiply by 2).
[5:4] DDC 1 IF mode
0x0
0x0
R/W
R/W
00
01
10
11
Variable IF mode.
0 Hz IF mode.
fS/4 Hz IF mode.
Test mode.
3
2
DDC 1 complex to real
enable
0
1
Complex (I and Q) outputs contain valid
data.
Real (I) output only. Complex to real enabled.
Uses extra fS/4 mixing to convert to real.
Reserved
Reserved.
0x0
R
Rev. 0 | Page 93 of 107
AD6684
Data Sheet
Address Name
Bits Bit Name
Settings
Description
Reset Access
[1:0] DDC 1 decimation rate
select
Decimation filter selection. Complex
outputs (complex to real disabled):
0x0
R/W
11
00
01
HB1 filter selection (decimate by 2).
HB2 + HB1 filter selection (decimate by 4).
HB3 + HB2 + HB1 filter selection (decimate
by 8).
10
HB4 + HB3 + HB2 + HB1 filter selection
(decimate by 16).
Real outputs (complex to real enabled):
HB1 filter selection (decimate by 1).
HB2 + HB1 filter selection (decimate by 2).
HB3 + HB2 + HB1 filter selection (decimate
by 4).
11
00
01
10
HB4 + HB3 + HB2 + HB1 filter selection
(decimate by 8).
11
00
HB1 filter selection: decimate by 1 or 2.
HB2 + HB1 filter selection (decimate by 2
or 4).
01
10
HB3 + HB2 + HB1 filter selection (decimate
by 4 or 8)
HB4 + HB3 + HB2 + HB1 filter selection
(decimate by 8 or 16)
0x0331
Pair map
DDC 1 input
select
[7:3] Reserved
Reserved.
0x0
0x1
R
2
DDC 1 Q input select
R/W
0
1
Channel A.
Channel B.
Reserved.
1
0
Reserved
0x0
0x1
R
DDC 1 I input select
R/W
0
1
Channel A.
Channel B.
0x0334
0x0335
0x0336
0x0337
0x0338
0x033A
0x033D
Pair map
DDC 1 Phase
Increment 0
[7:0] DDC 1 NCO frequency
value, twos
NCO phase increment value. Twos
complement phase increment value for
the NCO. Complex mixing frequency =
(DDC phase increment × fS)/248.
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
complement[7:0]
Pair map
DDC 1 Phase
Increment 1
[7:0] DDC 1 NCO frequency
value, twos
NCO phase increment value. Twos
complement phase increment value for
the NCO. Complex mixing frequency =
(DDC phase increment × fS)/248.
complement[15:8]
Pair map
DDC 1 Phase
Increment 2
[7:0] DDC 1 NCO frequency
value, twos
NCO phase increment value. Twos
complement phase increment value for
the NCO. Complex mixing frequency =
(DDC phase increment × fS)/248.
complement[23:16]
Pair map
DDC 1 Phase
Increment 3
[7:0] DDC 1 NCO frequency
value, twos
NCO phase increment value. Twos
complement phase increment value for
the NCO. Complex mixing frequency =
(DDC phase increment × fS)/248.
complement[31:24]
Pair map
DDC 1 Phase
Increment 4
[7:0] DDC 1 NCO frequency
value, twos
NCO phase increment value. Twos
complement phase increment value for
the NCO. Complex mixing frequency =
(DDC phase increment × fS)/248.
complement[39:32]
Pair map
DDC 1 Phase
Increment 5
[7:0] DDC 1 NCO frequency
value, twos
NCO phase increment value. Twos
complement phase increment value for
the NCO. Complex mixing frequency =
(DDC phase increment × fS)/248.
complement[47:40]
Pair map
DDC 1 Phase
Offset 0
[7:0] DDC 1 NCO phase value,
twos complement[7:0]
Twos complement phase offset value for
the NCO.
Rev. 0 | Page 94 of 107
Data Sheet
AD6684
Address Name
Bits Bit Name
Settings
Description
Reset Access
0x033E
0x033F
0x0340
0x0341
0x0342
0x0347
Pair map
DDC 1 Phase
Offset 1
[7:0] DDC 1 NCO phase value,
twos complement[15:8]
Twos complement phase offset value for
the NCO.
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
Pair map
DDC 1 Phase
Offset 2
[7:0] DDC 1 NCO phase value,
twos complement[23:16]
Twos complement phase offset value for
the NCO.
Pair map
DDC 1 Phase
Offset 3
[7:0] DDC 1 NCO phase value,
twos complement[31:24]
Twos complement phase offset value for
the NCO.
Pair map
DDC 1 Phase
Offset 4
[7:0] DDC 1 NCO phase value,
twos complement[39:32]
Twos complement phase offset value for
the NCO.
Pair map
DDC 1 Phase
Offset 5
[7:0] DDC 1 NCO phase value,
twos complement[47:40]
Twos complement phase offset value for
the NCO.
Pair map
DDC 1 test
enable
[7:3] Reserved
Reserved.
0x0
0x0
R
2
DDC 1 Q output test mode
enable
Q samples always use the Test Mode B/
Test Mode D block.
R/W
0
1
Test mode disabled.
Test mode enabled.
Reserved.
1
0
Reserved
0x0
0x0
R
DDC 1 I output test mode
enable
I samples always use the Test Mode A/
Test Mode C block.
R/W
0
1
Test mode disabled.
Test mode enabled.
Decimate by 2 high-pass/low-pass mode.
Enable LPF.
0x041E
Channel
7
6
High-pass/low-pass mode
0x0
R/W
map NSR
decimate by
2 control
0
1
Enable HPF.
Reserved
Reserved.
0x0
0x0
0x0
0x0
R
[5:4] Reserved
[3:1] Reserved
Reserved.
R/W
R
Reserved.
0
NSR decimate by 2 enable
R/W
0
1
Decimate by 2 disabled.
Decimate by 2 enabled.
Reserved.
0x0420
0x0422
NSR mode
7
Reserved
0x0
0x0
0x0
R/W
R
[6:4] Reserved
[3:1] NSR mode
Reserved.
R/W
000
001
21% BW mode.
28% BW mode.
Reserved.
0
Reserved
0x0
0x0
0x0
R
Channel
map NSR
tuning
[7:6] Reserved
Reserved.
R
[5:0] NSR tuning word
Noise shaped requantizer tuning
frequency (see the Noise Shaping
Requantizer (NSR) section for details).
R/W
Rev. 0 | Page 95 of 107
AD6684
Data Sheet
Address Name
Bits Bit Name
Reserved
[6:5] Reserved
Reserved
[3:2] Reserved
Settings
Description
Reserved.
Reserved.
Reserved.
Reserved.
Reset Access
0x0430
Pair map
7
0x0
0x0
0x0
0x0
0x0
R/W
R
VDR control
4
R/W
R
1
VDR bandwidth
R/W
0
1
25% BW mode.
43% BW mode. Only available in complex
mode.
0
VDR complex mode enable
0x1
R/W
0
1
Dual real mode. Ignore Bit 1.
Dual complex mode. Complex input,
Channel A/Channel C are I and Channel
B/Channel D are Q.
0x0434
0x0550
Channel
map VDR
tuning
[7:4] Reserved
Reserved.
0x0
0x0
R
[3:0] VDR center frequency
See the Variable Dynamic Range (VDR)
section for details.
R/W
frequency
Channel
map test
mode
7
User pattern selection
0x0
R/W
0
1
Continuous repeat.
Single pattern.
Reserved.
control
6
5
Reserved
0x0
0x0
R
Reset PN long generation
R/W
0
1
Long PN enabled.
Long PN held in reset.
4
Reset PN short generation
0x0
0x0
R/W
R/W
0
1
Short PN enabled.
Short PN held in reset.
[3:0] Test mode selection
0000
0001
0010
0011
0100
0101
0110
0111
1000
Off—normal operation.
Midscale short.
Positive full scale.
Negative full scale.
Alternating checker board.
PN sequence—long.
PN sequence—short.
1/0 word toggle.
User pattern test mode (used with the test
mode patern selection and the User
Pattern 1 through User Pattern 4 registers)
1111
Ramp output.
0x0551
0x0552
0x0553
0x0554
0x0555
Pair map
User Pattern
1 LSB
[7:0] User Pattern 1[7:0]
[7:0] User Pattern 1[15:8]
[7:0] User Pattern 2[7:0]
[7:0] User Pattern 2[15:8]
[7:0] User Pattern 3[7:0]
User Test Pattern 1 least significant byte
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
Pair map
User Pattern
1 MSB
User Test Pattern 1 most significant byte
User Test Pattern 2 least significant byte
User Test Pattern 2 most significant byte
User Test Pattern 3 least significant byte
Pair map
User Pattern
2 LSB
Pair map
User Pattern
2 MSB
Pair map
User Pattern
3 LSB
Rev. 0 | Page 96 of 107
Data Sheet
AD6684
Address Name
Bits Bit Name
Settings
Description
Reset Access
0x0556
0x0557
0x0558
0x0559
Pair map
User Pattern
3 MSB
[7:0] User Pattern 3[15:8]
User Test Pattern 3 most significant byte
0x0
0x0
0x0
R/W
R/W
R/W
Pair map
User Pattern
4 LSB
[7:0] User Pattern 4[7:0]
[7:0] User Pattern 4[15:8]
User Test Pattern 4 least significant byte
User Test Pattern 4 most significant byte
Reserved.
Pair map
User Pattern
4 MSB
Pair map
Output
Control
Mode 0
7
Reserved
0x0
0x0
R
[6:4] Converter Control Bit 1
selection
R/W
000
001
010
011
100
101
110
111
Tie low (1'b0).
Overrange bit.
Signal monitor bit or VDR punish Bit 0.
Fast detect (FD) bit or VDR punish Bit 1.
VDR high/low resolution bit.
SYSREF.
Reserved.
Reserved.
3
Reserved
Reserved.
0x0
0x0
R
[2:0] Converter Control Bit 0
selection
R/W
000
001
010
011
100
101
Tie low (1'b0)
Overrange bit.
Signal monitor or VDR punish Bit 0.
Fast detect (FD) bit or VDR punish Bit 1.
VDR high/low resolution bit.
SYSREF.
0x055A
Pair Map
Output
Control
Mode 1
[7:3] Reserved
Reserved.
0x0
0x1
R
[2:0] Converter control Bit 2
selection
R/W
000
001
010
011
100
101
110
111
Tie low (1'b0).
Overrange bit.
Signal monitor bit or VDR punish Bit 0.
Fast detect (FD) bit or VDR punish Bit 1.
VDR high/low resolution bit.
SYSREF.
Reserved.
Reserved.
0x0561
0x0564
Pair map
output
sample
mode
[7:3] Reserved
Reserved.
0x0
0x0
R
2
Sample invert
R/W
0
1
ADC sample data is not inverted.
ADC sample data is inverted.
[1:0] Data format select
[7:2] Reserved
0x1
R/W
00
01
Offset binary.
Twos complement (default).
Reserved.
Pair map
output
channel
select
0x0
0x0
0x0
R
1
0
Reserved
Reserved.
R/W
R/W
Converter channel swap
control
0
1
Normal channel ordering.
Channel swap enabled.
Rev. 0 | Page 97 of 107
AD6684
Data Sheet
Address Name
Bits Bit Name
Settings
Description
Reset Access
0x056E
0x056F
0x0570
JESD204B
map PLL
control
[7:4] JESD204B lane rate control
0x0
R/W
0000
0001
0011
0101
Lane rate = 6.75 to 13.5 Gbps.
Lane rate = 3.375 Gbps to 6.75 Gbps.
Lane rate = 13.5 to 15 Gbps.
Lane rate = 1.6875 Gbps to 3.375 Gbps.
Reserved.
[3:0] Reserved
0x0
0x0
R
R
JESD204B
map PLL
status
7
PLL lock status
0
1
Not locked.
Locked.
[6:4] Reserved
Reserved
Reserved.
0x0
0x0
0x0
0x1
R
3
Reserved.
R
[2:0] Reserved
Reserved.
Number of lanes (L) = 2Register0x0570, Bits[7:6]
L = 1.
L = 2.
R
JESD204B
map JTX
quick
config-
uration
[7:6] Quick Configuration L
R/W
0
1
[5:3] Quick Configuration M
[2:0] Quick Configuration F
Number of converters (M) = 2Register 0x0570, Bits[5:3]
0x1
0x1
R/W
R/W
0
1
10
M = 1.
M = 2.
M = 4.
Number of octets/frame (F) =
2Register 0x0570, Bits[2:0]
0
1
10
11
F = 1.
F = 2.
F = 4.
F = 8.
0x0571
JESD204B
map JTX
Link
7
Standby mode
0x0
R/W
0
1
Standby mode forces zeros for all
converter samples.
Standby mode forces code group
synchronization (K28.5 characters).
Control 1
6
5
Tail bit (t) PN
0x0
0x0
R/W
R/W
0
1
Disable.
Enable.
Long transport layer test
0
1
JESD204B test samples disabled.
JESD204B test samples enabled. The long
transport layer test sample sequence (as
specified in JESD204B Section 5.1.6.3) sent
on all link lanes.
4
Lane synchronization
0x1
0x1
R/W
R/W
0
1
Disable FACI uses /K28.7/.
Enable FACI uses /K28.3/ and /K28.7/.
[3:2] ILAS sequence mode
00
01
11
Initial lane alignment sequence disabled
(see JESD204B Section 5.3.3.5).
Initial lane alignment sequence enabled
(see JESD204B Section 5.3.3.5).
Initial lane alignment sequence always on
test mode. JESD204B data link layer test
mode where repeated lane alignment
sequence (as specified in JESD204B,
Section 5.3.3.8.2) sent on all lanes.
Rev. 0 | Page 98 of 107
Data Sheet
AD6684
Address Name
Bits Bit Name
Settings
Description
Reset Access
1
FACI
0x0
R/W
0
1
Frame alignment character insertion
enabled (JESD204B, Section 5.3.3.4).
Frame alignment character insertion
disabled; for debug only (JESD204B,
Section 5.3.3.4)
0
Link control
0x0
R/W
0
1
JESD204B serial transmit link enabled.
Transmission of the /K28.5/ characters for
code group synchronization is controlled
by the SYNCINB x signal pin.
JESD204B serial transmit link powered
down (held in reset and clock gated).
0x0572
JESD204B
map JTX
Link
[7:6] SYNCINB AB/
SYNCINB CD pin control
0x0
R/W
00
10
Normal mode.
Ignore SYNCINB AB/SYNCINB CD (force
CGS).
Control 2
11
Ignore SYNCINB AB/SYNCINB CD (force
ILAS/user data).
5
4
SYNCINB AB/
SYNCINB CD pin invert
0x0
0x0
R/W
R/W
0
1
SYNCINB AB/SYNCINB CD pin not inverted.
SYNCINB AB/SYNCINB CD pin inverted.
SYNCINB AB/
SYNCINB CD pin type
0
1
LVDS differential pair SYNC signal input.
CMOS single-ended SYNC signal input.
Reserved.
3
2
Reserved
0x0
0x0
R
8-bit/10-bit bypass
R/W
0
1
8-bit/10-bit enabled.
8-bit/10-bit bypassed (the most significant
two bits are 0).
1
0
8-bit/10-bit bit invert
Reserved
0x0
R/W
0
1
Normal.
Invert a b c d e f g h i j symbols.
Reserved.
0x0
0x0
R/W
R/W
0x0573
JESD204B
map JTX
Link
[7:6] Checksum mode
00
01
10
11
Checksum is the sum of all the 8-bit
registers in the link configuration table.
Checksum is the sum of all individual link
configuration fields (LSB aligned).
Checksum is disabled (set to 0). For test
purposes only.
Control 3
Unused.
[5:4] Test injection point
0x0
R/W
0
1
N' sample input.
10-bit data at 8-bit/10-bit output (for PHY
testing).
10
8-bit data at scrambler input.
Rev. 0 | Page 99 of 107
AD6684
Data Sheet
Address Name
Bits Bit Name
Settings
Description
Reset Access
[3:0] JESD204B test mode
patterns
0x0
R/W
0
1
10
Normal operation(test mode disabled).
Alternating checkerboard.
1/0 word toggle.
11
31-bit PN sequence: x31 + x28 + 1.
23-bit PN sequence: x23 + x18 + 1.
15-bit PN sequence: x15 + x14 + 1.
9-bit PN sequence: x9 + x5 + 1.
7-bit PN sequence: x7 + x6 + 1.
Ramp output.
100
101
110
111
1000
1110
1111
Continuous/repeat user test.
Single user test.
0x0574
JESD204B
[7:4] ILAS delay
0x0
R/W
map JTX
Link
Control 4
0
Transmit ILAS on first LMFC after SYNCINB x
is deasserted.
Transmit ILAS on second LMFC after
SYNCINB is deasserted.
1
10
Transmit ILAS on third LMFC after
SYNCINB x is deasserted.
11
Transmit ILAS on fourth LMFC after
SYNCINB is deasserted.
100
101
110
111
1000
1001
1010
1011
1100
1101
1110
1111
Transmit ILAS on fifth LMFC after SYNCINB x
is deasserted.
Transmit ILAS on sixth LMFC after
SYNCINB x is deasserted.
Transmit ILAS on seventh LMFC after
SYNCINB x is deasserted.
Transmit ILAS on eightth LMFC after
SYNCINB x is deasserted.
Transmit ILAS on nineth LMFC after
SYNCINB x is deasserted.
Transmit ILAS on 10th LMFC after
SYNCINB x is deasserted.
Transmit ILAS on 11th LMFC after
SYNCINB x is deasserted.
Transmit ILAS on 12th LMFC after
SYNCINB x is deasserted.
Transmit ILAS on 13th LMFC after
SYNCINB x is deasserted.
Transmit ILAS on 14th LMFC after
SYNCINB x is deasserted.
Transmit ILAS on 15th LMFC after
SYNCINB x is deasserted.
Transmit ILAS on 16th LMFC after
SYNCINB x is deasserted.
3
Reserved
Reserved.
0x0
0x0
R
[2:0] Link layer test mode
R/W
000
Normal operation (link layer test mode
disabled).
001
010
011
100
101
110
111
Continuous sequence of /D21.5/ characters.
Reserved.
Reserved.
Modified RPAT test sequence.
JSPAT test sequence.
JTSPAT test sequence.
Reserved.
Rev. 0 | Page 100 of 107
Data Sheet
AD6684
Address Name
Bits Bit Name
Settings
Description
Reset Access
0x0578
JESD204B
map JTX
LMFC offset
[7:5] Reserved
Reserved.
0x0
0x0
R
[4:0] LMFC phase offset value
LMFC phase offset value; reset value for
LMFC phase counter when SYSREF is
asserted. Used for deterministic delay
applications.
R/W
0x0580
0x0581
0x0583
0x0585
0x058B
JESD204B
map JTX DID
config-
[7:0] JESD204B Tx DID value
JESD204B serial device identification (DID) 0x0
number.
R/W
uration
JESD204B
map JTX BID
config-
[7:4] Reserved
Reserved.
0x0
0x0
R
[3:0] JESD204B Tx BID value
JESD204B serial bank identification (BID)
number (extension to DID).
R/W
uration
JESD204B
map JTX
LID0 config-
uration
[7:5] Reserved
Reserved.
0x0
0x0
R
[4:0] Lane 0 LID value
JESD204B serial lane identification (LID)
number for Lane 0.
R/W
JESD204B
map JTX
LID1 config-
uration
[7:5] Reserved
Reserved.
0x0
0x2
R
[4:0] Lane 1 LID Value
JESD204B serial lane identification (LID)
number for Lane 1.
R/W
JESD204B
map JTX
SCR L
config-
uration
7
JESD204B scrambling (SCR)
0x1
R/W
0
1
JESD204B scrambler disabled. SCR = 0.
JESD204B scrambler enabled. SCR = 1.
Reserved.
[6:5] Reserved
0x0
0x1
R
R
[4:0] JESD204B lanes (L)
0x0
0x1
One lane per link (L = 1).
Two lanes per link (L = 2).
0x058C
0x058D
JESD204B
map JTX F
config-
[7:0] Number of octets per
frame (F)
Number of octets per frame.
F = Register 0x058C, Bits[7:0] + 1.
0x1
R
uration
JESD204B
map JTX K
config-
[7:5] Reserved
Reserved.
0x0
R
[4:0] Number of frames per
multiframe (K)
JESD204B number of frames per multi-
frame (K = Register 0x058D, Bits[4:0] + 1).
Only values where F × K are divisible by 4
can be used.
0x1F
R/W
uration
00011
00111
01100
01111
10011
10111
11011
11111
K = 4.
K = 8.
K = 12.
K = 16.
K = 20.
K = 24.
K = 28.
K = 32.
0x058E
JESD204B
Map JTX M
config-
[7:0] Number of converters per
link
0x1
R
00000000 Link connected to one virtual converter
(M = 1).
00000001 Link connected to two virtual converters
(M = 2).
uration
00000011 Link connected to four virtual converters
(M = 4).
Rev. 0 | Page 101 of 107
AD6684
Data Sheet
Address Name
Bits Bit Name
Settings
Description
Reset Access
0x058F
JESD204B
[7:6] Number of control bits (CS)
per sample
0x0
R/W
map JTX CS
N config-
uration
0
1
No control bits (CS = 0).
One control bit (CS = 1), Control Bit 2 only.
10
Two control bits (CS = 2), Control Bit 2 and
Control Bit 1 only.
11
Three control bits (CS = 3), all control bits
(Bits[2:0]).
5
Reserved
Reserved.
0x0
0xF
R
[4:0] ADC converter resolution (N)
R/W
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
N = 7-bit resolution.
N = 8-bit resolution.
N = 9-bit resolution.
N = 10-bit resolution.
N = 11-bit resolution.
N = 12-bit resolution.
N = 13-bit resolution.
N = 14-bit resolution.
N = 15-bit resolution.
N = 16-bit resolution.
0x0590
JESD204B
map JTX
SCV NP
config-
[7:5] Subclass support
0x1
0xF
R/W
R/W
000
001
Subclass 0.
Subclass 1.
[4:0] ADC number of bits per
sample (N')
uration
00111
01111
N' = 8.
N' = 16.
Reserved.
0x0591
0x0592
JESD204B
map JTX JV
S config-
uration
[7:5] Reserved
0x1
0x0
R
R
[4:0] Samples per converter
frame cycle (S)
Samples per converter frame cycle
(S = Register 0x0591, Bits[4:0] + 1).
JESD204B
map JTX HD
CF config-
uration
7
HD value
0x0
R
0
1
High density format disabled.
High density format enabled.
Reserved.
[6:5] Reserved
0x0
0x0
R
R
[4:0] Control words per frame
clock cycle per link (CF)
Number of control words per frame clock
cycle per link (CF = Register 0x0592, Bits[4:0]).
0x05A0
0x05A1
0x05B0
JESD204B
map JTX
Checksum 0
config-
[7:0] Checksum 0 checksum
value for SERDOUTAB0 /
SERDOUTCD0
Serial checksum value for Lane 0, auto-
matically calculated for each lane. Sum (all
link configuration parameters for Lane 0)
mod 256.
0xC3
R
uration
JESD204B
map JTX
Checksum 1
config-
[7:0] Checksum 1 checksum
value for SERDOUTAB1 /
SERDOUTCD1
Serial checksum value for Lane 1, auto-
matically calculated for each lane. Sum (all
link configuration parameters for Lane 1)
mod 256.
0xC4
R
uration
JESD204B
Map JTX
Lane power-
down
[7:3] Reserved
Reserved.
0x1F
0x0
R/W
R/W
2
JESD204B Lane 1 power-
down
Physical Lane 1 force power-down.
1
0
Reserved
Reserved.
0x1
0x0
R/W
R/W
JESD204B lane 0 power-
down
Physical Lane 0 force power-down.
Rev. 0 | Page 102 of 107
Data Sheet
AD6684
Address Name
Bits Bit Name
Reserved
[6:4] Reserved
Reserved
Settings
Description
Reserved.
Reserved.
Reserved.
Reset Access
0x05B2
0x05B3
0x05C0
JESD204B
7
0x0
0x0
0x0
0x0
R
map JTX
Lane Assign-
ment 1
R/W
R
3
[2:0] SERDOUTAB0 /
SERDOUTCD0 lane
assignment
R/W
0
1
Logical Lane 0 (default).
Logical Lane 1.
Reserved.
JESD204B
map JTX
Lane Assign-
ment 2
7
Reserved
[6:4] Reserved
Reserved
0x0
0x1
0x0
0x1
R
Reserved.
R/W
R
3
Reserved.
[2:0] SERDOUTAB1 /
SERDOUTCD1 lane
assignment
R/W
0
1
Logical Lane 0.
Logical Lane 1 (default).
Reserved.
JESD204B
map
7
Reserved
0x0
0x1
R
[6:4] Swing voltage for
SERDOUTAB1 /
R/W
JESD204B
serializer
drive adjust
0
1
1.0 × DRVDD1 (differential).
0.850 × DRVDD1 (differential).
SERDOUTCD1
3
Reserved
Reserved.
0x0
0x1
R
[2:0] Swing voltage for
SERDOUTAB0 /
R/W
0
1.0 × DRVDD1 (differential).
SERDOUTCD0
0x05C4
JESD204B
serializer
preemphasis
selection
register for
Logical
7
Post tab polarity
Post tab polarity.
Normal.
Inverted.
0x0
0x0
R/W
R/W
0
1
[6:4] Sets post tab level
These bits set the post tab level.
0 dB.
0
Lane 0
1
3 dB.
10
6 dB.
11
9 dB.
100
101
110
111
12 dB.
Not valid.
Not valid.
Not valid.
Pretab polarity.
Normal.
Inverted.
These bits set the pretab level.
0 dB.
3
Pretab polarity
0x0
0x0
R/W
R/W
0
1
[2:0] Sets pretab level
0
1
3 dB.
10
6 dB.
11
9 dB.
100
101
110
111
12 dB.
Not valid.
Not valid.
Not valid.
Rev. 0 | Page 103 of 107
AD6684
Data Sheet
Address Name
Bits Bit Name
Settings
Description
Reset Access
0x05C6
JESD204B
7
Post tab polarity
Post tab polarity.
0x0
R/W
serializer
preemphasis
selection
register for
Logical
0
1
Normal.
Inverted.
[6:4] Sets post tab level
These bits set the post tab level.
0 dB.
0x0
R/W
0
Lane 1
1
3 dB.
10
6 dB.
11
9 dB.
100
101
110
111
12 dB.
Not valid.
Not valid.
Not valid.
3
Pretab polarity
This bit sets the pretab polarity.
Normal.
Inverted.
0x0
0x0
R/W
R/W
0
1
[2:0] Sets pretab level
These bits set the pretab level.
0
0 dB.
1
3 dB.
10
6 dB.
11
9 dB.
100
101
110
111
12 dB.
Not valid.
Not valid.
Not valid.
0x0922
0x1222
0x1228
Large dither [7:0] Large dither control
control
Enables/disables the large dither control.
Enable.
Disable.
0x70
0x0
R/W
R/W
R/W
1110000
1110001
PLL
[7:0] PLL calibration
PLL calibration.
Normal operation.
PLL calibration
calibration
0x00
0x04
JESD204B
start-up
[7:0] JESD204B start-up circuit
reset
JESD204B start-up circuit reset.
0xF
circuit reset
0x0F
0x4F
Normal operation.
Start-up circuit reset.
PLL loss of lock control.
Normal operation.
Clear loss of lock.
Reserved.
0x1262
0x18A6
PLL loss of
lock control
PLL loss of lock control
[7:5] Reserved
0x0
R/W
0x00
0x08
Pair map
0x0
0x0
0x0
0x0
R
VREF control
4
Reserved
Reserved.
R/W
R
[3:1] Reserved
Reserved.
0
VREF control
R/W
0
1
Internal reference.
External reference.
Reserved.
0x1908
Channel
map analog
input
[7:6] Reserved
[5:4] Reserved
0x0
0x0
0x0
0x0
R
Reserved.
R/W
R
3
2
Reserved
Reserved.
control
Analog input dc coupling
control
Analog input dc coupling control.
R/W
0
1
AC coupling.
DC coupling.
Reserved.
1
0
Reserved
Reserved
0x0
0x0
R
Reserved.
R/W
Rev. 0 | Page 104 of 107
Data Sheet
AD6684
Address Name
Bits Bit Name
Settings
Description
Reserved.
Input full-scale control
2.16 V p-p.
1.44 V p-p.
1.56 V p-p.
1.68 V p-p.
1.80 V p-p.
1.92 V p-p.
2.04 V p-p.
Reserved.
Buffer Control 1.
120 μA.
160 μA.
200 μA.
240 μA.
280 μA.
320 μA.
360 μA.
400 μA.
440 μA.
Reset Access
0x1910
Channel
map input
full-scale
range
[7:4] Reserved
0x0
R
[3:0] Input full-scale control
0xD
R/W
0000
1010
1011
1100
1101
1110
1111
0x1A4C
Channel
[7:6] Reserved
0x0
0xC
R
map Buffer
Control 1
[5:0] Buffer Control 1
R/W
00110
01000
01010
01100
01110
10000
10010
10100
10110
0x1A4D
Channel
map Buffer
Control 2
[7:6] Reserved
Reserved.
Buffer Control 2.
120 μA.
160 μA.
200 μA.
240 μA.
280 μA.
320 μA.
360 μA.
0x0
0xC
R
[5:0] Buffer Control 2
R/W
00110
01000
01010
01100
01110
10000
10010
10100
10110
400 μA.
440 μA.
0x18E0
0x18E1
0x18E2
0x18E3
External
VCM Buffer
Control 1
[7:0] External VCM Buffer
Control 1
See the Input Common Mode section for
details.
0x0
0x0
0x0
R/W
R/W
R/W
External
VCM Buffer
Control 2
[7:0] External VCM Buffer
Control 2
See the Input Common Mode section for
details.
External
VCM Buffer
Control 3
[7:0] External VCM Buffer
Control 3
See the Input Common Mode section for
details.
External
VCM buffer
control
7
6
Reserved
Reserved.
0x0
0x0
R/W
R/W
External VCM buffer
External VCM buffer.
Enable.
Disable.
1
0
[5:0] External VCM buffer
current setting
See the Input Common Mode section for
details.
0x0
R/W
0x18E6
Temperature [7:1] Reserved
Reserved.
0x0
0x0
R/W
R/W
diode
0
Temperature diode export
Temperature diode export.
Enable.
Disable.
export
1
0
Rev. 0 | Page 105 of 107
AD6684
Data Sheet
APPLICATIONS INFORMATION
POWER SUPPLY RECOMMENDATIONS
EXPOSED PAD THERMAL HEAT SLUG
RECOMMENDATIONS
The AD6684 must be powered by the following seven supplies:
AVDD1 = AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V,
DVDD = 0.975 V, DRVDD1 = 0.975 V, and SPIVDD = 1.8 V. For
applications requiring an optimal high power efficiency and low
noise performance, it is recommended that the ADP5054 quad
switching regulator be used to convert the 6.0 V or 12 V input rails
to intermediate rails (1.3 V, 2.4 V, and 3.0 V). These intermediate
rails are then postregulated by very low noise, low dropout (LDO)
regulators (ADP1762, ADP7159, ADP151, and ADP7118).
Figure 104 shows the recommended power supply scheme for
the AD6684.
It is required that the exposed pad on the underside of the ADC
be connected to AGND to achieve the best electrical and
thermal performance of the AD6684. Connect an exposed
continuous copper plane on the PCB to the AD6684 exposed
pad, Pin 0. The copper plane must have several vias to achieve
the lowest possible resistive thermal path for heat dissipation to
flow through the bottom of the PCB. These vias must be solder
filled or plugged. The number of vias and the fill determine the
resultant θJA measured on the board (see Table 7).
See Figure 105 for a PCB layout example. For detailed
information on packaging and the PCB layout of chip scale
packages, see the AN-772 Application Note, A Design and
Manufacturing Guide for the Lead Frame Chip Scale Package
(LFCSP).
6V/12V
INPUT
AVDD1: 0.95V
1.3V
ADP1762
(LDO)
FILTER
AVDD1_SR: 0.95V
DVDD: 0.95V
1.3V
ADP1762
(LDO)
ADP5054
(SWITCHING
REGULATOR)
FILTER
2.4V
3.0V
FILTER
FILTER
FILTER
DRVDD1: 0.95V
AVDD2: 1.8V
ADP7159
(LDO)
AVDD3: 2.5V
ADP7159
(LDO)
DRVDD2: 1.8V
SPIVDD: 1.8V
ADP151
(LDO)
FILTER
FILTER
ADP7118
(LDO)
Figure 104. High Efficiency, Low Noise Power Solution for the AD6684
It is not necessary to split all of these power domains in all cases.
The recommended solution shown in Figure 104 provides the
lowest noise, highest efficiency power delivery system for the
AD6684. If only one 0.975 V supply is available, route to AVDD1
first and then tap it off and isolate it with a ferrite bead or a
filter choke, preceded by decoupling capacitors for AVDD1_SR,
DVDD, and DRVDD, in that order. The user can employ several
different decoupling capacitors to cover both high and low
frequencies. These capacitors must be located close to the point
of entry at the PCB level and close to the devices, with minimal
trace lengths.
Figure 105. Recommended PCB Layout of Exposed Pad for the AD6684
AVDD1_SR (PIN 64) AND AGND_SR (PIN 63 AND
PIN 67)
AVDD1_SR (Pin 64) and AGND_SR (Pin 63 and Pin 67) can be
used to provide a separate power supply node to the SYSREF
circuits of the AD6684. If running in Subclass 1, the AD6684
can support periodic one-shot or gapped signals. To minimize
the coupling of this supply into the AVDD1 supply node,
adequate supply bypassing is needed.
Rev. 0 | Page 106 of 107
Data Sheet
AD6684
OUTLINE DIMENSIONS
10.10
10.00 SQ
9.90
0.60
0.42
0.24
0.30
0.23
0.18
0.60
0.42
0.24
PIN 1
INDICATOR
55
54
72
1
PIN 1
INDICATOR
9.85
0.50
BSC
9.75 SQ
9.65
7.45
7.30 SQ
7.15
EXPOSED
PAD
0.50
0.40
0.30
18
19
37
36
0.20 MIN
TOP VIEW
BOTTOM VIEW
8.50 REF
0.80 MAX
0.65 NOM
12° MAX
1.00
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.85
0.80
0.05 MAX
0.02 NOM
SEATING
PLANE
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
0.20 NOM
COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4
Figure 106. 72-Lead Lead Frame Chip Scale Package [LFCSP]
10 mm × 10 mm Body and 0.85 mm Package Height
(CP-72-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Junction Temperature Range
Package Description
Package Option
CP-72-10
CP-72-10
AD6684BCPZ-500
AD6684BCPZRL7-500
AD6684-500EBZ
−40°C to +105°C
−40°C to +105°C
72-Lead Lead Frame Chip Scale Package [LFCSP]
72-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board for AD6684
1 Z = RoHS Compliant Part.
©2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14994-0-10/16(0)
Rev. 0 | Page 107 of 107
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