AD674BJN [ADI]
Complete 12-Bit A/D Converters; 完整的12位A / D转换器
| 型号： | AD674BJN |
| 厂家： | 
ADI |
| 描述： | Complete 12-Bit A/D Converters |
| 文件： | 总12页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Complete 12-Bit
A/D Converters
a
AD674B*/AD774B*
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Complete Monolithic 12-Bit A/D Converters with
Reference, Clock, and Three-State Output Buffers
Industry Standard Pinout
High Speed Upgrades for AD574A
8- and 16-Bit Microprocessor Interface
8 ꢁs (Max) Conversion Time (AD774B)
15 ꢁs (Max) Conversion Time (AD674B)
ꢂ5 V, ꢂ10 V, 0 V–10 V, 0 V–20 V Input Ranges
Commercial, Industrial, and Military Temperature
Range Grades
5V SUPPLY
STATUS
STS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
V
LOGIC
DATA MODE SELECT
12/8
MSB
N
DB11 (MSB)
DB10
DB9
CHIP SELECT
CS
Y
B
B
L
CONTROL
3
3
BYTE ADDRESS/
4
SHORT CYCLE A
S
T
A
T
E
0
E
READ/CONVERT R/C
5
DB8
12
CLOCK
SAR
COMP
A
CHIP ENABLE
CE
6
DB7
N
Y
B
B
L
–
+
12V/15V SUPPLY
O
U
T
P
U
T
7
DB6
V
DIGITAL
DATA
OUTPUTS
CC
10V
I DAC
10V REFERENCE
REF
8
DB5
REF OUT
E
MIL-STD-883-Compliant Versions Available
ANALOG COMMON
AC
9
DB4
B
REFERENCE INPUT
N
Y
B
B
L
B
U
F
10
11
12
13
14
DB3
REF IN
I REF
–12V/–15V SUPPLY
199.95
kꢀ
+
–
DB2
F
V
EE
E
R
S
BIPOLAR OFFSET
E
DB1
BIPOFF
DAC
10V SPAN INPUT
VEE
C
N
DB0 (LSB)
10V
IN
LSB
20V SPAN INPUT
DIGITAL
COMMON DC
VOLTAGE
DIVIDER
20V
IN
AD674B/AD774B
PRODUCT DESCRIPTION
PRODUCT HIGHLIGHTS
The AD674B and AD774B are complete 12-bit successive-
approximation analog-to-digital converters with three-state
output buffer circuitry for direct interface to 8- and 16-bit
microprocessor busses. A high-precision voltage reference and
clock are included on chip, and the circuit requires only power
supplies and control signals for operation.
1. Industry Standard Pinout: The AD674B and AD774B use
the pinout established by the industry standard AD574A.
2. Analog Operation: The precision, laser-trimmed scaling and
bipolar offset resistors provide four calibrated ranges: 0 V to
10 V and 0 V to 20 V unipolar; –5 V to +5 V and –10 V to
+10 V bipolar. The AD674B and AD774B operate on +5 V
and 12 V or 15 V power supplies.
The AD674B and AD774B are pin-compatible with the indus-
try standard AD574A, but offer faster conversion time and bus-
access speed than the AD574A and lower power consumption.
The AD674B converts in 15 µs (maximum) and the AD774B
converts in 8 µs (maximum).
3. Flexible Digital Interface: On-chip multiple-mode three-state
output buffers and interface logic allow direct connection to
most microprocessors. The 12 bits of output data can be
read either as one 12-bit word or as two 8-bit bytes (one with
8 data bits, the other with 4 data bits and 4 trailing zeros).
The monolithic design is implemented using Analog Devices’
BiMOS II process allowing high-performance bipolar analog
circuitry to be combined on the same die with digital CMOS logic.
Offset, linearity, and scaling errors are minimized by active
laser trimming of thin-film resistors.
4. The internal reference is trimmed to 10.00 V with 1% maxi-
mum error and 10 ppm/°C typical temperature coefficient.
The reference is available externally and can drive up to
2.0 mA beyond the requirements of the converter and bipo-
lar offset resistors.
Five different grades are available. The J and K grades are
specified for operation over the 0°C to 70°C temperature range.
The A and B grades are specified from –40°C to +85°C, the T grade
is specified from –55°C to +125°C. The J and K grades are
available in a 28-lead plastic DIP or 28-lead SOIC. All other grades
are available in a 28-lead hermetically sealed ceramic DIP.
5. The AD674B and AD774B are available in versions compli-
ant with MIL-STD-883. Refer to the Analog Devices Mili-
tary Products Databook or current AD674B/AD774B/883B
data sheet for detailed specifications.
*Protected by U.S. Patent Nos. 4,250,445; 4,808,908; RE30586.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
(TMIN to TMAX with VCC = +15 V ꢂ 10% or +12 V ꢂ 5%,
VLOGIC = +5 V ꢂ 10%, VEE = –15 V ꢂ 10% or –12 V ꢂ 5%, unless otherwise noted.)
AD674B/AD774B–SPECIFICATIONS
J Grade
K Grade
A Grade
B Grade
T Grade
Model (AD674B or AD774B)
Min Typ Max Min Typ Max Min Typ Max Min Typ Max Min Typ Max
Unit
RESOLUTION
12
12
12
12
12
Bits
LINEARITY ERROR @ 25°C
TMIN to TMAX
ꢂ1
ꢂ1
ꢂ1/2
ꢂ1/2
ꢂ1
ꢂ1
ꢂ1/2
ꢂ1/2
ꢂ1/2
ꢂ1
LSB
LSB
DIFFERENTIAL LINEARITY ERROR
(Minimum Resolution for Which No
Missing Codes are Guaranteed)
12
12
12
12
12
Bits
LSB
LSB
UNIPOLAR OFFSET1 @ 25°C
BIPOLAR OFFSET1 @ 25°C
ꢂ2
ꢂ6
ꢂ2
ꢂ3
ꢂ2
ꢂ6
ꢂ2
ꢂ3
ꢂ2
ꢂ3
FULL-SCALE CALIBRATION ERROR1, 2
@ 25°C (with Fixed 50 Ω Resistor
from REF OUT to REF IN)
0.1 0.25
0.1 0.125
0.1 0.25
0.1 0.125
0.1 0.125
% of FS
TEMPERATURE RANGE
0
70
0
70
–40
+85
–40
+85
–55
+125
°C
TEMPERATURE DRIFT3
(Using Internal Reference)
Unipolar
ꢂ2
ꢂ2
ꢂ6
ꢂ1
ꢂ1
ꢂ2
ꢂ2
ꢂ2
ꢂ8
ꢂ1
ꢂ1
ꢂ5
ꢂ1
ꢂ2
ꢂ7
LSB
LSB
LSB
Bipolar Offset
Full-Scale Calibration
POWER SUPPLY REJECTION
Max Change in Full-Scale Calibration
V
CC = +15 V 1.5 V or +12 V 0.6 V
ꢂ2
ꢂ1/2
ꢂ2
ꢂ1
ꢂ1/2
ꢂ1
ꢂ2
ꢂ1/2
ꢂ2
ꢂ1
ꢂ1/2
ꢂ1
ꢂ1
ꢂ1/2
ꢂ1
LSB
LSB
LSB
VLOGIC = +5 V 0.5 V
VEE = –15 V 1.5 V or –12 V 0.6 V
ANALOG INPUT
Input Ranges
Bipolar
–5
–10
0
+5
+10 –10
10
20
–5
+5
+10
10
–5
–10
0
+5
+10
10
–5
–10
0
+5
+10
10
–5
–10
0
+5
+10
10
V
V
V
V
Unipolar
0
0
0
20
0
20
0
20
0
20
Input Impedance
10 V Span
20 V Span
3
6
5
10
7
14
3
6
5
7
3
6
5
7
3
6
5
7
3
6
5
7
kΩ
kΩ
10 14
10 14
10 14
10 14
POWER SUPPLIES
Operating Range
VLOGIC
VCC
VEE
4.5
11.4
–16.5
5.5
16.5 11.4
–11.4 –16.5
4.5
5.5
4.5
5.5
16.5
–11.4 –16.5
4.5
11.4
5.5
16.5
–11.4 –16.5
4.5
11.4
5.5
16.5
–11.4
V
V
V
16.5 11.4
–11.4 –16.5
Operating Current
ILOGIC
ICC
IEE
3.5
3.5
10
7
7
14
3.5
3.5
10 14
7
7
3.5
3.5
10 14
7
7
3.5
3.5
10
7
7
14
3.5
3.5
10 14
7
7
mA
mA
mA
POWER CONSUMPTION
220 375
175
220 375
175
220 375
175
220 375
175
220 375
175
mW4
mW5
INTERNAL REFERENCE VOLTAGE
Output Current
(Available for External Loads)
(External Load Should Not
Change During the Conversion)
9.9 10.0 10.1 9.9 10.0 10.1
2.0 2.0
9.9 10.0 10.1
9.9
10.0 10.1
9.9
10.0 10.1
V
2.0
2.0
2.0
mA
NOTES
1Adjustable to zero.
2Includes internal voltage reference error.
3Maximum change from 25°C value to the value at TMIN or TMAX
.
4Tested with REF OUT tied to REF IN through 50 Ω resistor, VCC = +16.5 V, VEE = –16.5 V, VLOGIC = +5.5 V, and outputs in high-Z mode.
5Tested with REF OUT tied to REF IN through 50 Ω resistor, VCC = +12 V, VEE = –12 V, VLOGIC = +5 V, and outputs in high-Z mode.
Specifications subject to change without notice.
Specifications shown in boldface are tested on all devices at final electrical test at TMIN, 25°C, and TMAX. Results from those tests are used to calculate outgoing quality levels. All min and
max specifications are guaranteed, although only those shown in boldface are tested.
–2–
REV. C
AD674B/AD774B
(For all grades TMIN to TMAX with VCC = +15 V ꢂ 10% or +12 V ꢂ 5%, VLOGIC = +5 V ꢂ 10%,
VEE = –15 V ꢂ 10% or –12 V ꢂ 5%, unless otherwise noted.)
DIGITAL SPECIFICATIONS
Parameter
Test Conditions
Min
Max
Unit
LOGIC INPUTS
VIH
VIL
IIH
IIL
CIN
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
2.0
VLOGIC + 0.5
V
V
µA
µA
pF
–0.5
–10
–10
+0.8
+10
+10
10
VIN = VLOGIC
VIN = 0 V
LOGIC OUTPUTS
VOH
VOL
IOZ
High Level Output Voltage
IOH = 0.5 mA
IOL = 1.6 mA
VIN = 0 to VLOGIC
2.4
V
V
µA
pF
Low Level Output Voltage
High-Z Leakage Current
High-Z Output Capacitance
0.4
+10
10
–10
COZ
(For all grades TMIN to TMAX with VCC = +15 V ꢂ 10% or +12 V ꢂ 5%,
VLOGIC = +5 V ꢂ 10%, VEE = –15 V ꢂ 10% or –12 V ꢂ 5%, unless otherwise noted.)
SWITCHING SPECIFICATIONS
CONVERTER START TIMING (Figure 1)
CE
tHEC
tHSC
J, K, A, B Grades
Symbol Min Typ Max Min Typ Max Unit
T Grade
tSSC
tSRC tHRC
CS
Parameter
Conversion Time
R/C
8-Bit Cycle (AD674B) tC
12-Bit Cycle (AD674B) tC
8-Bit Cycle (AD774B) tC
12-Bit Cycle (AD774B) tC
6
9
4
6
8
10
6
9
4
6
8
10
µs
µs
µs
µs
12 15
5
7.3
12 15
5
7.3
A
0
tHAC
6
8
200
6
8
tSAC
STS Delay from CE
CE Pulsewidth
CS to CE Setup
tDSC
tHEC
tSSC
225 ns
STS
50
50
50
50
50
0
50
50
50
50
50
0
ns
ns
ns
ns
ns
ns
ns
tC
tDSC
HIGH
IMPEDANCE
DB11 – DB0
CS Low During CE High tHSC
R/C to CE Setup tSRC
R/C LOW During CE High tHRC
A0 to CE Setup tSAC
A0 Valid During CE High tHAC
Figure 1. Convert Start Timing
CE
50
50
tHSR
tSSR
CS
READ TIMING—FULL CONTROL MODE (Figure 2)
J, K, A, B Grades T Grade
R/C
tSRR
tHRR
Parameter
Symbol Min Typ Max Min Typ Max Unit
A
0
tHAR
tSAR
Access Time
1
CL = 100 pF
tDD
75 150
150
75 150 ns
STS
tHD
DATA
VALID
Data Valid After CE Low tHD
252
203
252
154
ns
ns
150 ns
HIGH
IMPEDANCE
HIGH
DB11 – DB0
IMPEDANCE
tDD
5
Output Float Delay
CS to CE Setup
R/C to CE Setup
tHL
tHL
tSSR
tSRR
tSAR
tHSR
tHRR
tHAR
50
0
50
0
0
50
50
0
50
0
0
50
ns
ns
ns
ns
ns
ns
Figure 2. Read Cycle Timing
5V
A0 to CE Setup
CS Valid After CE Low
R/C High After CE Low
A0 Valid After CE Low
3kꢀ
DB
DB
N
N
100pF
100pF
3kꢀ
NOTES
HIGH-Z TO LOGIC 1
HIGH-Z TO LOGIC 0
1tDD is measured with the load circuit of Figure 3a and is defined as the time required
for an output to cross 0.4 V or 2.4 V.
High-Z to Logic 1
High-Z to Logic 0
20°C to TMAX
3At –40°C.
4At –55°C.
.
Figure 3a. Load Circuit for Access Time Test
5V
5tHL is defined as the time required for the data lines to change 0.5 V when loaded with
the circuit of Figure 3b.
3kꢀ
DB
DB
N
N
Specifications shown in boldface are tested on all devices at final electrical test with
worst case supply voltages at TMIN, 25°C, and TMAX. Results from those tests are used
to calculate outgoing quality levels. All min and max specifications are guaranteed,
although only those shown in boldface are tested.
100pF
100pF
3kꢀ
LOGIC 1 TO HIGH-Z
LOGIC 0 TO HIGH-Z
Logic 1 to High-Z
Logic 0 to High-Z
Specifications subject to change without notice.
Figure 3b. Load Circuit for Output Float Delay Test
REV. C
–3–
AD674B/AD774B
TIMING—STAND ALONE MODE (Figures 4a and 4b)
tHRL
J, K, A, B Grades
Symbol Min Typ Max Min Typ Max Unit
T Grade
R/C
Parameter
tDS
Data Access Time
Low R/C Pulsewidth
STS Delay from R/C
Data Valid After R/C Low tHDR
STS Delay After Data Valid tHS
tDDR
tHRL
tDS
150
200
150 ns
ns
225 ns
ns
50
50
25
STS
25
30
tC
200 600
30 200 600 ns
tHS
High R/C Pulsewidth
tHRH
150
150 ns
tHDR
HIGH–Z
DATA
VALID
Specifications subject to change without notice.
DB11–DB0
DATA VALID
ABSOLUTE MAXIMUM RATINGS*
VCC to Digital Common . . . . . . . . . . . . . . . . . . . 0 to +16.5 V
Flgure 4a. Standalone Mode Timing Low Pulse R/C
VEE to Digital Common . . . . . . . . . . . . . . . . . . . . 0 to –16.5 V
V
LOGIC to Digital Common . . . . . . . . . . . . . . . . . . . 0 to +7 V
Analog Common to Digital Common . . . . . . . . . . . . . . . 1 V
Digital Inputs to Digital Common . . . –0.5 V to VLOGIC +0.5 V
Analog Inputs to Analog Common . . . . . . . . . . . . VEE to VCC
20 VIN to Analog Common . . . . . . . . . . . . . . . . . . . . . . 24 V
REF OUT . . . . . . . . . . . . . . . . . . Indefinite Short to Common
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Momentary Short to VCC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 mW
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
R/C
tHRH
tDS
STS
tC
tDDR
tHDR
HIGH–Z
HIGH–Z
DATA
VALID
DB11–DB0
tHL
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
Figure 4b. Standalone Mode Timing High Pulse for R/C
ORDERING GUIDE
Conversion
Time (max) (TMIN to TMAX
INL
Package
Description
Package
Option2
Modell
Temperature
)
AD674BJN
AD674BKN
AD674BAR
AD674BBR
AD674BAD
AD674BBD
AD674BTD
AD774BJN
AD774BKN
AD774BAR
AD774BBR
AD774BAD
AD774BBD
AD774BTD
0°C to 70°C
15 µs
15 µs
15 µs
15 µs
15 µs
15 µs
15 µs
8 µs
1 LSB
1/2 LSB
1 LSB
1/2 LSB
1 LSB
1/2 LSB
1 LSB
1 LSB
1/2 LSB
1 LSB
1/2 LSB
Plastic DIP
Plastic DIP
N-28
N-28
R-28
R-28
D-28
D-28
D-28
N-28
N-28
R-28
R-28
D-28
D-28
D-28
0°C to 70°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
0°C to 70°C
Plastic SOIC
Plastic SOIC
Ceramic DIP
Ceramic DIP
Ceramic DIP
Plastic DIP
0°C to 70°C
8 µs
Plastic DIP
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
8 µs
Plastic SOIC
Plastic SOIC
Ceramic DIP
Ceramic DIP
Ceramic DIP
8 µs
8 µs
1 LSB
1/2 LSB
1 LSB
8 µs
8 µs
NOTES
1For details on grade and package offerings screened in accordance with MIL-STD-883, refer to the Analog Devices Military
Products Databook or the current AD674B/ AD774B/883B data sheet.
2N = Plastic DIP; D = Hermetic DIP; R = Plastic SOIC.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD674B/AD774B features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–4–
REV. C
AD674B/AD774B
DEFINITION OF SPECIFICATIONS
Quantization Uncertainty
Linearity Error
Analog-to-digital converters exhibit an inherent quantization
uncertainty of 1/2 LSB. This uncertainty is a fundamental
characteristic of the quantization process and cannot be reduced
for a converter of given resolution.
Linearity error refers to the deviation of each individual code
from a line drawn from “zero” through “full scale.” The point
used as “zero” occurs 1/2 LSB (1.22 mV for 10 V span) before
the first code transition (all zeroes to only the LSB “on”). “Full
scale” is defined as a level 1 1/2 LSB beyond the last code tran-
sition (to all ones). The deviation of a code from the true straight
line is measured from the middle of each particular code.
Left-Justified Data
The output data format is left-justified. This means that the
data represents the analog input as a fraction of full scale, rang-
ing from 0 to 4095/4096. This implies a binary point 4095 to
the left of the MSB.
The K, B, and T grades are guaranteed for maximum nonlinear-
ity of 1/2 LSB. For these grades, this means that an analog
value that falls exactly in the center of a given code width will
result in the correct digital output code. Values nearer the upper
or lower transition of the code width may produce the next upper
or lower digital output code. The J and A grades are guaranteed
to 1 LSB max error. For these grades, an analog value that
falls within a given code width will result in either the correct
code for that region or either adjacent one.
Full-Scale Calibration Error
The last transition (from 1111 1111 1110 to 1111 1111 1111)
should occur for an analog value 1 1/2 LSB below the nominal
full scale (9.9963 V for 10.000 V full scale). The full-scale cali-
bration error is the deviation of the actual level at the last transi-
tion from the ideal level. This error, which is typically 0.05% to
0.1% of full scale, can be trimmed out as shown in Figures 7
and 8. The full-scale calibration error over temperature is given
with and without the initial error trimmed out. The temperature
coefficients for each grade indicate the maximum change in the
full-scale gain from the initial value using the internal 10 V
reference.
Note that the linearity error is not user adjustable.
Differential Linearity Error (No Missing Codes)
A specification that guarantees no missing codes requires that
every code combination appear in a monotonic increasing sequence
as the analog input level is increased. Thus every code must have a
finite width. The AD674B and AD774B guarantee no missing codes
to 12-bit resolution, requiring that all 4096 codes must be present
over the entire operating temperature ranges.
Temperature Drift
The temperature drift for full-scale calibration, unipolar offset,
and bipolar offset specifies the maximum change from the initial
(25°C) value to the value at TMIN or TMAX
.
Unipolar Offset
Power Supply Rejection
The first transition should occur at a level 1/2 LSB above analog
common. Unipolar offset is defined as the deviation of the actual
transition from that point. This offset can be adjusted as discussed
later. The unipolar offset temperature coefficient specifies the
maximum change of the transition point over temperature,
with or without external adjustment.
The standard specifications assume use of +5.00 V and 15.00 V
or 12.00 V supplies. The only effect of power supply error on
the performance of the device will be a small change in the
full-scale calibration. This will result in a linear change in all
low-order codes. The specifications show the maximum full-
scale change from the initial value with the supplies at the
various limits.
Bipolar Offset
In the bipolar mode the major carry transition (0111 1111 1111
to 1000 0000 0000) should occur for an analog value 1/2 LSB
below analog common. The bipolar offset error and temperature
coefficient specify the initial deviation and maximum change in
the error over temperature.
Code Width
A fundamental quantity for A/D converter specifications is the
code width. This is defined as the range of analog input values for
which a given digital output code will occur. The nominal value
of a code width is equivalent to 1 least significant bit (LSB) of the
full-scale range or 2.44 mV out of 10 V for a 12-bit ADC.
REV. C
–5–
AD674B/AD774B
PIN CONFIGURATION
V
1
2
STS
28
LOGIC
27 DB11 (MSB)
26 DB10
12/8
3
CS
4
A
25 DB9
0
AD674B
OR
5
24 DB8
R/C
6
23
22
21
20
19
18
17
16
15
CE
DB7
AD774B
7
V
DB6
CC
TOPVIEW
(Not to Scale)
8
REF OUT
AGND
DB5
9
DB4
10
11
12
13
14
REF IN
DB3
V
DB2
EE
BIP OFF
DB1
10V
DB0 (LSB)
DGND
IN
IN
20V
PIN FUNCTION DESCRIPTIONS
Pin No. Type* Name and Function
Symbol
AGND
A0
9
4
P
DI
Analog Ground (Common)
Byte Address/Short Cycle. If a conversion is started with A0 Active LOW, a full 12-bit conversion
cycle is initiated. If A0 is Active HIGH during a convert start, a shorter 8-bit conversion cycle
results. During Read (R/C = 1) with 12/8 LOW, A0 = LOW enables the 8 most significant bits,
and A0 = HIGH enables DB3–DB0 and sets DB7–DB4 = 0.
BIP OFF
12
AI
Bipolar Offset. Connect through a 50 Ω resistor to REF OUT for bipolar operation or to Analog
Common for unipolar operation.
CE
6
3
DI
DI
Chip Enable. Chip Enable is Active HIGH and is used to initiate a convert or read operation.
CS
Chip Select. Chip Select is Active LOW.
DB11–DB8 27–24
DO
Data Bits 11 through 8. In the 12-bit format (see 12/8 and A0 pins) these pins provide the upper
4 bits of data. In the 8-bit format, they provide the upper 4 bits when A0 is LOW and are
disabled when A0 is HIGH.
DB7–DB4 23–20
DB3–DB0 19–16
DO
DO
Data Bits 7 through 4. In the 12-bit format these pins provide the middle 4 bits of data. In the
8-bit format they provide the middle 4 bits when A0 is LOW and all zeroes when A0 is HIGH.
Data Bits 3 through 0. In both the 12-bit and 8-bit format these pins provide the lower 4 bits of
data when A0 is HIGH; they are disabled when A0 is LOW.
DGND
REF OUT
R/C
15
8
P
Digital Ground (Common)
AO
DI
10 V Reference Output
5
Read/Convert. In the full control mode R/C is Active HIGH for a read operation and Active LOW
for a convert operation. In the standalone mode, the falling edge of R/C initiates a conversion.
Reference Input is connected through a 50 Ω resistor to +10 V Reference for normal operation.
REF IN
STS
10
28
AI
DO
Status is Active HIGH when a conversion is in progress and goes LOW when the conversion is
completed.
VCC
7
P
+12 V/+15 V Analog Supply
VEE
11
1
P
–12 V/–15 V Analog Supply
VLOGIC
10 VIN
P
5 V Logic Supply
13
AI
10 V Span Input, 0 V to +10 V unipolar mode or –5 V to +5 V bipolar mode. When using the
20 V Span, 10 VIN should not be connected.
20 VIN
14
2
AI
20 V Span Input, 0 V to +20 V unipolar mode or –10 V to +10 V bipolar mode. When using the
10 V Span, 20 VIN should not be connected.
The 12/8 pin determines whether the digital output data is to be organized as two 8-bit words
(12/8 LOW) or a single 12-bit word (12/8 HIGH).
12/8
DI
*Types: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO = Digital Output, P = Power
–6–
REV. C
AD674B/AD774B
CIRCUIT OPERATION
DRIVING THE ANALOG INPUT
The AD674B and AD774B are complete 12-bit monolithic A/D
converters that require no external components to provide the
complete successive-approximation analog-to-digital conversion
function. A block diagram is shown in Figure 5.
The AD674B and AD774B are successive-approximation analog-
to-digital converters. During the conversion cycle, the ADC input
current is modulated by the DAC test current at approximately
a 1 MHz rate. Thus it is important to recognize that the signal
source driving the ADC must be capable of holding a constant
output voltage under dynamically changing load conditions.
5V SUPPLY
STATUS
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
V
LOGIC
STS
DATA MODE SELECT
12/8
CHIP SELECT
CS
BYTE ADDRESS/
SHORT CYCLE A
MSB
N
DB11 (MSB)
FEEDBACKTO AMPLIFIER
V+
Y
B
B
L
CONTROL
3
DB10
DB9
3
4
S
T
A
T
E
0
E
READ/CONVERT R/C
5
DB8
12
CLOCK
SAR
COMP
A
CHIP ENABLE
CE
12V/15V SUPPLY
6
DB7
N
Y
B
B
L
–
ADC
O
U
T
P
U
T
7
DB6
+
V
DIGITAL
DATA
OUTPUTS
CURRENT
LIMITING
RESISTORS
CC
10V
I DAC
10V REFERENCE
REF
8
DB5
REF OUT
E
I
R
IN
IN
CURRENT
OUTPUT
DAC
ANALOG COMMON
AC
9
DB4
B
I
I
REFERENCE INPUT
N
Y
B
B
L
DIFF
B
U
F
TEST
10
11
12
13
14
DB3
IIN IS MODULATED BY
REF IN
I REF
COMPARATOR
–12V/–15V SUPPLY
CHANGES IN TEST CURRENT.
AMPLIFIER PULSE LOAD
199.95
kꢀ
+
DB2
F
V
EE
–
E
R
S
BIPOLAR OFFSET
RESPONSE LIMITED BY
E
DB1
BIPOFF
OPEN-LOOP OUTPUT IMPEDANCE.
DAC
V–
10V SPAN INPUT
VEE
C
N
DB0 (LSB)
10V
IN
LSB
SAR
ANALOG COMMON
20V SPAN INPUT
DIGITAL
COMMON DC
VOLTAGE
DIVIDER
20V
IN
AD674B/AD774B
Figure 6. Op Amp—ADC Interface
Figure 5. Block Diagram of AD674B and AD774B
The closed-loop output impedance of an op amp is equal to the
open-loop output impedance (usually a few hundred ohms)
divided by the loop gain at the frequency of interest. It is often
assumed that the loop gain of a follower-connected op amp is
sufficiently high to reduce the closed-loop output impedance to
a negligibly small value, particularly if the signal is low fre-
quency. However, the amplifier driving the ADC must either
have sufficient loop gain at 1 MHz to reduce the closed-loop
output impedance to a low value or have low open-loop output
impedance. This can be accomplished by using a wideband op
amp, such as the AD711.
When the control section is commanded to initiate a conversion
(as described later) it enables the clock and resets the
successive-approximation register (SAR) to all zeroes. Once a
conversion cycle has begun, it cannot be stopped or restarted
and data is not available from the output buffers. The SAR,
timed by the clock, will sequence through the conversion cycle
and return an end-of-convert flag to the control section. The
control section will then disable the clock, bring the output
status flag low, and enable control functions to allow data read
by external command.
If a sample-hold amplifier is required, the monolithic AD585 or
AD781 is recommended, with the output buffer driving the
AD674B or AD774B input directly. A better alternative is the
AD1674, which is a 10 µs sampling ADC in the same pinout as the
AD574A, AD674A, or AD774B and is functionally equivalent.
During the conversion cycle, the internal 12-bit current output
DAC is sequenced by the SAR from the most significant bit
(MSB) to least significant bit (LSB) to provide an output cur-
rent that accurately balances the input signal current through
the divider network. The comparator determines whether the
addition of each successively weighted bit current causes the
DAC current sum to be greater or less than the input current; if
the sum is less, the bit is left on; if more, the bit is turned off.
After testing all the bits, the SAR contains a 12-bit binary code
that accurately represents the input signal to within 1/2 LSB.
SUPPLY DECOUPLING AND LAYOUT
CONSIDERATION
It is critical that the power supplies be filtered, well regulated,
and free from high-frequency noise. Use of noisy supplies will
cause unstable output codes. Switching power supplies is not
recommended for circuits attempting to achieve 12-bit accuracy
unless great care is used in filtering any switching spikes present
in the output. Few millivolts of noise represent several counts of
error in a 12-bit ADC.
The temperature-compensated reference provides the primary
voltage reference to the DAC and guarantees excellent stability
with both time and temperature. The reference is trimmed to
10.00 V 1%; it can supply up to 2.0 mA to an external load in
addition to the requirements of the reference input resistor
(0.5 mA) and bipolar offset resistor (0.5 mA). Any external load
on the reference must remain constant during conversion. The
thin-film application resistors are trimmed to match the full-
scale output current of the DAC. The input divider network
provides a 10 V or 20 V input range. The bipolar offset resistor
is grounded for unipolar operation and connected to the 10 V
reference for bipolar operation.
Decoupling capacitors should be used on all power supply pins;
the 5 V supply decoupling capacitor should be connected directly
from Pin 1 to Pin 15 (digital common) and the +VCC and –VEE
pins should be decoupled directly to analog common (Pin 9). A
suitable decoupling capacitor is a 4.7 µF tantalum type in paral-
lel with a 0.1 µF ceramic disc type.
REV. C
–7–
AD674B/AD774B
Circuit layout should attempt to locate the ADC, associated
analog input circuitry, and interconnections as far as possible
from logic circuitry. For this reason, the use of wire-wrap circuit
construction is not recommended. Careful printed-circuit layout
and manufacturing is preferred.
UNIPOLAR CALIBRATION
The connections for unipolar ranges are shown in Figure 7. The
AD674B or AD774B is trimmed to a nominal 1/2 LSB offset so
that the exact analog input for a given code will be in the middle
of that code (halfway between the transitions to the codes above
and below it). Thus, when properly calibrated, the first transition
(from 0000 0000 0000 to 0000 0000 0001) will occur for an input
level of +1/2 LSB (1.22 mV for 10 V range).
UNIPOLAR RANGE CONNECTIONS FOR THE AD674B
AND AD774B
The AD674B and AD774B contain all the active components
required to perform a complete 12-bit A/D conversion. Thus,
for most situations, all that is necessary is connection of the
power supplies (+5 V, +12/+15 V, and –12/–15 V), the analog
input, and the conversion initiation command, as discussed on
the next page.
If Pin 12 is connected to Pin 9, the unit will behave in this manner,
within specifications. If the offset trim (R1) is used, it should be
trimmed as above, although a different offset can be set for a
particular system requirement. This circuit will give approximately
15 mV of offset trim range.
The full-scale trim is done by applying a signal 1 1/2 LSB below
the nominal full scale (9.9963 for a 10 V range). Trim R2 to
give the last transition (1111 1111 1110 to 1111 1111 1111).
AD674B/AD774B
OFFSET
R1
100kꢀ
2
3
4
5
STS 28
12/8
CS
A
0
–12V/
–15V
+12V/
+15V
HIGH BITS
BIPOLAR OPERATION
24–27
R/C
GAIN
The connections for bipolar ranges are shown in Figure 8.
Again, as for the unipolar ranges, if the offset and gain specifica-
tions are sufficient, one or both of the trimmers shown can be
replaced by a 50 Ω 1% fixed resistor. The analog input is
applied as for the unipolar ranges. Bipolar calibration is similar
to unipolar calibration. First, a signal 1/2 LSB above negative
full scale (–4.9988 V for the 5 V range) is applied and R1 is
trimmed to give the first transition (0000 0000 0000 to 0000
0000 0001). Then a signal 1 1/2 LSB below positive full scale
(+4.9963 V for the 5 V range) is applied and R2 trimmed to
give the last transition (1111 1111 1110 to 1111 1111 1111).
MIDDLE BITS
CE
6
20–23
R2
100ꢀ
100kꢀ
10 REF IN
LOW BITS
8
REF OUT
16–19
100ꢀ
12 BIP OFF
+5V
1
7
0TO 10V
10V
13
IN
+15V
ANALOG
INPUTS
14 20V
IN
–15V 11
0TO 20V
9
ANA COM
DIG COM 15
Figure 7. Unipolar Input Connections
AD674B/AD774B
All of the thin-film application resistors of the AD674B and
AD774B are factory trimmed for absolute calibration. Therefore,
in many applications, no calibration trimming will be required.
The absolute accuracy for each grade is given in the specification
tables. For example, if no trims are used, 2 LSB max zero offset
error and 0.25% (10 LSB) max full-scale error are guaranteed.
If the offset trim is not required, Pin 12 can be connected directly
to Pin 9; the two resistors and trimmer for Pin 12 are then not
needed. If the full-scale trim is not required, a 50 Ω 1% metal
film resistor should be connected between Pin 8 and Pin 10.
2
3
4
5
STS 28
12/8
CS
HIGH BITS
A
0
24–27
R/C
CE
MIDDLE BITS
6
R2
20–23
GAIN
10 REF IN
100ꢀ
LOW BITS
8
REF OUT
16–19
100ꢀ
R1
ꢂ5V
OFFSET
12 BIP OFF
+5V
1
7
+15V
10V
13
IN
ANALOG
INPUTS
14 20V
–15V 11
IN
The analog input is connected between Pins 13 and 9 for a 0 V
to 10 V input range, between Pins 14 and 9 for a 0 V to 20 V
input range. Input signals beyond the supplies are easily accommo-
dated. For the 10 V span input, the LSB has a nominal value of
2.44 mV; for the 20 V span, 4.88 mV. If a 10.24 V range is
desired (nominal 2.5 mV/bit), the gain trimmer (R2) should be
replaced by a 50 Ω resistor and a 200 Ω trimmer inserted in
series with the analog input to Pin 13 (for a full-scale range of
20.48 V [5 mV/bit] use a 500 Ω trimmer into Pin 14). The
gain trim described below is now done with these trimmers.
The nominal input impedance into Pin 13 is 5 kΩ, and into Pin
14 is 10 kΩ.
ꢂ10V
9
ANA COM
DIG COM 15
Figure 8. Bipolar Input Connections
GROUNDING CONSIDERATIONS
The analog common at Pin 9 is the ground reference point for
the internal reference and is thus the “high quality” ground for
the ADC; it should be connected directly to the analog reference
point of the system. To achieve the high-accuracy performance
available from the ADC in an environment of high digital noise
content, the analog and digital commons must be connected
together at the package. In some situations, the digital common
at Pin 15 can be connected to the most convenient ground ref-
erence point; digital power return is preferred.
–8–
REV. C
AD674B/AD774B
VALUE OF A AT LAST CONVERT COMMAND
0
Q
D
EOC 12
EOC 8
D
EN
EN
START CONVERT
R
S
Q
SAR
RESET
S
R
Q
QB
CE
HIGH IF CONVERSION
IN PROGRESS
CS
CLK EN
STATUS
R/C
NYBBLE A
ENABLE
A
0
NYBBLE B
ENABLE
READ
TO
OUTPUT
BUFFERS
NYBBLE C
ENABLE
12/8
NYBBLE = 0
ENABLE
Figure 9. Equivalent Internal Logic Circuitry
CONTROL LOGIC
Table I. Truth Table
The AD674B and AD774B contain on-chip logic to provide
conversion initiation and data read operations from signals
commonly available in microprocessor systems; this internal
logic circuitry is shown in Figure 9.
CE CS R/C 12/8 A0 Operation
0
X
1
1
1
1
1
X
1
0
0
0
0
0
X
X
0
0
1
X
X
X
X
1
X
X
0
1
X
0
None
None
The control signals CE, CS, and R/C control the operation of
the converter. The state of R/C when CE and CS are both
asserted determines whether a data read (R/C = 1) or a convert
(R/C = 0) is in progress. The register control inputs, A0 and
12/8, control conversion length and data format. If a conversion
is started with A0 low, a full 12-bit conversion cycle is initiated.
If A0 is high during a convert start, a shorter 8-bit conversion
cycle results. During data read operations, A0 determines
whether the three-state buffers containing the 8 MSBs of the
conversion result (A0 = 0) or the 4 LSBs (A0 = 1) are enabled.
The 12/8 pin determines whether the output data is to be orga-
nized as two 8-bit words (12/8 tied to DIGITAL COMMON)
or a single 12-bit word (12/8 tied to VLOGIC). In the 8-bit mode,
the byte addressed when A0 is high contains the 4 LSBs from
the conversion followed by four trailing zeroes. This organiza-
tion allows the data lines to be overlapped for direct interface to
8-bit buses without the need for external three-state buffers.
Initiate 12-Bit Conversion
Initiate 8-Bit Conversion
Enable 12-Bit Parallel Output
Enable 8 Most Significant Bits
Enable 4 LSBs + 4 Trailing Zeroes
1
1
0
0
1
The ADC may be operated in one of two modes, the full-control
mode and the standalone mode. The full-control mode uses all
the control signals and is useful in systems that address decode
multiple devices on a single data bus. The standalone mode is
useful in systems with dedicated input ports available. In gen-
eral, the standalone mode is capable of issuing start-convert
commands on a more precise basis and therefore produces
higher accuracy results. The following sections describe these
two modes in more detail.
FULL-CONTROL MODE
Chip Enable (CE), Chip Select (CS), and Read/Convert (R/C)
are used to control Convert or Read modes of operation. Either
CE or CS may be used to initiate a conversion. The state of R/C
when CE and CS are both asserted determines whether a data
Read (R/C = 1) or a Convert (R/C = 0) is in progress. R/C
should be LOW before both CE and CS are asserted; if R/C is
HIGH, a Read operation will momentarily occur, possibly
resulting in system bus contention.
An output signal, STS, indicates the status of the converter.
STS goes high at the beginning of a conversion and returns low
when the conversion cycle is complete.
REV. C
–9–
AD674B/AD774B
STANDALONE MODE
GENERAL A/D CONVERTER INTERFACE
“Standalone” mode is useful in systems with dedicated input
ports available and thus not requiring full bus interface capabil-
ity. Standalone mode applications are generally able to issue
conversion start commands more precisely than full-control
mode, resulting in improved accuracy.
CONSIDERATIONS
A typical A/D converter interface routine involves several opera-
tions. First, a write to the ADC address initiates a conversion.
The processor must then wait for the conversion cycle to com-
plete, since most integrated circuit ADCs take longer than one
instruction cycle to complete a conversion. Valid data can, of
course, only be read after the conversion is complete. The
AD674B and AD774B provide an output signal (STS) which
indicates when a conversion is in progress. This signal can be
polled by the processor by reading it through an external three-
state buffer (or other input port). The STS signal can also
generate an interrupt upon completion of conversion if the sys-
tem timing requirements are critical and the processor has other
tasks to perform during the ADC conversion cycle. Another
possible time-out method is to assume that the ADC will take its
maximum conversion time to convert, and insert a sufficient
number of “no-op” instructions to ensure that this amount of
processor time is consumed.
CE and 12/8 are wired HIGH, CS and A0 are wired LOW, and
conversion is controlled by R/C. The three-state buffers are
enabled when R/C is HIGH and a conversion starts when R/C
goes LOW. This gives rise to two possible control signals—a
high pulse or a low pulse. Operation with a low pulse is shown
in Figure 4a. In this case, the outputs are forced into the high
impedance state in response to the falling edge of R/C and
return to valid logic levels after the conversion cycle is completed.
The STS line goes HIGH 200 ns after R/C goes LOW and
returns low 600 ns after data is valid.
If conversion is initiated by a high pulse as shown in Figure 4b,
the data lines are enabled during the time when R/C is HIGH.
The falling edge of R/C starts the next conversion, and the data
lines return to three-state (and remain three-state) until the next
high pulse of R/C.
Once conversion is complete, the data can be read. For convert-
ers with more data bits than are available on the bus, a choice of
data formats is required, and multiple read operations are
needed. The AD674B and AD774B include internal logic to
permit direct interface to 8-bit and 16-bit data buses, selected
by the 12/8 input. In 16-bit bus applications (12/8 high) the
data lines (DB11 through DB0) may be connected to either the
12 most significant or 12 least significant bits of the data bus.
The remaining 4 bits should be masked in software. The inter-
face to an 8-bit data bus (12/8 low) is done in a left-justified for-
mat. The even address (A0 low) contains the 8 MSBs (DB11
through DB4). The odd address (A0 high) contains the 4 LSBs
(DB3 through DB0) in the upper half of the byte, followed by
four trailing zeroes, thus eliminating bit masking instructions.
CONVERSION TIMING
Once a conversion is started, the STS line goes HIGH. Convert
start commands will be ignored until the conversion cycle is
complete. The output data buffers can be enabled up to 1.2 µs
prior to STS going LOW. The STS line will return LOW at the
end of the conversion cycle.
The register control inputs, A0 and 12/8, control conversion
length and data format. If a conversion is started with A0 LOW,
a full 12-bit conversion cycle is initiated. If A0 is HIGH during a
convert start, a shorter 8-bit conversion cycle results.
During data read operations, A0 determines whether the three-
state buffers containing the 8 MSBs of the conversion result
(A0 = 0) or the 4 LSBs (A0 = 1) are enabled. The 12/8 pin
determines whether the output data is to be organized as two
8-bit words (12/8 tied LOW) or a single 12-bit word (12/8 tied
HIGH). In the 8-bit mode, the byte addressed when A0 is high
contains the 4 LSBs from the conversion followed by four trail-
ing zeroes. This organization allows the data lines to be over-
lapped for direct interface to 8-bit buses without the need for
external three-state buffers.
It is not possible to rearrange the output data lines for right-jus-
tified 8-bit bus interface.
D7
D0
XXX0 DB11
(EVEN ADDR) (MSB)
DB10 DB9 DB8 DB7 DB6 DB5 DB4
DB0
(LSB)
XXX1
(ODD ADDR)
DB3 DB2 DB1
0
0
0
0
Figure 10. Data Format for 8-Bit Bus
–10–
REV. C
AD674B/AD774B
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Ceramic DIP Package
(D-28)
0.05 (1.27)
0.045 (1.14)
0.050 (12.83)
28
1
15
30o
0.08 (2.0)
0.59
+
0.01
–
(14.98)
0.125 MIN (3.17)
SEATING
PLANE
14
0.085
(2.16)
+
1.42 (36.07)
1.40 (35.56)
0.145 0.02
–
0.095 (2.41)
(3.68)
+
0.010 0.002
–
+
(0.254 0.05)
0.050
–
+
0.010
–
(1.27)
+
0.1 (2.54)
0.6 (15.24)
0.017 0.003
–
+
0.047 0.007
(0.43)
–
(1.19)
28-Lead Plastic DIP Package
(N-28)
1.565 (39.70)
1.380 (35.10)
28
15
0.580 (14.73)
0.485 (12.32)
1
14
PIN 1
0.060 (1.52)
0.015 (0.38)
0.625 (15.87)
0.600 (15.24)
0.250
0.195 (4.95)
0.125 (3.18)
(6.35)
MAX
0.150
(3.81)
MIN
0.015 (0.381)
0.008 (0.204)
0.200 (5.05)
0.125 (3.18)
0.070
(1.77)
MAX
0.100
(2.54)
BSC
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
28-Lead Wide Body SOIC Package
(R-28)
0.7125 (18.10)
0.6969 (17.70)
28
15
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
1
14
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
ꢄ 45ꢃ
8ꢃ
0ꢃ
0.0500 0.0192 (0.49) SEATING
0.0118 (0.30)
0.0040 (0.10)
0.0500 (1.27)
0.0157 (0.40)
0.0125 (0.32)
0.0091 (0.23)
PLANE
(1.27)
BSC
0.0138 (0.35)
REV. C
–11–
AD674B/AD774B
Revision History
Location
Page
Data Sheet changed from REV. B to REV. C.
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Add 28-Lead Wide Body SOIC Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
–12–
REV. C
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