AD708AH_技术文档

Ultralow Offset Voltage

Dual Op Amp

a

AD708

FEATURES

Very High DC Precision

30 ␮V max Offset Voltage

CONNECTION DIAGRAMS

TO-99 (H) Package

0.3 ␮V/؇C max Offset Voltage Drift

0.35 ␮V p-p max Voltage Noise (0.1 Hz to 10 Hz)

5 Million V/V min Open Loop Gain

130 dB min CMRR

120 dB min PSRR

Matching Characteristics

30 ␮V max Offset Voltage Match

0.3 ␮V/؇C max Offset Voltage Drift Match

130 dB min CMRR Match

Single Version: AD707

Available in 8-Pin Plastic Mini-DIP,

Hermetic Cerdip and TO-99 Metal Can

Packages, Chips and /883B Parts Available.

Plastic (N ), and Cerdip (Q) Packages

PRODUCT DESCRIPTION

The AD708 is a very high precision, dual monolithic operational

amplifier. Each amplifier individually offers excellent dc precision

with the best available max offset voltage and offset voltage drift

of any dual bipolar op amp. In addition, the matching specifica-

tions are the best available in any dual op amp.

The AD708 sets a new standards for dual precision op amps by

providing 5 V/µV min open loop gain and guaranteed max input

voltage noise of 350 nV p-p (0.1 Hz to 10 Hz). All dc specifica-

tions show excellent stability over temperature, with offset

voltage drift typically 0.1 µV/°C and input bias current drift of

25 pA/°C max. Both CMRR (130 dB min) and PSRR (120 dB

min) are an order of magnitude improved over any available

single monolithic op amp except the AD707.

APPLICATION HIGHLIGHTS

1. The combination of outstanding matching and individual

specifications make the AD708 ideal for constructing high

gain, precision instrumentation amplifiers.

2. The low offset voltage drift and low noise of the AD708

allows the designer to amplify very small signals without

sacrificing overall system performance.

The AD708 is available in four performance grades. The

AD708J is rated over the commercial temperature range of 0°C

to +70°C and jis available in a plastic mini-DIP package. The

AD708A and AD708B are rated over the industrial temperature

range of –40°C to +85°C and are available in a cerdip and TO-

99 package. The AD708S is rated over the military temperature

range of –55°C to +125°C and is available in cerdip and TO-99

packages. Military versions are available processed to MIL-

STD-883B, Rev. C.

3. The AD708’s 10 V/µV typical open loop gain and 140 dB

common-mode rejection make it ideal for precision

applications.

4. Unmounted dice are available for hybrid circuit applications.

5. The AD708 is an improved replacement for the LT1002.

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700

Fax: 617/326-8703

(@ +25؇C and ؎15 V dc, unless otherwise noted)

AD708–SPECIFICATIONS

AD708J/A

Min Typ Max

AD708B

Min Typ

AD708S

Model

Conditions

Max

Min Typ

Max

Units

INPUT OFFSET VOLTAGE¹

30

50

0.3

100

150

1.0

5

50

65

0.4

5

30

50

0.3

µV

µV/°C

µV/Month

T_MINto T_MAX

15

0.1

0.3

15

0.1

0.3

Drift

Long Term Stability

INPUT BIAS CURRENT

1.0

2.0

15

2.5

4.0

40

0.5

1.0

10

1.0

2.0

25

0.5

1.0

10

1

4

30

nA

pA/°C

T_MINto T_MAX

Average Drift

OFFSET CURRENT

V_CM= 0 V

T_MINto T_MAX

0.5

2.0

2

2.0

4.0

60

0.1

0.2

1

1.0

1.5

25

0.1

0.2

1

1.5

25

nA

pA/°C

Average Drift

MATCHING CHARACTERISTICS²

Offset Voltage

80

50

30

µV

T_MINto T_MAX

150

1.0

4.0

5.0

75

50

µV

Offset Voltage Drift

Input Bias Current

0.4

1.0

2.0

0.3

1.0

2.0

µV/°C

nA

dB

T_MINto T_MAX

Common-Mode Rejection

Power Supply Rejection

120

110

135

140

130

120

140

130

120

140

dB

Channel Separation

INPUT VOLTAGE NOISE

0.1 Hz to 10 Hz

f = 10 Hz

f = 100 Hz

f = 1 kHz

0.23 0.6

10.3 18

10.0 13.0

0.23 0.6

10.3 12

10.0 11.0

0.23 0.35

10.3 12

10.0 11

µV p-p

nV/√Hz

9.6

11.0

9.6

11.0

9.6

11

INPUT CURRENT NOISE

0.1 Hz to 10 Hz

f = 10 Hz

f = 100 Hz

f = 1 kHz

14

35

14

35

14

35

pA p-p

pA/√Hz

0.32 0.9

0.14 0.27

0.12 0.18

0.32 0.8

0.14 0.23

0.12 0.17

0.32 0.8

0.14 0.23

0.12 0.17

COMMON-MODE

REJECTION RATIO

V_CM= ±13 V

T_MINto T_MAX

120

140

130

140

130

140

dB

OPEN-LOOP GAIN

V_O= ±10 V

R_LOAD≥ 2 kΩ

T_MINto T_MAX

3

10

5

10

4

10

7

V/µV

POWER SUPPLY

REJECTION RATIO

V_S= ±3 V to ±18 V 110

130

120

130

120

130

dB

T_MINto T_MAX

110

FREQUENCY RESPONSE

Closed Loop Bandwidth

Slew Rate

0.5

0.15 0.3

0.9

0.5

0.15 0.3

0.9

0.5

0.15 0.3

0.9

MHz

V/µs

INPUT RESISTANCE

Differential

Common Mode

60

200

400

200

400

MΩ

GΩ

OUTPUT VOLTAGE

R_LOAD≥ 10 kΩ

R_LOAD≥ 2 kΩ

R_LOAD≥ 1 kΩ

R_LOAD≥ 2 kΩ

T_MINto T_MAX

13.5 14

12.5 13.0

12.0 12.5

13.5 14.0

12.5 13.0

12.0 12.5

13.5 14

12.5 13

12.0 12.5

±V

12.0 13.0

60

12.0 13.0

60

12.0 13

±V

OPEN-LOOP OUTPUT

RESISTANCE

60

Ω

–2–

REV. B

AD708

AD708J/A

Min Typ

AD708B

Min Typ

AD708S

Min Typ

Model

Conditions

Max

Units

POWER SUPPLY

Quiescent Current

Power Consumption

4.5

5.5

4.5

5.5

4.5

5.5

mA

V_S= ±15 V

No Load

V_S= ±3 V

135

12

165

18

±18

135

12

165

18

±18

135

12

165

18

±18

mW

V

Operating Range

NOTES

±3

¹Input offset voltage specifications are guaranteed after 5 minutes of operation at T_A= +25°C.

²Matching is defined as the difference between parameters of the two amplifiers.

All min and max specifications are guaranteed. Specifications in boldface are tested on all production units at final electrical test. Results from those tests are used to

calculate outgoing quality levels.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS¹

METALIZATION PHOTOGRAPH

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±22 V

Dimensions shown in inches and (mm).

Internal Power Dissipation²

Contact factory for latest dimensions.

Input Voltage³. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±V_S

Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite

Differential Input Voltage . . . . . . . . . . . . . . . . . . +V_Sand –V_S

Storage Temperature Range (Q, H) . . . . . . . –65°C to +150°C

Storage Temperature Range (N) . . . . . . . . . –65°C to +125°C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C

NOTES

¹Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

²Thermal Characteristics

8-Pin Plastic Package:

8-Pin Cerdip package:

8-Pin Metal Can Package:

θ_JC= 33°C/Watt, θ_JA= 100°C/Watt

θ_JC= 30°C/Watt, θ_JA= 110°C/Watt

θ_JC= 65°C/Watt, θ_JA= 150°C/Watt.

³For supply voltages less than ±22 V, the absolute maximum input voltage is

equal to the supply voltage.

ORDERING GUIDE

Temperature

Range

Package

Description

Package

Option*

Model

AD708JN

AD708AQ

AD708BQ

AD708SQ

AD708AH

AD708BH

AD708SH

AD708SH/883B

AD708J Grade Chips

AD708S Grade Chips

0°C to +70°C

8-Pin Plastic DIP

8-Pin Cerdip

8-Pin Header

Die

N-8

Q-8

H-08A

–40°C to +85°C

–55°C to +125°C

–40°C to +85°C

–55°C to +125°C

0°C to +70°C

–55°C to +125°C

Die

*N = Plastic DIP; Q = Cerdip; H = Hermetic Metal Can.

–3–

REV. B

AD708–Typical Characteristics

(V_S= ؎15 V and T_A= +25؇C unless otherwise noted)

–4–

REV. B

AD708

π

REV. B

–5–

AD708–Matching Characteristics

Figure 18. Typical Distribution of Offset

Voltage Match

Figure 19. Typical Distribution of Offset

Voltage Drift Match

Figure 20. Typical Distribution of Input

Bias Current Match

Figure 21. Typical Distribution of Input

Offset Current Match

Figure 22. PSRR Match vs.

Temperature

Figure 23. CMRR Match vs.

Temperature

Crosstalk from Thermal Effects of Power Dissipation

Figure 26. Crosstalk under Forced

Source and Sink Conditions

Figure 24. Crosstalk with No Load

Figure 25. Crosstalk with 2 kΩ Load

–6–

REV. B

AD708

CROSSTALK PERFORMANCE OF THE AD708

The AD708 exhibits very low crosstalk as shown in Figures 24,

25 and 26. Figure 24 shows the offset voltage induced in side B

of the AD708 when side A’s output is moving slowly (0.2 Hz)

from –10 V to +10 V under no load. This is the least stressful

situation to the part since the overall power in the chip does not

change; only the location of the power in the output devices

changes. Figure 25 shows side B’s input offset voltage change

when side A is driving a 2 kΩ load. Here the power is being

changed in the chip with the maximum power change occurring

at ±7.5 V. Figure 26 shows crosstalk under the most severe

conditions. Side A is connected as a follower with 0 V input,

and is now forced to sink and source ±5 mA of output current

(Power = (30 V) (5 mA) = 150 mW). Even this large change in

power causes only an 8 µV (linear) change in side B’s input

offset voltage.

OPERATION WITH A GAIN OF –100

To show the outstanding dc precision of the AD708 in real

application, Table I shows an error budget calculation for a gain

of –100 configuration shown in Figure 27.

Table I.

Figure 28. Precision PGA

Maximum Error Contribution

A_V= 100 (S Grade)

(Full Scale: V_OUT= 10 V, V_IN= 100 mV)

are controlled by the select lines, A0 and A1 of the AD7502

multiplexer, and are 1, 10, 100 and 1000 in this design.

Error Sources

The input stage attains very high dc precision due to the 30 µV

maximum offset voltage match of the AD708S and the 1 nA

maximum input bias current match. The accuracy is maintained

over temperature because of the ultralow drift performance of

the AD708. The output stage uses an AD707J and well matched

resistors configured as a precision subtracter.

V_OS

I_OS

30 µV/100 mV

= 300 ppm

= 10 ppm

(100 kΩ)(1 nA)/10 V

Gain (2 kΩ load)

Noise

V_OSDrift

10 V/(5*10⁶))/100 mV = 20 ppm

0.35 µV/100 mV

(0.3 µV/°C)/100 mV

= 4 ppm

= 3 ppm/°C

= 334 ppm

+3 ppm/°C

To achieve 0.1% gain accuracy, along with high common-mode

rejection, the circuit should be trimmed as follows:

Total Unadjusted

Error

To maximize common-mode rejection:

@ 25°C

–55°C to +125°C

= 334 ppm > 11 Bits

= 634 ppm > 10 Bits

1. Set the select lines for Gain = 1 and ground V_INB

.

With Offset

Calibrated Out

2. Apply a precision dc voltage to V_INAand trim R_Auntil

V_O= –V_INAto the required precision.

@ 25°C

–55°C to +125°C

= 34 ppm > 14 Bits

= 334 ppm > 11 Bits

3. Next connect V_INBto V_INAand apply an input voltage equal

to the full-scale common-mode expected.

4. Trim R_Buntil V_O= 0 V.

To minimize gain errors:

1. Select Gain = 10 with the control lines and apply a differential

input voltage.

2. Adjust the 100 Ω potentiometer such that V_O= 10 V_IN(adjust

V_INmagnitude as necessary).

3. Repeat for Gain = 100 and Gain = 1000, adjusting 1 kΩ and

10 kΩ potentiometers, respectively.

The design shown should allow for 0.1% gain accuracy and

0.1 µV/V common-mode rejection when ±1% resistors and ±5%

potentiometers are used.

Figure 27. Gain of –100 Configuration

This error budget assumes no error in the resistor ratio and no

error from power supply variation (the 120 dB minimum PSRR

of the AD708S makes this a good assumption). The external

resistors can cause gain error from mismatch and drift over

temperature.

BRIDGE SIGNAL CONDITIONER

The AD708 can be used in the circuit in Figure 29 to produce

an accurate and inexpensive dynamic bridge conditioner. The

low offset voltage match and low offset voltage drift match of

the AD708 combine to achieve circuit performance better than

all but the best instrumentation amplifiers. The AD708’s out-

standing specs: open loop gain, input offset currents and low

input bias currents, do not limit circuit accuracy.

High Precision Programmable Gain Amplifier

The three op amp programmable gain amplifier shown in Figure

28 takes advantage of the outstanding matching characteristics of

the AD708 to achieve high dc precision. The gains of the circuit

REV. B

–7–

AD708

As configured, the circuit only requires a gain resistor, R_G, of

suitable accuracy and a stable, accurate voltage reference. The

transfer function is:

V_O= V_REF[∆R/(R+∆R)][R_G/R]

and the only significant errors due to the AD708S are:

V_OSout = (V_OSmatch)(2R_G/R) = 30 mV

V

_OSout(T) = (V_OSdrift)(2R_G/R) = 0.3 mV/°C

To achieve high accuracy, the resistor R_Gshould be 0.1% or

better and have a low drift coefficient.

Figure 31. Absolute Value Circuit Performance

(Input Signal = 0.05 Hz)

SELECTION OF PASSIVE COMPONENTS

To takc full advantagc of thc high precision and low drift

characteristics of the AD708, high quality passive components

must be used. Discrete resistors and resistor networks with

temperature coefficients of less than 10 ppm/°C are available

from Vishay, Caddock, PRP and others.

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Figure 29. Bridge Signal Conditioning Circuit

TO-99 (H) Package

Figure 30. Precision Absolute Value Circuit

Cerdip (Q) Package

PRECISION ABSOLUTE VALUE CIRCUIT

The AD708 is ideally suited to the precision absolute value

circuit shown in Figure 30. The low offset voltage match of the

AD708 enables this circuit to accurately resolve the input signal.

In addition, the tight offset voltage drift match maintains the

resolution of the circuit over the full military temperature range.

The AD708’s high dc open loop gain and exceptional gain

linearity allows the circuit to perform well at both large and

small signal levels.

In this circuit, the only significant dc errors are due to the offset

voltage of the two ampliliers, the input offset current match of

the amplifiers, and the mismatch of the resistors. Errors associ-

ated with the AD708S contribute less than 0.001% error over

–55°C to +125°C.

Mini-DIP (N) Package

Maximum error at 25°C

30 µV + 10 kΩ 1nA

(

)(

)

= 40 µV/10V = 4 ppm Maximum

10V

error at +125°C or –55°C

50 µV + 2 nA 10 kΩ

(

)(

)

= 7 ppm @ +125°C

10V

Figure 31 shows V_OUTvs. V_INfor this circuit with a ±3 mV

input signal at 0.05 Hz. Note that the circuit exhibits very low

offset at the zero crossing. This circuit can also produce V_OUT

–|V_IN| by reversing the polarity of the two diodes.

=

REV. B

–8–


型号：	AD708AH
厂家：	ADI
描述：	Ultralow Offset Voltage Dual Op Amp 超低失调电压双通道运算放大器运算放大器放大器电路
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