AD7091R [ADI]
1 MSPS, Ultralow Power, 12-Bit ADC in 10-Lead LFCSP and MSOP; 1 MSPS ，超低功耗， 12位ADC，采用10引脚LFCSP封装和MSOP
| 型号： | AD7091R |
| 厂家： | 
ADI |
| 描述： | 1 MSPS, Ultralow Power, 12-Bit ADC in 10-Lead LFCSP and MSOP |
| 文件： | 总20页 (文件大小：454K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1 MSPS, Ultralow Power,
12-Bit ADC in 10-Lead LFCSP and MSOP
Data Sheet
AD7091R
FEATURES
FUNCTIONAL BLOCK DIAGRAM
REGCAP
REF /REF
V
DD
IN
OUT
Fast throughput rate of 1 MSPS
Specified for VDD of 2.7 V to 5.25 V
Logic voltage VDRIVE of 1.65 V to 5.25 V
INL of 1 LSB maximum
Analog input range of 0 V to VREF
Ultralow power
2.5V
REF
AD7091R
SDO
SCLK
CS
SERIAL
INTERFACE
12-BIT
SAR
T/H
V
IN
V
349 µA typical at 3 V and 1 MSPS
264 nA typical at 3 V in power-down mode
Internal 2.5 V reference, 4.5 ppm/°C typical drift
Wide input bandwidth
DRIVE
CLK
OSC
CONVERSION
CONTROL LOGIC
CONVST
Flexible power/throughput rate management
High speed serial interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
BUSY indicator
Power-down mode
10-lead, 3 mm × 2 mm LFCSP and 10-lead MSOP packages
Temperature range of −40°C to +125°C
GND
Figure 1.
1100
1000
900
800
700
600
500
400
300
200
100
0
= V
= 3V
DRIVE
V
DD
APPLICATIONS
Battery-powered systems
Handheld meters
Medical instruments
Mobile communications
Instrumentation and control systems
Data acquisition systems
Optical sensors
V
DD
V
DRIVE
0
200
400
600
800
1000
Diagnostic/monitoring functions
Energy harvesting
THROUGHPUT RATE (kSPS)
Figure 2. Power vs. Throughput Rate
The AD7091R uses advanced design and process techniques to
achieve very low power dissipation at high throughput rates. An
on-chip, accurate 2.5 V reference is available.
GENERAL DESCRIPTION
The AD7091R is a 12-bit successive approximation analog-to-
digital converter (ADC) that offers ultralow power consumption
(typically 349 µA at 3 V and 1 MSPS) while achieving fast
throughput rates (1 MSPS with a 50 MHz SCLK). Operating
from a single 2.7 V to 5.25 V power supply, the part contains a
wide bandwidth track-and-hold amplifier that can handle input
frequencies in excess of 7 MHz. The AD7091R also features an
on-chip conversion clock, accurate reference, and high speed
serial interface.
PRODUCT HIGHLIGHTS
1. Lowest Power 12-Bit SAR ADC Available.
2. On-Chip, Accurate 2.5 V Reference.
3. High Throughput Rate with Ultralow Power Consumption.
4. Flexible Power/Throughput Rate Management.
Average power scales with the throughput rate. Power-down
mode allows the average power consumption to be reduced
when the device is not performing a conversion.
5. Single Supply Operation with VDRIVE Function.
The AD7091R operates from a single 2.7 V to 5.25 V supply.
The VDRIVE function allows the serial interface to connect
directly to 1.8 V to 3.3 V processors.
The conversion process and data acquisition are controlled using
CONVST
a
signal and an internal oscillator. The AD7091R has
a serial interface that allows data to be read after the conversion
while achieving a 1 MSPS throughput rate.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2012 Analog Devices, Inc. All rights reserved.
AD7091R
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Circuit Information.................................................................... 12
Converter Operation.................................................................. 12
ADC Transfer Function............................................................. 12
Internal/External Voltage Reference........................................ 12
Typical Connection Diagram ................................................... 13
Analog Input ............................................................................... 13
Modes of Operation ................................................................... 14
Power Consumption .................................................................. 14
Serial Interface ................................................................................ 16
With BUSY Indicator................................................................. 16
Without BUSY Indicator........................................................... 17
Software Reset............................................................................. 18
Interfacing With 8-/16-Bit SPI ................................................. 18
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
Thermal Resistance ...................................................................... 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 11
Theory of Operation ...................................................................... 12
REVISION HISTORY
8/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
Data Sheet
AD7091R
SPECIFICATIONS
VDD = 2.7 V to 5.25 V, VDRIVE = 1.65 V to 5.25 V, VREF = 2.5 V internal reference, fSAMPLE = 1 MSPS, fSCLK = 50 MHz, TA = −40°C to +125°C,
unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE1
Signal-to-Noise Ratio (SNR)2
fIN = 10 kHz sine wave
66.5
67.5
66
69
70
69
−84
−85
5
40
7.5
1.2
dB
dB
dB
dB
dB
ns
ps
MHz
MHz
fSAMPLE = 500 kSPS
Signal-to-Noise-and-Distortion Ratio (SINAD)2
Total Harmonic Distortion (THD)2
Spurious Free Dynamic Range (SFDR)2
Aperture Delay2
Aperture Jitter2
Full Power Bandwidth2
−79
−78
At −3 dB
At −0.1 dB
DC ACCURACY
Resolution
Integral Nonlinearity (INL)2, 3
12
Bits
VDRIVE ≤ 3.3 V
VDRIVE > 3.3 V with external VREF
Guaranteed no missing codes to 12 bits
0.8
1
1
0.9
2
3
LSB
LSB
LSB
LSB
LSB
LSB
Differential Nonlinearity (DNL)2
Offset Error2
Gain Error2
Total Unadjusted Error (TUE)2
0.3
0.6
0.8
−2
ANALOG INPUT
Input Voltage Range
DC Leakage Current
Input Capacitance4
0
VREF
1
V
µA
During acquisition phase
Outside acquisition phase
7
1
pF
pF
VOLTAGE REFERENCE INPUT/OUTPUT
REFOUT
REFIN
Drift
2.485
2.7
2.5
4.5
2.525
VDD
25
V
V
ppm/°C
LOGIC INPUTS
Input High Voltage (VINH
)
0.7 × VDRIVE
V
Input Low Voltage (VINL
Input Current (IIN)
)
0.3 × VDRIVE
1
5
V
µA
pF
Typically 10 nA, VIN = 0 V or VDRIVE
Input Capacitance (CIN)4
LOGIC OUTPUTS
Output High Voltage (VOH
)
ISOURCE = 200 µA
ISINK = 200 µA
VDRIVE − 0.2
V
V
µA
pF
Output Low Voltage (VOL
)
0.4
1
5
Floating State Leakage Current
Floating State Output Capacitance4
Output Coding
Straight binary
CONVERSION RATE
Conversion Time
650
350
1
ns
ns
MSPS
Track-and-Hold Acquisition Time2, 4
Full-scale step input
Throughput Rate
Rev. 0 | Page 3 of 20
AD7091R
Data Sheet
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
POWER REQUIREMENTS
VDD
VDRIVE
2.7
1.65
5.25
5.25
V
V
IDD
VIN = 0 V
Normal Mode—Static5
VDD = 5.25 V
VDD = 3 V
22
21.6
60
33
µA
µA
Normal Mode—Operational
Power-Down Mode
VDD = 5.25 V, fSAMPLE = 1 MSPS
VDD = 3 V, fSAMPLE = 1 MSPS
VDD = 3 V, fSAMPLE = 100 kSPS
388
349
55
449
408
µA
µA
µA
VDD = 5.25 V
VDD = 5.25 V, TA = −40°C to +85°C
VDD = 3 V
VDD = 3 V, TA = −40°C to +85°C
VIN = 0 V
0.334
0.334
0.264
0.264
4.4
1.4
4.2
1.2
µA
µA
µA
µA
IDRIVE
Normal Mode—Static6
VDRIVE = 5.25 V
VDRIVE = 3 V
32
28
500
500
nA
nA
Normal Mode—Operational
Power-Down Mode
VDRIVE = 5.25 V, fSAMPLE = 1 MSPS
VDRIVE = 3 V, fSAMPLE = 1 MSPS
42
17
86
20
µA
µA
VDRIVE = 5.25 V
VDRIVE = 3 V
7
2
41
28
nA
nA
Total Power Dissipation (PDD + PDRIVE
Normal Mode—Static5
)
VIN = 0 V
VDD = VDRIVE = 5.25 V
VDD = VDRIVE = 3 V
116
65
318
101
µW
µW
Normal Mode—Operational
Power-Down Mode
VDD = VDRIVE = 5.25 V, fSAMPLE = 1 MSPS
VDD = VDRIVE = 3 V, fSAMPLE = 1 MSPS
2.3
1
2.9
1.3
mW
mW
VDD = VDRIVE = 5.25 V
VDD = VDRIVE = 3 V
1.8
0.8
24
13
µW
µW
1 Dynamic performance is achieved with a burst SCLK. Operating a free running SCLK during acquisition phase degrades dynamic performance.
2 See the Terminology section.
3 For VDRIVE < VDD + 0.7 V.
4 Sample tested during initial release to ensure compliance.
5
CS
CS
CS
SCLK is operating in burst mode and is idling high. With a free running SCLK and pulled low, the IDD static current is increased by 30 µA typical at VDD = 5.25 V.
6
CS
SCLK is operating in burst mode and is idling high. With a free running SCLK and pulled low, the IDRIVE static current is increased by 32 µA typical at VDRIVE = 5.25 V.
Rev. 0 | Page 4 of 20
Data Sheet
AD7091R
TIMING SPECIFICATIONS
VDD = 2.75 V to 5.25 V, VDRIVE = 1.65 V to 5.25 V, TA = −40°C to +125°C, unless otherwise noted.1
Table 2.
Parameter
Limit at TMIN, TMAX
Unit
Description
fSCLK
t1
t2
t3
t4
t5
t6
t7
50
8
7
0.4 tSCLK
3
0.4 tSCLK
15
10
MHz max
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns max
ns min
Frequency of serial read clock
Delay from the end of a conversion until SDO three-state is disabled
Data access time after SCLK falling edge
SCLK high pulse width
SCLK to data valid hold time
SCLK low pulse width
SCLK falling edge to SDO high impedance
CONVST pulse width
t8
t9
650
6
Conversion time
low time before the end of a conversion
CS
Delay from
t10
t11
t12
t13
18
8
ns max
ns min
ns min
until SDO three-state is disabled
CS
high time before the end of a conversion
CS
8
Delay from the end of a conversion until
Power-up time with internal reference2
Power-up time with external reference
falling edge
CS
50
100
50
ms typ
µs max
ns min
tQUIET
Time between last SCLK edge and next CONVST pulse
1 Sample tested during initial release to ensure compliance.
2 With a 2.2 µF reference capacitor.
Rev. 0 | Page 5 of 20
AD7091R
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 3.
Parameter
Table 4. Thermal Resistance
Package Type
Rating
θJA
θJC
Unit
°C/W
°C/W
VDD to GND
VDRIVE to GND
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VREF + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDRIVE + 0.3 V
10 mA
−40°C to +125°C
−65°C to +150°C
150°C
10-Lead LFCSP
10-Lead MSOP
33.2
25.67
4
1.67
Analog Input Voltage to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
Input Current to Any Pin Except Supplies1
Operating Temperature Range
Storage Temperature Range
Junction Temperature
ESD
ESD CAUTION
HBM
FICDM
2.5 kV
1.5 kV
1 Transient currents of up to 100 mA do not cause silicon controlled rectifier
(SCR) latch-up.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 6 of 20
Data Sheet
AD7091R
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
1
2
3
4
5
10 V
DD
DRIVE
REF /REF
9
8
7
6
SDO
IN
OUT
AD7091R
TOP VIEW
(Not to Scale)
V
SCLK
CS
IN
REGCAP
GND
CONVST
V
V
DRIVE
1
2
3
4
5
10
9
DD
REF /REF
SDO
IN
OUT
AD7091R
TOP VIEW
(Not to Scale)
NOTES
8
SCLK
CS
V
1. THE EXPOSED PAD IS NOT CONNECTED INTERNALLY.
FOR INCREASED RELIABILITY OF THE SOLDER JOINTSAND
FOR MAXIMUM THERMAL CAPABILITY, SOLDER THE EXPOSED
PAD TO THE SUBSTRATE, GND.
IN
7
REGCAP
GND
6
CONVST
Figure 3. Pin Configuration, 10-Lead LFCSP
Figure 4. Pin Configuration, 10-Lead MSOP
Table 5. Pin Function Descriptions
Pin No.
LFCSP MSOP
Mnemonic
Description
1
1
VDD
Power Supply Input. The VDD range is from 2.7 V to 5.25 V. This supply pin should be decoupled to
GND. The typical recommended values are 10 µF and 0.1 µF.
2
2
REFIN/REFOUT Voltage Reference Input Output. Decouple this pin to GND. The typical recommended decoupling
capacitor value is 2.2 µF. The user can either access the internal 2.5 V reference or overdrive the
internal reference with an externally applied voltage. The reference voltage range for an externally
applied reference is 2.7 V to VDD
.
3
4
3
4
VIN
REGCAP
Analog Input. The single-ended analog input range is from 0 V to VREF.
Decoupling Capacitor Pin for Voltage Output from Internal Regulator. This output pin should be
decoupled separately to GND using a 1 μF capacitor. The voltage at this pin is 1.8 V typical.
5
6
7
5
6
7
GND
Analog Ground. This pin is the ground reference point for all circuitry on the AD7091R. The analog
input signal should be referred to this GND voltage.
Convert Start. Active low edge triggered logic input. The falling edge of CONVST places the track-
and-hold into hold mode and initiates a conversion.
Chip Select. Active low logic input. The serial bus is enabled when CS is held low, and in this mode CS
is used to frame the output data on the SPI bus.
CONVST
CS
8
9
8
9
SCLK
SDO
Serial Clock. This pin acts as the serial clock input.
Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits
are clocked out on the falling edge of the SCLK input. The data is provided MSB first.
10
11
10
VDRIVE
EPAD
Logic Power Supply Input. The voltage supplied at this pin determines the operating voltage of the
interface. Decoupling capacitors should be connected between VDRIVE and GND. The typical
recommended values are 10 µF and 0.1 µF. The voltage range of this pin is 1.65 V to 5.25 V.
Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder
joints and for maximum thermal capability, solder the exposed pad to the substrate, GND.
N/A
Rev. 0 | Page 7 of 20
AD7091R
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
72
70
68
66
64
62
60
0
V
V
= 2.7V
= 3.3V
= 25°C
DD
DRIVE
–20
–40
T
A
fIN = 10kHz
fSAMPLE = 1 MSPS
2.7V
3.0V
5.0V
SNR = 69.32dB
SINAD = 68.66dB
THD = –84.42dB
–60
–80
–100
–120
–140
T
= 25°C
A
1
10
100
0
100
200
300
400
500
INPUT FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 8. SNR vs. Analog Input Frequency
for Various Supply Voltages
Figure 5. Typical Dynamic Performance
1.0
0.8
0
T
= 25°C
V
V
= 2.7V
= 3.3V
= 25°C
fSAAMPLE = 1MSPS
DD
DRIVE
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
T
A
0.6
fSAMPLE = 1 MSPS
0.4
0.2
0.0
2.7V
3.0V
5.0V
–0.2
–0.4
–0.6
–0.8
–1.0
0
512
1024
1536
2048
2560
3072
3584
4096
1
10
INPUT FREQUENCY (kHz)
100
CODE
Figure 6. Typical INL Performance
Figure 9. THD vs. Analog Input Frequency
for Various Supply Voltages
–50
–55
–60
–65
–70
–75
–80
–85
1.0
0.8
T
V
= 25°C
= 3V
V
V
= 2.7V
A
DD
= 3.3V
DD
DRIVE
fIN = 10kHz
fSAMPLE = 1MSPS
T
= 25°C
A
0.6
fSAMPLE = 1 MSPS
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
512
1024
1536
2048
2560
3072
3584
4096
10
100
1k
10k
SOURCE IMPEDANCE (Ω)
CODE
Figure 10. THD vs. Source Impedance
Figure 7. Typical DNL Performance
Rev. 0 | Page 8 of 20
Data Sheet
AD7091R
2.502
2.500
2.498
2.496
2.494
2.492
2.490
2.488
2.486
2.484
72
70
68
66
64
62
V
= V
= 3V
DD
DRIVE
2.7V
3.0V
5.0V
+25°C
–40°C
+85°C
+125°C
T
= 25°C
A
60
0
20
40
60
80
100
1
10
100
INPUT FREQUENCY (kHz)
CURRENT LOAD (µA)
Figure 11. SINAD vs. Analog Input Frequency
for Various Supply Voltages
Figure 14. Reference Voltage Output vs. Current Load
for Various Temperatures
450
430
410
390
370
350
330
310
290
270
250
60
50
V
= V
= 3V
fSAMPLE = 1MSPS
DD
DRIVE
53423
65k SAMPLES
T
= 25°C
A
40
30
20
10
0
–40°C
+25°C
+85°C
6458
2047
5655
2049
+125°C
2.7
3.2
3.7
4.2
4.7
5.2
2046
2048
2050
V
SUPPLY VOLTAGE (V)
CODE
DD
Figure 12. Histogram of Codes at Code Center (VREF/2)
Figure 15. Operational IDD Supply Current vs. VDD Supply Voltage
for Various Temperatures
90
12
10
8
fSAMPLE = 1MSPS
IN
V
= 1.8V, +25°C
DRIVE
V
= 0V
80
70
60
50
40
30
20
10
0
V
= 1.8V, +125°C
DRIVE
V
= 1.8V, –40°C
= 3V, +25°C
DRIVE
V
= 3V, +125°C
DRIVE
6
4
V
DRIVE
V
= 3V, –40°C
DRIVE
–40°C
+25°C
+85°C
+125°C
2
0
1.65
2.65
V
3.65
4.65
10
20
30
40
50
SUPPLY VOLTAGE (V)
SDO CAPACITANCE LOAD (pF)
DRIVE
Figure 13. tSDO Delay vs. SDO Capacitance Load and VDRIVE
Figure 16. Operational IDRIVE Supply Current vs. VDRIVE Supply Voltage
for Various Temperatures
Rev. 0 | Page 9 of 20
AD7091R
Data Sheet
4000
V
V
V
= 3V, V
= 5V, V
= 5V, V
= 3V
= 5V
= 3.3V
DD
DD
DD
DRIVE
DRIVE
DRIVE
3500
3000
2500
2000
1500
1000
500
0
–40
25
85
125
OPERATING TEMPERATURE (°C)
Figure 17. Total Power-Down Supply Current (IDD and IDRIVE) vs. Temperature
for Various Supply Voltages
Rev. 0 | Page 10 of 20
Data Sheet
AD7091R
TERMINOLOGY
Total Unadjusted Error (TUE)
TUE is a comprehensive specification that includes the gain,
linearity, and offset errors.
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. For the
AD7091R, the endpoints of the transfer function are zero scale
(a point 0.5 LSB below the first code transition) and full scale (a
point 0.5 LSB above the last code transition).
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the fundamental.
For the AD7091R, THD is defined as
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
2
2
2
2
2
V2 +V3 +V4 +V5 +V6
THD dB = 20 log
( )
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
Offset Error
Offset error is the deviation of the first code transition (00 ...
000) to (00 ... 001) from the ideal (such as GND + 0.5 LSB).
through the sixth harmonics.
Gain Error
Spurious Free Dynamic Range (SFDR)
Gain error is the deviation of the last code transition (111 ... 110)
to (111 ... 111) from the ideal (such as VREF − 1.5 LSB) after the
offset error has been adjusted out.
SFDR, also known as peak harmonic or spurious noise, is defined
as the ratio of the rms value of the next largest component in the
ADC output spectrum (up to fSAMPLE/2 and excluding dc) to the
rms value of the fundamental. Usually, the value of this specifi-
cation is determined by the largest harmonic in the spectrum,
but for ADCs where the harmonics are buried in the noise floor,
the largest harmonic would be a noise peak.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode after the
end of a conversion. The track-and-hold acquisition time is the
time required for the output of the track-and-hold amplifier to
reach its final value, within 0.5 LSB, after a conversion (see the
Serial Interface section for more details).
Aperture Delay
Aperture delay is the measured interval between the leading
edge of the sampling clock and the point at which the ADC
samples data.
Signal-to-Noise Ratio (SNR)
SNR is the measured ratio of signal to noise at the output of the
ADC. The signal is the rms amplitude of the fundamental. Noise
is the sum of all nonfundamental signals up to half the sampling
frequency (fSAMPLE/2), excluding dc.
Aperture Jitter
Aperture jitter is the sample-to-sample variation in the effective
point in time at which the data is sampled.
The ratio is dependent on the number of quantization levels in the
digitization process: the more levels, the smaller the quantization
noise. The theoretical signal-to-noise ratio for an ideal N-bit
converter with a sine wave input is given by
Full Power Bandwidth
Full power bandwidth is the input frequency at which the
amplitude of the reconstructed fundamental is reduced by
0.1 dB or 3 dB for a full-scale input.
Signal-to-Noise Ratio = (6.02N + 1.76) dB
Therefore, for a 12-bit converter, the SNR is 74 dB.
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is the measured ratio of signal to noise and distortion at
the output of the ADC. The signal is the rms value of the sine
wave, and noise is the rms sum of all nonfundamental signals
up to half the sampling frequency (fSAMPLE/2), including
harmonics, but excluding dc.
Rev. 0 | Page 11 of 20
AD7091R
Data Sheet
THEORY OF OPERATION
CIRCUIT INFORMATION
CHARGE
REDISTRIBUTION
DAC
The AD7091R is a 12-bit successive approximation analog-to-
digital converter (ADC) that offers ultralow power consumption
(typically 349 µA at 3 V and 1 MSPS) while achieving fast
throughput rates (1 MSPS with a 50 MHz SCLK). The part can be
operated from a single power supply in the range of 2.7 V to 5.25 V.
SAMPLING
CAPACITOR
A
V
IN
CONTROL
LOGIC
SW1
B
SW2
CONVERSION
PHASE
COMPARATOR
GND
LDO/2
The AD7091R provides an on-chip track-and-hold ADC with
a serial interface housed in a tiny 10-lead LFCSP and 10-lead
MSOP packages. These packages offer considerable space-saving
advantages compared with alternative solutions. The serial clock
input accesses data from the part. The clock for the successive
approximation ADC is generated internally. The reference voltage
for the AD7091R is generated internally by an accurate on-chip
reference source. The analog input range for the AD7091R is
Figure 19. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7091R is straight binary. The designed
code transitions occur midway between successive integer LSB
values, such as 0.5 LSB, 1.5 LSB, and so on. The LSB size for the
AD7091R is VREF/4096. The ideal transfer characteristics for the
AD7091R are shown in Figure 20.
0 V to VREF
.
The AD7091R also features a power-down option to save power
between conversions. The power-down feature is implemented
across the standard serial interface as described in the Modes of
Operation section.
111 ... 111
111 ... 110
111 ... 000
1LSB = V
/4096
REF
011 ... 111
CONVERTER OPERATION
The AD7091R is a successive approximation ADC based
around a charge redistribution DAC. Figure 18 and Figure 19
show simplified schematics of the ADC. Figure 18 shows the
ADC during its acquisition phase. SW2 is closed and SW1 is in
Position A, the comparator is held in a balanced condition, and
the sampling capacitor acquires the signal on VIN.
000 ... 010
000 ... 001
000 ... 000
1LSB
V
– 1LSB
REF
0V
ANALOG INPUT
Figure 20. AD7091R Ideal Transfer Characteristics
INTERNAL/EXTERNAL VOLTAGE REFERENCE
CHARGE
REDISTRIBUTION
DAC
The AD7091R allows the choice of an internal voltage reference
or an external voltage reference.
SAMPLING
CAPACITOR
The internal reference provides an accurate 2.5 V low temperature
drift voltage reference. The internal reference is available at the
REFIN/REFOUT pin. When using the internal reference, this pin
should be decoupled using a capacitor with a typical value of 2.2 µF
to achieve the specified performance. With a fully discharged
2.2 µF reference capacitor, the internal reference requires 50 ms
typically to fully charge to the 2.5 V REFOUT voltage level.
A
V
IN
CONTROL
LOGIC
SW1
B
ACQUISITION
PHASE
SW2
COMPARATOR
GND
LDO/2
Figure 18. ADC Acquisition Phase
When the ADC starts a conversion, SW2 opens and SW1 moves
to Position B (see Figure 19), causing the comparator to become
unbalanced. The control logic and the charge redistribution DAC
are used to add and subtract fixed amounts of charge from the
sampling capacitor to bring the comparator back into a balanced
condition. When the comparator is rebalanced, the conversion
is complete. The control logic generates the ADC output code.
Figure 20 show the ideal ADC transfer function.
In power-down mode, the internal voltage reference is shut down.
After exiting power-down mode, adequate time should be allowed
for the reference capacitor to recharge before performing a con-
version. The time required to recharge the reference capacitor is
dependent on the amount of charge remaining on the capacitor
when exiting power-down mode.
If the on-chip reference is used externally to the AD7091R, it is
recommended to buffer this reference before supplying the
external circuitry.
Alternatively, the AD7091R reference voltage can be applied
externally. If an external reference is applied to the device, the
internal reference is automatically overdriven. An externally
applied reference voltage should be in the range of 2.7 V to
5.25 V and should be connected to the REFIN/REFOUT pin.
Rev. 0 | Page 12 of 20
Data Sheet
AD7091R
analog input signal never exceeds VREF or VDD by more than
300 mV. These diodes can conduct a maximum of 10 mA
without causing irreversible damage to the part.
TYPICAL CONNECTION DIAGRAM
Figure 22 shows a typical connection diagram for the AD7091R.
A positive power supply in the range of 2.7 V to 5.25 V should
be connected to the VDD pin, with typical values for decoupling
capacitors being 100 nF and 10 µF. These capacitors should be
placed as close as possible to the device pins. With the power
supply connected to the VDD pin, the AD7091R operates with
the internal 2.5 V reference, and the REFIN/REFOUT pin should
be decoupled using a capacitor with a typical value of 2.2 µF to
achieve the specified performance and provide an analog input
range of 0 V to VREF. The typical value for the regulator bypass
decoupling capacitor (REGCAP) is 1 µF. The voltage applied to
the VDRIVE input controls the voltage of the serial interface;
therefore, this pin should be connected to the supply voltage of
the microprocessor. VDRIVE can be set in the range of 1.65 V to
5.25 V. Typical values for the VDRIVE decoupling capacitors are
100 nF and 10 µF. The conversion result is output in a 12-bit
word with the MSB first.
V
V
DD
REF
D1
D2
D3
C2
3.6pF
R1
V
IN
C1
C3
2.5pF
1pF
NOTES
1. DURING THE CONVERSION PHASE, THE SWITCH IS OPEN.
DURING THE TRACK PHASE, THE SWITCH IS CLOSED.
Figure 21. Equivalent Analog Input Circuit
Capacitor C1 in Figure 21 is typically about 1 pF and can
primarily be attributed to pin capacitance. Resistor R1 is a
lumped component made up of the on resistance of a switch.
This resistor is typically about 500 Ω. Capacitor C2 is the ADC
sampling capacitor and typically has a capacitance of 3.6 pF.
The AD7091R requires the user to initiate a software reset upon
power-up (see the Software Reset section).
In applications where harmonic distortion and signal-to-noise
ratio are critical, the analog input should be driven from a low
impedance source. Large source impedances significantly affect
the ac performance of the ADC. This may necessitate using an
input buffer amplifier as shown in Figure 22. The choice of the
op amp is a function of a particular application.
If an external reference is applied to the device, the internal
reference is automatically overdriven. An externally applied
reference voltage should be in the range of 2.7 V to 5.25 V and
should be connected to the REFIN/REFOUT pin.
If the BUSY indicator feature is required, a pull-up resistor of
typically 100 kΩ to VDRIVE should be connected to the SDO pin.
In addition, for applications in which power consumption is a
concern, the power-down mode can be used to improve the
power performance of the ADC (see the Modes of Operation
section for more details).
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance depends on the amount of total harmonic distortion
(THD) that can be tolerated. The THD increases as the source
impedance increases and performance degrades. Figure 10 shows a
graph of THD vs. source impedance when using a supply voltage
of 3 V and a sampling rate of 1 MSPS.
ANALOG INPUT
Figure 21 shows an equivalent circuit of the AD7091R analog
input structure. The D1 and D2 diodes provide ESD protection
for the analog input. The D3 diode is a parasitic diode between
Use an external filter—such as a one-pole, low-pass RC filter, or
similar, as shown in Figure 22—on the analog input connected
to the AD7091R to achieve the specified performances.
V
IN and VREF. To prevent the diodes from becoming forward-
biased and from starting to conduct current, ensure that the
WITH BUSY
INDICATION
V
DRIVE
1.65V TO 5.25V
10µF
100kΩ
2.7V TO 5.25V
10µF
100nF
100nF
SDO
V
V
DRIVE
DD
REGCAP
SCLK
CS
MICROPROCESSOR/
MICROCONTROLLER/
DSP
AD7091R
1µF
REF
REF
/
CONVST
OUT
51Ω
IN
V
IN
GND
ANALOG
INPUT
4.7nF
2.2µF
Figure 22. AD7091R Typical Connection Diagram
Rev. 0 | Page 13 of 20
AD7091R
Data Sheet
The serial interface of the AD7091R is functional in power-
down mode; therefore, users can read back the conversion
result after the part enters power-down mode.
MODES OF OPERATION
The mode of operation of the AD7091R is selected by controlling
CONVST
the logic state of the
complete.
signal when a conversion is
To exit this mode of operation and power up the AD7091R,
CONVST
CONVST
pull
high at any time. On the rising edge of
,
CONVST
The logic level of the
pin at the end of a conversion
the device begins to power up. The internal circuitry of the
determines whether the AD7091R remains in normal mode or
enters power-down mode (see the Normal Mode and Power-
Down Mode sections). Similarly, if the device is already in
AD7091R requires 100 μs to power up from power-down mode.
If the internal reference is used, the reference capacitor must be
fully recharged before accurate conversions are possible.
CONVST
power-down mode,
controls whether the device
To start the next conversion after exiting power-down mode,
operate the interface as described in the Normal Mode section.
returns to normal mode or remains in power-down mode.
These modes of operation provide flexible power management
options, allowing optimization of the ratio of the power dissipation
to the throughput rate for different application requirements.
POWER CONSUMPTION
The two modes of operation for the AD7091R—normal mode
and power-down mode (see the Modes of Operation section for
more information)—produce different power vs. throughput
rate performances. Using a combination of normal mode and
power-down mode achieves the optimum power performance.
Normal Mode
The normal mode of operation is intended to achieve the fastest
throughput rate performance. Users do not have to worry about
power-up times because the AD7091R remains fully powered at
all times. Figure 29 shows the general timing diagram of the
AD7091R in normal mode.
To calculate the overall power consumption, the IDRIVE current
should also be taken into consideration. Figure 16 shows the IDRIVE
current at various supply voltages. Figure 23 and Figure 24 show
the power consumption for VDRIVE with various throughput rates.
In this mode, the conversion is initiated on the falling edge
CONVST
of
ensure that the part remains fully powered up at all
CONVST
, as described in the Serial Interface section. To
Improved power consumption for the AD7091R can be achieved
by carefully selecting the VDD and VDRIVE supply voltages and the
SDO line capacitance (see Figure 15 and Figure 16).
times,
the conversion is complete. At the end of a conversion (denoted
CONVST
must return high after t7 and remain high until
as EOC in Figure 27), the logic state of
is tested.
Normal Mode
To read back data stored in the conversion result register, wait until
With a 3 V VDD supply and a throughput rate of 1 MSPS, the IDD
current consumption for the part in normal operational mode is
349 μA (composed of 21.6 μA of static current and 327.4 μA of
dynamic current during conversion). The dynamic current
consumption is directly proportional to the throughput rate.
CS
the conversion is complete, and then pull low. The conversion
data is subsequently clocked out on the SDO pin (see Figure 29).
Because the output shift register is 12 bits wide, data is shifted
out of the device as a 12-bit word under the control of the serial
clock input (SCLK). After reading back the data, the user can
The following example calculates the power consumption of
AD7091R when operating in normal mode with a 500 kSPS
throughput rate and a 3 V supply.
CONVST
pull
low again to start another conversion after the
tQUIET time has elapsed.
Power-Down Mode
The dynamic conversion time contributes 491 μW to the overall
power dissipation as follows:
The power-down mode of operation is intended for use in
applications where slower throughput rates and lower power
consumption are required. In this mode, the ADC can be
powered down either between each conversion or between a
series of conversions performed at a high throughput rate, with
the ADC powered down for relatively long durations between
these bursts of several conversions. When the AD7091R is in
power-down mode, the serial interface remains active even
though all analog circuitry, including the internal voltage
reference, is powered down.
((500 kSPS/1 MSPS) × 327.4 μA) × 3 V = 491 μW
The contribution to the total power dissipated by the normal
mode static operation is
21.6 μA × 3 V = 65 μW
Therefore, the total power dissipated at 500 kSPS is
491 μW + 65 μW = 556 μW
CONVST
To enter power-down mode, pull
until the end of a conversion (denoted as EOC in Figure 30). After
CONVST
low and keep it low
the conversion is complete, the logic level of the
pin is
signal is logic low at this point, the part
enters power-down mode.
CONVST
tested. If the
Rev. 0 | Page 14 of 20
Data Sheet
AD7091R
Normal and Power-Down Mode Combination
V
DRIVE supply. Power consumption for the VDRIVE supply can be
calculated by the same principles as those for the VDD supply.
A combination of normal mode and power-down mode
achieves the optimum power performance.
Additionally, Figure 24 shows the reduction in power consumption
that can be achieved when power-down mode is used compared
with using only normal mode at lower throughput rates.
1100
The internal circuitry of the AD7091R requires 100 μs to power
up from power-down mode. Power-down mode can therefore
be performed at sampling rates of less than 10 kSPS.
= 3V
DRIVE
V
= V
DD
1000
900
800
700
600
500
400
300
200
100
0
Recharging the reference capacitor should also be considered
when using the on-chip reference. The AD7091R can fully
charge a 2.2 µF reference capacitor in typically 50 ms. However,
the time to charge the reference capacitor is dependent on the
amount of charge remaining on the capacitor when exiting
power-down mode. The reference capacitor loses charge very
slowly, resulting in much faster recharge times.
V
DD
Figure 25 shows the AD7091R conversion sequence with a
combination of normal mode and power-down mode with a
throughput of 5 kSPS when using an external reference. With a VDD
supply voltage of 3 V, the static current is 21.6 μA. The dynamic
current is 327.4 μA at 1 MSPS. The current consumption during
power-down mode is 264 nA. A conversion requires 650 ns to
complete, and the AD7091R requires 100 μs to power up from
power-down mode when using an external reference.
V
DRIVE
0
200
400
600
800
1000
THROUGHPUT RATE (kSPS)
Figure 23. Power Dissipation vs. Throughput Rate (Full Range)
1000
100
10
V
V
= V
= 0V
= 3V
DD
DRIVE
IN
EXTERNAL REFERENCE
The dynamic conversion time contributes 4.9 μW to the overall
power dissipation as follows:
((5 kSPS/1 MSPS) × 327.4 μA) × 3 V = 4.9 μW
The contribution to the total power dissipated by the normal
mode static operation and power-down mode is
1
((100.6 μs/200 μs) × 21.6 μA) × 3 V +
0.1
((99.4 μs/200 μs) × 264 nA) × 3 V = 33 μW
V
V
V
V
(NO PD)
DD
(NO PD)
0.01
0.001
DRIVE
DD
The conversion time of 650 ns is included in the static opera-
tion time.
DRIVE
0.01
0.1
1
10
100
The total power dissipated at 5 kSPS is
4.9 μW + 33 μW = 37.9 μW
THROUGHPUT RATE (kSPS)
Figure 24. Power Dissipation vs. Throughput Rate (Lower Range)
Figure 23 and Figure 24 show the typical power vs. throughput
rate for the AD7091R at 3 V for the VDD supply and for the
EOC
CONVST
650ns
CONVERSION
99µs
POWER-DOWN
100µs
POWER-UP
CS
SDO
DATA
200µs
Figure 25. 10 SPS with Normal and Power-Down Mode
Rev. 0 | Page 15 of 20
AD7091R
Data Sheet
SERIAL INTERFACE
CONVST
the AD7091R to enter power-down mode,
should be
The AD7091R serial interface consists of four signals: SDO,
taken high before the end of the conversion. A conversion
requires 650 ns to complete. When the conversion process is
finished, the track-and-hold goes back to track mode. Before
CONVST
CS
SCLK,
, and . The serial interface is used for
accessing data from the result register and controlling the
modes of operation of the device. SCLK is the serial clock input
for the device, and SDO data transfers take place with respect to
CS
the end of a conversion, pull
indicator feature.
low to enable the BUSY
CONVST
this SCLK. The
conversion process and to select the mode of operation of the
CS
signal is used to initiate the
The conversion result is shifted out of the device as a 12-bit
CS
at the
AD7091R (see the Modes of Operation section).
is used to
takes the SDO line out of a
CS
word under the control of SCLK and the logic state of
CS
end of a conversion. At the end of a conversion, SDO is driven
low. SDO remains low until the MSB (DB11) of the conversion
result is clocked out on the first falling edge of SCLK. DB10 to
DB0 are shifted out on the subsequent falling edges of SCLK.
The 13th SCLK falling edge returns SDO to a high impedance
state. Data is propagated on SCLK falling edges and is valid on
both the rising and falling edges of the next SCLK. The timing
diagram for this mode is shown in Figure 27.
frame the data. The falling edge of
high impedance state. A rising edge on
high impedance state.
returns the SDO to a
CS
The logic level of at the end of a conversion determines whether
the BUSY indicator feature is enabled. This feature affects the
propagation of the MSB with respect to
CS
and SCLK.
WITH BUSY INDICATOR
CONVST
When the BUSY indicator feature is enabled, the SDO pin can
be used as an interrupt signal to indicate that a conversion is
complete. The connection diagram for this configuration is
shown in Figure 26. Note that a pull-up resistor to VDRIVE is
required on the SDO pin. This allows the host to detect when
the SDO pin exits the three-state condition after the end of a
conversion. In this mode, 13 SCLK cycles are required: 12 clock
cycles to propagate out the data and an additional clock cycle to
return the SDO pin to the three-state condition.
If another conversion is required, pull
repeat the read cycle.
low again and
CS1
CONVERT
V
DRIVE
DIGITAL HOST
100kΩ
CS
CONVST
SDO
DATA IN
AD7091R
SCLK
IRQ
To enable the BUSY indicator feature, a conversion should first
CLK
CONVST
be started. A high-to-low transition on
initiates a
Figure 26. Connection Diagram with BUSY Indicator
conversion. This puts the track-and-hold into hold mode and
samples the analog input at this point. If the user does not want
EOC
t7
CONVST
tQUIET
t8
CS
t9
t3
3
4
5
10
11
1
2
12
SCLK
SDO
13
t5
t1
t6
t2
t4
DB0
DB11
DB10
DB9
DB8
DB7
DB2
DB1
THREE-STATE
THREE-STATE
NOTES
1. EOC IS THE END OF A CONVERSION.
Figure 27. Serial Port Timing with BUSY Indicator
Rev. 0 | Page 16 of 20
Data Sheet
AD7091R
The data is shifted out of the device as a 12-bit word under the
WITHOUT BUSY INDICATOR
CS
control of SCLK and . The MSB (Bit DB11) is clocked out on the
To operate the AD7091R without the BUSY indicator feature
enabled, a conversion should first be started. A high-to-low
CS
falling edge of . DB10 to DB0 are shifted out on the subsequent
falling edges of SCLK. The 12th falling SCLK edge returns SDO
to a high impedance state. After all the data is clocked out, pull
CONVST
transition on
initiates a conversion. This puts the
track-and-hold into hold mode and samples the analog input
at this point. If the user does not want the AD7091R to enter
CS
high again. SCLK should idle low in this mode to ensure that
the MSB is not lost. Data is propagated on SCLK falling edges
and is valid on both the rising and falling edges of the next SCLK.
The timing diagram for this operation is shown in Figure 28.
CONVST
power-down mode,
should be taken high before the
end of the conversion. A conversion requires 650 ns to complete.
When the conversion process is finished, the track-and-hold
goes back to track mode. To prevent the BUSY indicator feature
from becoming enabled, ensure that
the end of the conversion.
EOC
CONVST
If another conversion is required, pull
the read cycle.
low and repeat
CS
is pulled high before
t7
CONVST
tQUIET
t8
t12
CS
t11
t3
5
1
2
3
4
10
11
12
SCLK
t5
t6
t10
t2
t4
SDO
DB11
DB10
DB9
DB8
DB7
DB2
DB1
DB0
THREE-STATE
THREE-STATE
NOTES
1. EOC IS THE END OF A CONVERSION.
Figure 28. Serial Port Timing Without BUSY Indicator
Rev. 0 | Page 17 of 20
AD7091R
Data Sheet
SOFTWARE RESET
INTERFACING WITH 8-/16-BIT SPI
The AD7091R requires the user to initiate a software reset when
power is first applied. It should be noted that failure to apply
the correct software reset command may result in a device
malfunction.
It is also possible to interface the AD7091R with a conventional
8-/16-bit SPI bus.
Performing conversions and reading results can be achieved by
configuring the host SPI interface to 16 bits, which results in
providing an additional four SCLK cycles to complete a conversion
compared with the standard interface methods (see the With
BUSY Indicator and Without BUSY Indicator sections). After
the 13th SCLK falling edge with the BUSY indicator feature
enabled or the 12th SCLK falling edge with the BUSY indicator
feature disabled, SDO returns to a high impedance state. The
additional four bits should be treated as don’t cares by the host.
All other timings are as outlined in Figure 27 and Figure 28,
with tQUIET starting after the 16th SCLK cycle.
To issue a software reset,
1. Start a conversion.
CS
2. Read back the conversion result by pulling
conversion is complete.
low after the
CS
3. Between the second and eighth SCLK cycles, pull
to short cycle the read operation.
high
4. At the end of the next conversion, the software reset is
executed.
If using the on-chip internal reference, the user should wait until
the reference capacitor is fully charged to meet the specified
performance.
A software reset can be performed by configuring the SPI bus to
eight bits and performing the operation outlined in the Software
Reset section.
The timing diagram for this operation is shown in Figure 31.
EOC
t7
CONVST
t8
t12
CS
t10
CONVERSION DATA
SDO
NOTES
1.
DON’T CARE.
2. EOC IS THE END OF A CONVERSION.
Figure 29. Serial Interface Read Timing—Normal Mode
EOC
POWER-DOWN MODE
CONVST
t13
t8
t12
CS
t10
CONVERSION DATA
SDO
NOTES
1.
DON’T CARE.
2. EOC IS THE END OF A CONVERSION.
Figure 30. Entering/Exiting Power-Down Mode
Rev. 0 | Page 18 of 20
Data Sheet
AD7091R
EOC/
SOFTWARE
RESET
EOC
t7
t7
CONVST
t8
t8
t12
CS
t10
SDO
SHORT CYCLE READ
t3
SCLK
1
2
6
7
8
t5
NOTES
1.
DON’T CARE.
2. EOC IS THE END OF A CONVERSION.
Figure 31. Software Reset Timing
Rev. 0 | Page 19 of 20
AD7091R
Data Sheet
OUTLINE DIMENSIONS
2.54
2.44
2.34
3.10
3.00
2.90
0.50 BSC
6
10
2.10
2.00
1.90
1.00
0.90
0.80
EXPOSED
PAD
0.35
0.30
0.25
PIN 1 INDEX
AREA
5
1
PIN 1
INDICATOR
(R 0.15)
BOTTOM VIEW
TOP VIEW
0.80
0.75
0.70
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SEATING
PLANE
0.30
0.25
0.20
0.203 REF
SECTION OF THIS DATA SHEET.
COMPLIANT TOJEDEC STANDARDS MO-229-WCED-3
Figure 32. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 2 mm Body, Very Very Thin, Dual Lead
(CP-10-12)
Dimensions shown in millimeters
3.10
3.00
2.90
10
1
6
5
5.15
4.90
4.65
3.10
3.00
2.90
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.70
0.55
0.40
0.15
0.05
0.23
0.13
6°
0°
0.30
0.15
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 33. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option Branding
AD7091RBCPZ-RL
AD7091RBCPZ-RL7
AD7091RBRMZ
AD7091RBRMZ-RL7
EVAL-AD7091RSDZ
EVAL-SDP-CB1Z
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
10-Lead Mini Small Outline Package [MSOP]
10-Lead Mini Small Outline Package [MSOP]
Evaluation Board
CP-10-12
CP-10-12
RM-10
C7P
C7P
DRQ
DRQ
RM-10
Evaluation Controller Board
1 Z = RoHS Compliant Part.
©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10494-0-8/12(0)
Rev. 0 | Page 20 of 20
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