AD7124-8BCPZ-RL_技术文档

8-Channel, Low Noise, Low Power, 24-Bit,

Sigma-Delta ADC with PGA and Reference

AD7124-8

Data Sheet

Low-side power switch

General-purpose outputs

Multiple filter options

FEATURES

3 power modes

RMS noise

Internal temperature sensor

Self and system calibration

Sensor burnout detection

Automatic channel sequencer

Per channel configuration

Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 µA typical)

Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 µA typical)

Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 µA typical)

Up to 22 noise free bits in all power modes (gain = 1)

Output data rate

Power supply: 2.7 V to 3.6 V and 1.8 V

Independent interface power supply

Power-down current: 5 µA maximum

Temperature range: −40°C to +125°C

32-lead LFCSP

3-wire or 4-wire serial interface

SPI, QSPI™, MICROWIRE™, and DSP compatible

Schmitt trigger on SCLK

Full power: 9.38 SPS to 19,200 SPS

Mid power: 2.34 SPS to 4800 SPS

Low power: 1.17 SPS to 2400 SPS

Rail-to-rail analog inputs for gains > 1

Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle

settling)

Diagnostic functions (which aid safe integrity level (SIL)

certification)

Crosspoint multiplexed analog inputs

8 differential/15 pseudo differential inputs

Programmable gain (1 to 128)

Band gap reference with 15 ppm/°C drift maximum (70 µA)

Matched programmable excitation currents

Internal clock oscillator

ESD: 4 kV

APPLICATIONS

Temperature measurement

Pressure measurement

Industrial process control

Instrumentation

On-chip bias voltage generator

Smart transmitters

FUNCTIONAL BLOCK DIAGRAM

AV

REGCAPA

IOV

DD REGCAPD

DD

REFOUT

REFIN1(+) REFIN1(–)

BANDGAP

REF

V

REFIN2(+)

REFIN2(–)

BIAS

AV

DD

SS

AV

SS

1.9V

LDO

1.8V

LDO

AV

CROSSPOINT

MUX

AIN0/IOUT/VBIAS

AIN1/IOUT/VBIAS

AV

DD

REFERENCE

AIN2/IOUT/VBIAS/P1

AIN3/IOUT/VBIAS/P2

AIN4/IOUT/VBIAS/P3

AIN5/IOUT/VBIAS/P4

AIN6/IOUT/VBIAS

BUFFERS

DOUT/RDY

BUF

SERIAL

INTERFACE

AND

CONTROL

LOGIC

VARIABLE

DIGITAL

FILTER

24-BIT

Σ-Δ ADC

BURNOUT

DETECT

DIN

PGA1

PGA2

AIN7/IOUT/VBIAS

SCLK

CS

AIN8/IOUT/VBIAS

AIN9/IOUT/VBIAS

X-MUX

AIN10/IOUT/VBIAS

AIN11/IOUT/VBIAS

AIN12/IOUT/VBIAS

ANALOG

BUFFERS

AV

SS

CHANNEL

SEQUENCER

SYNC

CLK

AIN13/IOUT/VBIAS

AIN14/IOUT/VBIAS/REFIN2(+)

AIN15/IOUT/VBIAS/REFIN2(–)

GPOs

DIAGNOSTICS

TEMPERATURE

SENSOR

AV

DD

COMMUNICATIONS

POWER SUPPLY

SIGNAL CHAIN

DIGITAL

INTERNAL

CLOCK

DIAGNOSTICS

EXCITATION

CURRENTS

PSW

POWER

SWITCH

AD7124-8

AV

SS

AV

DGND

SS

Figure 1.

Rev. D

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Last Content Update: 02/23/2017

COMPARABLE PARTS

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REFERENCE MATERIALS

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• Highly Integrated Analog Front-Ends with 24-bit

Converter Cores Achieve Industry’s Best Combination of

Low Power and Noise Performance

EVALUATION KITS

• AD7124-8 Evaluation Board

Technical Articles

• ADC Requirements for RTD Temperature Measurement

Systems

DOCUMENTATION

Application Notes

• AN-1392: How to Calculate Offset Errors and Input

Impedance in ADC Converters with Chopped Amplifiers

DESIGN RESOURCES

• AD7124-8 Material Declaration

• PCN-PDN Information

Data Sheet

• AD7124-8: 8-Channel, Low Noise, Low Power, 24-Bit,

• Quality And Reliability

• Symbols and Footprints

Sigma-Delta ADC with PGA and Reference Data Sheet

User Guides

• UG-856: Evaluation Board for the AD7124-8 8-Channel,

Low Noise, Low Power, 24-bit Σ-Δ ADC with In-Amp and

Reference

DISCUSSIONS

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SOFTWARE AND SYSTEMS REQUIREMENTS

• AD7124 No-OS Software

SAMPLE AND BUY

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• AD7124-4/AD7124-8 Eval+ Software

TECHNICAL SUPPORT

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number.

TOOLS AND SIMULATIONS

• AD7124-8 IBIS Model

REFERENCE DESIGNS

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AD7124-8

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Calibration................................................................................... 51

Span and Offset Limits .............................................................. 52

System Synchronization ............................................................ 53

Digital Filter .................................................................................... 54

Sinc⁴Filter ................................................................................... 54

Sinc³Filter ................................................................................... 56

Fast Settling Mode (Sinc⁴+ Sinc¹Filter).................................. 58

Fast Settling Mode (Sinc³+ Sinc¹Filter).................................. 60

Post Filters ................................................................................... 62

Summary of Filter Options ....................................................... 65

Diagnostics ...................................................................................... 66

Signal Chain Check.................................................................... 66

Reference Detect......................................................................... 66

Calibration, Conversion, and Saturation Errors .................... 66

Overvoltage/Undervoltage Detection ..................................... 66

Power Supply Monitors ............................................................. 67

LDO Monitoring ........................................................................ 67

MCLK Counter........................................................................... 67

SPI SCLK Counter...................................................................... 67

SPI Read/Write Errors ............................................................... 68

SPI_IGNORE Error ................................................................... 68

Checksum Protection ................................................................ 68

Memory Map Checksum Protection ....................................... 68

ROM Checksum Protection...................................................... 69

Burnout Currents ....................................................................... 70

Temperature Sensor ................................................................... 70

Grounding and Layout .................................................................. 71

Applications Information.............................................................. 72

Temperature Measurement Using a Thermocouple.............. 72

Temperature Measurement Using an RTD............................. 73

Flowmeter.................................................................................... 75

On-Chip Registers.......................................................................... 77

Communications Register......................................................... 78

Status Register............................................................................. 78

ADC_CONTROL Register ....................................................... 79

Data Register............................................................................... 81

IO_CONTROL_1 Register........................................................ 81

IO_CONTROL_2 Register........................................................ 83

ID Register................................................................................... 84

Error Register.............................................................................. 84

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

General Description......................................................................... 4

Specifications..................................................................................... 5

Timing Characteristics .............................................................. 10

Absolute Maximum Ratings.......................................................... 13

Thermal Resistance .................................................................... 13

ESD Caution................................................................................ 13

Pin Configuration and Function Descriptions........................... 14

Terminology .................................................................................... 17

Typical Performance Characteristics ........................................... 18

RMS Noise and Resolution............................................................ 27

Full Power Mode......................................................................... 27

Mid Power Mode........................................................................ 30

Low Power Mode........................................................................ 33

Getting Started ................................................................................ 36

Overview...................................................................................... 36

Power Supplies ............................................................................ 37

Digital Communication............................................................. 37

Configuration Overview ........................................................... 39

ADC Circuit Information.............................................................. 44

Analog Input Channel ............................................................... 44

External Impedance when using a Gain of 1.......................... 45

Programmable Gain Array (PGA)........................................... 46

Reference ..................................................................................... 46

Bipolar/Unipolar Configuration .............................................. 46

Data Output Coding .................................................................. 47

Excitation Currents .................................................................... 47

Bridge Power-Down Switch...................................................... 47

Logic Outputs.............................................................................. 47

Bias Voltage Generator .............................................................. 48

Clock ............................................................................................ 48

Power Modes............................................................................... 48

Standby and Power-Down Modes............................................ 48

Digital Interface.......................................................................... 49

DATA_STATUS .......................................................................... 51

RDY

CS

_DEL and _EN Bits)51

Serial Interface Reset (DOUT_

Reset ............................................................................................. 51

Rev. D | Page 2 of 92

Data Sheet

AD7124-8

ERROR_EN Register ..................................................................85

MCLK_COUNT Register ..........................................................86

Channel Registers........................................................................87

Configuration Registers .............................................................89

Filter Registers .............................................................................90

Offset Registers............................................................................91

Gain Registers..............................................................................91

Outline Dimensions........................................................................92

Ordering Guide ...........................................................................92

REVISION HISTORY

7/2016—Rev. C to Rev. D

Change to Table 4............................................................................13

Changes to Figure 16 Through Figure 21 ....................................19

Changes to Figure 22 Through Figure 25 ....................................20

Changes to Figure 29, Figure 32, and Figure 33..........................21

Changes to Figure 36 Through Figure 39 ....................................22

Changes to Figure 40 Through Figure 45 ....................................23

Changes to Figure 46 and Figure 47 .............................................24

Changes to Figure 63 ......................................................................26

Change to Table 17..........................................................................30

Change to Accessing the ADC Register Map Section................38

Change to Table 63..........................................................................76

Change to ID Register Section ......................................................83

Changes to Table 73 ........................................................................86

Changes to Ordering Guide...........................................................91

Change to Features Section..............................................................1

Changes to Specifications Section and Table 2..............................5

Changes to Table 4 ..........................................................................13

Change to Table 8............................................................................27

Changes to Table 9 and Table 10 ...................................................28

Change to Table 25..........................................................................32

Changes to Table 28 ........................................................................33

Change to Table 29..........................................................................34

Change to Accessing the ADC Register Map Section and

Table 38.............................................................................................38

Changes to Diagnostics Section, Table 44, and Table 45 ...........41

Added External Impedance When Using a Gain of 1 Section

and Figure 74, Figure 75, and Figure 76; Renumbered

Sequentially......................................................................................45

Changes to Standby and Power-Down Modes Section..............48

Changes to Single Conversion Mode Section..............................49

Changes to Continuous Read Mode Section...............................51

Changes to Sinc⁴Output Data Rate/Settling Time Section.......54

Changes to Sinc⁴Zero Latency Section .......................................55

Changes to Sinc³Output Data Rate and Settling Time Section......56

Changes to Sinc³Zero Latency Section........................................57

Change to Output Data Rate and Settling Time, Sinc⁴+ Sinc¹

Filter Section ....................................................................................59

Change to Output Data Rate and Settling Time, Sinc³+ Sinc¹

Filter Section ....................................................................................60

Changes to SPI_IGNORE Error Section......................................68

Added ROM Checksum Protection Section................................69

Changes to Table 63 ........................................................................77

Changes to ID Register Section, Error Register Section, and

Table 70.............................................................................................84

Changes to ERROR_EN Register Section and Table 71 ............85

Changes to Table 73 ........................................................................88

7/2015—Rev. A to Rev. B

Changes to Figure 29 ......................................................................21

Change to Single Conversion Mode Section...............................49

Changes to Calibration Section.....................................................51

Changes to Figure 82 ......................................................................53

Changes to Figure 90 ......................................................................56

Changes to Figure 98 ......................................................................58

Changes to Figure 104 ....................................................................60

Changes to Reference Detect Section and Figure 118................65

Changes to Table 70 ........................................................................83

Changes to Table 71 ...............................................................................84

Changes to Table 75 ........................................................................89

5/2015—Rev. 0 to Rev. A

Changes to Temperature Measurement Using a Thermocouple

Section ..............................................................................................71

Changed AINM to AINP, Table 70...............................................83

Changed REFOUT to Internal Reference, Table 73 ...................86

12/2015—Rev. B to Rev. C

4/2015—Revision 0: Initial Version

Changed +105°C to +125°C......................................... Throughout

Change to Features Section..............................................................1

Change to General Description Section.........................................4

Changes to Table 2 ............................................................................5

Added Endnote 4, Table 2; Renumbered Sequentially.................9

Rev. D | Page 3 of 92

AD7124-8

Data Sheet

GENERAL DESCRIPTION

The AD7124-8 is a low power, low noise, completely integrated

analog front end for high precision measurement applications.

The device contains a low noise, 24-bit Σ-Δ analog-to-digital

converter (ADC), and can be configured to have 8 differential

inputs or 15 single-ended or pseudo differential inputs. The on-

chip low gain stage ensures that signals of small amplitude can

be interfaced directly to the ADC.

on each enabled channel, simplifying communication with the

device. As many as 16 channels can be enabled at any time, a

channel being defined as an analog input or a diagnostic such

as a power supply check or a reference check. This unique

feature allows diagnostics to be interleaved with conversions.

The AD7124-8 also supports per channel configuration. The

device allows eight configurations or setups. Each configuration

consists of gain, filter type, output data rate, buffering, and

reference source. The user can assign any of these setups on a

channel by channel basis.

One of the major advantages of the AD7124-8 is that it gives the

user the flexibility to employ one of three integrated power

modes. The current consumption, range of output data rates,

and rms noise can be tailored with the power mode selected.

The device also offers a multitude of filter options, ensuring that

the user has the highest degree of flexibility.

The AD7124-8 also has extensive diagnostic functionality

integrated as part of its comprehensive feature set. These

diagnostics include a cyclic redundancy check (CRC), signal

chain checks, and serial interface checks, which lead to a more

robust solution. These diagnostics reduce the need for external

components to implement diagnostics, resulting in reduced

board space needs, reduced design cycle times, and cost savings.

The failure modes effects and diagnostic analysis (FMEDA) of a

typical application has shown a safe failure fraction (SFF) greater

than 90% according to IEC 61508.

The AD7124-8 can achieve simultaneous 50 Hz and 60 Hz

rejection when operating at an output data rate of 25 SPS (single

cycle settling), with rejection in excess of 80 dB achieved at lower

output data rates.

The AD7124-8 establishes the highest degree of signal chain

integration. The device contains a precision, low noise, low

drift internal band gap reference and accepts an external

differential reference, which can be internally buffered. Other

key integrated features include programmable low drift excitation

current sources, burnout currents, and a bias voltage generator,

which sets the common-mode voltage of a channel to AV_DD/2.

The low-side power switch enables the user to power down

bridge sensors between conversions, ensuring the absolute

minimal power consumption of the system. The device also

allows the user the option of operating with either an internal

clock or an external clock.

The device operates with a single analog power supply from 2.7 V

to 3.6 V or a dual 1.8 V power supply. The digital supply has a

range of 1.65 V to 3.6 V. It is specified for a temperature range

of −40°C to +125°C. The AD7124-8 is housed in a 32-lead

LFCSP package.

Note that, throughout this data sheet, multifunction pins, such

RDY

as DOUT/

, are referred to either by the entire pin name or

RDY

by a single function of the pin, for example,

that function is relevant.

, when only

The integrated channel sequencer allows several channels to be

enabled simultaneously, and the AD7124-8 sequentially converts

Table 1. AD7124-8 Overview

Parameter

Low Power Mode

2400 SPS

24 nV

Mid Power Mode

4800 SPS

20 nV

Full Power Mode

19,200 SPS

23 nV

Maximum Output Data Rate

RMS Noise (Gain = 128)

Peak-to-Peak Resolution at 1200 SPS

(Gain = 1)

16.4 bits

17.1 bits

18 bits

Typical Current (ADC + PGA)

255 µA

355 µA

930 µA

Rev. D | Page 4 of 92

Data Sheet

AD7124-8

SPECIFICATIONS

AV_DD= 2.9 V to 3.6 V (full power mode), 2.7 V to 3.6 V (mid and low power mode), IOV_DD= 1.65 V to 3.6 V, AV_SS= DGND = 0 V,

REFINx(+) = 2.5 V, REFINx(−) = AV_SS, master clock = 614.4 kHz, all specifications T_MINto T_MAX, unless otherwise noted.

Table 2.

Parameter¹

Min

Typ

Max

Unit

Test Conditions/Comments

ADC

Output Data Rate, f_ADC

Low Power Mode

Mid Power Mode

Full Power Mode

No Missing Codes²

1.17

2.34

9.38

24

2400

4800

19,200

SPS

Bits

FS³> 2, sinc⁴filter

FS³> 8, sinc³filter

24

Resolution

See the RMS Noise and Resolution

section

RMS Noise and Update Rates

Integral Nonlinearity (INL)

See the RMS Noise and Resolution

section

Gain = 1²

Gain > 1⁴

−4

1

2

+4

ppm of FSR

−15

+15

Offset Error⁵

Before Calibration

15

200/gain

µV

Gain = 1 to 8

Gain = 16 to 128

After Internal Calibration/System

Calibration

Offset Error Drift vs. Temperature⁶

In order of

noise

Low Power Mode

10

80

40

10

40

20

10

nV/°C

Gain = 1 or gain > 16

Gain = 2 to 8

Gain = 16

Gain = 1 or gain > 16

Gain = 2 to 8

Gain = 16

Mid Power Mode

Full Power Mode

Gain Error^{5, 7}

Before Internal Calibration

−0.0025

−0.016

+0.0025

+0.016

%

Gain = 1, T_A= 25°C

Gain > 1

Gain = 2 to 8, T_A= 25°C

Gain = 16 to 128

−0.3

+0.004

0.025

In order of

noise

After Internal Calibration

After System Calibration

Gain Error Drift vs. Temperature

Power Supply Rejection

Low Power Mode

1

2

ppm/°C

A_IN= 1 V/gain, external reference

Gain = 2 to 16

Gain = 1 or gain > 16

Gain = 2 to 16

87

96

92

100

99

dB

Mid Power Mode²

Gain = 1 or gain > 16

Full Power Mode

Common-Mode Rejection⁸

At DC²

85

105

102^{9, 2}

115

105^{9, 2}

90

115

dB

A_IN= 1 V, gain = 1

At DC

A_IN= 1 V/gain, gain 2 or 4

A_IN= 1 V/gain, gain ≥ 8

120

Sinc³, Sinc⁴Filter²

At 50 Hz, 60 Hz

At 50 Hz

120

dB

10 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz

50 SPS, 50 Hz 1 Hz

60 SPS, 60 Hz 1 Hz

At 60 Hz

Rev. D | Page 5 of 92

AD7124-8

Data Sheet

Parameter¹

Min

Typ

Max

Unit

Test Conditions/Comments

Fast Settling Filters²

At 50 Hz

At 60 Hz

Post Filters²

115

dB

First notch at 50 Hz, 50 Hz 1 Hz

First notch at 60 Hz, 60 Hz 1 Hz

At 50 Hz, 60 Hz

130

dB

20 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz

25 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz

Normal Mode Rejection²

Sinc⁴Filter

External Clock

At 50 Hz, 60 Hz

120

80

dB

10 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz

50 SPS, REJ60¹⁰=1, 50 Hz 1 Hz,

60 Hz 1 Hz

At 50 Hz

At 60 Hz

120

dB

50 SPS, 50 Hz 1 Hz

60 SPS, 60 Hz 1 Hz

Internal Clock

At 50 Hz, 60 Hz

98

66

dB

10 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz

50 SPS, REJ60¹⁰= 1, 50 Hz 1 Hz,

60 Hz 1 Hz

At 50 Hz

At 60 Hz

92

dB

50 SPS, 50 Hz 1 Hz

60 SPS, 60 Hz 1 Hz

Sinc³Filter

External Clock

At 50 Hz, 60 Hz

100

65

dB

10 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz

50 SPS, REJ60¹⁰= 1, 50 Hz 1 Hz,

60 Hz 1 Hz

At 50 Hz

At 60 Hz

100

dB

50 SPS, 50 Hz 1 Hz

60 SPS, 60 Hz 1 Hz

Internal Clock

At 50 Hz, 60 Hz

73

52

dB

10 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz

50 SPS, REJ60¹⁰= 1, 50 Hz 1 Hz,

60 Hz 1 Hz

At 50 Hz

At 60 Hz

68

dB

50 SPS, 50 Hz 1 Hz

60 SPS, 60 Hz 1 Hz

Fast Settling Filters

External Clock

At 50 Hz

40

dB

First notch at 50 Hz, 50 Hz 0.5 Hz

First notch at 60 Hz, 60 Hz 0.5 Hz

At 60 Hz

Internal Clock

At 50 Hz

At 60 Hz

24.5

dB

First notch at 50 Hz, 50 Hz 0.5 Hz

First notch at 60 Hz, 60 Hz 0.5 Hz

Post Filters

External Clock

At 50 Hz, 60 Hz

86

62

dB

20 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz

25 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz

Internal Clock

At 50 Hz, 60 Hz

67

50

dB

20 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz

25 SPS, 50 Hz 1 Hz, 60 Hz 1 Hz

Rev. D | Page 6 of 92

Data Sheet

AD7124-8

Parameter¹

Min

Typ

V_REF/gain

Max

Unit

Test Conditions/Comments

ANALOG INPUTS¹¹

Differential Input Voltage Ranges¹²

V

V_REF= REFINx(+) − REFINx(−), or

internal reference

Absolute A_INVoltage Limits²

Gain = 1 (Unbuffered)

Gain = 1 (Buffered)

AV_SS− 0.05

AV_SS+ 0.1

AV_SS− 0.05

AV_DD+ 0.05

AV_DD− 0.1

AV_DD+ 0.05

V

Gain > 1

Analog Input Current

Gain > 1 or Gain = 1 (Buffered)

Low Power Mode

Absolute Input Current

Differential Input Current

Analog Input Current Drift

Mid Power Mode

1

0.2

25

nA

pA/°C

Absolute Input Current

Differential Input Current

Analog Input Current Drift

Full Power Mode

1.2

0.4

25

nA

pA/°C

Absolute Input Current

Differential Input Current

Analog Input Current Drift

Gain = 1 (Unbuffered)

Absolute Input Current

Analog Input Current Drift

REFERENCE INPUT

3.3

1.5

25

nA

pA/°C

Current varies with input voltage

2.65

1.1

µA/V

nA/V/°C

Internal Reference

Initial Accuracy

Drift

2.5 − 0.2%

2.5

2

2.5 + 0.2%

8

15

10

V

T_A= 25°C

T_A= 25°C to 125°C

T_A= −40°C to +125°C

ppm/°C

mA

Output Current

Load Regulation

Power Supply Rejection

External Reference

50

85

µV/mA

dB

External REFIN Voltage²

Absolute REFIN Voltage Limits²

1

2.5

AV_DD

AV_DD+ 0.05

AV_DD− 0.1

V

REFIN = REFINx(+) − REFINx(−)

Unbuffered

Buffered

AV_SS− 0.05

AV_SS+ 0.1

Reference Input Current

Buffered

Low Power Mode

Absolute Input Current

Reference Input Current Drift

Mid Power Mode

0.5

10

nA

pA/°C

Absolute Input Current

Reference Input Current Drift

Full Power Mode

1

10

nA

pA/°C

Absolute Input Current

Reference Input Current Drift

Unbuffered

3

10

nA

pA/°C

Absolute Input Current

Reference Input Current Drift

Normal Mode Rejection

Common-Mode Rejection

12

µA

nA/°C

6

Same as for analog inputs

100

dB

Rev. D | Page 7 of 92

AD7124-8

Data Sheet

Parameter¹

Min

Typ

Max

Unit

Test Conditions/Comments

EXCITATION CURRENT SOURCES (IOUT0/IOUT1)

Output Current

Available on any analog input pin

50/100/250/

500/750/1000

µA

Initial Tolerance

Drift

Current Matching

4

50

0.5

%

T_A= 25°C

ppm/°C

%

Matching between IOUT0 and

IOUT1, V_OUT= 0 V

Drift Matching²

Line Regulation (AV_DD

Load Regulation

Output Compliance²

5

2

0.2

30

ppm/°C

%/V

V

)

AV_DD= 3 V 5%

AV_SS− 0.05

AV_DD− 0.37

AV_DD− 0.48

50 µA/100 µA/250 µA/500 µA

current sources, 2% accuracy

750 µA and 1000 µA current

sources, 2% accuracy

V

BIAS VOLTAGE (V_BIAS) GENERATOR

V_BIAS

Available on any analog input pin

AV_SS+ (AV_DD

AV_SS)/2

−

V

V_BIASGenerator Start-Up Time

6.7

µs/nF

Dependent on the capacitance

connected to AINx

TEMPERATURE SENSOR

Accuracy

0.5

°C

Sensitivity

13,584

codes/°C

LOW-SIDE POWER SWITCH

On Resistance (R_ON

)

7

10

30

Ω

mA

Allowable Current²

BURNOUT CURRENTS

A_INCurrent

Continuous current

0.5/2/4

µA

Analog inputs must be buffered

DIGITAL OUTPUTS (P1 to P4)

Output Voltage

High, V_OH

Low, V_OL

AV_DD− 0.6

V

I_SOURCE= 100 µA

I_SINK= 100 µA

0.4

DIAGNOSTICS

Power Supply Monitor Detect Level

Analog Low Dropout Regulator (ALDO)

Digital LDO (DLDO)

Reference Detect Level

AINM/AINP Overvoltage Detect Level

AINM/AINP Undervoltage Detect Level

INTERNAL/EXTERNAL CLOCK

Internal Clock

1.6

1.55

1

V

AV_DD− AV_SS≥ 2.7 V

IOV_DD≥ 1.75 V

REF_DET_ERR bit active if V_REF< 0.7 V

0.7

AV_DD+ 0.04

AV_SS− 0.04

614.4 + 5%

Frequency

Duty Cycle

614.4 − 5%

614.4

50:50

kHz

%

External Clock

Frequency

Duty Cycle Range

2.4576

45:55 to 55:45

MHz

%

Internal divide by 4

LOGIC INPUTS²

Input Voltage

Low, V_INL

0.3 × IOV_DD

0.35 × IOV_DD

0.7

V

1.65 V ≤ IOV_DD< 1.9 V

1.9 V ≤ IOV_DD< 2.3 V

2.3 V ≤ IOV_DD≤ 3.6 V

1.65 V ≤ IOV_DD< 1.9 V

1.9 V ≤ IOV_DD< 2.3 V

2.3 V ≤ IOV_DD< 2.7 V

2.7 V ≤ IOV_DD≤ 3.6 V

1.65 V ≤ IOV_DD≤ 3.6 V

V_IN= IOV_DDor GND

All digital inputs

High, V_INH

0.7 × IOV_DD

0.65 × IOV_DD

1.7

2

0.2

−1

Hysteresis

Input Currents

Input Capacitance

0.6

+1

µA

pF

10

Rev. D | Page 8 of 92

Data Sheet

AD7124-8

Parameter¹

Min

Typ

Max

Unit

Test Conditions/Comments

LOGIC OUTPUTS (INCLUDING CLK)

Output Voltage²

High, V_OH

V

I_SOURCE= 100 µA

I_SINK= 100 µA

IOV_DD− 0.35

−1

Low, V_OL

0.4

+1

V

µA

pF

Floating State Leakage Current

Floating State Output Capacitance

Data Output Coding

SYSTEM CALIBRATION²

Calibration Limit

Full-Scale

10

Offset binary

1.05 × FS

2.1 × FS

V

Zero-Scale

Input Span

−1.05 × FS

0.8 × FS

POWER SUPPLY VOLTAGES FOR ALL POWER

MODES

AV_DDto AV_SS

Low Power Mode

Mid Power Mode

Full Power Mode

IOV_DDto GND

AV_SSto GND

IOV_DDto AV_SS

2.7

2.9

1.65

−1.8

3.6

0

V

5.4

POWER SUPPLY CURRENTS^{11, 13}

I_AVDD, External Reference

Low Power Mode

Gain = 1²

Gain = 1 I_AVDDIncrease per AINx Buffer²

Gain = 2 to 8

Gain = 16 to 128

I_AVDDIncrease per Reference Buffer²

125

15

205

235

10

140

25

250

300

20

µA

All buffers off

All gains

Mid Power Mode

Gain = 1²

Gain = 1 I_AVDDIncrease per AINx Buffer²

Gain = 2 to 8

150

30

275

330

20

170

40

345

430

30

µA

All buffers off

Gain = 16 to 128

I_AVDDIncrease per Reference Buffer²

Full Power Mode

All gains

Gain = 1²

Gain = 1 I_AVDDIncrease per AINx Buffer²

Gain = 2 to 8

315

90

660

875

85

350

135

830

1200

120

µA

All buffers off

Gain = 16 to 128

I_AVDDIncrease per Reference Buffer²

I_AVDDIncrease

All gains

Due to Internal Reference²

50

70

µA

Independent of power mode; the

reference buffers are not required

when using this reference

2

Due to V_BIAS

15

4

20

5

µA

Independent of power mode

Due to Diagnostics²

I_IOVDD

Low Power Mode

Mid Power Mode

Full Power Mode

20

25

55

35

40

80

µA

Rev. D | Page 9 of 92

AD7124-8

Data Sheet

Parameter¹

Min

Typ

Max

Unit

Test Conditions/Comments

POWER-DOWN CURRENTS¹³

Independent of power mode

LDOs on only

Standby Current

I_AVDD

I_IOVDD

7

8

15

20

µA

Power-Down Current

I_AVDD

I_IOVDD

1

3

2

µA

¹Temperature range = −40°C to +125°C.

²These specifications are not production tested but are supported by characterization data at the initial product release.

³FS is the decimal equivalent of the FS[10:0] bits in the filter registers.

⁴The nonlinearity is production tested in full power mode. For the other power modes, this specification is supported by characterization data at the initial product

release.

⁵Following a system or internal zero-scale calibration, the offset error is in the order of the noise for the programmed gain and output data rate selected. A system full-

scale calibration reduces the gain error to the order of the noise for the programmed gain and output data rate.

⁶Recalibration at any temperature removes these errors.

⁷Gain error applies to both positive and negative full-scale. A factory calibration is performed at gain = 1, T_A= 25°C.

⁸When gain > 1, the common-mode voltage is between (AV_SS+ 0.1 + 0.5/gain) and (AV_DD− 0.1 − 0.5/gain).

⁹Specification is for a wider common-mode voltage between (AV_SS− 0.05 + 0.5/gain) and (AV_DD− 0.1 − 0.5/gain).

¹⁰REJ60 is a bit in the filter registers. When the first notch of the sinc filter is at 50 Hz, a notch is placed at 60 Hz when REJ60 is set to 1. This gives simultaneous 50 Hz and

60 Hz rejection.

¹¹When the gain is greater than 1, the analog input buffers are enabled automatically. The buffers can only be disabled when the gain equals 1.

¹²When V_REF= (AV_DD− AV_SS), the typical differential input equals 0.92 × V_REF/gain for the low and mid power modes and 0.86 × V_REF/gain for full power mode.

¹³The digital inputs are equal to IOV_DDor DGND with excitation currents and bias voltage generator disabled.

TIMING CHARACTERISTICS

AV_DD= 2.9 V to 3.6 V (full power mode), 2.7 V to 3.6 V (mid and low power mode), IOV_DD= 1.65 V to 3.6 V, AV _SS= DGND = 0 V, Input

Logic 0 = 0 V, Input Logic 1 = IOV_DD, unless otherwise noted.

Table 3.

Parameter^{1, 2}

Min

100

Typ

Max

Unit

ns

Test Conditions/Comments

t₃

t₄

SCLK high pulse width

SCLK low pulse width

t₁₂

Delay between consecutive read/write operations

Full power mode

Mid power mode

3/MCLK³

12/MCLK

24/MCLK

ns

µs

Low power mode

t₁₃

DOUT/RDY high time if DOUT/RDY is low and the next

conversion is available

Full power mode

Mid power mode

Low power mode

6

25

50

µs

t₁₄

SYNC low pulse width

3/MCLK

12/MCLK

24/MCLK

ns

Full power mode

Mid power mode

Low power mode

READ OPERATION

t₁

0

80

ns

CS falling edge to DOUT/RDY active time

SCLK active edge⁵to data valid delay

Bus relinquish time after CS inactive edge

SCLK inactive edge to CS inactive edge

SCLK inactive edge to DOUT/RDY high

4

t₂

0

10

0

6, 7

t₅

t₆

8

t₇

10

ns

The DOUT_RDY_DEL bit is cleared, the CS_EN bit is

cleared

110

t₅

ns

The DOUT_RDY_DEL bit is set, the CS_EN bit is cleared

7

t_7A

Data valid after CS inactive edge, the CS_EN bit is set

Rev. D | Page 10 of 92

Data Sheet

AD7124-8

Parameter^{1, 2}

Min

Typ

Max

Unit

Test Conditions/Comments

WRITE OPERATION

t₈

0

ns

CS falling edge to SCLK active edge⁵setup time

Data valid to SCLK edge setup time

Data valid to SCLK edge hold time

CS rising edge to SCLK edge hold time

t₉

t₁₀

t₁₁

30

25

0

¹These specifications were sample tested during the initial release to ensure compliance. All input signals are specified with t_R= t_F= 5 ns (10% to 90% of IOV_DDand

timed from a voltage level of IOV_DD/2.

²See Figure 3, Figure 4, Figure 5, and Figure 6.

³MCLK is the master clock frequency.

⁴These specifications are measured with the load circuit shown in Figure 2 and defined as the time required for the output to cross the V_OLor V_OHlimits.

⁵The SCLK active edge is the falling edge of SCLK.

⁶These specifications are derived from the measured time taken by the data output to change by 0.5 V when loaded with the circuit shown in Figure 2. The measured

number is then extrapolated back to remove the effects of charging or discharging the 25 pF capacitor. The times quoted in the timing characteristics are the true bus

relinquish times of the device and, therefore, are independent of external bus loading capacitances.

⁷RDY

RDY

returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while

although subsequent reads must not occur close to the next output update. In continuous read mode, the digital word can be read only once.

is high,

8

CS

RDY

CS

When the _EN bit is cleared, the DOUT/

pin changes from its DOUT function to its

CS

function, following the last inactive edge of the SCLK. When _EN is set,

the DOUT pin continues to output the LSB of the data until the inactive edge.

Timing Diagrams

I

(100µA)

SINK

TO OUTPUT PIN

25pF

IOV /2

DD

I

(100µA)

SOURCE

Figure 2. Load Circuit for Timing Characterization

CS (I)

t₆

t₅

t₁

DOUT/RDY (O)

MSB

t₂

LSB

t₇

t₃

SCLK (I)

t₄

I = INPUT, O = OUTPUT

CS

Figure 3. Read Cycle Timing Diagram ( _EN Bit Cleared)

Rev. D | Page 11 of 92

AD7124-8

Data Sheet

CS (I)

t₆

t₁

t₅

DOUT/RDY (O)

MSB

LSB

t_7A

t₂

t₃

SCLK (I)

t₄

I = INPUT, O = OUTPUT

CS

Figure 4. Read Cycle Timing Diagram ( _EN Bit Set)

CS (I)

t₁₁

t₈

SCLK (I)

DIN (I)

t₉

t₁₀

MSB

LSB

I = INPUT, O = OUTPUT

Figure 5. Write Cycle Timing Diagram

t₁₂

WRITE

t₁₂

DIN

t₁₂

READ

DOUT/RDY

SCLK

Figure 6. Delay Between Consecutive Serial Operations

CS

DIN

t₁₃

DOUT/RDY

SCLK

RDY

High Time when DOUT/

Figure 7. DOUT/

is Initially Low and the Next Conversion is Available

SYNC (I)

t₁₄

MCLK (I)

SYNC

Figure 8.

Pulse Width

Rev. D | Page 12 of 92

Data Sheet

AD7124-8

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.

THERMAL RESISTANCE

θ_JAis specified for the worst case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 4.

Parameter

Rating

AV_DDto AV_SS

IOV_DDto DGND

IOV_DDto AV_SS

AV_SSto DGND

−0.3 V to +3.96 V

−0.3 V to +5.94 V

−1.98 V to +0.3 V

−0.3 V to AV_DD+ 0.3 V

−0.3 V to IOV_DD+ 0.3 V

10 mA

Table 5. Thermal Resistance

Package Type

θ_JA

θ_JC

Unit

32-Lead LFCSP

32.5

32.71

°C/W

Analog Input Voltage to AV_SS

Reference Input Voltage to AV_SS

Digital Input Voltage to DGND

Digital Output Voltage to DGND

AINx/Digital Input Current

Operating Temperature Range

Storage Temperature Range

Maximum Junction Temperature

Lead Temperature, Soldering

Reflow

ESD CAUTION

−40°C to +125°C

−65°C to +150°C

150°C

260°C

ESD Ratings

Human Body Model (HBM)

4 kV

Field-Induced Charged Device

Model (FICDM)

1250 V

Machine Model

400 V

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Rev. D | Page 13 of 92

AD7124-8

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REGCAPD

IOV

DGND

AIN0/IOUT/VBIAS 4

AIN1/IOUT/VBIAS 5

1

2

3

24 REGCAPA

23

22 REFOUT

21 AIN15/IOUT/VBIAS/REFIN2(–)

20 AIN14/IOUT/VBIAS/REFIN2(+)

19

AIN13/IOUT/VBIAS

AV

DD

SS

AD7124-8

TOP VIEW

(Not to Scale)

6

AIN2/IOUT/VBIAS/P1

AIN3/IOUT/VBIAS/P2 7

AIN4/IOUT/VBIAS/P3 8

18 AIN12/IOUT/VBIAS

17 AIN11/IOUT/VBIAS

NOTES

1. CONNECT EXPOSED PAD TO AV

.

SS

Figure 9. Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

REGCAPD

IOV_DD

Description

1

2

Digital LDO Regulator Output. Decouple this pin to DGND with a 0.1 µF capacitor.

Serial Interface Supply Voltage, 1.65 V to 3.6 V. IOV_DDis independent of AV_DD. Therefore, the serial interface

can operate at 1.65 V with AV_DDat 3.6 V, for example.

3

4

DGND

AIN0/IOUT/VBIAS

Digital Ground Reference Point.

Analog Input 0/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via

the configuration registers to be the positive or negative terminal of a differential or pseudo differential

input. Alternatively, the internal programmable excitation current source can be made available at this pin.

Either IOUT1 or IOUT0 can be switched to this output. A bias voltage midway between the analog power

supply rails can be generated at this pin.

5

6

AIN1/IOUT/VBIAS

Analog Input 1/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via

the configuration registers to be the positive or negative terminal of a differential or pseudo differential

input. Alternatively, the internal programmable excitation current source can be made available at this pin.

Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power

supply rails can be generated at this pin.

AIN2/IOUT/VBIAS/P1 Analog Input 2/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 1. This

input pin is configured via the configuration registers to be the positive or negative terminal of a

differential or pseudo differential input. Alternatively, the internal programmable excitation current source

can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin. This pin can also be configured

as a general-purpose output bit, referenced between AV_SSand AV_DD

.

7

8

AIN3/IOUT/VBIAS/P2 Analog Input 3/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 2. This

input pin is configured via the configuration registers to be the positive or negative terminal of a

differential or pseudo differential input. Alternatively, the internal programmable excitation current source

can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin. This pin can also be configured

as a general-purpose output bit, referenced between AV_SSand AV_DD

.

AIN4/IOUT/VBIAS/P3 Analog Input 4/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 3. This

input pin is configured via the configuration registers to be the positive or negative terminal of a

differential or pseudo differential input. Alternatively, the internal programmable excitation current source

can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin. This pin can also be configured

as a general-purpose output bit, referenced between AV_SSand AV_DD

.

Rev. D | Page 14 of 92

Data Sheet

AD7124-8

Pin No.

Mnemonic

Description

9

AIN5/IOUT/VBIAS/P4 Analog Input 5/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 4. This

input pin is configured via the configuration registers to be the positive or negative terminal of a

differential or pseudo differential input. Alternatively, the internal programmable excitation current source

can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin. This pin can also be configured

as a general-purpose output bit, referenced between AV_SSand AV_DD

.

10

11

12

AIN6/IOUT/VBIAS

AIN7/IOUT/VBIAS

REFIN1(+)

Analog Input 6/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via

the configuration registers to be the positive or negative terminal of a differential or pseudo differential

input. Alternatively, the internal programmable excitation current source can be made available at this pin.

Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power

supply rails can be generated at this pin.

Analog Input 7/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via

the configuration registers to be the positive or negative terminal of a differential or pseudo differential

input. Alternatively, the internal programmable excitation current source can be made available at this pin.

Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power

supply rails can be generated at this pin.

Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−).

REFIN1(+) can be anywhere between AV_DDand AV_SS+ 1 V. The nominal reference voltage (REFIN1(+) −

REFIN1(−)) is 2.5 V, but the device functions with a reference from 1 V to AV_DD

.

13

14

REFIN1(−)

AIN8/IOUT/VBIAS

Negative Reference Input. This reference input can be anywhere between AV_SSand AV_DD− 1 V.

Analog Input 8/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the

configuration registers to be the positive or negative terminal of a differential or pseudo differential input.

Alternatively, the internal programmable excitation current source can be made available at this pin. Either

IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply

rails can be generated at this pin.

15

16

17

18

19

20

AIN9/IOUT/VBIAS

AIN10/IOUT/VBIAS

AIN11/IOUT/VBIAS

AIN12/IOUT/VBIAS

AIN13/IOUT/VBIAS

Analog Input 9/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the

configuration registers to be the positive or negative terminal of a differential or pseudo differential input.

Alternatively, the internal programmable excitation current source can be made available at this pin. Either

IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply

rails can be generated at this pin.

Analog Input 10/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the

configuration registers to be the positive or negative terminal of a differential or pseudo differential input.

Alternatively, the internal programmable excitation current source can be made available at this pin. Either

IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply

rails can be generated at this pin.

Analog Input 11/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the

configuration registers to be the positive or negative terminal of a differential or pseudo differential input.

Alternatively, the internal programmable excitation current source can be made available at this pin. Either

IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply

rails can be generated at this pin.

Analog Input 12/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the

configuration registers to be the positive or negative terminal of a differential or pseudo differential input.

Alternatively, the internal programmable excitation current source can be made available at this pin. Either

IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply

rails can be generated at this pin.

Analog Input 13/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured via the

configuration registers to be the positive or negative terminal of a differential or pseudo differential input.

Alternatively, the internal programmable excitation current source can be made available at this pin. Either

IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply

rails can be generated at this pin.

AIN14/IOUT/VBIAS/ Analog Input 14/Output of Internal Excitation Current Source/Bias Voltage/Positive Reference Input. This

REFIN2(+)

input pin is configured via the configuration registers to be the positive or negative terminal of a

differential or pseudo differential input. Alternatively, the internal programmable excitation current source

can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin. This pin also functions as a

positive reference input for REFIN2( ). REFIN2(+) can be anywhere between AV_DDand AV_SS+ 1 V. The

nominal reference voltage (REFIN2(+) to REFIN2(−)) is 2.5 V, but the device functions with a reference from 1 V

to AV_DD

.

Rev. D | Page 15 of 92

AD7124-8

Data Sheet

Pin No.

Mnemonic

Description

21

AIN15/IOUT/VBIAS/ Analog Input 15/Output of Internal Excitation Current Source/Bias Voltage/Negative Reference Input. This

REFIN2(−)

input pin is configured via the configuration registers to be the positive or negative terminal of a

differential or pseudo differential input. Alternatively, the internal programmable excitation current source

can be made available at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage

midway between the analog power supply rails can be generated at this pin. This pin also functions as the

negative reference input for REFIN2( ). This reference input can be anywhere between AV_SSand AV_DD− 1 V.

22

23

REFOUT

AV_SS

Internal Reference Output. The buffered output of the internal 2.5 V voltage reference is available on this pin.

Analog Supply Voltage. The voltage on AV_DDis referenced to AV_SS. The differential between AV_DDand AV_SS

must be between 2.7 V and 3.6 V in mid or low power mode and between 2.9 V and 3.6 V in full power

mode. AV_SScan be taken below 0 V to provide a dual power supply to the AD7124-8. For example, AV_SS

can be tied to −1.8 V and AV_DDcan be tied to +1.8 V, providing a 1.8 V supply to the ADC.

24

25

26

27

REGCAPA

PSW

AV_DD

Analog LDO Regulator Output. Decouple this pin to AV_SSwith a 0.1 µF capacitor.

Low-Side Power Switch to AV_SS.

Analog Supply Voltage, Relative to AV_SS.

Synchronization Input. This pin is a logic input that allows synchronization of the digital filters and analog

modulators when using a number of AD7124-8 devices. When SYNC is low, the nodes of the digital filter,

the filter control logic, and the calibration control logic are reset, and the analog modulator is held in a

reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low.

SYNC

28

DOUT/RDY

Serial Data Output/Data Ready Output. DOUT/RDY functions as a serial data output pin to access the

output shift register of the ADC. The output shift register can contain data from any of the on-chip data or

control registers. In addition, DOUT/RDY operates as a data ready pin, going low to indicate the completion of a

conversion. If the data is not read after the conversion, the pin goes high before the next update occurs.

The DOUT/RDY falling edge can also be used as an interrupt to a processor, indicating that valid data is

available. With an external serial clock, the data can be read using the DOUT/RDY pin. When CS is low, the

data/control word information is placed on the DOUT/RDY pin on the SCLK falling edge and is valid on

the SCLK rising edge.

29

30

DIN

Serial Data Input to the Input Shift Register on the ADC. Data in the input shift register is transferred to

the control registers within the ADC, with the register selection bits of the communications register

identifying the appropriate register.

Serial Clock Input. This serial clock input is for data transfers to and from the ADC. The SCLK pin has a Schmitt-

triggered input, making the interface suitable for opto-isolated applications. The serial clock can be continuous

with all data transmitted in a continuous train of pulses. Alternatively, it can be a noncontinuous clock

with the information being transmitted to or from the ADC in smaller batches of data.

SCLK

31

32

CLK

CS

Clock Input/Clock Output. The internal clock can be made available at this pin. Alternatively, the internal

clock can be disabled, and the ADC can be driven by an external clock. This allows several ADCs to be

driven from a common clock, allowing simultaneous conversions to be performed.

Chip Select Input. This is an active low logic input that selects the ADC. Use CS to select the ADC in systems

with more than one device on the serial bus or as a frame synchronization signal in communicating with the

device. CS can be hardwired low if the serial peripheral interface (SPI) diagnostics are unused, allowing the

ADC to operate in 3-wire mode with SCLK, DIN, and DOUT interfacing with the device.

EP

Exposed Pad. Connect the exposed pad to AV_SS.

Rev. D | Page 16 of 92

Data Sheet

AD7124-8

TERMINOLOGY

AINP

AINP refers to the positive analog input.

Offset Error

Offset error is the deviation of the first code transition from the

ideal AINP voltage (AINM + 0.5 LSB) when operating in the

unipolar mode.

AINM

AINM refers to the negative analog input.

In bipolar mode, offset error is the deviation of the midscale

transition (0111 … 111 to 1000 … 000) from the ideal AINP

voltage (AINM − 0.5 LSB).

Integral Nonlinearity (INL)

INL is the maximum deviation of any code from a straight line

passing through the endpoints of the transfer function. The

endpoints of the transfer function are zero scale (not to be

confused with bipolar zero), a point 0.5 LSB below the first code

transition (000 … 000 to 000 … 001), and full scale, a point

0.5 LSB above the last code transition (111 … 110 to 111 …

111). The error is expressed in ppm of the full-scale range.

Offset Calibration Range

In the system calibration modes, the AD7124-8 calibrates offset

with respect to the analog input. The offset calibration range

specification defines the range of voltages that the AD7124-8

can accept and still calibrate offset accurately.

Gain Error

Full-Scale Calibration Range

Gain error is the deviation of the last code transition (111 …

110 to 111 … 111) from the ideal AINP voltage (AINM +

The full-scale calibration range is the range of voltages that the

AD7124-8 can accept in the system calibration mode and still

calibrate full scale correctly.

V

_REF/gain − 3/2 LSBs). Gain error applies to both unipolar

and bipolar analog input ranges.

Input Span

Gain error is a measure of the span error of the ADC. It

includes full-scale errors but not zero-scale errors. For unipolar

input ranges, it is defined as full-scale error minus unipolar

offset error; whereas for bipolar input ranges it is defined as

full-scale error minus bipolar zero error.

In system calibration schemes, two voltages applied in sequence

to the AD7124-8 analog input define the analog input range.

The input span specification defines the minimum and

maximum input voltages from zero to full scale that the

AD7124-8 can accept and still calibrate gain accurately.

Rev. D | Page 17 of 92

AD7124-8

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

2500

350

300

250

200

150

10,000 SAMPLES

2000

1500

1000

100

50

500

0

CODES (HEX)

Figure 10. Noise Histogram Plot (Full Power Mode, Post Filter, Output Data

Rate = 25 SPS, Gain = 1)

Figure 13. Noise Histogram Plot (Full Power Mode, Post Filter, Output Data

Rate = 25 SPS, Gain = 128)

1200

400

10,000 SAMPLES

350

300

250

200

1000

800

600

400

150

100

50

200

0

CODES (HEX)

Figure 11. Noise Histogram Plot (Mid Power Mode, Post Filter, Output Data

Rate = 25 SPS, Gain = 1)

Figure 14. Noise Histogram Plot (Mid Power Mode, Post Filter, Output Data

Rate = 25 SPS, Gain = 128)

700

400

10,000 SAMPLES

350

300

250

200

150

100

600

500

400

300

200

100

50

0

CODES (HEX)

Figure 15. Noise Histogram Plot (Low Power Mode, Post Filter, Output Data

Rate = 25 SPS, Gain = 128)

Figure 12. Noise Histogram Plot (Low Power Mode, Post Filter, Output Data

Rate = 25 SPS, Gain = 1)

Rev. D | Page 18 of 92

Data Sheet

AD7124-8

60

40

60

100 UNITS

40

20

0

–20

–40

–60

–20

–40

–60

–40 –25 –10

5

20

35

50

65

80

95 110 125

–40 –25 –10

5

20

35

50

65

80

95 110 125

TEMPERATURE (°C)

Figure 16. Input Referred Offset Error vs. Temperature

(Gain = 8, Full Power Mode)

Figure 19. Input Referred Offset Error vs. Temperature

(Gain = 16, Full Power Mode)

60

40

60

40

100 UNITS

20

0

–20

–40

–60

–20

–40

–60

–40 –25 –10

5

20

35

50

65

80

95 110 125

–40 –25 –10

5

20

35

50

65

80

95 110 125

TEMPERATURE (°C)

Figure 17. Input Referred Offset Error vs. Temperature

(Gain = 8, Mid Power Mode)

Figure 20. Input Referred Offset Error vs. Temperature

(Gain = 16, Mid Power Mode)

60

40

60

40

100 UNITS

20

0

–20

–40

–60

–20

–40

–60

–40 –25 –10

5

20

35

50

65

80

95 110 125

–40 –25 –10

5

20

35

50

65

80

95 110 125

TEMPERATURE (°C)

Figure 18. Input Referred Offset Error vs. Temperature

(Gain = 8, Low Power Mode)

Figure 21. Input Referred Offset Error vs. Temperature

(Gain = 16, Low Power Mode)

Rev. D | Page 19 of 92

AD7124-8

Data Sheet

60

0.045

0.040

0.035

0.030

0.025

0.020

0.015

0.010

0.005

0

100 UNITS

56 UNITS

40

20

0

–20

–40

–60

–0.005

–40 –25 –10

5

20

35

50

65

80

95 110 125

–40 –25 –10

5

20

35

50

65

80

95 110 125

TEMPERATURE (°C)

Figure 22. Input Referred Offset Error vs. Temperature

(Gain = 1, Analog Input Buffers Enabled)

Figure 25. Input Referred Gain Error vs. Temperature (Gain = 16)

0.0010

0.0005

0

3

56 UNITS

GAIN = 1

GAIN = 8

GAIN = 16

2

1

0

–0.0005

–0.0010

–0.0015

–1

–2

–3

–40 –25 –10

5

20

35

50

65

80

95 110 125

–2.5 –2.0 –1.5 –1.0 –0.5

0

0.5

1.0

1.5

2.0

2.5

ANALOG INPUT VOLTAGE × GAIN (V)

TEMPERATURE (°C)

Figure 26. INL vs. Differential Input Signal (Analog Input × Gain),

ODR = 50 SPS, External 2.5 V Reference

Figure 23. Input Referred Gain Error vs. Temperature (Gain = 1)

4

0.015

56 UNITS

GAIN = 1

GAIN = 8

GAIN = 16

3

2

0.010

0.005

0

1

0

–1

–2

–3

–4

–0.005

–0.010

–2.5

–1.5

–0.5

0.5

1.5

2.5

–40 –25 –10

5

20

35

50

65

80

95 110 125

ANALOG INPUT VOLTAGE × GAIN (V)

TEMPERATURE (°C)

Figure 24. Input Referred Gain Error vs. Temperature (Gain = 8)

Figure 27. INL vs. Differential Input Signal (Analog Input × Gain),

ODR = 50 SPS, Internal Reference

Rev. D | Page 20 of 92

Data Sheet

AD7124-8

30

25

109 UNITS

20

15

10

5

20

15

10

5

0

INITIAL ACCURACY (V)

EXCITATION CURRENT MATCHING (%)

Figure 28. Internal Reference Voltage Histogram

Figure 31. IOUTx Current Initial Matching Histogram (500 µA)

2.5020

2.5015

2.5010

2.5005

2.5000

2.4995

2.4990

2.4985

2.4980

2.4975

2.4970

2.4965

490

30 UNITS

29 UNITS

485

480

475

470

465

460

–40 –25 –10

5

20

35

50

65

80

95 110 125

–40 –25 –10

5

20

35

50

65

80

95 110 125

TEMPERATURE (°C)

Figure 29. Internal Reference Voltage vs. Temperature

Figure 32. Excitation Current Drift (500 µA)

25

0

109 UNITS

29 UNITS

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

20

15

10

5

0

–40 –25 –10

5

20

35

50

65

80

95 110 125

TEMPERATURE (°C)

EXCITATION CURRENT ACCURACY (%)

Figure 30. IOUTx Current Initial Accuracy Histogram (500 µA)

Figure 33. Excitation Current Drift Matching (500 µA)

Rev. D | Page 21 of 92

AD7124-8

Data Sheet

450

400

350

300

250

200

150

100

50

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

50µA

100µA

250µA

500µA

750µA

1mA

0.2

GAIN = 1, AIN BUFFERS OFF

GAIN = 2 TO 8

0.1

0

GAIN = 1, AIN BUFFERS ON

GAIN = 16 TO 128

0

0.33 0.66 0.99 1.32 1.65 1.98 2.31 2.64 2.97 3.30

–40 –25 –10

5

20

35

50

65

80

95 110 125

V

(V)

LOAD

TEMPERATURE (°C)

Figure 34. Output Compliance (AV_DD= 3.3 V)

Figure 37. Analog Current vs. Temperature (Mid Power Mode)

350

300

250

200

150

100

1.000

0.995

0.990

0.985

0.980

0.975

0.970

0.965

0.960

50µA

100µA

250µA

500µA

750µA

GAIN = 1, AIN BUFFERS OFF

50

GAIN = 1, AIN BUFFERS ON

GAIN = 2 TO 8

0.955

0.950

GAIN = 16 TO 128

0

0.33 0.66 0.99 1.32 1.65 1.98 2.31 2.64 2.97 3.30

–40 –25 –10

5

20

35

50

65

80

95 110 125

V

(V)

LOAD

TEMPERATURE (°C)

Figure 35. Output Compliance (AV_DD= 3.3 V)

Figure 38. Analog Current vs. Temperature (Low Power Mode)

1200

1000

800

600

400

200

0

70

GAIN = 1, AIN BUFFERS OFF

GAIN = 2 TO 8

FULL POWER

MID POWER

GAIN = 1, AIN BUFFERS ON

GAIN = 16 TO 128

LOW POWER

60

50

40

30

20

10

0

–40 –25 –10

5

20

35

50

65

80

95 110 125

–40 –25 –10

5

20

35

50

65

80

95 110 125

TEMPERATURE (°C)

Figure 36. Analog Current vs. Temperature (Full Power Mode)

Figure 39. Digital Current vs. Temperature

Rev. D | Page 22 of 92

Data Sheet

AD7124-8

6

2

0

4

2

0

–2

–4

–6

–8

–10

–2

–4

–6

–8

–10

GAIN = 1

GAIN = 2

GAIN = 8

GAIN = 32

GAIN = 128

GAIN = 1

GAIN = 4

GAIN = 16

GAIN = 64

GAIN = 2

GAIN = 8

GAIN = 32

GAIN = 128

GAIN = 4

GAIN = 16

GAIN = 64

–12

–14

–40 –25 –10

5

20

35

50

65

80

95 110 125

–40 –25 –10

5

20

35

50

65

80

95 110 125

TEMPERATURE (°C)

Figure 40. Absolute Analog Input Current vs. Temperature (Full Power Mode)

Figure 43. Differential Analog Input Current vs. Temperature (Full Power Mode)

4

3

1

0

2

–1

–2

1

0

A)

–3

–4

–5

–6

–7

–8

–9

n

(

–1

–2

–3

–4

–5

NT

CURE

GAIN = 1

GAIN = 4

GAIN = 16

GAIN = 64

GAIN = 2

GAIN = 8

GAIN = 32

GAIN = 128

GAIN = 1

GAIN = 4

GAIN = 16

GAIN = 64

GAIN = 2

GAIN = 8

GAIN = 32

GAIN = 128

–6

–7

–40 –25 –10

5

20

35

50

65

80

95 110 125

–40 –25 –10

5

20

35

50

65

80

95 110 125

TEMPERATURE (°C)

Figure 41. Absolute Analog Input Current vs. Temperature (Mid Power Mode)

Figure 44. Differential Analog Input Current vs. Temperature (Mid Power Mode)

2

1

0

–1

–2

–3

–4

–1

–2

–3

–4

GAIN = 1

GAIN = 4

GAIN = 16

GAIN = 64

GAIN = 2

GAIN = 8

GAIN = 32

GAIN = 128

GAIN = 1

GAIN = 4

GAIN = 16

GAIN = 64

GAIN = 2

GAIN = 8

GAIN = 32

GAIN = 128

–5

–6

–5

–6

–40 –25 –10

5

20

35

50

65

80

95 110 125

–40 –25 –10

5

20

35

50

65

80

95 110 125

TEMPERATURE (°C)

Figure 42. Absolute Analog Input Current vs. Temperature (Low Power Mode)

Figure 45. Differential Analog Input Current vs. Temperature (Low Power Mode)

Rev. D | Page 23 of 92

AD7124-8

Data Sheet

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

23

22

21

20

19

18

17

16

15

14

G = 1 BUFF OFF

G = 1

G = 2

G = 4

13

12

11

10

G = 8

G = 16

G = 32

FULL POWER

G = 64

MID POWER

LOW POWER

G = 128

–4.0

–40 –25 –10

5

20

35

50

65

80

95 110 125

1

10

100

1k

10k

OUTPUT DATA RATE, SETTLED (SPS)

TEMPERATURE (°C)

Figure 49. Peak-to-Peak Resolution vs. Output Data Rate (Settled), Sinc³Filter

(Full Power Mode)

Figure 46. Reference Input Current vs. Temperature (Reference Buffers Enabled)

1.2

23

22

32 UNITS

1.0

0.8

21

20

19

18

17

16

0.6

0.4

0.2

15

G = 1 BUFF OFF

G = 1

14

0

G = 2

G = 4

13

–0.2

–0.4

–0.6

G = 8

G = 16

G = 32

G = 64

G = 128

12

11

10

–40 –30 –20 –10

0

15 25 40 50 60 70 85 95 105 115 125

TEMPERATURE (°C)

1

10

100

1k

10k

OUTPUT DATA RATE (SPS)

Figure 50. Peak-to-Peak Resolution vs. Output Data Rate, Sinc⁴+ Sinc¹Filter

(Full Power Mode)

Figure 47. Temperature Sensor Accuracy

23

22

23

22

21

20

21

20

19

18

17

16

19

18

17

16

15

14

G = 1 BUFF OFF

G = 1

14

G = 2

G = 4

13

12

11

10

G = 8

G = 16

12

G = 32

G = 64

11

10

G = 64

G = 128

1

10

100

1k

10k

1

10

100

1k

10k

OUTPUT DATA RATE (SPS)

OUTPUT DATA RATE, SETTLED (SPS)

Figure 51. Peak-to-Peak Resolution vs. Output Data Rate, Sinc³+ Sinc¹Filter

(Full Power Mode)

Figure 48. Peak-to-Peak Resolution vs. Output Data Rate (Settled), Sinc⁴Filter

(Full Power Mode)

Rev. D | Page 24 of 92

Data Sheet

AD7124-8

23

22

23

22

21

20

21

20

19

18

17

16

19

18

17

16

15

14

G = 1 BUFF OFF

G = 1

G = 1 BUFF OFF

G = 1

14

G = 2

G = 4

13

12

11

10

13

12

11

10

G = 8

G = 16

G = 32

G = 64

G = 128

G = 32

G = 64

G = 128

1

10

100

1k

10k

100k

1

10

100

1k

OUTPUT DATA RATE, SETTLED (SPS)

OUTPUT DATA RATE (SPS)

Figure 52. Peak-to-Peak Resolution vs. Output Data Rate (Settled), Sinc⁴Filter

(Mid Power Mode)

Figure 55. Peak-to-Peak Resolution vs. Output Data Rate, Sinc³+ Sinc¹Filter

(Mid Power Mode)

23

22

23

22

21

20

21

20

19

18

17

16

19

18

17

16

15

G = 1 BUFF OFF

G = 1 AIN BUFF OFF

G = 1

14

G = 2

G = 4

13

12

11

10

G = 8

G = 16

G = 32

G = 64

G = 128

12

G = 32

G = 64

11

G = 128

10

1

10

100

1k

10k

100k

1

10

100

1k

10k

OUTPUT DATA RATE, SETTLED (SPS)

Figure 53. Peak-to-Peak Resolution vs. Output Data Rate (Settled), Sinc³Filter

(Mid Power Mode)

Figure 56. Peak-to-Peak Resolution vs. Output Data Rate (Settled), Sinc⁴Filter

(Low Power Mode)

23

22

23

22

21

20

19

18

17

16

18

17

16

15

G = 1 AIN BUFF OFF

G = 1 BUFF OFF

14

G = 1

14

G = 2

13

G = 4

13

12

G = 8

G = 16

G = 32

G = 64

G = 128

G = 16

G = 32

G = 64

G = 128

12

11

10

11

10

9

1

10

100

1k

1

10

100

1k

10k

OUTPUT DATA RATE (SPS)

OUTPUT DATA RATE, SETTLED (SPS)

Figure 54. Peak-to-Peak Resolution vs. Output Data Rate, Sinc⁴+ Sinc¹Filter

(Mid Power Mode)

Figure 57. Peak-to-Peak Resolution vs. Output Data Rate (Settled), Sinc³Filter

(Low Power Mode)

Rev. D | Page 25 of 92

AD7124-8

Data Sheet

35

30

25

20

15

10

5

23

22

GAIN = 1, LOW POWER

GAIN = 1, MID POWER

GAIN = 1, FULL POWER

GAIN = 8, LOW POWER

GAIN = 8, MID POWER

GAIN = 8, FULL POWER

GAIN = 16, LOW POWER

GAIN = 16, MID POWER

GAIN = 16, FULL POWER

21

20

19

18

17

16

15

G = 1 BUFF OFF

G = 1

14

G = 2

G = 4

13

12

11

10

G = 8

G = 16

G = 32

G = 64

G = 128

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1

10

100

1k

OUTPUT DATA RATE (SPS)

WAIT TIME IN STANDBY MODE (Seconds)

Figure 58. Peak-to-Peak Resolution vs. Output Data Rate, Sinc⁴+ Sinc¹Filter

(Low Power Mode)

Figure 61. Digital Current vs. Wait Time in Standby Mode, ADC in Single

Conversion Mode (50 SPS)

1000

23

22

LOW POWER, EXTERNAL REF

MID POWER, EXTERNAL REF

FULL POWER, EXTERNAL REF

LOW POWER INTERNAL REF

21

20

800

600

400

200

0

MID POWER, INTERNAL REF

FULL POWER, INTERNAL REF

19

18

17

16

15

G = 1 BUFF OFF

G = 1

14

G = 2

G = 4

13

12

11

10

G = 8

G = 16

G = 32

G = 64

G = 128

–0.08 –0.06 –0.04 –0.02

0

0.02

0.04

0.06

0.08

1

10

100

1k

OUTPUT DATA RATE (SPS)

ANALOG INPUT VOLTAGE (V)

Figure 59. Peak-to-Peak Resolution vs. Output Data Rate, Sinc³+ Sinc¹Filter

(Low Power Mode)

Figure 62. RMS Noise vs. Analog Input Voltage for the Internal Reference and

External Reference (Gain = 32, 50 SPS)

400

4

29 UNITS

GAIN = 1, LOW POWER

GAIN = 1, MID POWER

350

300

250

200

150

100

50

GAIN = 1, FULL POWER

GAIN = 8, LOW POWER

GAIN = 8, MID POWER

GAIN = 8, FULL POWER

GAIN = 16, LOW POWER

GAIN = 16, MID POWER

GAIN = 16, FULL POWER

3

2

1

0

–1

–2

–3

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

–40 –25 –10

5

20

35

50

65

80

95 110 125

WAIT TIME IN STANDBY MODE (Seconds)

TEMPERATURE (°C)

Figure 60. Analog Current vs. Wait Time in Standby Mode, ADC in Single

Conversion Mode (50 SPS)

Figure 63. Internal Oscillator Error vs. Temperature

Rev. D | Page 26 of 92

Data Sheet

AD7124-8

RMS NOISE AND RESOLUTION

Table 7 through Table 36 show the rms noise, peak-to-peak

noise, effective resolution, and noise-free (peak-to-peak)

resolution of the AD7124-8 for various output data rates, gain

settings, and filters. The numbers given are for the bipolar input

range with an external 2.5 V reference. These numbers are

typical and are generated with a differential input voltage of 0 V

when the ADC is continuously converting on a single channel.

It is important to note that the effective resolution is calculated

using the rms noise, whereas the peak-to-peak resolution (shown

in parentheses) is calculated based on peak-to-peak noise

(shown in parentheses). The peak-to-peak resolution represents

the resolution for which there is no code flicker.

Effective Resolution = Log₂(Input Range/RMS Noise)

Peak-to-Peak Resolution = Log₂(Input Range/Peak-to-Peak

Noise

FULL POWER MODE

Sinc⁴

Table 7. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Full Power Mode

Output Output Data

Filter

Word Rate

(Dec.) (SPS)

Data

Rate (Zero

Latency

Mode) (SPS)

f_3dB

(Hz)

Gain = 1 Gain = 2

0.24 (1.5) 0.15 (0.89)

0.23 (1.5) 0.14 (0.89)

0.31 (2.1) 0.22 (1.3)

Gain = 4

0.091 (0.6)

0.094 (0.6)

0.13 (0.89)

0.19 (1.4)

0.2 (1.3)

Gain = 8

0.071 (0.41)

0.076 (0.42)

0.1 (0.6)

0.14 (0.97)

0.16 (1.1)

0.17 (1.2)

0.19 (1.3)

0.29 (2)

Gain = 16

0.045 (0.26)

0.048 (0.27)

0.069 (0.41)

0.09 (0.63)

0.1 (0.75)

0.11 (0.78)

0.13 (0.86)

0.2 (1.2)

Gain = 32

0.031 (0.17)

0.03 (0.19)

0.044 (0.26)

0.063 (0.39)

0.068 (0.43)

0.077 (0.5)

0.09 (0.54)

0.13 (0.84)

0.18 (1.2)

0.26 (2)

Gain = 64

0.025 (0.15)

0.025 (0.16)

0.035 (0.22)

0.053 (0.34)

0.059 (0.42)

0.064 (0.41)

0.072 (0.48)

0.11 (0.7)

Gain = 128

0.023 (0.14)

0.025 (0.15)

0.034 (0.22)

0.043 (0.27)

0.048 (0.28)

0.056 (0.35)

0.063 (0.45)

0.098 (0.6)

0.14 (0.86)

0.19 (1.4)

2047

1920

960

480

384

320

240

120

60

9.4

2.34

2.5

2.16

2.3

10

20

5

4.6

40

10

9.2

0.42 (3)

0.3 (2.1)

50

12.5

15

11.5

13.8

18.4

36.8

73.6

147.2

294.4

552

0.48 (3.2) 0.33 (2.1)

0.51 (3.3) 0.35 (2.4)

60

0.23 (1.3)

0.28 (1.8)

0.37 (2.5)

0.53 (4.1)

0.74 (5.7)

1.1 (8.4)

80

20

0.6 (4.8)

0.41 (3)

160

320

640

1280

2400

4800

9600

19,200

40

0.86 (6.9) 0.55 (4.1)

80

1.2 (8.9)

1.7 (13)

2.4 (19)

3.3 (25)

4.9 (38)

8.8 (76)

72 (500)

0.76 (6.1)

1.1 (8.8)

1.6 (13)

2.3 (16)

3.4 (25)

6.8 (61)

38 (270)

0.4 (2.7)

0.57 (4.1)

0.82 (6)

0.26 (1.8)

0.38 (2.9)

0.55 (4)

0.15 (0.95)

0.22 (1.6)

30

160

320

600

1200

2400

4800

15

0.38 (2.5)

0.53 (4)

0.3 (2.3)

0.26 (1.8)

8

1.5 (12)

1.2 (8)

0.76 (6)

0.43 (3.2)

0.37 (2.7)

4

1104

2208

4416

2.4 (20)

2 (13)

1.3 (9.1)

0.83 (6.4)

1.7 (13)

0.68 (4.8)

0.58 (4.3)

2

4.9 (34)

4.3 (27)

2.6 (21)

1.3 (12)

1.2 (9.4)

1

21 (150)

13 (95)

7.5 (57)

4.4 (33)

3.3 (26)

2.8 (23)

Table 8. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Full Power Mode

Filter

Word

(Dec.) (SPS)

Output

Data Rate

Output Data Rate

(Zero Latency

Mode) (SPS)

Gain = 1

24 (21.7)

Gain = 2

24 (21.4)

Gain = 4

23.7 (21)

Gain = 8

Gain = 16 Gain = 32 Gain = 64 Gain = 128

2047

1920

960

480

384

320

240

120

60

9.4

2.34

2.5

23.1 (20.5) 22.7 (20.2) 22.3 (19.8) 21.6 (19)

23 (20.5) 22.6 (20.1) 22.3 (19.7) 21.6 (19)

20.7 (18.1)

10

20

5

23.9 (21.2) 23.5 (20.8) 23.2 (20.4) 22.5 (20)

23.5 (20.7) 23 (20.3) 22.6 (19.8) 22.1 (19.3) 21.7 (18.9) 21.2 (18.6) 20.5 (17.8) 19.8 (17.1)

23.3 (20.5) 22.9 (20.2) 22.5 (19.6) 21.9 (19.1) 21.5 (18.7) 21.1 (18.5) 20.4 (17.7) 19.6 (17)

23.2 (20.3) 22.8 (20) 22.4 (19.5) 21.8 (19) 21.4 (18.6) 21 (18.3) 20.2 (17.6) 19.4 (16.6)

23 (20) 22.6 (19.7) 22.1 (19.3) 21.6 (18.9) 21.2 (18.5) 20.7 (18.1) 20 (17.3)

22.5 (19.5) 22.1 (19.2) 21.7 (18.9) 21 (18.3)

22 (19.1)

21.5 (18.5) 21.1 (18.1) 20.7 (17.7) 20.1 (17.2) 19.7 (16.8) 19.2 (16.3) 18.5 (15.6) 17.6 (14.8)

22.1 (19.5) 21.8 (19.2) 21.1 (18.4) 20.1 (17.4)

40

10

50

12.5

15

60

80

20

19.2 (16.4)

160

320

640

1280

2400

4800

9600

19,200

40

20.6 (18)

20.1 (17.5) 19.5 (16.9) 18.6 (16)

80

21.6 (18.6) 21.2 (18.2) 20.6 (17.8) 20.2 (17.4) 19.7 (17)

19 (16.3)

18.1 (15.5)

30

160

320

600

1200

2400

4800

15

21 (18)

20.5 (17.6) 20.2 (17.2) 19.5 (16.7) 19.1 (16.3) 18.7 (15.9) 18 (15.1)

17.2 (14.4)

8

20.5 (17.5) 20.1 (17.2) 19.7 (16.7) 19 (16.2)

18.6 (15.7) 18.2 (15.3) 17.5 (14.6) 16.7 (13.8)

4

20 (17)

19.5 (16.5) 19 (16)

18.5 (15.3) 18 (15.1)

18.3 (15.6) 17.9 (15.1) 17.5 (14.6) 16.8 (14)

16 (13.2)

17.2 (14.5) 16.9 (13.9) 16.5 (13.5) 15.9 (12.7) 15 (12)

15.5 (12.7) 15.4 (12.4) 15.1 (12.2) 14.6 (11.5) 13.8 (10.8)

2

19.1 (16)

1

16.1 (13.3) 16 (13.2)

15.9 (13)

Rev. D | Page 27 of 92

AD7124-8

Data Sheet

Sinc³

Table 9. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Full Power Mode

Output

Data Rate

Output (Zero

Filter

Word Rate

(Dec.) (SPS)

Data

Latency

Mode)

(SPS)

f_3dB

(Hz)

Gain = 1

0.23 (1.5)

0.24 (1.5)

0.31 (1.8)

0.4 (2.6)

Gain = 2

0.15 (0.89)

0.18 (1.2)

0.26 (1.6)

0.3 (2.2)

Gain = 4

0.096 (0.58)

0.096 (0.6)

0.12 (0.82)

0.17 (1.2)

0.2 (1.6)

Gain = 8

0.07 (0.38)

0.07 (0.4)

0.09 (0.55)

0.11 (0.82)

0.17 (1.1)

0.19 (1.3)

0.26 (1.8)

0.37 (2.6)

0.52 (3.7)

0.75 (5.1)

1.1 (8.5)

Gain = 16

0.046 (0.25)

0.05 (0.26)

0.059 (0.35)

0.088 (0.52)

0.1 (0.75)

0.12 (0.8)

0.17 (1.1)

0.25 (1.6)

0.34 (2.2)

0.53 (3.5)

0.73 (5.5)

1 (7.7)

Gain = 32

0.033 (0.16)

0.034 (0.17)

0.041 (0.24)

0.055 (0.36)

0.075 (0.51)

0.084 (0.54)

0.12 (0.85)

0.17 (1.2)

0.25 (1.7)

0.35 (2.4)

0.49 (3.9)

0.68 (5.6)

1.5 (11)

Gain = 64

Gain = 128

0.017 (0.09)

0.018 (0.09)

0.027 (0.14)

0.039 (0.22)

0.056 (0.33)

0.06 (0.37)

0.097 (0.55)

0.12 (0.78)

0.17 (1.2)

0.25 (1.8)

0.35 (2.7)

0.48 (3.6)

0.9 (6.7)

2047

1920

1280

640

384

320

160

80

9.4

3.13

3.33

5

2.56

0.023 (0.11)

0.023 (0.12)

0.033 (0.18)

0.048 (0.27)

0.062 (0.39)

0.068 (0.44)

0.1 (0.66)

0.14 (1)

10

2.72

20

5.44

30

10

8.16

50

16.67

20

13.6

0.53 (3.3)

0.55 (3.6)

0.78 (5.1)

1.1 (7)

60

16.32

32.64

65.28

130.56

261.12

522.24

870.4

1740.8

2611.2

5222.4

0.37 (2.4)

0.53 (3.4)

0.73 (4.9)

1.1 (6.8)

1.5 (9.8)

2.2 (16)

0.24 (1.8)

0.35 (2.3)

0.49 (3.2)

0.67 (4.5)

0.99 (6.6)

1.5 (11)

120

240

480

960

1920

3200

6400

9600

19,200

40

80

40

160

1.5 (11)

0.19 (1.4)

0.28 (2.1)

0.4 (3.2)

20

320

2.3 (16)

10

640

3.2 (26)

6

1066.67

2133.33

3200

6400

4.9 (38)

3.2 (24)

2.1 (15)

1.6 (12)

0.56 (4.2)

1.1 (8.4)

3

25 (170)

110 (820)

890 (6500)

13 (89)

7.1 (54)

4.3 (35)

2.4 (18)

2

54 (390)

430 (3000)

28 (210)

220 (1500)

14 (110)

110 (790)

7.4 (57)

3.9 (27)

2.3 (17)

1.7 (13)

1

55 (390)

28 (190)

14 (100)

7.6 (56)

Table 10. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Full Power Mode

Output

Data

Word Rate

(Dec.) (SPS)

Output Data

Rate (Zero

Latency Mode)

(SPS)

Filter

Gain = 1

Gain = 2

24 (21.4)

Gain = 4

Gain = 8

Gain = 16

22.7 (20.3)

22.6 (20.2)

22.3 (19.8)

21.8 (19.2)

21.4 (18.7)

21.3 (18.6)

20.8 (18.1)

20.3 (17.6)

19.8 (17.1)

19.2 (16.4)

18.7 (15.8)

18.2 (15.3)

17 (14.1)

Gain = 32

22.2 (19.9)

22.2 (19.8)

21.9 (19.3)

21.4 (18.7)

21 (18.2)

Gain = 64

21.7 (19.3)

21.2 (18.7)

20.6 (18.1)

20.3 (17.6)

20.1 (17.4)

19.6 (16.9)

19.1 (16.3)

18.6 (15.8)

18.1 (15.2)

17.6 (14.6)

17.1 (14.2)

16.3 (13.2)

15 (12.2)

Gain = 128

21 (18.7)

2047

1920

1280

640

384

320

160

80

9.4

3.13

3.33

5

24 (21.7)

23.6 (21)

23.1 (20.6)

22.7 (20.1)

22.2 (19.5)

21.8 (19.1)

21.7 (18.9)

21.2 (18.4)

20.7 (17.9)

20.2 (17.4)

19.7 (16.9)

19.1 (16.2)

18.6 (15.6)

17.2 (14.1)

15.4 (12.5)

12.5 (9.6)

10

24 (21.7)

24 (21.4)

23.6 (21)

21 (18.7)

20

24 (21.4)

23.7 (21)

23.2 (20.5)

22.8 (20)

20.5 (18.1)

19.9 (17.4)

19.4 (16.9)

19.3 (16.7)

18.7 (16.1)

18.3 (15.6)

17.8 (15)

30

10

23.6 (20.9)

23.2 (20.5)

23.1 (20.4)

22.6 (19.9)

22.1 (19.4)

21.6 (18.8)

21.1 (18.3)

20.6 (17.6)

19.9 (17)

23.2 (20.5)

22.8 (20.1)

22.7 (20)

50

16.67

20

22.4 (19.6)

22.3 (19.4)

21.8 (19)

60

20.8 (18.1)

20.3 (17.5)

19.8 (17)

120

240

480

960

1920

3200

6400

9600

19,200

40

22.2 (19.5)

21.7 (19)

80

21.3 (18.6)

20.8 (18.1)

20.3 (17.5)

19.7 (16.8)

19.2 (16.3)

17.4 (14.5)

15.4 (12.6)

12.5 (9.7)

40

160

21.2 (18.5)

20.7 (18)

19.3 (16.5)

18.8 (16)

20

320

17.3 (14.4)

16.8 (13.8)

16.3 (13.4)

15.4 (12.5)

14.5 (11.6)

12.3 (9.5)

10

640

20.1 (17.2)

19.6 (16.6)

17.6 (14.8)

15.5 (12.6)

12.5 (9.7)

18.3 (15.3)

17.8 (14.8)

16.7 (13.8)

15.3 (12.5)

12.4 (9.6

6

1066.67

2133.33

3200

6400

3

17.6 (14.8)

15.5 (12.6)

12.5 (9.7)

2

15.4 (12.4)

12.5 (9.6)

1

12.4 (9.6)

Post Filters

Table 11. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Full Power Mode

Output Data Rate (SPS)

Gain = 1

0.51 (3.3)

0.53 (3.3)

0.57 (3.6)

0.6 (3.9)

Gain = 2

0.34 (2.1)

0.36 (2.1)

0.37 (2.2)

0.38 (2.2)

Gain = 4

0.21 (1.3)

0.23 (1.3)

0.25 (1.6)

0.26 (1.6)

Gain = 8

0.16 (0.97)

0.18 (1)

Gain = 16

0.11 (0.65)

0.12 (0.75)

0.13 (0.82)

Gain = 32

Gain = 64

Gain = 128

0.051(0.3)

16.67

20

0.075 (0.41)

0.078 (0.45)

0.082 (0.47)

0.084 (0.55)

0.062 (0.34)

0.062 (0.38)

0.072 (0.44)

0.051 (0.3)

0.055 (0.31)

0.063 (0.43)

25

0.18 (1.2)

0.19 (1.2)

27.27

Rev. D | Page 28 of 92

Data Sheet

AD7124-8

Table 12. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Full Power Mode

Output Data Rate (SPS)

Gain = 1

Gain = 2

Gain = 4

Gain = 8

21.9 (19.3)

21.7 (19.2)

21.7 (19)

Gain = 16

21.5 (18.9)

21.3 (18.7)

21.2 (18.5)

Gain = 32

21 (18.5)

Gain = 64

20.3 (17.8)

20.3 (17.7)

20.1 (17.4)

Gain = 128

19.5 (17)

16.67

20

23.2 (20.5)

23.1 (20.4)

23 (20.3)

22.8 (20.2)

22.7 (20.2)

22.7 (20.1)

22.6 (20.1)

22.5 (19.9)

22.3 (19.9)

22.2 (19.6)

22.2 (19.5)

20.9 (18.4)

20.9 (18.3)

20.8 (18.1)

19.5 (17)

25

19.5 (17)

27.27

19.2 (16.5)

Fast Settling Filter (Sinc⁴+ Sinc¹)

Table 13. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Full Power Mode (Average by 16)

Filter

Word

(Dec.)

Output

Data Rate

(SPS)

Gain = 1

0.19 (1.2)

0.32 (2.1)

0.69 (4.6)

0.71 (5.1)

2.4 (18)

Gain = 2

0.11 (0.75)

0.2 (1.3)

0.44 (3)

0.49 (3.1)

1.6 (10)

3 (20)

Gain = 4

0.077 (0.52)

0.13 (0.97)

0.29 (2.1)

0.3 (2.2)

Gain = 8

0.063 (0.34)

0.1 (0.63)

0.23 (1.6)

0.25 (1.7)

0.87 (5.5)

1.4 (8.8)

Gain = 16

0.036 (0.21)

0.067 (0.46)

0.14 (0.99)

0.16 (1.1)

Gain = 32

0.027 (0.17)

0.045 (0.28)

0.1 (0.72)

Gain = 64

0.021 (0.11)

0.039 (0.23)

0.081 (0.54)

0.09 (0.6)

Gain = 128

0.019 (0.098)

0.031 (0.2)

0.07 (0.49)

0.082 (0.57)

0.3 (2)

384

120

24

20

2

2.63

8.42

42.11

50.53

505.26

1010.53

0.11 (0.78)

0.47 (2.9)

1.1 (8.3)

0.56 (3.5)

0.33 (2.1)

1

4.8 (35)

1.9 (12)

0.89 (5.2)

0.57 (3.7)

0.49 (3)

0.44 (3)

Table 14. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Full Power Mode (Average by 16)

Filter Word

(Dec.)

Output Data Rate

(SPS)

Gain = 1

24 (22)

Gain = 2

Gain = 4

Gain = 8

Gain = 16

23 (20.5)

Gain = 32

22.5 (19.8)

21.9 (19.1)

20.5 (17.7)

20.4 (17.6)

18.4 (15.7)

18.1 (15.4)

Gain = 64

21.8 (19.5)

20.9 (18.4)

19.9 (17.1)

19.7 (17)

Gain = 128

21 (18.6)

384

120

24

20

2

2.63

24 (21.7)

23.9 (21.2)

23.3 (20.3)

22.1 (19.2)

22 (19.1)

23.3 (20.8)

22.5 (19.9)

21.4 (18.6)

21.2 (18.5)

19.5 (16.8)

18.8 (16.1)

8.42

23.9 (21.2)

22.8 (20)

22.7 (19.9)

21 (18.1)

20 (17.1)

23.6 (20.8)

22.4 (19.7)

22.3 (19.6)

20.6 (17.9)

19.7 (16.9)

22.2 (19.4)

21.1 (18.3)

20.9 (18.1)

19.1 (16.4)

18.4 (15.9)

20.2 (17.6)

19.1 (16.3)

18.9 (16.1)

17 (14.3)

42.11

50.53

505.26

1010.53

20.2 (17.2)

19.3 (16.6)

17.8 (15.2)

17.3 (14.7)

1

16.5 (13.7)

Fast Settling Filter (Sinc³+ Sinc¹)

Table 15. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Full Power Mode (Average by 16)

Filter Word

(Dec.)

Output Data Rate

(SPS)

Gain = 1

0.22 (1.4)

0.31 (2.1)

0.7 (4.8)

0.77 (5.2)

6.1 (46)

Gain = 2

0.13 (0.75)

0.21 (1.3)

0.46 (3.1)

0.5 (3.4)

Gain = 4

0.081 (0.44)

0.13 (0.89)

0.29 (2.1)

0.31 (2.3)

1.8 (12)

Gain = 8

0.048 (0.3)

0.1 (0.63)

0.22 (1.5)

0.24 (1.6)

1.1 (7.5)

Gain = 16

0.039 (0.24)

0.068 (0.47)

0.14 (0.95)

0.17 (1)

Gain = 32

0.026 (0.18)

0.047 (0.28)

0.098 (0.67)

0.11 (0.73)

0.4 (2.7)

Gain = 64

0.025 (0.13)

0.036 (0.25)

0.079 (0.56)

0.09 (0.66)

0.31 (2.2)

Gain = 128

0.019 (0.11)

0.033 (0.17)

0.071 (0.44)

0.077 (0.48)

0.27 (2)

384

120

24

20

2

2.78

8.89

44.44

53.33

533.33

1066.67

3.2 (23)

0.65 (4.3)

2.9 (22)

1

44 (320)

22 (160)

11 (80)

5.7 (40)

1.5 (11)

0.83 (6.2)

0.54 (4)

Table 16. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Full Power Mode (Average by 16)

Filter Word

(Dec.)

Output Data Rate

(SPS)

Gain = 1

24 (21.8)

24 (21.2)

22.8 (20)

22.6 (19.9)

19.7 (16.8)

16.8 (13.9)

Gain = 2

Gain = 4

Gain = 8

Gain = 16

22.9 (20.3)

22.1 (19.4)

21.1 (18.3)

20.8 (18.2)

18.9 (16.1)

16.7 (13.8)

Gain = 32

22.5 (19.8)

21.7 (19.1)

20.6 (17.8)

20.4 (17.7)

18.6 (15.8)

16.6 (13.8)

Gain = 64

21.6 (19.2)

21 (18.3)

Gain = 128

21 (18.4)

384

120

24

20

2

2.78

24 (21.7)

23.9 (21.4)

23.2 (20.4)

22.1 (19.2)

22 (19.1)

23.6 (21)

8.89

23.5 (20.9)

22.4 (19.6)

22.3 (19.5)

19.6 (16.8)

16.8 (13.9)

22.6 (19.9)

21.4 (18.7)

21.3 (18.6)

19.1 (16.3)

16.7 (13.9)

20.2 (17.8)

19.1 (16.5)

19 (16.3)

44.44

53.33

533.33

1066.67

19.9 (17.1)

19.7 (16.9)

17.9 (15.1)

16.5 (13.6)

19.4 (16.6)

16.8 (13.9)

17.2 (14.3)

16.1 (13.3)

1

Rev. D | Page 29 of 92

AD7124-8

Data Sheet

MID POWER MODE

Sinc⁴

Table 17. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Mid Power Mode

Output

Data

Word Rate

(Dec.) (SPS)

Output Data

Rate (Zero

Latency

Filter

f_3dB

Mode) (SPS)

(Hz)

Gain = 1 Gain = 2

Gain = 4

Gain = 8

0.062 (0.38)

0.073 (0.38)

0.085 (0.52)

0.1 (0.82)

0.2 (1.1)

Gain = 16

0.048 (0.24)

0.064 (0.36)

0.1 (0.55)

0.14 (0.85)

0.2 (1.1)

Gain = 32

0.036 (0.17)

0.037 (0.19)

0.052(0.25)

0.072 (0.41)

0.098 (0.64)

0.14 (0.87)

0.15 (0.95)

0.17 (1.1)

0.2 (1.3)

Gain = 64

Gain = 128

0.02 (0.1)

0.021 (0.1)

0.035 (0.2)

0.048 (0.28)

0.07 (0.43)

0.09 (0.57)

0.11 (0.7)

0.12 (0.75)

0.13 (0.82)

0.19 (1.2)

0.26 (1.5)

0.4 (2.6)

2047

1920

960

480

240

120

96

2.34

2.5

0.586

0.625

1.25

2.5

0.52

0.575

1.15

2.3

0.22 (1.4) 0.14 (0.88) 0.095 (0.6)

0.25 (1.4) 0.17 (0.88) 0.11 (0.6)

0.024 (0.14)

0.04 (0.21)

0.057 (0.34)

0.081 (0.47)

0.11 (0.74)

0.13 (0.78)

0.14 (0.89)

0.18 (1.1)

0.23 (1.4)

0.33 (2)

5

0.34 (2)

0.21 (1.2)

0.13 (0.77)

0.19 (1.1)

0.27 (1.6)

0.37 (2.3)

0.41 (2.5)

0.44 (3)

10

0.44 (2.8) 0.28 (1.8)

0.67 (3.8) 0.4 (2.4)

20

5

4.6

40

10

9.2

0.98 (6)

1 (7.4)

0.58 (3.6)

0.67 (4.2)

0.7 (4.3)

0.8 (5.1)

1.2 (7.6)

1.7 (11)

2.3 (15)

3.6 (24)

6.8 (53)

37 (270)

0.27 (1.7)

0.28 (1.9)

0.33 (2.1)

0.37 (2.4)

0.54 (3.4)

0.79 (4.7)

1.2 (7.2)

50

12.5

15

11.5

13.8

18.4

36.8

73.6

138

276

552

1104

0.23 (1.3)

0.24 (1.4)

0.27 (1.6)

0.39 (2.4)

0.58 (3.4)

0.84 (5)

80

60

1.1 (7.2)

1.3 (8.4)

1.8 (11)

2.6 (17)

3.7 (23)

5.3 (36)

9.3 (72)

71 (500)

60

80

20

0.53 (3.4)

0.73 (4.6)

1 (6.6)

30

160

320

600

1200

2400

4800

40

0.28 (1.9)

0.4 (2.5)

15

80

8

150

300

600

1200

1.5 (9.6)

2.4 (16)

0.56 (4)

0.46 (2.8)

0.68 (4.3)

1.3 (10)

4

1.9 (13)

1.3 (8.2)

0.85 (6)

0.6 (4.5)

2

4.8 (35)

4.1 (34)

2.5 (19)

1.7 (13)

1.2 (9.7)

1

21 (160)

13 (98)

7.2 (55)

4.3 (33)

3.1 (24)

2.6 (21)

Table 18. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Mid Power Mode

Output

Data

Word Rate

(Dec.) (SPS)

Output Data

Rate (Zero

Latency Mode)

(SPS)

Filter

Gain = 1

Gain = 2

Gain = 4

Gain = 8

Gain = 16

22.6 (20.3)

22.2 (19.7)

21.5 (19.1)

21.1 (18.5)

20.6 (18.1)

20.4 (17.9)

20.3 (17.8)

20.1 (17.6)

19.6 (17)

Gain = 32

22.1 (19.7)

22 (19.7)

Gain = 64

21.6 (19.1)

20.9 (18.5)

20.4 (17.8)

19.9 (17.3)

19.4 (16.8)

19.2 (16.6)

19.1 (16.4)

18.9 (16.2)

18.4 (15.8)

17.9 (15.3)

17.4 (14.8)

16.8 (14)

Gain = 128

20.9 (18.5)

20.8 (18.5)

20.1 (17.6)

19.6 (17.1)

19.1 (16.5)

18.7 (16)

2047

1920

960

480

240

120

96

2.34

2.5

0.586

0.625

1.25

2.5

24 (21.8)

24 (21.4)

23.6 (21)

23.3 (20.6)

23 (20.6)

24 (21.8)

23.8 (21.4) 23.5 (21)

23.5 (21) 23.2 (20.6)

23.1 (20.4) 22.7 (20.1)

5

23.8 (21.2)

23.4 (20.8)

22.8 (20.3)

22.3 (19.7)

22.2 (19.5)

22.1 (19.4)

21.9 (19.2)

21.4 (18.8)

20.9 (18.2)

20.4 (17.7)

19.8 (17.1)

19 (16.1)

22.8 (20.2)

22.2 (19.6)

21.6 (19.1)

21.1 (18.5)

21 (18.3)

21.5 (19.2)

21 (18.5)

10

20

5

22.5 (20)

22 (19.4)

22.1 (19.6)

21.7 (19)

20.6 (17.9)

20.1 (17.5)

19.9 (17.3)

19.8 (17.2)

19.6 (16.9)

19.1 (16.3)

18.6 (15.9)

18.1 (15.3)

17.5 (14.7)

16.5 (13.6)

15.1 (12.2)

40

10

50

12.5

15

21.8 (19.2) 21.5 (18.9)

21.7 (19.1) 21.4 (18.7)

21.5 (18.9) 21.1 (18.5)

18.5 (15.8)

18.4 (15.7)

18.2 (15.5)

17.7 (15)

80

60

20.9 (18.2)

20.7 (18)

60

80

20

30

160

320

600

1200

2400

4800

40

21 (18.9)

20.5 (17.8) 20.2 (17.5)

20 (17.3) 19.7 (17)

20.7 (18.5)

20.2 (17.5)

19.6 (17)

15

80

19 (16.5)

17.2 (14.6)

16.6 (13.9)

16 (13.1)

8

150

300

600

1200

19 (16.4)

18.5 (15.9)

17.9 (15.2)

16.9 (14)

4

19.4 (16.7) 19 (16.3)

18.5 (15.5) 18 (15.1)

18.3 (15.6)

17.2 (14.2)

15.5 (12.6)

2

15.8 (12.9)

14.6 (11.7)

15 (12)

1

16.1 (13.3)

16 (13.2)

15.9 (12.9)

15.4 (12.5)

13.9 (10.9)

Rev. D | Page 30 of 92

Data Sheet

AD7124-8

Sinc³

Table 19. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Mid Power Mode

Output

Output Data Rate

Filter

Word

Data

Rate

(Zero

Latency

f_3dB

(Dec.) (SPS)

Mode) (SPS) (Hz)

Gain = 1

0.25 (1.5)

0.35 (2.2)

0.5 (3.1)

0.6 (3.8)

0.83 (5.6)

1.1 (7.5)

1.2 (7.7)

1.7 (11)

Gain = 2

0.17 (1)

0.23 (1.3)

0.31 (1.9)

0.38 (2.4)

0.54 (3.3)

0.72 (4.4)

0.8 (4.8)

1.1 (7)

Gain = 4

Gain = 8

Gain = 16

Gain = 32

Gain = 64

0.03 (0.16)

Gain = 128

2047

960

480

320

160

96

80

40

20

10

5

2.34

5

0.78

1.67

3.33

5

0.64

0.087 (0.58) 0.065 (0.4)

0.14 (0.82) 0.1 (0.58)

0.049 (0.27) 0.034 (0.19)

0.074 (0.43) 0.053 (0.31)

0.022 (0.11)

1.36

0.041 (0.22) 0.034 (0.17)

0.6 (0.35) 0.049 (0.28)

0.076 (0.46) 0.062 (0.35)

10

2.72

0.19 (1.3)

0.24 (1.6)

0.34 (2.2)

0.44 (2.9)

0.48 (3.1)

0.7 (4.6)

0.94 (6.2)

1.4 (9.3)

2.5 (19)

0.14 (0.89)

0.17 (1.1)

0.24 (1.6)

0.31 (2)

0.35 (2.2)

0.47 (3.2)

0.7 (5)

0.1 (0.63)

0.13 (0.8)

0.18 (1.1)

0.24 (1.5)

0.25 (1.6)

0.36 (2.2)

0.53 (3.2)

0.78 (5.3)

1.2 (8.7)

2.4 (18)

0.075 (0.44)

0.089 (0.54)

0.13 (0.77)

0.17 (1)

15

4.08

30

10

8.16

0.1 (0.65)

0.14 (0.82)

0.15 (0.94)

0.21 (1.5)

0.31 (2.1)

0.46 (3.1)

0.67 (5)

0.088 (0.53)

0.11 (0.7)

0.12 (0.77)

0.18 (1.1)

0.26 (1.8)

0.38 (2.5)

0.57 (3.9)

0.89 (6.8)

1.6 (12)

50

16.67

20

13.6

60

16.32

32.64

65.28

130.6

261.1

435.2

652.8

1306

0.18 (1.1)

0.26 (1.7)

0.37 (2.3)

0.56 (3.9)

0.84 (6.4)

1.5 (11)

120

240

480

960

1600

2400

4800

40

80

2.5 (16)

1.6 (9.7)

2.2 (15)

4.1 (34)

13 (90)

160

320

533.33

800

1600

3.5 (24)

1 (7)

6.7 (53)

1.8 (14)

4.2 (30)

14 (110)

110 (760)

3

25 (170)

110 (740)

7.1 (53)

1.1 (7.8)

2

54 (360)

27 (200)

7.4 (51)

3.9 (29)

2.3 (16)

1

880 (5800) 430 (3100) 220 (1500)

55 (400)

27 (180)

14 (110)

7.5 (56)

Table 20. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Mid Power Mode

Output

Data

Rate

Output Data

Rate (Zero

Latency

Filter

Word

(Dec.)

(SPS)

Mode) (SPS)

Gain = 1

Gain = 2

Gain = 4

Gain = 8

Gain = 16

22.6 (20.1)

22 (19.5)

Gain = 32

22.1 (19.6)

21.5 19)

Gain = 64

21.3 (18.9)

20.8 (18.4)

20.3 (17.8)

20 (17.4)

Gain = 128

20.7 (18.4)

20.1 (17.8)

19.6 (17.1)

19.3 (16.8)

18.8 (16.2)

18.4 (15.8)

18.3 (15.6)

17.7 (15.1)

17.2 (14.4)

16.7 (13.9)

16.1 (13.3)

15.4 (12.6)

14.6 (11.7)

12.4 (9.4)

2047

960

480

320

160

96

80

40

20

10

5

2.34

5

0.78

1.67

3.33

5

24 (21.7)

23.8 (21.2)

23.6 (21)

23.2 (20.6)

22.6 (20)

23.8 (21.1) 23.4 (20.8)

23.3 (20.6) 22.9 (20.3)

23.1 (20.5)

22.6 (19.9)

22.3 (19.6)

21.8 (19.1)

21.4 (18.7)

21.3 (18.6)

20.8 (18.1)

20.3 (17.6)

19.8 (17)

10

22.1 (19.4)

21.8 (19.1)

21.3 (18.6)

20.9 (18.2)

20.8 (18.1)

20.3 (17.6)

19.8 (17)

21.5 (18.9)

21.2 (18.6)

20.7 (18.1)

20.3 (17.7)

20.2 (17.6)

19.7 (17.1)

19.2 (16.6)

18.6 (15.9)

18 (15.1)

21 (18.4)

15

23 (20.3)

22.6 (20)

20.7 (18.1)

20.2 (17.6)

19.8 (17.2)

19.7 (17.1)

19.2 (16.5)

18.7 (16)

30

10

22.5 (19.8) 22.1 (19.5)

22.1 (19.4) 21.7 (19.1)

19.5 (16.9)

19.1 (16.5)

19.1 (16.3)

18.5 (15.7)

18 (15.2)

50

16.67

20

60

22 (19.3)

21.5 (18.8) 21.1 (18.5)

21 (18.3) 20.6 (18)

21.6 (19)

120

240

480

960

1600

2400

4800

40

80

160

320

533.33

800

1600

20.4 (17.7) 20.1 (17.3)

19.5 (16.5) 19.2 (16.2)

17.6 (14.8) 17.5 (14.8)

15.5 (12.7) 15.5 (12.7)

19.2 (16.4)

18.4 (15.4)

17.2 (14.3)

15.4 (12.6)

12.5 (9.7)

18.1 (15.3)

17.5 (14.6)

16.7 (13.8)

15.3 (12.4)

12.5 (9.6)

17.4 (14.6)

16.8 (13.9)

16.1 (13.3)

15 (12.3)

19 (16)

3

17.4 (14.5)

15.5 (12.6)

12.5 (9.7)

17 (14.1)

2

15.4 (12.6)

12.5 (9.6)

1

12.5 (9.7)

12.4 (9.5)

Post Filters

Table 21. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Mid Power Mode

Output Data Rate (SPS)

Gain = 1

1.1 (6.3)

1.1 (6.9)

1.2 (8)

Gain = 2

0.69 (4)

0.7 (4)

Gain = 4

0.41 (2.5)

0.46 (2.8)

0.48 (2.8)

Gain = 8

Gain = 16

0.23 (1.4)

0.23 (1.5)

0.25 (1.5)

0.28 (1.6)

Gain = 32

0.17 (0.96)

0.18 (0.96)

0.17 (1)

Gain = 64

Gain = 128

0.11 (0.61)

0.12 (0.67)

0.12 (0.74)

0.13 (0.79)

16.67

20

0.31 (2)

0.13 (0.79)

0.14 (0.81)

0.15 (0.9)

0.16 (1)

0.33 (2.1)

0.36 (2.3)

25

0.8 (4.6)

0.82 (4.8)

27.27

1.3 (9.2)

0.19 (1.1)

Table 22. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Mid Power Mode

Output Data Rate (SPS)

Gain = 1

22.1 (19.6)

22.1 (19.5)

22 (19.2)

21.9 (19)

Gain = 2

Gain = 4

Gain = 8

Gain = 16

20.4 (17.8)

20.4 (17.7)

20.3 (17.6)

21.1 (17.6)

Gain = 32

19.8 (17.3)

19.7 (17.2)

19.7 (17.1)

Gain = 64

19.2 (16.6)

19 (16.6)

Gain = 128

18.4 (16)

16.67

20

21.8 (19.2)

21.6 (19.1)

21.5 (19)

21.5 (18.9)

21.4 (18.8)

21.3 (18.8)

20.9 (18.3)

20.9 (18.2)

20.7 (18.1)

18.3 (15.8)

18.2 (15.7)

18.2 (15.6)

25

18.9 (16.4)

18.9 (16.3)

27.27

Rev. D | Page 31 of 92

AD7124-8

Data Sheet

Fast Settling Filter (Sinc⁴+ Sinc¹)

Table 23. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Mid Power Mode (Average by 16)

Filter Word

(Dec.)

Output Data Rate

(SPS)

Gain = 1

0.36 (2.4)

0.67 (4.2)

1.5 (9)

Gain = 2

0.23 (1.5)

0.44 (2.7)

0.96 (6.1)

1 (7.7)

Gain = 4

0.15 (0.82)

0.26 (1.6)

0.57 (3.7)

0.62 (4)

Gain = 8

0.1 (0.71)

0.18 (1.1)

0.42 (2.6)

0.46 (3)

Gain = 16

0.078 (0.44)

0.14 (0.8)

0.32 (1.9)

0.33 (2)

Gain = 32

0.056 (0.35)

0.1 (0.54)

0.22 (1.5)

0.24 (1.6)

0.41 (2.7)

0.62 (4.2)

Gain = 64

Gain = 128

0.038 (0.21)

0.067 (0.41)

0.15 (0.95)

0.17 (1.2)

96

30

6

2.63

0.045 (0.26)

0.08 (0.48)

0.18 (1.1)

0.2 (1.3)

8.42

42.11

50.53

126.32

252.63

5

1.6 (9.3)

2.5 (15)

5.2 (21)

2

1.6 (11)

1 (7.2)

0.76 (4.9)

1.4 (9.8)

0.57 (3.7)

0.92 (6.2)

0.32 (2.4)

0.49 (3)

0.29 (1.9)

1

3.1 (19)

1.8 (11)

0.41 (3)

Table 24. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Mid Power Mode (Average by 16)

Filter Word

(Dec.)

Output Data Rate

(SPS)

Gain = 1

23.7 (21)

Gain = 2

Gain = 4

Gain = 8

22.5 (19.8)

21.7 (19.1)

20.5 (17.9)

20.4 (17.8)

19.6 (17)

Gain = 16

21.9 (19.4)

21 (18.6)

Gain = 32

21.4 (18.8)

20.6 (18.1)

19.4 (16.7)

19.3 (16.6)

18.6 (15.8)

17.9 (15.2)

Gain = 64

20.7 (18.2)

19.9 (17.3)

18.7 (16)

Gain = 128

20 (17.5)

96

30

6

2.63

23.4 (20.7)

22.4 (19.8)

21.3 (18.6)

21.2 (18.4)

20.5 (17.8)

19.6 (17)

23 (20.5)

8.42

22.8 (20.2)

21.7 (19.1)

21.5 (19)

22.2 (19.5)

21.1 (18.4)

20.9 (18.2)

20.2 (17.4)

19.4 (16.8)

19.1 (16.5)

18 (15.2)

42.11

50.53

126.32

252.63

19.9 (17.3)

19.8 (17.2)

19.1 (16.4)

18.4 (15.6)

5

18.5 (15.9)

17.9 (15.2)

17.3 (14.7)

17.8 (15)

2

20.9 (18.3)

19.9 (17.3)

17.1 (14.3)

16.5 (13.7)

1

18.8 (16)

Fast Settling Filter (Sinc³+ Sinc¹)

Table 25. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Mid Power Mode (Average by 16)

Filter Word

(Dec.)

Output Data Rate

(SPS)

Gain = 1

0.39 (2.4)

0.71 (4.2)

1.5 (9.5)

1.6 (11)

6 (37)

Gain = 2

0.25 (1.5)

0.43 (2.5)

0.93 (6)

1 (6.9)

Gain = 4

0.16 (1)

Gain = 8

0.11 (0.67)

0.19 (1.1)

0.43 (2.6)

0.46 (2.8)

1 (7.2)

Gain = 16

0.08 (0.48)

0.15 (1)

Gain = 32

0.058 (0.31)

0.098 (0.64)

0.22 (1.5)

0.24 (1.6)

0.43 (3)

Gain = 64

0.047 (0.27)

0.083 (0.47)

0.18 (1.1)

0.2 (1.2)

Gain = 128

0.039 (0.23)

0.068 (0.4)

0.15 (0.98)

0.17 (1.1)

96

30

6

2.78

8.89

0.27 (1.6)

0.59 (3.8)

0.66 (4.2)

1.8 (11)

44.44

53.33

133.33

266.67

0.32 (2.1)

0.35 (2.3)

0.63 (4.5)

3 (20)

5

2

3.2 (20)

23 (160)

0.33 (2.2)

0.84 (6.4)

0.27 (1.8)

1

44 (320)

12 (83)

5.7 (41)

1.6 (9.9)

0.56 (3.5)

Table 26. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Mid Power Mode (Average by 16)

Filter

Word Output Data

(Dec.) Rate (SPS)

Gain = 1

23.6 (21)

22.7 (20.2)

21.7 (19)

21.5 (18.8)

19.7 (17)

16.8 (13.9)

Gain = 2

Gain = 4

Gain = 8

Gain = 16

21.9 (19.3)

21 (18.3)

Gain = 32

21.4 (18.9)

20.6 (17.9)

19.4 (16.7)

19.3 (16.6)

18.5 (15.7)

16.6 (13.9)

Gain = 64

20.7 (18.1)

19.8 (17.3)

18.7 (16.1)

18.6 (16)

Gain = 128

19.9 (17.4)

19.1 (16.6)

18 (15.3)

96

30

6

2.78

23.3 (20.7)

22.5 (19.9)

21.4 (18.7)

21.2 (18.5)

19.6 (16.9)

16.7 (13.9)

22.9 (20.3)

22.2 (19.6)

21 (18.3)

22.5 (19.8)

21.7 (19.1)

20.5 (17.9)

20.4 (17.8)

19.2 (16.4)

16.7 (13.9)

8.89

44.44

53.33

133.33

266.67

19.9 (17.2)

19.8 (17.1)

18.9 (16.1)

16.7 (13.9)

5

20.9 (18.2)

19.4 (16.8)

16.7 (13.9)

17.8 (15.1)

17.1 (14.4)

16.1 (13.4)

2

17.8 (15.1)

16.5 (13.6)

1

Rev. D | Page 32 of 92

Data Sheet

AD7124-8

LOW POWER MODE

Sinc⁴

Table 27. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Low Power Mode

Output

Data

Rate

Output (Zero

Filter

Word

Data

Rate

(Dec.) (SPS)

Latency

Mode)

(SPS)

f_3dB

(Hz)

Gain = 1

0.22 (1.2)

0.24 (1.5)

0.37 (2.1)

0.5 (3)

Gain = 2

0.15 (0.89)

0.23 (1.2)

0.3 (1.7)

0.42 (2.5)

0.61 (3.5)

0.82 (5)

Gain = 4

0.095 (0.67)

0.13 (0.82)

0.18 (1.2)

0.26 (1.9)

0.38 (2.5)

0.53 (3.7)

0.6 (4.2)

Gain = 8

0.071 (0.41)

0.1 (0.61)

0.13 (0.77)

0.2 (1.1)

Gain = 16

Gain = 32

Gain = 64

Gain = 128

0.035 (0.16) 0.024 (0.12)

0.041 (0.23) 0.035 (0.17)

2047

1920

960

480

240

120

60

1.17

1.25

2.5

5

0.293

0.3125

0.625

1.25

2.5

0.269

0.288

0.575

1.15

2.3

0.053 (0.26) 0.043 (0.2)

0.068 (0.37) 0.055 (0.26)

0.099 (0.56) 0.078 (0.39)

0.06 (0.31)

0.085 (0.5)

0.12 (0.68)

0.17 (0.95)

0.2 (1.1)

0.052 (0.26)

0.072 (0.43)

0.096 (0.6)

0.14 (0.9)

0.16 (1)

10

0.65 (4.1)

0.9 (5.8)

1.3 (8)

0.14 (0.8)

0.2 1.2)

0.1 (0.6)

0.15 (0.85)

0.21 (1)

0.24 (1.5)

0.26 (1.7)

0.3 (2)

20

5

4.6

0.28 (1.7)

0.38 (2.4)

0.46 (2.8)

0.47 (3.2)

0.55 (3.7)

0.85 (5.7)

1.2 (7.5)

40

10

9.2

0.29 (1.8)

0.32 (2.1)

0.35 (2.2)

0.4 (2.7)

0.56 (3.9)

0.87 (5.6)

1.4 (8.5)

3 (19)

48

50

12.5

15

11.5

13.8

18.4

36.8

69

1.4 (9.3)

1.6 (10)

1.8 (12)

2.6 (17)

3.7 (24)

5.2 (35)

9.4 (57)

72 (470)

0.95 (6)

40

60

0.99 (6.6)

1.2 (7.5)

1.8 (11)

0.64 (4.5)

0.77 (5.1)

1.1 (7.2)

0.21 (1.3)

0.25 (1.6)

0.33 (2.1)

0.48 (2.9)

0.76 (5.2)

1.4 (9)

0.17 (1.1)

0.19 (1.3)

0.28 (1.6)

0.39 (2.6)

0.6 (3.9)

30

80

20

15

160

300

600

1200

2400

40

0.41 (2.5)

0.58 (3.9)

1 (6)

8

75

2.5 (17)

1.6 (11)

4

150

300

600

138

276

552

4 (24)

2.6 (17)

2.1 (13)

2

7.6 (47)

5.8 (36)

4.9 (32)

1.9 (11)

4.8 (29)

1.3 (7.8)

1

39 (240)

22 (130)

16 (110)

8 (49)

3.3 (21)

2.6 (18)

Table 28. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Low Power Mode

Output

Data

Rate

Output Data

Rate (Zero

Latency

Filter

Word

(Dec.)

(SPS)

Mode) (SPS)

Gain = 1

Gain = 2

Gain = 4

Gain = 8

Gain = 16

Gain = 32

21.8 (19.7)

21.8 (19.6)

21.4 (19.2)

20.9 (18.6)

20.5 (18)

Gain = 64

21.3 (18.9)

21.2 (18.9)

20.8 (18.4)

20.3 (17.9)

19.8 (17.2)

19.3 (16.8)

18.8 (16.3)

18.6 (16.1)

18.5 (15.9)

18.3 (15.6)

17.8 (15.2)

17.3 (14.7)

16.7 (13.9)

15.7 (13.1)

14.5 (11.9)

Gain = 128

20.6 (18.3)

20.1 (17.8)

19.5 (17.2

19.1 (16.5)

18.6 (16)

2047

1920

960

480

240

120

60

1.17

1.25

2.5

5

0.29311

0.3125

0.625

1.25

2.5

24 (22)

23.8 (21.4)

23.8 (21.3)

23.4 (21)

23.7 (20.9)

23.6 (20.8)

23.2 (20.5)

22.7 (20)

23.2 (20.5) 22.7 (20.2)

23.1 (20.5) 22.6 (20.1)

24 (21.7)

23.7 (21.2)

23.3 (20.7)

22.9 (20.2)

22.4 (19.7)

21.9 (19.2)

21.7 (19)

22.6 (20)

22.1 (19.7)

23 (20.5)

22.1 (19.6) 21.6 (19.1)

21.6 (19.1) 21.1 (18.6)

21.1 (18.5) 20.6 (18)

10

22.5 (19.9)

22 (19.4)

22.2 (19.4)

21.7 (18.9)

21.2 (18.4)

21 (18.2)

20

5

20 (17.5)

40

10

21.5 (18.9)

21.3 (18.7)

21.2 (18.5)

21 (18.3)

20.6 (18)

20.1 (17.4)

19.5 (17.3)

19.3 (16.7)

19.2 (16.5)

19 (16.2)

18.1 (15.4)

17.9 (15.2)

17.8 (15.1)

17.6 (14.9)

17.1 (14.5)

16.6 (13.9)

16 (13.3)

48

50

12.5

15

20.4 (17.8) 19.9 (17.2)

20.3 (17.6) 19.8 (17.1)

20.1 (17.4) 19.6 (16.8)

19.5 (16.8) 19.1 (16.3)

40

60

21.6 (18.9)

21.4 (18.7)

20.9 (18.2)

20.4 (17.7)

19.9 (17.1)

19 (16.4)

20.9 (18.1)

20.6 (17.9)

20.1 (17.4)

19.6 (16.8)

18.9 (16.2)

17.7 (15.1)

15.8 (13.3)

30

80

20

15

160

300

600

1200

2400

40

20.4 (17.8)

19.9 (17.2)

19.3 (16.7)

18.3 (15.7)

16 (13.4)

18.5 (15.7)

18 (15.3)

8

75

19 (16.3)

18.2 (15.6) 17.8 (15.2)

17 (14.3) 16.7 (14)

15.3 (12.5) 15.2 (12.5)

18.5 (15.8)

4

150

300

600

17.3 (14.7)

16.3 (13.8)

15 (12.4)

2

14.9 (12.3)

13.9 (11)

1

16.1 (13.4)

Rev. D | Page 33 of 92

AD7124-8

Data Sheet

Sinc³

Table 29. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Low Power Mode

Output

Data

Rate

Output (Zero

Filter

Word Rate

(Dec.) (SPS)

Data

Latency

Mode)

(SPS)

f_3dB

(Hz)

Gain = 1

0.26 (1.5)

0.51 (3.1)

0.75 (4.5)

0.88 (5.5)

1.3 (7.8)

1.7 (9.9)

1.8 (12)

Gain = 2

0.17 (0.9)

0.31 (1.9)

0.45 (2.8)

0.55 (3.3)

0.77 (4.9)

1 (6.4)

Gain = 4

0.099 (0.6)

0.2 (1.3)

0.29 (2)

Gain = 8

0.072 (0.36)

0.15 (0.86)

0.21 (1.3)

0.26 (1.6)

0.36 (2.2)

0.47 (3.1)

0.52 (3.4)

0.73 (5)

Gain = 16

0.055 (0.27)

0.11 (0.65)

0.16 (0.9)

0.19 (1.2)

0.27 (1.7)

0.36 (2.2)

0.39 (2.5)

0.55 (3.7)

0.8 (5.3)

Gain = 32

0.039 (0.21)

0.078 (0.45)

0.11 (0.65)

0.14 (0.79)

0.19 (1.2)

0.26 (1.7)

0.27 (1.8)

0.41 (2.5)

0.56 (3.5)

0.9 (6.5)

Gain = 64

Gain = 128

0.026 (0.13)

0.05 (0.28)

0.071 (0.39)

0.089 (0.53)

0.12 (0.72)

0.16 (1)

2047

480

240

160

80

48

40

20

10

5

1.17

5

0.39

1.67

3.33

5

0.32

0.032 (0.16)

0.063 (0.37)

0.085 (0.51)

0.1 (0.62)

0.15 (0.94)

0.2 ( 1.3)

0.21 (1.4)

0.3 (1.9)

1.36

10

2.72

15

4.08

0.3 (2.4)

0.47 (3.3)

0.63 (4.6)

0.71 (5)

30

10

8.16

50

16.67

20

13.6

60

16.32

32.64

65.28

130.6

217.6

326.4

652.8

1.1 (7)

0.18 (1.3)

0.26 (1.6)

0.37 (2.3)

0.55 (3.3)

0.91 (6)

120

240

480

800

1200

2400

40

2.5 (17)

1.6 (10)

0.9 (6.1)7

1.5 (9.9)

2.6 (19)

80

3.5 (25)

2.4 (16)

1.1 (7.6)

0.45 (2.8)

0.7 (4.5)

160

266.67

400

800

6.8 (48)

4.3 (32)

2 (15)

1.3 (9)

3

25 (180)

110 (740)

870 (5600)

13 (98)

7.4 (53)

4.5 (34)

2.7 (18)

1.6 (11)

1.1 (7.7)

2

55 (390)

430 (2900)

28 (180)

220 (1400)

15 (100)

110 (670)

7.6 (57)

4 (32)

2.4 (16)

1.6 (12)

1

56 (370)

28 (180)

14 (100)

7.6 (52)

Table 30. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate, Low Power Mode

Output

Data Rate

(Zero

Filter

Word

(Dec.)

Output

Data Rate

(SPS)

Latency

Mode)

(SPS)

Gain = 1

Gain = 2

Gain = 4

Gain = 8

Gain = 16

22.4 (20.1)

21.4 (18.9)

20.9 (18.4)

20.6 (18)

Gain = 32

21.9 (19.5)

20.9 (18.4)

20.4 (17.9)

20.1 (17.6)

19.6 (17)

Gain = 64

21.2 (18.9)

20.2 (17.7)

19.8 (17.2)

19.5 (16.9)

19 (16.3)

Gain = 128

20.5 (18.2)

19.6 (17.1)

19.1 (16.6)

18.8 (16.2)

18.3 (15.7)

17.9 (15.2)

17.7 (15.1)

17.2 (14.6)

16.7 (14.1)

16.1 (13.5)

15.4 (12.7)

14.5 (11.6)

12.3 (9.6)

2047

480

240

160

80

48

40

20

10

5

1.17

5

0.39

1.67

3.33

5

24 (21.7)

23.8 (21.4)

22.9 (20.3)

22.4 (19.8)

22.1 (19.5)

21.6 (19)

23.6 (21)

23 (20.7)

23.2 (20.6)

22.7 (20.1)

22.4 (19.8)

21.9 (19.3)

21.5 (18.9)

21.4 (18.7)

20.9 (18.2)

20.4 (17.6)

19.5 (16.7)

17.6 (14.8)

15.5 (12.7)

12.5 (9.8)

22.6 (19.9)

22.1 (19.3)

21.8 (19)

22 (19.5)

10

21.5 (18.9)

21.2 (18.6)

20.7 (18.1)

20.3 (17.6)

20.2 (17.5)

19.7 (16.9)

19.1 (16.3)

18.2 (15.4)

17.1 (14.2)

15.4 (12.6)

12.5 (9.8

15

30

10

21.3 (18.5)

20.9 (18.1)

20.8 (17.9)

20.3 (17.4)

19.7 (16.9)

18.8 (16)

20.1 (17.5)

19.7 (17.1)

19.6 (16.9)

19.1 (16.4)

18.6 (15.9)

17.9 (15.1)

16.8 (14.1)

15.3 (12.4)

12.5 (9.7)

50

16.67

20

21.2 (18.6)

21.1 (18.4)

20.6 (17.9)

20 (17.2)

19.2 (16.5)

19.1 (16.4)

18.6 (15.9)

18.1 (15.4)

17.4 (14.6)

16.6 (13.8)

15.2 (12.3)

12.5 (9.7)

18.6 (15.9)

18.5 (15.8)

18 (15.3)

60

120

480

800

1200

2400

40

80

17.4 (14.8)

16.8 (14.1)

16.1 (13.3)

15 (12.2)

160

266.67

400

800

19.2 (16.3)

17.5 (14.6)

15.5 (12.7)

12.5 (9.8)

3

17.4 (14.5)

15.4 (12.7)

12.5 (9.8)

2

1

12.5 (9.6)

Post Filters

Table 31. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Low Power Mode

Output Data Rate (SPS)

Gain = 1

1.7 (12)

1.7 (11)

1.8 (11)

1.9 (11)

Gain = 2

0.96 (5.8)

1.1 (6.4)

1.1 (6.7)

1.1 (7.3)

Gain = 4

Gain = 8

0.45 (2.6)

0.46 (2.6)

0.52 (2.7)

0.54 (2.9)

Gain = 16

0.34 (1.9)

0.36 (1.9)

0.37 (2)

Gain = 32

0.25 (1.5)

0.26 (1.5)

0.26 (1.6)

0.27 (1.8)

Gain = 64

Gain = 128

16.67

20

0.65 (4)

0.2 (1.2)

0.16 (0.92)

0.17 (0.93)

0.17 (1.1)

0.18 (1.3)

0.65 (4.2)

0.68 (4.2)

0.69 (4.4)

0.21 (1.2)

0.22 (1.2)

0.23 (1.4)

25

27.27

0.4 (2.1)

Table 32. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Low Power Mode

Output Data Rate (SPS)

Gain = 1

Gain = 2

Gain = 4

Gain = 8

Gain = 16

19.8 (17.3)

19.7 (17.3)

19.6 (17.2)

Gain = 32

19.3 (16.7)

19.2 (16.7)

19.2 (16.6)

19.1 (16.4)

Gain = 64

18.6 (16.1)

18.5 (15.9)

18.4 (15.8)

Gain = 128

17.9 (15.4)

17.8 (15.4)

17.8 (15.1)

17.7 (14.9)

16.67

20

21.5 (18.8)

21.4 (18.8)

21.3 (18.7)

21.2 (18.6)

21.2 (18.5)

21.1 (18.4)

20.9 (18.2)

20.8 (18.2)

20.8 (18.1)

21.4 (17.9)

20.4 (17.9)

20.2 (17.8)

20.2 (17.7)

25

27.27

Rev. D | Page 34 of 92

Data Sheet

AD7124-8

Fast Settling Filter (Sinc⁴+ Sinc¹)

Table 33. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Low Power Mode (Average by 8)

Filter Word

(Dec.)

Output Data Rate

(SPS)

Gain = 1

0.53 (3.4)

0.89 (5.4)

2.1 (12)

2.2 (13)

3.7 (25)

8.4 (52)

Gain = 2

0.34 (2.2)

0.6 (3.6)

1.4 (8.3)

1.4 (9.7)

2.5 (18)

5.4 (34)

Gain = 4

0.19 (1.2)

0.36 (2.2)

0.82 (5.6)

0.93 (6.5)

1.5 (10)

Gain = 8

0.16 (0.97)

0.27 (1.8)

0.64 (3.9)

0.71 (4.2)

1.3 (7.5)

Gain = 16

0.1 (0.61)

0.21 (1.2)

0.43 (2.7)

0.5 (3.1)

Gain = 32

0.082 (0.48)

0.15 (0.93)

0.33 (2.1)

0.35 (2.4)

0.59 (3.5)

0.97 (6.1)

Gain = 64

0.065 (0.38)

0.12 (0.65)

0.25 (1.6)

0.28 (1.7)

0.47 (3.2)

0.75 (5.4)

Gain = 128

0.058 (0.37)

0.093 (0.59)

0.21 (1.4)

96

30

6

2.27

7.27

36.36

43.64

109.1

218.18

5

0.23 (1.5)

2

0.86 (5.6)

1.6 (9.8)

0.39 (2.4)

1

3.3 (21)

2.6 (16)

0.63 (4.7)

Table 34. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Low Power Mode (Average by 8)

Filter Word

(Dec.)

Output Data

Rate (SPS)

Gain = 1

Gain = 2

22.8 (20.1)

22 (19.4)

Gain = 4

Gain = 8

Gain = 16

21.5 (19)

Gain = 32

20.9 (18.3)

20 (17.4)

Gain = 64

20.2 (17.6)

19.4 (16.9)

18.3 (15.6)

18.1 (15.5)

17.3 (14.6)

16.7 (13.8)

Gain = 128

19.4 (16.7)

18.7 (16)

96

30

6

2.27

23.2 (20.5)

22.4 (19.8)

21.2 (18.6)

21.1 (18.5)

20.4 (17.6)

19.2 (16.6)

22.7 (20)

21.9 (19.3)

21.1 (18.4)

19.9 (17.3)

19.8 (17.2)

18.9 (16.3)

17.9 (15.2)

7.27

21.7 (19.1)

20.5 (17.8)

20.4 (17.6)

19.6 (16.9)

18.5 (15.9)

20.5 (18)

36.36

43.64

109.1

218.18

20.8 (18.1)

20.7 (18)

19.5 (16.8)

19.3 (16.6)

18.5 (15.8)

17.6 (15)

18.9 (16.2)

18.8 (16)

17.5 (14.8)

17.4 (14.7)

16.6 (14)

5

2

19.9 (17.1)

18.8 (16.2)

18 (15.4)

1

17.3 (14.7)

15.9 (13)

Fast Settling Filter (Sinc³+ Sinc¹)

Table 35. RMS Noise (Peak-to-Peak Noise) vs. Gain and Output Data Rate (µV), Low Power Mode (Average by 8)

Filter Word

(Dec.)

Output Data Rate

(SPS)

Gain = 1

0.53 (3.6)

0.92 (5.4)

2.1 (13)

Gain = 2

0.33 (2.1)

0.58 (3.4)

1.3 (8.3)

1.5 (8.6)

5.9 (39)

Gain = 4

0.21 (1.4)

0.4 (2.3)

0.83 (6)

Gain = 8

0.15 (0.93)

0.28 (1.6)

0.61 (4.1)

0.7 (4.4)

1.9 (15)

Gain = 16

0.11 (0.6)

0.2 (1.1)

0.44 (3)

Gain = 32

0.073 (0.44)

0.14 (0.79)

0.33 (2.1)

0.36 (2.3)

0.7 (4.7)

Gain = 64

0.064 (0.39)

0.11 (0.62)

0.26 (1.6)

0.3 (1.7)

Gain = 128

0.051 (0.29)

0.094 (0.51)

0.21 (1.3)

0.23 (1.4)

0.4 (2.4)

96

30

6

2.5

8

40

5

48

2.3 (14)

0.87 (6.6)

3.2 (23)

0.5 (3.3)

1.1 (8.5)

5.8 (40)

2

120

240

11 (72)

0.5 (3.3)

1

88 (530)

45 (250)

22 (140)

11 (82)

3 (22)

01.6 (11)

0.94 (6.3)

Table 36. Effective Resolution (Peak-to-Peak Resolution) vs. Gain and Output Data Rate (Bits), Low Power Mode (Average by 8)

Filter Word

(Dec.)

Output Data Rate

(SPS)

Gain = 1

Gain = 2

22.8 (20.2)

22 (19.5)

Gain = 4

Gain = 8

22 (19.4)

21.1 (18.6)

20 (17.2)

19.8 (17)

18.3 (15.3)

15.7 (12.9)

Gain = 16

21.4 (19)

Gain = 32

21 (18.4)

Gain = 64

20.2 (17.6)

19.4 (16.9)

18.2 (15.6)

18 (15.5)

Gain = 128

19.6 (17)

96

30

6

2.5

8

23.2 (20.4)

22.4 (19.8)

21.2 (18.6)

21 (18.4)

22.5 (19.8)

21.6 (19)

20.6 (18.1)

19.4 (16.7)

19.3 (16.5)

18.1 (15.2)

15.7 (12.9)

20.1 (17.6)

18.9 (16.2)

18.7 (16.1)

17.8 (15)

18.7 (16.2)

17.5 (14.9)

17.4 (14.8)

16.6 (14)

40

20.9 (18.2)

20.7 (18.1)

18.7 (16)

20.5 (17.7)

20.4 (17.5)

18.6 (15.8)

15.8 (13.2)

5

48

2

120

240

18.7 (16.1)

15.8 (13.2)

17.3 (14.6)

15.6 (12.8)

1

15.8 (13.2)

15.7 (12.8)

15.3 (12.6)

Rev. D | Page 35 of 92

AD7124-8

Data Sheet

GETTING STARTED

AV

DD

AV_DD

REFIN1(+)

IN+

OUT–

V_BIAS

OUT+

AIN0

REFERENCE

DETECT

AIN1

AIN2

AIN3

AV

DD

IN+

IN–

OUT–

OUT+

DOUT/RDY

DIN

SERIAL

INTERFACE

AND

CONTROL

LOGIC

DIGITAL

FILTER

Σ-Δ

ADC

PGA

X-MUX

AIN12

AIN13

REFIN2(+)

SCLK

CS

REFIN2(–)

CHANNEL

SEQUENCER

TEMP

SENSOR

AV

SS

IOV

DD

R

REF

INTERNAL

CLOCK

VDD

DIAGNOSTICS

CLK

REFIN1(–)

PSW

SYNC

AD7124-8

AV

SS

AV

SS

DGND

REGCAPA

REGCAPD

NOTES

1. SIMPLIFIED BLOCK DIAGRAM SHOWN.

Figure 64. Basic Connection Diagram

Programmable Gain Array (PGA)

OVERVIEW

The analog input signal can be amplified using the PGA. The

PGA allows gains of 1, 2, 4, 8, 16, 32, 64, and 128.

The AD7124-8 is a low power ADC that incorporates a Σ-Δ modu-

lator, buffer, reference, gain stage, and on-chip digital filtering,

which is intended for the measurement of wide dynamic ranges,

low frequency signals (such as those in pressure transducers),

weigh scales, and temperature measurement applications.

Burnout Currents

Two burnout currents, which can be programmed to 500 nA,

2 µA, or 4 µA, are included on chip to detect the presence of the

external sensor.

Power Modes

The AD7124-8 offers three power modes: high power mode,

mid power mode, and low power mode. This allows the user

total flexibility in terms of speed, rms noise, and current

consumption.

Σ-Δ ADC and Filter

The AD7124-8 contains a fourth-order Σ-Δ modulator followed

by a digital filter. The device has the following filter options:

•

Sinc⁴

Analog Inputs

Sinc³

The device can have 8 differential or 15 pseudo differential analog

inputs. The analog inputs can be buffered or unbuffered. The

AD7124-8 uses flexible multiplexing; thus, any analog input pin

can be selected as a positive input (AINP) and any analog input

pin can be selected as a negative input (AINM).

Fast filter

Post filter

Zero latency

Channel Sequencer

Multiplexer

The AD7124-8 allows up to 16 configurations, or channels.

These channels can consist of analog inputs, reference inputs, or

power supplies such that diagnostic functions, such as power

supply monitoring, can be interleaved with conversions. The

sequencer automatically converts all enabled channels. When

each enabled channel is selected, the time required to generate

the conversion is equal to the settling time for the selected channel.

The on-chip multiplexer increases the channel count of the device.

Because the multiplexer is included on chip, any channel

changes are synchronized with the conversion process.

Reference

The device contains a 2.5 V reference, which has a drift of

15 ppm/°C maximum.

Per Channel Configuration

Reference buffers are also included on chip, which can be used

with the internal reference and externally applied references.

The AD7124-8 allows up to eight different setups, each setup

consisting of a gain, output data rate, filter type, and a reference

source. Each channel is then linked to a setup.

Rev. D | Page 36 of 92

Data Sheet

AD7124-8

Serial Interface

The device has two independent power supply pins: AV_DDand

IOV_DD.

The AD7124-8 has a 3-wire or 4-wire SPI. The on-chip registers

are accessed via the serial interface.

•

AV_DDis referred to AV_SS. AV_DDpowers the internal analog

regulator that supplies the ADC.

Clock

•

IOV_DDis referred to DGND. This supply sets the interface

logic levels on the SPI interface and powers an internal

regulator for operation of the digital processing.

The device has an internal 614.4 kHz clock. Use either this

clock or an external clock as the clock source for the device. The

internal clock can also be made available on a pin if a clock

source is required for external circuitry.

Single Supply Operation (AV_SS= DGND)

When the AD7124-8 is powered from a single supply that is

connected to AV_DD, AV_SSand DGND can be shorted together

on one single ground plane. With this setup, an external level

shifting circuit is required when using truly bipolar inputs to shift

the common-mode voltage. Recommended regulators include

the ADP162, which has a low quiescent current.

Temperature Sensor

The on-chip temperature sensor monitors the die temperature.

Digital Outputs

The AD7124-8 has four general-purpose digital outputs. These

can be used for driving external circuitry. For example, an

external multiplexer can be controlled by these outputs.

Split Supply Operation (AV_SS≠ DGND)

Calibration

The AD7124-8 can operate with AV_SSset to a negative voltage,

allowing true bipolar inputs to be applied. This allows a truly

fully differential input signal centered around 0 V to be applied

to the AD7124-8 without the need for an external level shifting

circuit. For example, with a 3.6 V split supply, AV_DD= +1.8 V

and AV_SS= −1.8 V. In this use case, the AD7124-8-internally

level shifts the signals, allowing the digital output to function

between DGND (nominally 0 V) and IOV_DD.

Both internal calibration and system calibration are included on

chip; therefore, the user has the option of removing offset or

gain errors internal to the device only, or removing the offset or

gain errors of the complete end system.

Excitation Currents

The device contains two excitation currents that can be set

independently to 50 µA, 100 µA, 250 µA, 500 µA, 750 µA, or 1 mA.

When using a split supply for AV_DDand AV_SS, the absolute

maximum ratings must be considered (see the Absolute

Maximum Ratings section). Ensure that IOV_DDis set below

3.6 V to stay within the absolute maximum ratings for the device.

Bias Voltage

A bias voltage generator is included on chip so that signals from

thermocouples can be biased suitably. The bias voltage is set to

AV_DD/2 and can be made available on any input. It can supply

multiple channels.

DIGITAL COMMUNICATION

The AD7124-8 has a 3-wire or 4-wire SPI interface that is

compatible with QSPI, MICROWIRE, and DSPs. The interface

Bridge Power Switch (PSW)

A low-side power switch allows the user to power down bridges

that are interfaced to the ADC.

CS

operates in SPI Mode 3 and can be operated with

tied low. In

SPI Mode 3, SCLK idles high, the falling edge of SCLK is the

drive edge, and the rising edge of SCLK is the sample edge. This

means that data is clocked out on the falling/drive edge and data

is clocked in on the rising/sample edge.

Diagnostics

The AD7124-8 includes numerous diagnostics features such as

•

Reference detection

Overvoltage/undervoltage detection

CRC on SPI communications

CRC on the memory map

SPI read/write checks

DRIVE EDGE

SAMPLE EDGE

These diagnostics allow a high level of fault coverage in an

application.

Figure 65. SPI Mode 3, SCLK Edges

Accessing the ADC Register Map

POWER SUPPLIES

The communications register controls access to the full register

map of the ADC. This register is an 8-bit, write only register.

On power-up or after a reset, the digital interface defaults to a

state where it expects a write to the communications register;

therefore, all communication begins by writing to the

communications register.

The AD7124-8 operates with an analog power supply voltage

from 2.7 V to 3.6 V in low or mid power mode and from 2.9 V

to 3.6 V in full power mode. The device accepts a digital power

supply from 1.65 V to 3.6 V.

Rev. D | Page 37 of 92

AD7124-8

Data Sheet

8 BITS, 16 BITS,

OR 24 BITS OF DATA

The data written to the communications register determines

which register is accessed and if the next operation is a read or

write. The register address bits (Bit 5 to Bit 0) determine the

specific register to which the read or write operation applies.

8-BIT COMMAND

CS

When the read or write operation to the selected register is

complete, the interface returns to its default state, where it

expects a write operation to the communications register.

CMD

DATA

DIN

SCLK

In situations where interface synchronization is lost, a write

operation of at least 64 serial clock cycles with DIN high returns

the ADC to its default state by resetting the entire device, including

Figure 66. Writing to a Register (8-Bit Command with Register Address

Followed by Data of 8 Bits, 16 Bits, or 24 Bits; Data Length Is Dependent on

the Register Selected)

CS

the register contents. Alternatively, if

is used with the digital

CS

interface, returning

high resets the digital interface to its

default state and aborts any current operation.

8 BITS, 16 BITS,

24 BITS, OR

32 BITS OUTPUT

Figure 66 and Figure 67 illustrate writing to and reading from a

register by first writing the 8-bit command to the communications

register followed by the data for the addressed register.

8-BIT COMMAND

CS

Reading the ID register is the recommended method for verifying

correct communication with the device. The ID register is a read

only register and contains the value 0x14 for the AD7124-8. The

communication register and ID register details are described in

Table 37 and Table 38.

CMD

DIN

DOUT/RDY

DATA

SCLK

Figure 67. Reading from a Register (8-Bit Command with Register Address

Followed by Data of 8 Bits, 16 Bits, 24 Bits, or 32 Bits; Data Length on DOUT Is

Dependent on the Register Selected, CRC Enabled)

Table 37. Communications Register

Reg.

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0x00

COMMS

[7:0]

WEN

R/W

RS[5:0]

0x00

W

Table 38. ID Register

Reg.

Name

Bits

Bit 7

Bit 6

Bit 3

Bit 2

Bit 1

Reset

RW

0x05

ID

[7:0]

DEVICE_ID

SILICON_REVISION

0x14

R

Rev. D | Page 38 of 92

Data Sheet

AD7124-8

Channel Configuration

CONFIGURATION OVERVIEW

The AD7124-8 has 16 independent analog input channels and

eight independent setups. The user can select any of the analog

input pairs on any channel, as well as any of the eight setups for

any channel, giving the user full flexibility in the channel configura-

tion. This also allows per channel configuration when using all

differential inputs because each channel can have its own

dedicated setup.

After power-on or reset, the AD7124-8 default configuration is

as follows:

•

Channel: Channel 0 is enabled, AIN0 is selected as the

positive input, and AIN1 is selected as the negative input.

Setup 0 is selected.

•

Setup: the input and reference buffers are disabled, the gain

is set to 1, and the external reference is selected.

ADC control: the AD7124-8 is in low power mode,

continuous conversion mode and the internal oscillator is

enabled and selected as the master clock source.

Diagnostics: the only diagnostic enabled is the

SPI_IGNORE_ERR function.

Along with the analog inputs, signals such as the power supply

or reference can also be used as inputs; they are routed to the

multiplexer internally when selected. The AD7124-8 allows the

user to define 16 configurations, or channels, to the ADC. This

allows diagnostics to be interleaved with conversions.

•

Channel Registers

Note that only a few of the register setting options are shown;

this list is just an example. For full register information, see the

On-Chip Registers section.

Use the channel registers to select which input pins are either the

positive analog input or the negative analog input for that

channel. This register also contains a channel enable/disable bit

and the setup selection bits, which are used to select which of

the eight available setups to use for this channel.

Figure 68 shows an overview of the suggested flow for changing

the ADC configuration, divided into the following three blocks:

•

Channel configuration (see Box A in Figure 68)

Setup (see Box B in Figure 68)

Diagnostics (see Box C in Figure 68)

ADC control (see Box D in Figure 68)

When the AD7124-8 is operating with more than one channel

enabled, the channel sequencer cycles through the enabled

channels in sequential order, from Channel 0 to Channel 15. If a

channel is disabled, it is skipped by the sequencer. Details of the

channel register for Channel 0 are shown in Table 39.

A

CHANNEL CONFIGURATION

SELECT POSITIVEAND NEGATIVE INPUT FOR EACH ADC CHANNEL

SELECT ONE OF 8 SETUPS FORADC CHANNEL

B

C

D

SETUP

8 POSSIBLE ADC SETUPS

SELECT FILTER, OUTPUT DATA RATE, GAIN AND MORE

DIAGNOSTICS

ENABLE CRC, SPI READ AND WRITE CHECKS

ENABLE LDO CHECKS, AND MORE

ADC CONTROL

SELECT ADC OPERATING MODE, CLOCK SOURCE,

SELECT POWER MODE, DATA + STATUS, AND MORE

Figure 68. Suggested ADC Configuration Flow

Table 39. Channel 0 Register

Reg. Name

Bits Bit 7

Bit 6

AINP[2:0]

Bit 5

Setup

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset RW

0x09 CHANNEL_0 [15:8] Enable

[7:0]

0

AINP[4:3]

0x8001 RW

AINM[4:0]

Rev. D | Page 39 of 92

AD7124-8

Data Sheet

ADC Setups

bipolar mode, the ADC accepts negative differential input voltages,

and the output coding is offset binary. In unipolar mode, the ADC

accepts only positive differential voltages, and the coding is straight

binary. In either case, the input voltage must be within the AV_DD

and AV_SSsupply voltages. The user can also select the reference

source using these registers. Four options are available: an

internal 2.5 V reference, an external reference connected

between REFIN1(+) and REFIN1(−), an external reference

connected between REFIN2(+) and REFIN2(−), or AV_DDto AV_SS.

The PGA gain is also set; gains of 1, 2, 4, 8, 16, 32, 64, and 128

are provided. The analog input buffers and reference input

buffers for the setup can also be enabled using this register.

The AD7124-8 has eight independent setups. Each setup

consists of the following four registers:

•

Configuration register

Filter register

Offset register

Gain register

For example, Setup 0 consists of Configuration Register 0, Filter

Register 0, Offset Register 0, and Gain Register 0. Figure 69

shows the grouping of these registers. The setup is selectable

from the channel registers detailed in the Channel Configuration

section. This allows each channel to be assigned to one of eight

separate setups. Table 40 through Table 43 show the four

registers that are associated with Setup 0. This structure is

repeated for Setup 1 to Setup 7.

Filter Registers

The filter registers select which digital filter is used at the output

of the ADC modulator. The filter type and the output data rate

are selected by setting the bits in this register. For more information,

see the Digital Filter section.

Configuration Registers

The configuration registers allow the user to select the output

coding of the ADC by selecting between bipolar and unipolar. In

CONFIGURATION

REGISTERS

FILTER

REGISTERS

GAIN

REGISTERS

OFFSET

REGISTERS

CONFIG_0

CONFIG_1

CONFIG_2

CONFIG_3

CONFIG_4

CONFIG_5

CONFIG_6

CONFIG_7

FILTER_0

FILTER_1

FILTER_2

FILTER_3

FILTER_4

FILTER_5

FILTER_6

FILTER_7

GAIN_0

GAIN_1

GAIN_2

GAIN_3

GAIN_4

GAIN_5

GAIN_6

GAIN_7

OFFSET_0

OFFSET_1

OFFSET_2

OFFSET_3

OFFSET_4

OFFSET_5

OFFSET_6

OFFSET_7

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

SELECT PERIPHERAL

FUNCTIONS FOR

ADC CHANNEL

SELECT DIGITAL

FILTER TYPE

AND OUTPUT DATA RATE

GAIN CORRECTION

OPTIONALLY

OFFSET CORRECTION

OPTIONALLY PROGRAMMED

PER SETUP AS REQUIRED

PROGRAMMED

PER SETUP AS REQUIRED

4

ANALOG INPUT BUFFERS

REFERENCE BUFFERS

BURNOUT

SINC

3

SINC

4

1

SINC + SINC

3

1

SINC + SINC

REFERENCE SOURCE

GAIN

ENHANCED 50Hz/60Hz REJECTION

Figure 69. ADC Setup Register Grouping

Table 40. Configuration 0 Register

Reg. Name

0x19 CONFIG_0 [15:8]

[7:0] REF_BUFM

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Burnout

Bit 0

Reset

RW

0

Bipolar

REF_BUFP

0x0860

RW

AIN_BUFP

AIN_BUFM

REF_SEL

PGA

Table 41. Filter 0 Register

Reg. Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

REJ60

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0x28 FILTER_0

[23:9]

[15:8]

[7:0]

Filter

POST_FILTER

SINGLE_CYCLE 0x060180 RW

FS[10:8]

0

FS[7:0]

Table 42. Offset 0 Register

Reg. Name

Bits

Bits[23:0]

Reset

RW

0x29 OFFSET_0 [23:0]

Offset[23:0]

0x800000 RW

Table 43. Gain 0 Register

Reg. Name

Bits

Bits[23:0]

Reset

RW

0x31 GAIN_0

[23:0]

Gain[23:0]

0x5XXXXX RW

Rev. D | Page 40 of 92

Data Sheet

AD7124-8

When a diagnostic is enabled, the corresponding flag is contained

in the error register. All enabled flags are OR’ed to control the

ERR flag in the status register. Thus, if an error occurs (for example,

the SPI CRC check detects an error), the relevant flag (for example,

the SPI_CRC_ERR flag) in the error register is set. The ERR flag

in the status register is also set. This is useful when the status bits

are appended to conversions. The ERR bit indicates if an error has

occurred. The user can then read the error register for more

details on the error source.

Offset Registers

The offset registers hold the offset calibration coefficient for the

ADC. The power-on reset value of an offset register is 0x800000.

The offset registers are 24-bit read/write registers. The power-

on reset value is automatically overwritten if an internal or

system zero-scale calibration is initiated by the user or if the offset

registers are written to by the user.

Gain Registers

The gain registers are 24-bit registers that hold the gain

calibration coefficient for the ADC. The gain registers are

read/write registers. The gain is factory calibrated at a gain of 1;

thus, the default value varies from device to device. The default

value is automatically overwritten if an internal or system full-

scale calibration is initiated by the user. For more information

on calibration, see the Calibration section.

The frequency of the on-chip oscillator can also be monitored

on the AD7124-8. The MCLK_COUNT register monitors the

master clock pulses. Table 44 to Table 46 give more detail on the

diagnostic registers. See the Diagnostics section for more detail

on the diagnostics available.

ADC Control Register

The ADC control register configures the core peripherals for use

by the AD7124-8 and the mode for the digital interface. The

power mode (full power, mid power, or low power) is selected

via this register. Also, the mode of operation is selected, for example,

continuous conversion or single conversion. The user can also

select the standby and power-down modes, as well as any of the

calibration modes. In addition, this register contains the clock

source select bits and the internal reference enable bits. The

reference select bits are contained in the setup configuration

registers (see the ADC Setups section for more information).

Diagnostics

The ERROR_EN register enables and disables the numerous

diagnostics on the AD7124-8. By default, the SPI_IGNORE

function is enabled, which indicates inappropriate times to

write to the ADC (for example, during power-up and during a

reset). Other diagnostics include

•

SPI read and write checks, which ensure that only valid

registers are accessed

•

SCLK counter, which ensures that the correct number of

SCLK pulses are used

SPI CRC

Memory map CRC

LDO checks

The digital interface operation is also selected via the ADC

control register. This register allows the user to enable the data

plus status read and continuous read mode. For more details, see

the Digital Interface section. The details of this register are

shown in Table 47.

•

Table 44. Error Register

Reg. Name Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0x06 Error [23:16]

0

LDO_CAP_ERR ADC_CAL_ERR ADC_CONV_ ADC_SAT_

0x000000

R

ERR

0

[15:8]

[7:0]

AINP_OV_

ERR

AINP_UV_

ERR

AINM_OV_

ERR

AINM_UV_ REF_DET_ERR

ERR

0

DLDO_PSM_

ERR

ALDO_PSM_

ERR

SPI_IGNORE_ SPI_SCLK_

ERR

SPI_READ_ SPI_WRITE_

SPI_CRC_ERR

MM_CRC_

ERR

ROM_CRC_

ERR

CNT_ERR

ERR

Table 45. Error Enable Register

Reg. Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

LDO_CAP_CHK

Bit 2

Bit 1

Bit 0

Reset

RW

0x07 ERROR_EN [23:16]

0

MCLK_CNT_

EN

LDO_CAP_

CHK_TEST_EN

ADC_CAL_

ERR_EN

ADC_CONV_ ADC_SAT_

ERR_EN ERR_EN

DLDO_PSM_ ALDO_PSM_

0x000040 RW

[15:8]

[7:0]

AINP_OV_

ERR_EN

AINP_UV_

ERR_EN

AINM_OV_

AINM_UV_ REF_DET_

ERR_EN ERR_EN

SPI_READ_ SPI_WRITE_ SPI_CRC_

CNT_ERR_EN ERR_EN ERR_EN ERR_EN

DLDO_PSM_

TRIP_TEST_EN ERR_EN

ERR_EN

TRIP_TEST_EN

ALDO_PSM_ SPI_IGNORE_ SPI_SCLK_

ERR_EN ERR_EN

MM_CRC_

ERR_EN

ROM_CRC_

ERR_EN

Table 46. MCLK Count Register

Reg.

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0x08

MCLK_COUNT

[7:0]

MCLK_COUNT

0x00

R

Table 47. ADC Control Register

Reg. Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

DATA_STATUS

Bit 1

CS

Bit 0

REF_EN

Reset

RW

0x01 ADC_CONTROL [15:8]

[7:0]

0

RDY

CONT_READ

Mode

0x0000

RW

DOUT_

_DEL

_EN

CLK_SEL

POWER_MORE

Rev. D | Page 41 of 92

AD7124-8

Data Sheet

Understanding Configuration Flexibility

Programming the gain and offset registers is optional for any

use case, as indicated by the dashed lines between the register

blocks. If an internal or system offset or full-scale calibration is

performed, the gain and offset registers for the selected channel

are automatically updated.

In Figure 70, Figure 71, and Figure 72, the registers shown in

black font are programmed for this configuration. The registers

shown in gray font are redundant.

The most straightforward implementation of the AD7124-8 is

to use differential inputs with adjacent analog inputs and run all

of them with the same setup, gain correction, and offset correction

register. For example, the user requires four differential inputs.

In this case, the user selects the following differential inputs: AIN0/

AIN1, AIN2/AIN3, AIN4/AIN5, AIN6/AIN7.

An alternative way to implement these four fully differential inputs

is by taking advantage of the eight available setups. Motivation for

this includes having a different speed, noise, or gain requirement on

some of the four differential inputs vs. other inputs, or there may be

a specific offset or gain correction for particular channels. Figure 71

shows how each of the differential inputs can use a separate setup,

allowing full flexibility in the configuration of each channel.

CHANNEL

REGISTERS

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

CH0

CH1

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

CH2

CH3

CONFIGURATION

REGISTERS

FILTER

GAIN

OFFSET

REGISTERS

CH4

CONFIG_0

FILTER_0

GAIN_0

OFFSET_0

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

CH5

CONFIG_1

CONFIG_2

CONFIG_3

CONFIG_4

CONFIG_5

CONFIG_6

CONFIG_7

FILTER_1

FILTER_2

FILTER_3

FILTER_4

FILTER_5

FILTER_6

FILTER_7

GAIN_1

GAIN_2

GAIN_3

GAIN_4

GAIN_5

GAIN_6

GAIN_7

OFFSET_1

OFFSET_2

OFFSET_3

OFFSET_4

OFFSET_5

OFFSET_6

OFFSET_7

CH6

CH7

CH8

CH9

CH10

CH11

CH12

CH13

CH14

CH15

SELECT PERIPHERAL

FUNCTIONS FOR

ADC CHANNEL

SELECT DIGITAL

FILTER TYPE

AND OUTPUT DATA RATE

GAIN CORRECTION

OPTIONALLY

OFFSET CORRECTION

OPTIONALLY PROGRAMMED

PER SETUP AS REQUIRED

PROGRAMMED

PER SETUP AS REQUIRED

4

ANALOG INPUT BUFFERS

REFERENCE BUFFERS

BURNOUT

SINC

3

SINC

4

1

SELECT ANALOG INPUT PARTS

ENABLE THE CHANNEL

SELECT SETUP 0

SINC + SINC

3

1

REFERENCE SOURCE

GAIN

SINC + SINC

ENHANCED 50Hz/60Hz REJECTION

Figure 70. Four Fully Differential Inputs, All Using a Single Setup (CONFIG_0, FILTER_0, GAIN_0, OFFSET_0)

CHANNEL

REGISTERS

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

CH0

0x09

CH1

CH2

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

CH3

CONFIGURATION

REGISTERS

FILTER

GAIN

OFFSET

REGISTERS

CH4

CONFIG_0

FILTER_0

GAIN_0

OFFSET_0

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

CH5

CONFIG_1

CONFIG_2

CONFIG_3

CONFIG_4

CONFIG_5

CONFIG_6

CONFIG_7

FILTER_1

FILTER_2

FILTER_3

FILTER_4

FILTER_5

FILTER_6

FILTER_7

GAIN_1

GAIN_2

GAIN_3

GAIN_4

GAIN_5

GAIN_6

GAIN_7

OFFSET_1

OFFSET_2

OFFSET_3

OFFSET_4

OFFSET_5

OFFSET_6

OFFSET_7

CH6

CH7

CH8

CH9

CH10

CH11

CH12

CH13

CH14

CH15

SELECT PERIPHERAL

FUNCTIONS FOR

ADC CHANNEL

SELECT DIGITAL

FILTER TYPE

AND OUTPUT DATA RATE

GAIN CORRECTION

OPTIONALLY

OFFSET CORRECTION

OPTIONALLY PROGRAMMED

PER SETUP AS REQUIRED

PROGRAMMED

PER SETUP AS REQUIRED

4

ANALOG INPUT BUFFERS

REFERENCE BUFFERS

BURNOUT

SINC

0x18

3

SINC

4

1

SELECT ANALOG INPUT PARTS

ENABLE THE CHANNEL

SELECT SETUP

SINC + SINC

3

1

REFERENCE SOURCE

GAIN

SINC + SINC

ENHANCED 50Hz/60Hz REJECTION

Figure 71. Four Fully Differential Inputs with a Separate Setup per Channel

Rev. D | Page 42 of 92

Data Sheet

AD7124-8

Figure 72 shows an example of how the channel registers span

between the analog input pins and the setup configurations

downstream. In this random example, two differential inputs and

two single-ended inputs are required. The single-ended inputs are

the AIN0/AIN7 and AIN6/AIN7 combinations. The first differen-

tial input pair (AIN0/AIN1) uses Setup 0. The two single-ended

input pairs (AIN0/AIN7 and AIN6/AIN7) are set up as diagnostics;

therefore, they use a separate setup (Setup 1). The final differential

input (AIN2/AIN3) also uses a separate setup: Setup 2.

In the example shown in Figure 72, the CHANNEL_0 to

CHANNEL_3 registers are used. Setting the MSB (the enable

bit) in each of these registers enables the four combinations via

the crosspoint multiplexer. When the AD7124-8 converts, the

sequencer transitions in ascending sequential order from

CHANNEL_0 to CHANNEL_1 to CHANNEL_2, and then on

to CHANNEL_3 before looping back to CHANNEL_0 to repeat

the sequence.

Given that three setups are selected for use, the CONFIG_0,

CONFIG_1, and CONFIG_2 registers are programmed as

required, and the FILTER_0, FILTER_1, and FILTER_2 registers

are also programmed as required. Optional gain and offset

correction can be employed on a per setup basis by

programming the GAIN_0, GAIN_1, and GAIN_2 registers

and the OFFSET_0, OFFSET_1, and OFFSET_2 registers.

CHANNEL

REGISTERS

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

CHANNEL_0

CHANNEL_1

CHANNEL_2

CHANNEL_3

CHANNEL_4

CHANNEL_5

CHANNEL_6

CHANNEL_7

CHANNEL_8

CHANNEL_9

CHANNEL_10

CHANNEL_11

CHANNEL_12

CHANNEL_13

CHANNEL_14

CHANNEL_15

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

CONFIGURATION

REGISTERS

FILTER

GAIN

OFFSET

REGISTERS

CONFIG_0

FILTER_0

GAIN_0

OFFSET_0

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

0x28

0x31

0x32

0x33

0x34

0x35

0x36

0x37

0x38

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x30

CONFIG_

1

FILTER_1

FILTER_2

FILTER_3

FILTER_4

FILTER_5

FILTER_6

FILTER_7

GAIN_1

GAIN_2

GAIN_3

GAIN_4

GAIN_5

GAIN_6

GAIN_7

OFFSET_1

OFFSET_2

OFFSET_3

OFFSET_4

OFFSET_5

OFFSET_6

OFFSET_7

CONFIG_

2

CONFIG_3

CONFIG_4

CONFIG_5

CONFIG_6

CONFIG_7

SELECT PERIPHERAL

FUNCTIONS FOR

ADC CHANNEL

SELECT DIGITAL

FILTER TYPE

AND OUTPUT DATA RATE

GAIN CORRECTION

OPTIONALLY

OFFSET CORRECTION

OPTIONALLY PROGRAMMED

PER SETUP AS REQUIRED

PROGRAMMED

PER SETUP AS REQUIRED

4

ANALOG INPUT BUFFERS

REFERENCE BUFFERS

BURNOUT

SINC

0x18

3

SINC

4

1

SELECT ANALOG INPUT PARTS

ENABLE THE CHANNEL

SELECT SETUP

SINC + SINC

3

1

REFERENCE SOURCE

GAIN

SINC + SINC

ENHANCED 50Hz/60Hz REJECTION

Figure 72. Mixed Differential and Single-Ended Configuration Using Multiple Shared Setups

Rev. D | Page 43 of 92

AD7124-8

Data Sheet

ADC CIRCUIT INFORMATION

The channels are configured using the AINP[4:0] bits and the

AINM[4:0] bits in the channel registers (see Table 48). The device

can be configured to have 8 differential inputs, 15 pseudo dif-

ferential inputs, or a combination of both. When using differential

inputs, use adjacent analog input pins to form the input pair. Using

adjacent pins minimizes any mismatch between the channels.

ANALOG INPUT CHANNEL

The AD7124-8 uses flexible multiplexing; thus, any of the analog

input pins, AIN0 to AIN15, can be selected as a positive input

or a negative input. This feature allows the user to perform

diagnostics such as checking that pins are connected. It also

simplifies printed circuit board (PCB) design. For example,

the same PCB can accommodate 2-wire, 3-wire, and 4-wire

resistance temperature detectors (RTDs).

The inputs can be buffered or unbuffered at a gain of 1 but are

automatically buffered when the gain exceeds 1. The AINP and

AINM buffers are enabled/disabled separately using the AIN_BUFP

and AIN_BUFM bits in the configuration register (see Table 49).

In buffered mode, the input channel feeds into a high impedance

input stage of the buffer amplifier. Therefore, the input can tolerate

significant source impedances and is tailored for direct connection

to external resistive type sensors such as strain gages or RTDs.

AV

DD

AIN0

AV

SS

DD

When the device is operated in unbuffered mode, the device has

a higher analog input current. Note that this unbuffered input

path provides a dynamic load to the driving source. Therefore,

resistor/capacitor (RC) combinations on the input pins can

cause gain errors, depending on the output impedance of the

source that is driving the ADC input.

AV

DD

AIN1

BURNOUT

CURRENTS

AV

SS

PGA

TO ADC

DD

The absolute input voltage in unbuffered mode (gain = 1)

includes the range between AV_SS− 50 mV and AV_DD+ 50 mV.

The absolute input voltage range in buffered mode at a gain of 1 is

restricted to a range between AV_SS+ 100 mV and AV_DD− 100 m V.

The common-mode voltage must not exceed these limits;

otherwise, linearity and noise performance degrade.

AIN14

AV

SS

AV

SS

DD

AIN15

When the gain is greater than 1, the analog input buffers are

automatically enabled. The PGA placed in front of the input

buffers is rail-to-rail; thus, in this case, the absolute input voltage

includes the range from AV_SS− 50 mV to AV_DD+ 50 mV.

AV

SS

Figure 73. Analog Input Multiplexer Circuit

Table 48. Channel Register

Reg.

0x09 to CHANNEL_0 to [15:8] Enable

0x18 CHANNEL_15

Name

Bits

Bit 7

Bit 6

AINP[2:0]

Bit 5

Setup

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

AINP[4:3]

Reset

RW

0

0x8001 RW

[7:0]

AINM[4:0]

Table 49. Configuration Register

Reg.

0x19 to CONFIG_0 to [15:8]

0x20 CONFIG_7

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 3

Bit 2

Bit 1

Burnout

Bit 0

Reset

RW

0

Bipolar

REF_BUFP

0x0860 RW

[7:0]

REF_BUFM AIN_BUFP

AIN_BUFM

REF_SEL

PGA

Rev. D | Page 44 of 92

Data Sheet

AD7124-8

6000

5000

4000

3000

2000

1000

0

RC: 100Ω RESISTOR

1µF CAPICITOR

EXTERNAL IMPEDANCE WHEN USING A GAIN OF 1

0.01µF CAPACITOR TO GND

When a gain of 1 is used, the PGA is powered down, reducing

the current consumption. A capacitive network is included at

the PGA output for electromagnetic compatibility (EMC)

purposes. For a gain of 1, this capacitive network is connected

directly to the analog input pins as the PGA is bypassed (see

Figure 76).

RC: 100Ω RESISTOR

0.1µF CAPICITOR

0.01µF CAPICITOR TO GND

RC: 100Ω RESISTOR

0.01µF CAPICITOR

0.01µF CAPICITOR TO GND

Care must be taken when using a gain of 1 with large external

loads in multiplexed applications because the internal capacitive

network disturbs the analog input signal when the channel is

selected. Large external loads affect the initial error on the gain

of 1 channel. The external RC antialiasing filter determines the

recovery time of the channel. When the gain of 1 channel is

selected, the maximum possible error (initial error) is

–1000

1

10

100

1000

10000

SETTLED OUTPUT DATA RATE (sps)

Figure 74. Error vs. Settled Output Data Rate

(100 kΩ Resistors in Attenuator Circuit)

V

_ERROR= C_PAR× (V_{IN_PREV_CH}× GAIN_PREV_CH − V_IN) ÷

(C_PAR+ C_FILT

7000

6000

5000

4000

3000

2000

1000

0

)

(1)

RC: 1kΩ RESISTOR

0.01µF CAPICITOR

0.01µF CAPACITOR TO GND

where:

RC: 1kΩ RESISTOR

0.01µF CAPICITOR

NO CAPICITOR TO GND

C

_PARis the internal capacitance (63 pF due to 10 pF/25 pF

network plus 3 pF of parasitic capacitance).

_FILTis the external filter capacitance on the gain of 1 channel.

_{IN_PREV_CH}is the input voltage of the previous selected channel.

C

V

GAIN_PREV_CH is the gain of the previous selected channel.

If a fast output data rate is selected, the error in the conversion

has a magnitude comparable with Equation 1. For slower output

data rates, the error is reduced as the ADC takes more time to

process the analog input, which allows the front end to settle.

The settling time is dependent on the time constant of the

external antialiasing filter.

–1000

1

10

100

1000

10000

SETTLED OUTPUT DATA RATE (sps)

Figure 75. Error vs. Settled Output Data Rate (47 kΩ Resistors in Attenuator Circuit)

Figure 74 and Figure 75 show the error for different RC filter

combinations on the gain of 1 channel when a resistor

attenuator is connected to the analog input and the ADC is

multiplexed.

Figure 74 and Figure 75 show that, at low output data rates, the

ADC allows sufficient time for the gain of 1 channel to settle for

any external load resistance and RC filter values. At intermediate

output data rates, reducing the values of the external RC compo-

nents reduces the time constant of the external filter so that the

analog input can settle within the allowed time. For high output

data rates, the settling time allowed by the ADC is short; therefore,

a large capacitor from AINP to AINM minimizes the error.

For gains > 1, the PGA is used, which isolates the internal

capacitive network from the analog input pins. Therefore, for

gains > 1, there are no restrictions on the external circuitry.

ATTENUATOR RC ANTIALIASING

CIRCUIT

FILTER

AD7124-8

BUFFER

AVSS

10pF

AINP

AINM

PGA2

25pF

10pF

ADC

AVSS

BUFFER

Figure 76. Input Schematic

Rev. D | Page 45 of 92

AD7124-8

Data Sheet

pin. A 0.1 µF decoupling capacitor is required on REFOUT

when the internal reference is active.

PROGRAMMABLE GAIN ARRAY (PGA)

When the gain stage is enabled, the output from the multiplexer

is applied to the input of the PGA. The presence of the PGA means

that signals of small amplitude can be gained within the

AD7124-8 and still maintain excellent noise performance.

The common-mode range for the differential reference inputs is

from AV_SS− 50 mV to AV_DD+ 50 mV when the reference buffers

are disabled. The reference inputs can also be buffered on-chip.

The buffers require 100 mV of headroom. The reference voltage

of REFIN (REFINx(+) − REFINx(−)) is 2.5 V nominal, but the

AD7124-8 is functional with reference voltages from 1 V to AV_DD.

BUF

24-BIT

Σ-Δ ADC

PGA1

PGA2

In applications where the excitation (voltage or current) for the

transducer on the analog input also drives the reference voltage

for the devices, the effect of the low frequency noise in the excita-

tion source is removed, because the application is ratiometric. If

the AD7124-8 is used in nonratiometric applications, use a low

noise reference.

BUF

ANALOG

BUFFERS

Figure 77. PGA

The AD7124-8 can be programmed to have a gain of 1, 2, 4, 8,

16, 32, 64, or 128 by using the PGA bits in the configuration

register (see Table 49). The PGA consists of two stages. For a

gain of 1, both stages are bypassed. For gains of 2 to 8, a single

stage is used, whereas for gains greater than 8, both stages are used.

The recommended 2.5 V reference voltage sources for the AD7124-8

include the ADR4525, which is a low noise, low power reference.

Note that the reference input provides a high impedance, dynamic

load when unbuffered. Because the input impedance of each

reference input is dynamic, resistor/capacitor combinations on

these inputs can cause dc gain errors if the reference inputs are

unbuffered, depending on the output impedance of the source

driving the reference inputs.

The analog input range is V_REF/gain. Therefore, with an external

2.5 V reference, the unipolar ranges are from 0 mV to 19.53 mV

to 0 V to 2.5 V, and the bipolar ranges are from 19.53 mV to

2.5 V. For high reference values, for example, V_REF= AV_DD, the

analog input range must be limited. Consult the Specifications

section for more details on these limits.

Reference voltage sources typically have low output impedances

and are, therefore, tolerant to having decoupling capacitors on

REFINx(+) without introducing gain errors in the system. Deriving

the reference input voltage across an external resistor means that

the reference input sees a significant external source impedance.

In this situation, using the reference buffers is required.

3V

REFERENCE

The AD7124-8 has an embedded 2.5 V reference. The embedded

reference is a low noise, low drift reference with 15 ppm/°C drift

maximum. Including the reference on the AD7124-8 reduces

the number of external components needed in applications such

as thermocouples, leading to a reduced PCB size.

ADR4525

REFINx(+)

REFINx(–)

2.5V REF

4.7µF

0.1µF

1µF

4.7µF

REFIN1(+)

REFIN1(–)

REFOUT

BAND GAP

REF

REFIN2(+)

REFIN2(–)

AV

DD

Figure 79. ADR4525 to AD7124-8 Connections

AV

SS

BIPOLAR/UNIPOLAR CONFIGURATION

The analog input to the AD7124-8 can accept either unipolar or

bipolar input voltage ranges, which allows the user to tune the

ADC input range to the sensor output range. When a split

power supply is used, the device accepts truly bipolar inputs.

When a single power supply is used, a bipolar input range does

not imply that the device can tolerate negative voltages with

respect to system AV_SS. Unipolar and bipolar signals on the

AINP input are referenced to the voltage on the AINM input.

For example, if AINM is 1.5 V and the ADC is configured for

unipolar mode with a gain of 1, the input voltage range on the

AINP input is 1.5 V to 3 V when V_REF= AV_DD= 3 V. If the ADC

is configured for bipolar mode, the analog input range on the

AINP input is 0 V to AV_DD. The bipolar/unipolar option is chosen

by programming the bipolar bit in the configuration register.

REFERENCE

BUFFERS

24-BIT

Σ-Δ ADC

Figure 78. Reference Connections

This reference can be used to supply the ADC (by setting the

REF_EN bit in the ADC_CONTROL register to 1) or an external

reference can be applied. For external references, the ADC has a

fully differential input capability for the channel. In addition,

the user can select one of two external reference options (REFIN1

or REFIN2). The reference source for the AD7124-8 is selected

using the REF_SEL bits in the configuration register (see Table 49).

When the internal reference is selected, it is internally connected

to the modulator. It can also be made available on the REFOUT

Rev. D | Page 46 of 92

Data Sheet

AD7124-8

IOUT0 IOUT1

DATA OUTPUT CODING

VBIAS

When the ADC is configured for unipolar operation, the output

code is natural (straight) binary with a zero differential input

voltage resulting in a code of 00 … 00, a midscale voltage resulting

in a code of 100 … 000, and a full-scale input voltage resulting

in a code of 111 … 111. The output code for any analog input

voltage can be represented as

AV

DD

AIN0

SS

VBIAS

Code = (2^N× A_IN× Gain)/V_REF

AV

DD

AV

When the ADC is configured for bipolar operation, the output

code is offset binary with a negative full-scale voltage resulting

in a code of 000 … 000, a zero differential input voltage resulting

in a code of 100 … 000, and a positive full-scale input voltage

resulting in a code of 111 … 111. The output code for any

analog input voltage can be represented as

DD

AIN1

BURNOUT

CURRENTS

SS

PGA

TO ADC

Code = 2^{N − 1}× [(A_IN× Gain/V_REF) + 1]

AV

SS

where:

VBIAS

N = 24.

AV

DD

A_INis the analog input voltage.

Gain is the gain setting (1 to 128).

AIN15

EXCITATION CURRENTS

SS

The AD7124-8 also contains two matched, software configurable,

constant current sources that can be programmed to equal 50 µA,

100 µA, 250 µA, 500 µA, 750 µA, or 1 mA. These current sources

can be used to excite external resistive bridges or RTD sensors.

Both current sources source currents from AV_DDand can be

directed to any of the analog input pins (see Figure 80).

Figure 80. Excitation Current and Bias Voltage Connections

BRIDGE POWER-DOWN SWITCH

In bridge applications such as strain gages and load cells, the

bridge itself consumes the majority of the current in the system.

For example, a 350 Ω load cell requires 8.6 mA of current when

excited with a 3 V supply. To minimize the current consumption of

the system, the bridge can be disconnected (when it is not being

used) using the bridge power-down switch. The switch can with-

stand 30 mA of continuous current, and it has an on resistance

of 10 Ω maximum. The PDSW bit in the IO_CONTROL_1

register controls the switch.

The pins on which the currents are made available are programmed

using the IOUT1_CH and IOUT0_CH bits in the IO_CONTROL_1

register (see Table 50). The magnitude of each current source is

individually programmable using the IOUT1 and IOUT0 bits in

the IO_CONTROL_1 register. In addition, both currents can be

output to the same analog input pin.

LOGIC OUTPUTS

Note that the on-chip reference does not need to be enabled

when using the excitation currents.

The AD7124-8 has four general-purpose digital outputs: P1

to P4. These are enabled using the GPIO_CTRL bits in the

IO_CONTROL_1 register (see Table 50). The pins can be

pulled high or low using the GPIO_DATx bits in the register;

that is, the value at the pin is determined by the setting of the

GPIO_DATx bits. The logic levels for these pins are determined

by AV_DDrather than by IOV_DD. When the IO_CONTROL_1

register is read, the GPIO_DATx bits reflect the actual value at

the pins; this is useful for short-circuit detection.

Table 50. Input/Output Control 1 Register

Reg.

Name

Bits

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0x03

IO_

CONTROL_

1

[23:16]

[15:8]

[7:0]

GPIO_DAT4

PDSW

GPIO_DAT3

0

GPIO_DAT2

GPIO_DAT1

IOUT1

GPIO_CTRL4

GPIO_CTRL3

GPIO_CTRL2

IOUT0

GPIO_CTRL1

0x000000

RW

IOUT1_CH

IOUT0_CH

Rev. D | Page 47 of 92

AD7124-8

Data Sheet

These pins can be used to drive external circuitry, for example,

an external multiplexer. If an external multiplexer is used to

increase the channel count, the multiplexer logic pins can be

controlled via the AD7124-8 general-purpose output pins. The

general-purpose output pins can be used to select the active

multiplexer pin. Because the operation of the multiplexer is

independent of the AD7124-8, reset the modulator and filter

the division factor being dependent on the power mode. Thus,

the range of output data rates and performance is affected by

the power mode.

Table 51. Power Modes

Power

Mode

Master Clock Output Data

(kHz)

614.4

153.6

76.8

Rate¹(SPS)

9.37 to 19,200

2.34 to 4800

1.17 to 2400

Current

Full Power

Mid Power

Low Power

See the

Specifications

section

SYNC

using the

pin or by writing to the mode or configuration

register each time that the multiplexer channel is changed.

BIAS VOLTAGE GENERATOR

¹Unsettled, using a sinc³/sinc⁴filter.

A bias voltage generator is included on the AD7124-8 (see

Figure 80). It biases the negative terminal of the selected input

channel to (AV_DD− AV_SS)/2. This function is useful in thermocou-

ple applications, as the voltage generated by the thermocouple

must be biased around some dc voltage if the ADC operates from a

single power supply. The bias voltage generator is controlled using

the VBIASx bits in the IO_CONTROL_2 register (see Table 52).

The power-up time of the bias voltage generator is dependent

on the load capacitance. Consult the Specifications section for

more details.

STANDBY AND POWER-DOWN MODES

In standby mode, most blocks are powered down. The LDOs

remain active so that registers maintain their contents. If

enabled, the reference, internal oscillator, digital outputs P1 to

P4, the bias voltage generator, and the low-side power switch

remain active. These blocks can be disabled also, if required, by

setting the corresponding bits appropriately. The excitation

currents, reference detection, and LDO capacitor detection

functions are disabled in standby mode.

Other diagnostics remain active if enabled when the ADC is in

standby mode. Diagnostics can be enabled or disabled while in

standby mode. However, any diagnostics that require the master

clock (undervoltage/overvoltage detection, LDO trip tests,

memory map CRC, and MCLK counter) must be enabled when

the ADC is in continuous conversion mode or idle mode; these

diagnostics do not function if enabled in standby mode.

CLOCK

The AD7124-8 includes an internal 614.4 kHz clock on chip.

This internal clock has a tolerance of 5%. Use either the

internal clock or an external clock as the clock source to the

AD7124-8. The clock source is selected using the CLK_SEL bits

in the ADC_CONTROL register (see Table 53).

The internal clock can also be made available at the CLK pin. This

is useful when several ADCs are used in an application and the

devices must be synchronized. The internal clock from one device

can be used as the clock source for all ADCs in the system. Using a

common clock, the devices can be synchronized by applying a

The standby current is typically 15 µA when the LDOs only are

enabled. If functions such as the bias voltage generator remain

active in standby mode, the current increases by 36 µA typically.

If the internal oscillator remains active in standby mode, the

current increases by 22 µA typically. When exiting standby

mode, the AD7124-8 requires 130 MCLK cycles to power up

and settle. The internal oscillator, if disabled in standby mode,

requires an additional 40 µs to power up and settle. If an external

master clock is being used, ensure that it is active before issuing

the command to exit standby mode. Do not write to the ADC_

CONTROL register again until the ADC has powered up and

settled.

SYNC

common reset to all devices, or the

pin can be pulsed.

POWER MODES

The AD7124-8 has three power modes: full power mode, mid

power mode, and low power mode. The mode is selected using

the POWER_MODE bits in the ADC_CONTROL register. The

power mode affects the power consumption of the device as

well as changing the master clock frequency. A 614.4 kHz clock

is used by the device. However, this clock is internally divided,

Table 52. Input/Output Control 2 Register

Reg. Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0x04 IO_CONTROL_2 VBIAS15

VBIAS7

VBIAS14

VBIAS6

VBIAS13

VBIAS5

VBIAS12

VBIAS4

VBIAS11

VBIAS3

VBIAS10

VBIAS2

VBIAS9

VBIAS1

VBIAS8

VBIAS0

0x0000 RW

Table 53. ADC Control Register

Reg.

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

RW

0x01

ADC_CONTROL

0

DOUT_

CONT_READ DATA_STATUS CS

_EN

REF_EN

0x0000 RW

RDY

_DEL

POWER_MODE

Mode

CLK_SEL

Rev. D | Page 48 of 92

Data Sheet

AD7124-8

In power-down mode, all blocks are powered down, including

the LDOs. All registers lose their contents, and the digital outputs

P1 to P4 are placed in tristate. To prevent accidental entry to

power-down mode, the ADC must first be placed into standby

mode. If an external master clock is being used, keep it active

until the device is placed in power-down mode. Exiting power-

before the next output update occurs. In continuous read mode,

the data register can be read only once.

CS

The serial interface can operate in 3-wire mode by tying

low.

RDY

In this case, the SCLK, DIN, and DOUT/

with the AD7124-8. The end of the conversion can be monitored

RDY

lines communicate

using the

bit in the status register. This scheme is suitable

CS

down mode requires 64 SCLK cycles with

= 0 and DIN = 1,

CS

for interfacing to microcontrollers. If is required as a decoding

signal, it can be generated from a port pin. For microcontroller

interfaces, it is recommended that SCLK idle high between data

transfers.

that is, a serial interface reset. The AD7124-8 requires 2 ms

typically to power up and settle. The POR_FLAG in the status

register can be monitored to determine the end of the power

up/settling period. After this time, the user can access the on-chip

registers. The power-down current is 2 µA typically.

CS

The AD7124-8 can be operated with

synchronization signal. This scheme is useful for DSP interfaces.

CS

being used as a frame

DIGITAL INTERFACE

In this case, the first bit (MSB) is effectively clocked out by

CS

,

The programmable functions of the AD7124-8 are controlled

using a set of on-chip registers. Data is written to these registers

via the serial interface. Read access to the on-chip registers is

also provided by this interface. All communications with the

device must start with a write to the communications register.

After power-on or reset, the device expects a write to its

communications register. The data written to this register

determines whether the next operation is a read operation or a

write operation, and determines to which register this read or

write operation occurs. Therefore, write access to any of the

other registers on the devices begins with a write operation to

the communications register, followed by a write to the selected

register. A read operation from any other register (except when

continuous read mode is selected) starts with a write to the

communications register, followed by a read operation from the

selected register.

because

normally occurs after the falling edge of SCLK in

DSPs. SCLK can continue to run between data transfers,

provided the timing numbers are obeyed.

CS

must be used to frame read and write operations and the

_EN bit in the ADC_CONTROL register must be set when

the diagnostics SPI_READ_ERR, SPI_WRITE_ERR, or

SPI_SCLK_CNT_ERR are enabled.

The serial interface can be reset by writing a series of 1s on the

DIN input. See the Reset section for more details. Reset returns

the interface to the state in which it is expecting a write to the

communications register

The AD7124-8 can be configured to continuously convert or

perform a single conversion (see Figure 81 through Figure 83).

Single Conversion Mode

In single conversion mode, the AD7124-8 performs a single

conversion and is placed in standby mode after the conversion

is complete. If a master clock is present (external master clock

CS

The serial interface of the AD7124-8 consists of four signals:

RDY

,

DIN, SCLK, and DOUT/

the on-chip registers, whereas DOUT/

the on-chip registers. SCLK is the serial clock input for the

RDY

. The DIN line transfers data into

RDY

accesses data from

RDY

or the internal oscillator is enabled), DOUT/

goes low to

indicate the completion of a conversion. When the data-word is

RDY

device, and all data transfers (either on DIN or DOUT/

RDY

)

read from the data register, DOUT/

register can be read several times, if required, even when

RDY

goes high. The data

occur with respect to the SCLK signal. The DOUT/

also operates as a data ready signal; the line goes low when a

DOUT/

is high. Do not read the ADC_CONTROL register

new data-word is available in the output register. It is reset high

when a read operation from the data register is complete. It also

goes high before the data register updates to indicate when not

to read from the device, to ensure that a data read is not attempted

close to the completion of a conversion because the mode bits are

being updated by the ADC to indicate that the ADC is in standby

mode.

CS

while the register is being updated.

is used to select a device.

If several channels are enabled, the ADC automatically sequences

through the enabled channels and performs a conversion on

It can decode the AD7124-8 in systems where several components

are connected to the serial bus.

RDY

each channel. When a conversion is started, DOUT/

goes

high and remains high until a valid conversion is available and

CS RDY

Figure 3 and Figure 4 show timing diagrams for interfacing to the

is low. As soon as the conversion is available, DOUT/

CS

AD7124-8 with decoding the devices. Figure 3 shows the timing

goes low. The ADC then selects the next channel and begins a

conversion. The user can read the present conversion while the

next conversion is being performed. As soon as the next conver-

sion is complete, the data register is updated; therefore, the user

has a limited period in which to read the conversion. When the

ADC has performed a single conversion on each of the selected

channels, it returns to standby mode.

for a read operation from the output shift register of the AD7124-8.

Figure 4 shows the timing for a write operation to the input

shift register. A delay is required between consecutive SPI

communications. Figure 5 shows the delay required between SPI

read/write operations. It is possible to read the same word from

RDY

the data register several times, even though the DOUT/

line returns high after the first read operation. However, care

must be taken to ensure that the read operations are complete

Rev. D | Page 49 of 92

AD7124-8

Data Sheet

If the DATA_STATUS bit in the ADC_CONTROL register is set

to 1, the contents of the status register are output along with the

conversion each time that the data read is performed. The four

LSBs of the status register indicate the channel to which the conver-

sion corresponds.

When several channels are enabled, the ADC automatically

sequences through the enabled channels, performing one

conversion on each channel. When all channels are converted,

the sequence starts again with the first channel. The channels

are converted in order from lowest enabled channel to highest

enabled channel. The data register is updated as soon as each

Continuous Conversion Mode

RDY

conversion is available. The DOUT/

pin pulses low each

Continuous conversion is the default power-up mode. The

time a conversion is available. The user can then read the

conversion while the ADC converts the next enabled channel.

RDY

AD7124-8 converts continuously, and the

register goes low each time a conversion is complete. If

RDY

bit in the status

CS

is low,

line also goes low when a conversion is complete.

If the DATA_STATUS bit in the ADC_CONTROL register is set

to 1, the contents of the status register, along with the conversion

data, are output each time the data register is read. The status

register indicates the channel to which the conversion corresponds.

the DOUT/

To read a conversion, write to the communications register,

indicating that the next operation is a read of the data register.

RDY

When the data-word is read from the data register, DOUT/

goes high. The user can read this register additional times, if

required. However, the user must ensure that the data register is

not being accessed at the completion of the next conversion;

otherwise the new conversion word is lost.

CS

0x01

0x0004

0x42

DIN

DATA

DOUT/RDY

SCLK

Figure 81. Single Conversion Configuration

CS

DIN

0x42

DOUT/RDY

DATA

SCLK

Figure 82. Continuous Conversion Configuration

CS

0x01

0x0800

DIN

DOUT/RDY

DATA

SCLK

Figure 83. Continuous Read Configuration

Rev. D | Page 50 of 92

Data Sheet

AD7124-8

Continuous Read Mode

CS

By setting the _EN bit in the ADC_CONTROL register to 1, the

RDY

DOUT/

pin continues to output the LSB of the register

In continuous read mode, it is not required to write to the

communications register before reading ADC data; apply the

RDY

CS

being read until

CS

is taken high. This configuration is useful if

CS

the

signal is used to frame all read operations. If

CS

is not

required number of SCLKs after DOUT/

goes low to

indicate the end of a conversion. When the conversion is read,

RDY

used to frame all read operations, set _EN to 0 so that

DOUT/

returns high until the next conversion is available.

RDY

DOUT/

edge in the read operation.

CS

changes functionality following the last SCLK

In this mode, the data can be read only once. Ensure that the data-

word is read before the next conversion is complete. If the user

has not read the conversion before the completion of the next

conversion, or if insufficient serial clocks are applied to the

AD7124-8 to read the word, the serial output register is reset

when the next conversion is complete, and the new conversion

is placed in the output serial register. The ADC must be configured

for continuous conversion mode to use continuous read mode.

CS

_EN must be set to 1 and the signal must be used to frame all

read and write operations when the SPI_READ_ERR,

SPI_WRITE_ERR, and SPI_SCLK_CNT_ERR diagnostic

functions are enabled.

CS

The serial interface is always reset on the

rising edge, that is,

the interface is reset to a known state whereby it awaits a write

to the communications register. Therefore, if a read or write

operation is performed by performing multiple 8- bit data

To enable continuous read mode, set the CONT_READ bit in

the ADC_CONTROL register. When this bit is set, the only serial

interface operations possible are reads from the data register. To

exit continuous read mode, write a read data command (0x42)

CS

transfers,

must be held low until the all bits are transferred.

RESET

RDY

while the DOUT/

pin is low. Alternatively, apply a software

CS

The circuitry and serial interface of the AD7124-8 can be reset

by writing 64 consecutive 1s to the device. This resets the logic,

the digital filter, and the analog modulator, and all on-chip

registers are reset to their default values. A reset is automatically

performed on power-up. A reset requires a time of 90 MCLK

cycles. The POR_FLAG bit in the status register is set to 1 when

the reset is initiated and then is set to 0 when the reset is complete.

A reset is useful if the serial interface becomes asynchronous

due to noise on the SCLK line.

reset, that is, 64 SCLKs with

= 0 and DIN = 1. This resets the

ADC and all register contents. These are the only commands

that the interface recognizes after it is placed in continuous read

mode. DIN must be held low in continuous read mode until an

instruction is to be written to the device.

If multiple ADC channels are enabled, each channel is output in

turn, with the status bits being appended to the data if DATA_

STATUS is set in the ADC_CONTROL register. The status

register indicates the channel to which the conversion corresponds.

CALIBRATION

DATA_STATUS

The AD7124-8 provides four calibration modes that can be

used to eliminate the offset and gain errors on a per setup basis:

The contents of the status register can be appended to each

conversion on the AD7124-8. This is a useful function if several

channels are enabled. Each time a conversion is output, the

contents of the status register are appended. The four LSBs of

the status register indicate to which channel the conversion

corresponds. In addition, the user can determine if any errors

are being flagged via the ERROR_FLAG bit. To append the status

register contents to every conversion, the DATA_STATUS bit in

the ADC_CONTROL register is set to 1.

•

Internal zero-scale calibration mode

Internal full-scale calibration mode

System zero-scale calibration mode

System full-scale calibration mode

Only one channel can be active during calibration. After each

conversion, the ADC conversion result is scaled using the ADC

calibration registers before being written to the data register.

The default value of the offset register is 0x800000, and the nominal

value of the gain register is 0x5XXXXX. The calibration range

of the ADC gain is from 0.4 × V_REF/gain to 1.05 × V_REF/gain.

SERIAL INTERFACE RESET (DOUT_RDY_DEL AND

CS_EN BITS)

RDY

The instant at which the DOUT/

pin changes from being a

pin is programmable on the AD7124-8. By

RDY

The following equations show the calculations that are used in

each calibration mode. In unipolar mode, the ideal

relationship—that is, not taking into account the ADC gain

error and offset error—is as follows:

RDY

default, the DOUT/

DOUT pin to a

pin changes functionality after a period of

time following the last SCLK rising edge, the SCLK edge on which

the LSB is read by the processor. This time is 10 ns minimum by

RDY





0.75×V_IN

V_REF

default and, by setting the DOUT_

_DEL bit in the ADC_





Data =

×2²³− (Offset − 0x800000) ×



CONTROL register to 1, can be extended to 110 ns minimum.





Gain

×2

0x400000

Rev. D | Page 51 of 92

AD7124-8

Data Sheet

In bipolar mode, the ideal relationship—that is, not taking into

account the ADC gain error and offset error—is as follows:

Offset and system full-scale calibrations can be performed in

any power mode. Internal full-scale calibrations can be performed

in the low power or mid power modes only. Thus, when using

full power mode, the user must select mid or low power mode

to perform the internal full-scale calibration. However, an internal

full-scale calibration performed in low or mid power mode is

valid in full power mode, if the same gain is used.





0.75×V_IN

V_REF





Data =

×2²³− (Offset − 0x800000) ×







Gain

+ 0x800000

0x400000

The offset error is typically 15 µV for gains of 1 to 8 and

200/gainµV for higher output data rates. An internal or system

offset calibration reduces the offset error to the order of the

noise. The gain error is factory calibrated at ambient temperature

and at a gain of 1. Following this calibration, the gain error is

0.0025% maximum. Therefore, internal full-scale calibrations

at a gain of 1 are not supported on the AD7124-8. For other

gains, the gain error is −0.3%. An internal full-scale calibration at

ambient temperature reduces the gain error to 0.016%

maximum for gains of 2 to 8 and 0.025% typically for higher

gains. A system full-scale calibration reduces the gain error to the

order of the noise.

To start a calibration, write the relevant value to the mode bits

RDY

in the ADC_CONTROL register. The DOUT/

pin and the

bit in the status register go high when the calibration

initiates. When the calibration is complete, the contents of the

RDY

corresponding offset or gain register are updated, the

bit

pin returns low (if

is low), and the AD7124-8 reverts to idle mode.

RDY

in the status register is reset, the DOUT/

CS

During an internal offset calibration, the selected positive

analog input pin is disconnected, and it is connected internally

to the selected negative analog input pin. For this reason, it is

necessary to ensure that the voltage on the selected negative

analog input pin does not exceed the allowed limits and is free

from excessive noise and interference.

The AD7124-8 provides the user with access to the on-chip

calibration registers, allowing the microprocessor to read the

calibration coefficients of the device and to write its own

calibration coefficients from prestored values in the EEPROM.

A read or write of the offset and gain registers can be performed

at any time except during an internal or self-calibration. The

values in the calibration registers are 24 bits wide. The span and

offset of the device can also be manipulated using the registers.

To perform an internal full-scale calibration, a full-scale input

voltage is automatically connected to the selected analog input

for this calibration. A full-scale calibration is recommended

each time the gain of a channel is changed to minimize the full-

scale error. When performing internal calibrations, the internal

full-scale calibration must be performed before the internal

zero-scale calibration. Therefore, write the value 0x800000 to

the offset register before performing the internal full-scale

calibration, which ensures that the offset register is at its default

value.

SPAN AND OFFSET LIMITS

Whenever a system calibration mode is used, the amount of

offset and span that can be accommodated is limited. The

overriding requirement in determining the amount of offset

and gain that can be accommodated by the device is the

requirement that the positive full-scale calibration limit is

≤1.05 × V_REF/gain. This allows the input range to go 5% above

the nominal range. The built-in headroom in the AD7124-8

analog modulator ensures that the device still operates correctly

with a positive full-scale voltage, which is 5% beyond the nominal.

System calibrations expect the system zero-scale (offset) and

system full-scale (gain) voltages to be applied to the ADC pins

before initiating the calibration modes. As a result, errors

external to the ADC are removed. The system zero-scale

calibration must be performed before the system full-scale

calibration.

From an operational point of view, treat a calibration like

another ADC conversion. Set the system software to monitor

The range of input span in both the unipolar and bipolar modes

has a minimum value of 0.8 × V_REF/gain and a maximum value

of 2.1 × V_REF/gain. However, the span, which is the difference

between the bottom of the AD7124-8 input range and the top of

its input range, must account for the limitation on the positive

full-scale voltage. The amount of offset that can be accommodated

depends on whether the unipolar or bipolar mode is being used.

The offset must account for the limitation on the positive full-

scale voltage. In unipolar mode, there is considerable flexibility in

handling negative (with respect to AINM) offsets. In both

unipolar and bipolar modes, the range of positive offsets that

can be handled by the device depends on the selected span.

Therefore, in determining the limits for system zero-scale and

full-scale calibrations, the user must ensure that the offset range

plus the span range does exceed 1.05 × V_REF/gain. This is best

illustrated by looking at a few examples.

RDY

the

bit in the status register or the DOUT/

pin to

determine the end of a calibration via a polling sequence or an

interrupt-driven routine.

An internal/system offset calibration and system full-scale

calibration requires a time equal to the settling time of the

selected filter to be completed. The internal full-scale

calibration requires a time equal to one settling period for a

gain of 1 and a time of four settling periods for gains greater

than 1.

A calibration can be performed at any output data rate. Using

lower output data rates results in better calibration accuracy and

is accurate for all output data rates. A new calibration is required

for a given channel if the reference source or the gain for that

channel is changed.

Rev. D | Page 52 of 92

Data Sheet

AD7124-8

If the device is used in unipolar mode with a required span of

0.8 × V_REF/gain, the offset range that the system calibration can

handle is from −1.05 × V_REF/gain to +0.25 × V_REF/gain. If the

device is used in unipolar mode with a required span of

SYNC

the

pin is low, the AD7124-8 is maintained in this state. On

SYNC

rising edge, the modulator and filter exit this reset

state and, on the next clock edge, the device starts to gather

input samples again. In a system using multiple AD7124-8

devices, a common signal to their

operation. This is normally performed after each AD7124-8 has

performed its own calibration or has calibration coefficients

loaded into its calibration registers. The conversions from the

AD7124-8 devices are then synchronized.

V_REF/gain, the offset range that the system calibration can

SYNC

pins synchronizes their

handle is from −1.05 × V_REF/gain to +0.05 × V_REF/gain. Similarly,

if the device is used in unipolar mode and required to remove

an offset of 0.2× V_REF/gain, the span range that the system

calibration can handle is 0.85 × V_REF/gain.

If the device is used in bipolar mode with a required span of

0.4 × V_REF/gain, then the offset range that the system

calibration can handle is from −0.65 × V_REF/gain to +0.65 ×

The device exits reset on the master clock falling edge following

SYNC

the

devices are being synchronized, pull the

master clock rising edge to ensure that all devices begin

SYNC

low to high transition. Therefore, when multiple

SYNC

pin high on the

V_REF/gain. If the device is used in bipolar mode with a required

span of V_REF/gain, the offset range the system calibration can

handle is from −0.05 × V_REF/gain to +0.05 × V_REF/gain.

Similarly, if the device is used in bipolar mode and required to

remove an offset of 0.2 × V_REF/gain, the span range that the

system calibration can handle is 0.85 × V_REF/gain.

sampling on the master clock falling edge. If the

pin is

not taken high in sufficient time, it is possible to have a

difference of one master clock cycle between the devices; that is,

the instant at which conversions are available differs from

device to device by a maximum of one master clock cycle.

SYSTEM SYNCHRONIZATION

SYNC

The

In this mode, the rising edge of

RDY

pin can also be used as a start conversion command.

SYNC

The

input allows the user to reset the modulator and the

SYNC

starts conversion and the

indicates when the conversion is complete.

digital filter without affecting any of the setup conditions on the

device. This allows the user to start gathering samples of the

analog input from a known point in time, that is, the rising edge

falling edge of

The settling time of the filter must be allowed for each data

register update. For example, if the ADC is configured to use

the sinc⁴filter and zero latency is disabled, the settling time

equals 4/f_ADCwhere f_ADCis the output data rate when

continuously converting on a single channel.

SYNC

of

. Take

low for at least four master clock cycles to

implement the synchronization function.

If multiple AD7124-8 devices are operated from a common

master clock, they can be synchronized so that their data

registers are updated simultaneously. A falling edge on the

SYNC

pin resets the digital filter and the analog modulator and

places the AD7124-8 into a consistent, known state. While the

Rev. D | Page 53 of 92

AD7124-8

Data Sheet

DIGITAL FILTER

Table 54. Filter Registers

Reg.

Name

Bit 7

Bit 6

Filter

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

0x060180

RW

0x21 to

0x28

FILTER_0 to

FILTER_7

REJ60

POST_FILTER

SINGLE_CYCLE

RW

0

FS[10:8]

FS[7:0]

The AD7124-8 offers a great deal of flexibility in the digital

filter. The device has several filter options. The option selected

affects the output data rate, settling time, and 50 Hz and 60 Hz

rejection. The following sections describe each filter type,

indicating the available output data rates for each filter option.

The filter response along with the settling time and 50 Hz and

60 Hz rejection is also discussed.

When a channel change occurs, the modulator and filter are

reset. The settling time is allowed to generate the first

conversion after the channel change. Subsequent conversions on

this channel occur at 1/f_ADC

.

CHANNEL B

CHANNEL

CHANNEL A

CONVERSIONS CH A CH A CH A

CH B CH B CH B

1/f

DT/f_CLK

ADC

NOTES

1. DT = DEAD TIME.

The filter bits in the filter register select between the sinc type filter.

Figure 85. Sinc⁴Channel Change

SINC⁴FILTER

When the AD7124-8 is powered up, the sinc⁴filter is selected by

default. This filter gives excellent noise performance over the

complete range of output data rates. It also gives the best 50 Hz/

60 Hz rejection, but it has a long settling time. In Figure 84, the

blocks shown in gray are unused.

When conversions are performed on a single channel and a

step change occurs, the ADC does not detect the change in the

analog input. Therefore, it continues to output conversions

at the programmed output data rate. However, it is at least four

conversions later before the output data accurately reflects the

analog input. If the step change occurs while the ADC is

processing a conversion, then the ADC takes five conversions

after the step change to generate a fully settled result.

POST

FILTER

3

4

SINC /SINC

MODULATOR

FILTER

ANALOG

INPUT

AVERAGING

BLOCK

FULLY

SETTLED

Figure 84. Sinc⁴Filter

ADC

OUTPUT

Sinc⁴Output Data Rate/Settling Time

The output data rate (the rate at which conversions are available

on a single channel when the ADC is continuously converting)

is equal to

1/f

ADC

Figure 86. Asynchronous Step Change in the Analog Input

The 3 dB frequency for the sinc⁴filter is equal to

f

_ADC= f_CLK/(32 × FS[10:0])

where:

_ADCis the output data rate.

_CLKis the master clock frequency (614.4 kHz in full power mode,

f

_3dB= 0.23 × f_ADC

Table 55 gives some examples of the relationship between the

values in the FS[10:0] bits and the corresponding output data

rate and settling time.

f

153.6 kHz in mid power mode, and 76.8 kHz in low power mode).

FS[10:0] is the decimal equivalent of the FS[10:0] bits in the

filter register. FS[10:0] can have a value from 1 to 2047.

Table 55. Examples of Output Data Rates and the

Corresponding Settling Times for the Sinc⁴Filter

The output data rate can be programmed from

Output Data

Rate (SPS)

Settling

Time (ms)

Power Mode

FS[10:0]

1920

384

320

480

96

•

9.38 SPS to 19,200 SPS for full power mode

2.35 SPS to 4800 SPS for mid power mode

1.17 SPS to 2400 SPS for low power mode

Full Power (f_CLK

614.4 kHz)

=

10

50

60

10

50

60

10

50

60

400.15

80.15

66.82

400.61

80.61

67.28

401.22

81.22

67.89

The settling time for the sinc⁴filter is equal to

_SETTLE= (4 × 32 × FS[10:0] + Dead Time)/f_CLK

Mid Power (f_CLK

153.6 kHz)

t

80

where Dead Time = 61 when FS[10:0] = 1 and 95 when

FS[10:0] > 1

Low Power (f_CLK

76.8 kHz)

=

240

48

40

Rev. D | Page 54 of 92

Data Sheet

AD7124-8

Sinc⁴Zero Latency

When the analog input is constant or a channel change occurs,

valid conversions are available at a near constant output data

rate. When conversions are being performed on a single

channel and a step change occurs on the analog input, the ADC

continues to output fully settled conversions if the step change is

synchronized with the conversion process. If the step change is

asynchronous, one conversion is output from the ADC, which is

not completely settled (see Figure 87).

Zero latency is enabled by setting the SINGLE_CYCLE bit in

the filter register to 1. With zero latency, the conversion time

when continuously converting on a single channel approximately

equals the settling time. The benefit of this mode is that a similar

period of time elapses between all conversions irrespective of

whether the conversions occur on one channel or whether several

channels are used. When the analog input is continuously sampled

on a single channel, the output data rate equals

ANALOG

INPUT

FULLY

SETTLED

f

_ADC= f_CLK/(4 × 32 × FS[10:0])

ADC

OUTPUT

where:

f

_ADCis the output data rate.

_CLKis the master clock frequency.

1/f_ADC

FS[10:0] is the decimal equivalent of the FS[10:0] bits in the

setup filter register.

Figure 87. Sinc⁴Zero Latency Operation

Sequencer

When the user selects another channel, there is an extra delay in

the first conversion of

The description in the Sinc4 Filter section is valid when

manually switching channels, for example, writing to the device

to change channels. When multiple channels are enabled, the

on-chip sequencer is automatically used; the device

automatically sequences between all enabled channels. In this

case, the first conversion takes the complete settling time as

listed in Table 55. For all subsequent conversions, the time

needed for each conversion is the settling time also, but the

dead time is reduced to 30.

Dead Time/f_CLK

where Dead Time = 61 when FS[10:0] = 1 and 95 when

FS[10:0] > 1.

At low output data rates, this extra delay has little impact on the

value of the settling time. However, at high output data rates, the

delay must be considered. Table 56 summarizes the output data

rate when continuously converting on a single channel and the

settling time when switching between channels for a sample of

FS[10:0] values.

Sinc⁴50 Hz and 60 Hz Rejection

Figure 88 shows the frequency response of the sinc⁴filter when

the output data rate is programmed to 50 SPS and zero latency

is disabled. For the same configuration but with zero latency

When switching between channels, the AD7124-8 allows the

complete settling time to generate the first conversion after the

channel change. Therefore, the ADC automatically operates in

zero latency mode when several channels are enabled—setting

the SINGLE_CYCLE bit has no benefits.

enabled, the filter response remains the same but the output data

rate is 12.5 SPS. The sinc⁴filter provides 50 Hz ( 1 Hz) rejection in

excess of 120 dB minimum, assuming a stable master clock.

0

Table 56. Examples of Output Data Rates and the

–10

Corresponding Settling Times for the Sinc⁴Filter (Zero Latency)

–20

Output Data

Rate (SPS)

Settling

Time (ms)

–30

Power Mode

FS[10:0]

1920

384

320

480

96

–40

Full Power (f_CLK

614.4 kHz)

=

2.5

12.5

15

400.15

80.15

66.82

400.61

80.61

67.28

401.22

81.22

67.89

–50

–60

–70

Mid Power (f_CLK

153.6 kHz)

2.5

12.5

15

–80

–90

80

–100

–110

–120

Low Power (f_CLK

76.8 kHz)

=

240

48

2.5

12.5

15

0

25

50

75

100

125

150

40

FREQUENCY (Hz)

Figure 88. Sinc⁴Filter Response (50 SPS Output Data Rate, Zero Latency

Disabled or 12.5 SPS Output Data Rate, Zero Latency Enabled)

Rev. D | Page 55 of 92

AD7124-8

Data Sheet

0

–10

Figure 89 shows the frequency response of the sinc⁴filter when

the output data rate is programmed to 60 SPS and zero latency

is disabled. For the same configuration but with zero latency

–20

–30

enabled, the filter response remains the same but the output

–40

data rate is 15 SPS. The sinc⁴filter provides 60 Hz ( 1 Hz)

–50

rejection of 120 dB minimum, assuming a stable master clock.

–60

0

–70

–10

–80

–20

–90

–30

–100

–110

–120

–40

–50

–60

0

25

50

75

100

125

150

FREQUENCY (Hz)

–70

Figure 91. Sinc⁴Filter Response (50 SPS Output Data Rate, Zero Latency

Disabled or 12.5 SPS Output Data Rate, Zero Latency Enabled, REJ60 = 1)

–80

–90

–100

–110

–120

SINC³FILTER

A sinc³filter can be used instead of the sinc⁴filter. The filter is

selected using the filter bits in the filter register. This filter has

good noise performance, moderate settling time, and moderate

50 Hz and 60 Hz ( 1 Hz) rejection. In Figure 92, the blocks

shown in gray are unused.

0

30

60

90

120

150

FREQUENCY (Hz)

Figure 89. Sinc⁴Filter Response (60 SPS Output Data Rate, Zero Latency

Disabled or 15 SPS Output Data Rate, Zero Latency Enabled)

When the output data rate is 10 SPS with zero latency disabled

POST

FILTER

or 2.5 SPS with zero latency enabled, simultaneous 50 Hz and

60 Hz rejection is obtained. The sinc⁴filter provides 50 Hz

SINC³/SINC⁴

MODULATOR

FILTER

( 1 Hz) and 60 Hz ( 1 Hz) rejection of 120 dB minimum,

AVERAGING

BLOCK

assuming a stable master clock.

0

Figure 92. Sinc³Filter

–10

Sinc³Output Data Rate and Settling Time

–20

–30

The output data rate (the rate at which conversions are available on

a single channel when the ADC is continuously converting) equals

–40

–50

f

_ADC= f_CLK/(32 × FS[10:0])

where:

_ADCis the output data rate.

_CLKis the master clock frequency (614.4 kHz in full power mode,

153.6 kHz in mid power mode and 76.8 kHz in low power mode).

FS[10:0] is the decimal equivalent of the FS[10:0] bits in the

filter register. FS[10:0] can have a value from 1 to 2047.

–60

–70

f

–80

–90

–100

–110

–120

0

30

60

90

120

150

FREQUENCY (Hz)

The output data rate can be programmed from

Figure 90. Sinc⁴Filter Response (10 SPS Output Data Rate, Zero Latency

Disabled or 2.5 SPS Output Data Rate, Zero Latency Enabled)

•

9.38 SPS to 19,200 SPS for full power mode

2.35 SPS to 4800 SPS for mid power mode

1.17 SPS to 2400 SPS for low power mode

Simultaneous 50 Hz/60 Hz rejection can also be achieved using

the REJ60 bit in the filter register. When the sinc filter places a

notch a 50 Hz, the REJ60 bit places a first order notch at 60 Hz.

The output data rate is 50 SPS when zero latency is disabled and

12.5 SPS when zero latency is enabled. Figure 91 shows the

frequency response of the sinc⁴filter. The filter provides 50 Hz

1 Hz and 60 Hz 1 Hz rejection of 82 dB minimum, assuming

a stable master clock.

The settling time for the sinc³filter is equal to

_SETTLE= (3 × 32 × FS[10:0] + Dead Time)/f_CLK

t

where Dead Time = 61 when FS[10:0] = 1 and 95 FS[10:0] >1.

The 3 dB frequency is equal to

f

_3dB= 0.272 × f_ADC

Rev. D | Page 56 of 92

Data Sheet

AD7124-8

Table 57 gives some examples of FS[10:0] settings and the

corresponding output data rates and settling times.

When the analog input is continuously sampled on a single

channel, the output data rate equals

f

_ADC= f_CLK/(3 × 32 × FS[10:0])

Table 57. Examples of Output Data Rates and the

Corresponding Settling Times for the Sinc³Filter

where:

f

_ADCis the output data rate.

_CLKis the master clock frequency.

Output Data

Rate (SPS)

Settling

Power Mode

FS[10:0]

1920

384

320

480

96

Time (ms)

300.15

60.15

Full Power (f_CLK

614.4 kHz)

=

10

50

60

10

50

60

10

50

60

FS[10:0] is the decimal equivalent of the FS[10:0] bits in the

filter register.

50.15

When switching channels, there is an extra delay in the first

conversion of

Mid Power (f_CLK

153.6 kHz)

300.61

60.61

Dead Time/f_CLK

80

50.61

where Dead Time = 61 when FS[10:0] = 1 or 95 when FS[10:0] > 1.

Low Power (f_CLK

76.8 kHz)

=

240

48

301.22

61.22

At low output data rates, this extra delay has little impact on the

value of the settling time. However, at high output data rates, the

delay must be considered. Table 58 summarizes the output data rate

when continuously converting on a single channel and the settling

time when switching between channels for a sample of FS[10:0].

40

51.22

When a channel change occurs, the modulator and filter are

reset. The complete settling time is allowed to generate the first

conversion after the channel change (see Figure 93). Subsequent

When the user selects another channel, the AD7124-8 allows

the complete settling time to generate the first conversion after

the channel change. Therefore, the ADC automatically operates

in zero latency mode when several channels are enabled—setting

the SINGLE_CYCLE bit has no benefits.

conversions on this channel are available at 1/f_ADC

.

CHANNEL A

CHANNEL B

CHANNEL

CONVERSIONS

CH A

CH B

1/f

ADC

When the analog input is constant or a channel change occurs,

valid conversions are available at a near constant output data

rate. When conversions are being performed on a single channel

and a step change occurs on the analog input, the ADC continues

to output fully settled conversions if the step change is synchronized

with the conversion process. If the step change is asynchronous,

one conversion is output from the ADC that is not completely

settled (see Figure 95).

NOTES

DT/f_CLK

1. DT = DEAD TIME.

Figure 93. Sinc³Channel Change

When conversions are performed on a single channel and a step

change occurs, the ADC does not detect the change in the

analog input. Therefore, it continues to output conversions at

the programmed output data rate. However, it is at least three

conversions later before the output data accurately reflects the

analog input. If the step change occurs while the ADC is processing

a conversion, the ADC takes four conversions after the step

change to generate a fully settled result.

ANALOG

INPUT

FULLY

SETTLED

ADC

OUTPUT

ANALOG

INPUT

FULLY

SETTLED

ADC

OUTPUT

1/f_ADC

Figure 95. Sinc³Zero Latency Operation

1/f_ADC

Figure 94. Asynchronous Step Change in the Analog Input

Sinc³Zero Latency

Table 58. Examples of Output Data Rates and the

Corresponding Settling Times for the Sinc³Filter (Zero Latency)

Output Data

Rate (SPS)

Settling

Time (ms)

Power Mode

FS[10:0]

1920

384

320

480

96

Zero latency is enabled by setting the SINGLE_CYCLE bit in

the filter register to 1. With zero latency, the conversion time

when continuously converting on a single channel approximately

equals the settling time. The benefit of this mode is that a similar

period of time elapses between all conversions irrespective of

whether the conversions occur on one channel or whether

several channels are used.

Full Power (f_CLK

614.4 kHz)

=

3.33

16.67

20

300.15

60.15

50.15

300.61

60.61

50.61

301.22

61.22

51.22

Mid Power (f_CLK

153.6 kHz)

3.33

16.67

20

80

Low Power (f_CLK

76.8 kHz)

=

240

48

3.33

16.67

20

40

Rev. D | Page 57 of 92

AD7124-8

Data Sheet

Sequencer

When the output data rate is 10 SPS with zero latency disabled

or 3.33 SPS with zero latency enabled, simultaneous 50 Hz and

60 Hz rejection is obtained. The sinc³filter has rejection of 100 dB

minimum at 50 Hz 1 Hz and 60 Hz 1 Hz (see Figure 98).

The description in the Sinc³Filter section is valid when manually

switching channels, for example, writing to the device to change

channels. When multiple channels are enabled, the on-chip

sequencer is automatically used; the device automatically

sequences between all enabled channels. In this case, the first

conversion takes the complete settling time as listed in Table 57.

For all subsequent conversions, the time needed for each conversion

is also the settling time, but the dead time is reduced to 30.

0

–10

–20

–30

–40

–50

Sinc³50 Hz and 60 Hz Rejection

–60

Figure 96 shows the frequency response of the sinc³filter when

–70

the output data rate is programmed to 50 SPS and zero latency

is disabled. For the same configuration but with zero latency

–80

–90

–100

–110

–120

enabled, the filter response remains the same but the output

data rate is 16.67 SPS. The sinc³filter gives 50 Hz 1 Hz

rejection of 95 dB minimum for a stable master clock.

0

30

60

90

120

150

0

FREQUENCY (Hz)

–10

Figure 98. Sinc³Filter Response (10 SPS Output Data Rate, Zero Latency

Disabled or 3.33 SPS Output Data Rate, Zero Latency Enabled)

–20

–30

Simultaneous 50 Hz and 60 Hz rejection can also be achieved

using the REJ60 bit in the filter register. When the sinc filter

places a notch a 50 Hz, the REJ60 bit places a first order notch

at 60 Hz. The output data rate is 50 SPS when zero latency is

disabled and 16.67 SPS when zero latency is enabled. Figure 99

shows the frequency response of the sinc³filter with this configura-

tion. Assuming a stable clock, the rejection at 50 Hz and 60 Hz

( 1 Hz) is in excess of 67 dB minimum.

–40

–50

–60

–70

–80

–90

–100

–110

–120

0

25

50

75

100

125

150

–10

–20

FREQUENCY (Hz)

Figure 96. Sinc³Filter Response (50 SPS Output Data Rate, Zero Latency

Disabled or 16.67 SPS Output Data Rate, Zero Latency Enabled)

–30

–40

Figure 97 shows the frequency response of the sinc³filter when

the output data rate is programmed to 60 SPS and zero latency

is disabled. For the same configuration but with zero latency

enabled, the filter response remains the same but the output

data rate is 20 SPS. The sinc³filter has rejection of 95 dB

minimum at 60 Hz 1 Hz, assuming a stable master clock.

0

–50

–60

–70

–80

–90

–100

–110

–120

–10

–20

0

25

50

75

100

125

150

FREQUENCY (Hz)

–30

Figure 99. Sinc³Filter Response (50 SPS Output Data Rate, Zero Latency

Disabled or 16.67 SPS Output Data Rate, Zero Latency Enabled, REJ60 = 1)

–40

–50

FAST SETTLING MODE (SINC⁴+ SINC¹FILTER)

–60

In fast settling mode, the settling time is close to the inverse of

the first filter notch; therefore, the user can achieve 50 Hz and/or

60 Hz rejection at an output data rate close to 1/50 Hz or 1/60 Hz.

The settling time is approximately equal to 1/output data rate.

Therefore, the conversion time is near constant when converting

on a single channel or when converting on several channels.

–70

–80

–90

–100

–110

–120

0

30

60

90

120

150

FREQUENCY (Hz)

Figure 97. Sinc³Filter Response (60 SPS Output Data Rate, Zero Latency

Disabled or 20 SPS Output Data Rate, Zero Latency Enabled)

Rev. D | Page 58 of 92

Data Sheet

AD7124-8

CHANNEL A

CONVERSIONS CH A CH A CH A CH A CH A

CHANNEL B

CHANNEL

Enable the fast settling mode using the filter bits in the filter

register. In fast settling mode, a sinc¹filter is included after the

sinc⁴filter. The sinc¹filter averages by 16 in the full power and

mid power modes and averages by 8 in the low power mode. In

Figure 100, the blocks shown in gray are unused.

CH B CH B CH B CH B

1/f

DT/f

CLK

NOTES

1. DT = DEAD TIME.

ADC

Figure 101. Fast Settling, Sinc⁴+ Sinc¹Filter

POST

FILTER

When the device is converting on a single channel and a step

change occurs on the analog input, the ADC does not detect the

change and continues to output conversions. If the step change

is synchronized with the conversion, only fully settled results

are output from the ADC. However, if the step change is

asynchronous to the conversion process, there is one intermediate

result, which is not completely settled (see Figure 102).

SINC³/SINC⁴

FILTER

MODULATOR

AVERAGING

BLOCK

Figure 100. Fast Settling Mode, Sinc⁴+ Sinc¹Filter

Output Data Rate and Settling Time, Sinc⁴+ Sinc¹Filter

ANALOG

INPUT

When continuously converting on a single channel, the output

data rate is

VALID

ADC

OUTPUT

f

_ADC= f_CLK/((4 + Avg − 1) × 32 × FS[10:0])

where:

_ADCis the output data rate.

_CLKis the master clock frequency (614.4 kHz in full power mode,

f

1/f_ADC

Figure 102. Step Change on the Analog Input, Sinc⁴+ Sinc¹Filter

153.6 kHz in mid power mode, and 76.8 kHz in low power mode).

Avg is 16 for the full or mid power mode and 8 for low power

mode.

FS[10:0] is the decimal equivalent of the FS[10:0] bits in the

filter register. FS[10:0] can have a value from 1 to 2047.

Sequencer

The description in the Fast Settling Mode (Sinc4 + Sinc1 Filter)

section is valid when manually switching channels, for example,

writing to the device to change channels. When multiple

channels are enabled, the on-chip sequencer is automatically

used; the device automatically sequences between all enabled

channels. In this case, the first conversion takes the complete

settling time as listed in Table 59. For all subsequent

conversions, the time needed for each conversion is also the

settling time, but the dead time is reduced to 30.

50 Hz and 60 Hz Rejection, Sinc⁴+ Sinc¹Filter

When another channel is selected by the user, there is an extra

delay in the first conversion. The settling time is equal to

t

_SETTLE= ((4 + Avg − 1) × 32 × FS[10:0] + Dead Time)/f_CLK

where Dead Time = 95.

The 3 dB frequency is equal to

f

_3dB= 0.44 × f_ADC

Figure 103 shows the frequency response when FS[10:0] is set to

24 in the full power mode or 6 in the mid power mode or low

power mode. Table 59 lists the corresponding output data rate.

The sinc filter places the first notch at

Table 59 lists sample FS[10:0] settings and the corresponding

output data rates and settling times.

Table 59. Examples of Output Data Rates and the

Corresponding Settling Times (Fast Settling Mode, Sinc⁴+ Sinc¹)

f

_NOTCH= f_CLK/(32 × FS[10:0])

First

Output

Settling

The sinc¹filter places notches at f_NOTCH/Avg (Avg equaling 16 for

the full power mode and mid power mode and equaling 8 for

the low power mode). Notches are also placed at multiples of

this frequency; therefore, when FS[10:0] is set to 6 in the full

power mode or mid power mode, a notch is placed at 800 Hz

due to the sinc filter and notches are placed at 50 Hz and

multiples of 50 Hz due to the averaging. In low power mode, a

notch is placed at 400 Hz due to the sinc filter and notches are

placed at 50 Hz and multiples of 50 Hz due to the averaging.

Notch

FS[10:0] (Hz)

Data Rate Time

Power Mode

(SPS)

8.42

(ms)

Full Power (f_CLK

614.4 kHz,

Average by 16)

=

120

24

20

30

6

10

50

60

10

50

60

10

50

60

118.9

23.9

42.11

50.53

8.42

19.94

119.36

24.36

20.4

Mid Power (f_CLK

153.6 kHz,

Average by 16)

=

42.11

50.53

7.27

5

Low Power (f_CLK

76.8 kHz,

Average by 8)

=

30

6

138.72

28.72

24.14

36.36

43.64

The notch at 50 Hz is a first-order notch; therefore, the notch is

not wide. This means that the rejection at 50 Hz exactly is good,

assuming a stable master clock. However, in a band of 50 Hz 1 Hz,

the rejection degrades significantly. The rejection at 50 Hz 0.5 Hz

is 40 dB minimum, assuming a stable clock; therefore, a good

master clock source is recommended when using fast settling mode.

5

When the analog input is constant or a channel change occurs,

valid conversions are available at a near constant output data rate.

Rev. D | Page 59 of 92

AD7124-8

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

FAST SETTLING MODE (SINC³+ SINC¹FILTER)

In fast settling mode, the settling time is close to the inverse of

the first filter notch; therefore, the user can achieve 50 Hz and/or

60 Hz rejection at an output data rate close to 1/50 Hz or 1/60 Hz.

The settling time is approximately equal to 1/output data rate.

Therefore, the conversion time is near constant when converting

on a single channel or when converting on several channels.

Enable the fast settling mode using the filter bits in the filter

register. In fast settling mode, a sinc¹filter is included after the

sinc³filter. The sinc1 filter averages by 16 in the full power and

mid power modes and averages by 8 in low power mode. In

Figure 106, the blocks shown in gray are unused.

–120

0

30

60

90

120

150

FREQUENCY (Hz)

POST

FILTER

Figure 103. 50 Hz Rejection

SINC³/SINC⁴

MODULATOR

FILTER

Figure 104 shows the filter response when FS[10:0] is set to 20

in full power mode or 5 in the mid power and low power modes. In

AVERAGING

BLOCK

this case, a notch is placed at 60 Hz and multiples of 60 Hz. The

Figure 106. Fast Settling Mode, Sinc³+ Sinc¹Filter

rejection at 60 Hz 0.5 Hz is equal to 40 dB minimum.

Output Data Rate and Settling Time, Sinc³+ Sinc¹Filter

0

–10

When continuously converting on a single channel, the output

data rate is

–20

–30

f

_ADC= f_CLK/((3 + Avg − 1) × 32 × FS[10:0])

where:

_ADCis the output data rate.

_CLKis the master clock frequency (614.4 kHz in full power mode,

153.6 kHz in mid power mode, and 76.8 kHz in low power mode).

Avg is 16 in full or mid power mode and 8 in low power mode.

FS[10:0] is the decimal equivalent of the FS[10:0] bits in the

filter register. FS[10:0] can have a value from 1 to 2047.

–40

–50

–60

f

–70

–80

–90

–100

–110

–120

0

30

60

90

120

150

When another channel is selected by the user, there is an extra

delay in the first conversion. The settling time is equal to

FREQUENCY (Hz)

Figure 104. 60 Hz Rejection

t

_SETTLE= ((3 + Avg − 1) × 32 × FS[10:0] + Dead Time)/f_CLK

Simultaneous 50 Hz/60 Hz rejection is achieved when FS[10:0]

is set to 384 in full power mode or 30 in the mid power and low

power modes. Notches are placed at 10 Hz and multiples of 10 Hz,

where Dead Time = 95.

The 3 dB frequency is equal to

thereby giving simultaneous 50 Hz and 60 Hz rejection. The

f

_3dB= 0.44 × f_NOTCH

rejection at 50 Hz 0.5 Hz and 60 Hz 0.5 Hz is 44 dB typically.

Table 60 lists some sample FS[10:0] settings and the

corresponding output data rates and settling times.

0

–10

–20

Table 60. Examples of Output Data Rates and the

Corresponding Settling Times (Fast Settling Mode, Sinc³+ Sinc¹)

First Notch Output Data Settling

–30

–40

–50

Power Mode

FS[10:0] (Hz)

Rate (SPS)

Time (ms)

112.65

22.65

–60

Full Power (f_CLK

614.4 kHz,

Average by 16)

=

120

24

20

30

6

10

50

60

10

50

60

10

50

60

8.89

–70

44.44

53.33

8.89

–80

18.9

–90

Mid Power (f_CLK

153.6 kHz,

Average by 16)

=

113.11

23.11

–100

–110

–120

44.44

53.33

8

5

19.36

Low Power (f_CLK

76.8 kHz,

Average by 8)

=

30

6

126.22

26.22

0

30

60

90

120

150

FREQUENCY (Hz)

40

5

48

22.06

Figure 105. Simultaneous 50 Hz and 60 Hz Rejection

Rev. D | Page 60 of 92

Data Sheet

AD7124-8

When the analog input is constant or a channel change occurs,

valid conversions are available at a near constant output data rate.

The notch at 50 Hz is a first-order notch; therefore, the notch is not

wide. This means that the rejection at 50 Hz exactly is good, assum-

ing a stable master clock. However, in a band of 50 Hz 1 Hz, the

CHANNEL A

CHANNEL B

CHANNEL

rejection degrades significantly. The rejection at 50 Hz 0.5 Hz is

40 dB minimum, assuming a stable clock; therefore, a good master

CONVERSIONS CH A CH A CH A CH A CH A

CH B CH B CH B CH B

clock source is recommended when using fast settling mode.

1/f

DT/f

CLK

ADC

NOTES

1. DT = DEAD TIME.

0

Figure 107. Fast Settling, Sinc³+ Sinc¹Filter

–10

–20

When the device is converting on a single channel and a step

change occurs on the analog input, the ADC does not detect

the change and continues to output conversions. When the step

change is synchronized with the conversion, only fully settled

results are output from the ADC. However, if the step change is

asynchronous to the conversion process, one intermediate result

is not completely settled (see Figure 108).

–30

–40

–50

–60

–70

–80

–90

ANALOG

INPUT

–100

–110

–120

VALID

ADC

OUTPUT

0

30

60

90

120

150

FREQUENCY (Hz)

Figure 109. 50 Hz Rejection

1/f_ADC

Figure 110 shows the filter response when FS[10:0] is set to 20

in full power mode or 5 in the mid power and low power modes. In

Figure 108. Step Change on the Analog Input, Sinc³+ Sinc¹Filter

Sequencer

this case, a notch is placed at 60 Hz and multiples of 60 Hz. The

rejection at 60 Hz 0.5 Hz is equal to 40 dB minimum.

The description in the Fast Settling Mode (Sinc3 + Sinc1 Filter)

section is valid when manually switching channels, for example,

writing to the device to change channels. When multiple

channels are enabled, the on-chip sequencer is automatically

used; the device automatically sequences between all enabled

channels. In this case, the first conversion takes the complete

settling time as listed in Table 60. For all subsequent conversions,

the time needed for each conversion is also the settling time,

but the dead time is reduced to 30_.

0

–10

–20

–30

–40

–50

–60

–70

–80

50 Hz and 60 Hz Rejection, Sinc³+ Sinc¹Filter

–90

–100

–110

–120

Figure 109 shows the frequency response when FS[10:0] is set to

24 in the full power mode or 6 in the mid power mode or low

power mode. Table 60 lists the corresponding output data rate.

0

30

60

90

120

150

FREQUENCY (Hz)

The sinc filter places the first notch at

Figure 110. 60 Hz Rejection

f

_NOTCH= f_CLK/(32 × FS[10:0])

Simultaneous 50 Hz/60 Hz rejection is achieved when FS[10:0]

is set to 384 in full power mode or 30 in the mid power and low

power modes. Notches are placed at 10 Hz and multiples of 10 Hz,

thereby giving simultaneous 50 Hz and 60 Hz rejection. The

rejection at 50 Hz 0.5 Hz and 60 Hz 0.5 Hz is 42 dB typically.

The averaging block places notches at f_NOTCH/Avg (Avg equaling

16 for the full power mode and mid power mode and equaling 8

for the low power mode). Notches are also placed at multiples of

this frequency; therefore, when FS[10:0] is set to 6 in full power

mode or mid power mode, a notch is placed at 800 Hz due to

the sinc filter and notches are placed at 50 Hz and multiples of

50 Hz due to the averaging. In low power mode, a notch is

placed at 400 Hz due to the sinc filter and notches are placed at

50 Hz and multiples of 50 Hz due to the averaging.

Rev. D | Page 61 of 92

AD7124-8

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

filters are realized by post filtering the output of the sinc³filter.

The filter bits must be set to all 1s to enable the post filter. The post

filter option to use is selected using the POST_FILTER bits in the

filter register. In Figure 112, the blocks shown in gray are unused.

POST

FILTER

SINC³/SINC⁴

MODULATOR

FILTER

AVERAGING

BLOCK

Figure 112. Post Filters

Table 61 shows the output data rates with the accompanying

settling times and the rejection.

–120

0

30

60

90

120

150

FREQUENCY (Hz)

When continuously converting on a single channel, the first

conversion requires a time of t_SETTLE. Subsequent conversions

occur at 1/f_ADC. When multiple channels are enabled (either

manually or using the sequencer), the settling time is required

to generate a valid conversion on each enabled channel.

Figure 111. Simultaneous 50 Hz and 60 Hz Rejection

POST FILTERS

The post filters provide rejection of 50 Hz and 60 Hz

simultaneously and allow the user to trade off settling time and

rejection. These filters can operate up to 27.27 SPS or can reject

up to 90 dB of 50 Hz 1 Hz and 60 Hz 1 Hz interference. These

Table 61. AD7124-8 Post Filters: Output Data Rate, Settling Time (t_SETTLE), and Rejection

Output Data

Rate (SPS)

f_3dB

(Hz)

t_SETTLE, Full Power

Mode (ms)

t_SETTLE, Mid Power

Mode (ms)

t_SETTLE, Low Power

Mode (ms)

Simultaneous Rejection of 50 Hz 1 Hz

and 60 Hz 1 Hz (dB)¹

27.27

25

20

17.28

15.12

13.38

12.66

38.498

41.831

51.831

61.831

38.998

42.331

52.331

62.331

39.662

42.995

52.995

62.995

47

62

86

92

16.67

¹Stable master clock used.

Rev. D | Page 62 of 92

Data Sheet

AD7124-8

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

100

200

300

400

500

600

40

45

50

55

60

65

70

FREQUENCY (Hz)

Figure 113. DC to 600 Hz, 27.27 SPS Output Data Rate, 36.67 ms Settling Time

Figure 116. Zoom in 40 Hz to 70 Hz, 25 SPS Output Data Rate, 40 ms Settling Time

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

40

45

50

55

60

65

70

0

100

200

300

400

500

600

FREQUENCY (Hz)

Figure 114. Zoom in 40 Hz to 70 Hz, 27.27 SPS Output Data Rate, 36.67 ms

Settling Time

Figure 117. DC to 600 Hz, 20 SPS Output Data Rate, 50 ms Settling Time

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

40

100

200

300

400

500

600

40

45

50

55

60

65

70

FREQUENCY (Hz)

Figure 115. DC to 600 Hz, 25 SPS Output Data Rate, 40 ms Settling Time

Figure 118. Zoom in 40 Hz to 70 Hz, 20 SPS Output Data Rate, 50 ms Settling Time

Rev. D | Page 63 of 92

AD7124-8

Data Sheet

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

100

200

300

400

500

600

40

45

50

55

60

65

70

FREQUENCY (Hz)

Figure 119. DC to 600 Hz,16.667 SPS Output Data Rate, 60 ms Settling Time

Figure 120. Zoom in 40 Hz to 70 Hz, 16.667 SPS Output Data Rate, 60 ms

Settling Time

Rev. D | Page 64 of 92

Data Sheet

AD7124-8

Table 62 shows some sample configurations and the

corresponding performance in terms of throughput and 50 Hz

and 60 Hz rejection.

SUMMARY OF FILTER OPTIONS

The AD7124-8 has several filter options. The filter that is

chosen affects the output data rate, settling time, the rms noise,

the stop band attenuation, and the 50 Hz and 60 Hz rejection.

Table 62. Filter Summary¹

Filter

Sinc⁴

Power Mode

All

Output Data Rate (SPS)

REJ60

50 Hz Rejection (dB)²

120 dB (50 Hz and 60 Hz)

120 dB (50 Hz only)

82 dB (50 Hz and 60 Hz)

120 dB (60 Hz only)

120 dB (50 Hz only)

82 dB (50 Hz and 60 Hz)

120 dB (60 Hz only)

100 dB (50 Hz and 60 Hz)

95 dB (50 Hz only)

10

50

60

0

1

0

1

0

1

0

Sinc⁴, Zero Latency

Sinc³

All

12.5

15

All

10

50

60

67 dB (50 Hz and 60 Hz)

95 dB (60 Hz only)

Fast Settling (Sinc⁴+ Sinc¹)

Fast Settling (Sinc³+ Sinc¹)

Post Filter

Full/mid

Low

Full/mid

Low

Full/mid

Low

Full/mid

Low

Full/mid

Low

Full/mid

Low

All

50.53

43.64

42.11

36.36

8.4

7.27

53.33

48

44.44

40

8.89

8

40 dB (60 Hz only)

40 dB (50 Hz only)

40 dB (50 Hz and 60 Hz)

40 dB (60 Hz only)

40 dB (50 Hz only)

40 dB (50 Hz and 60 Hz)

47 dB (50 Hz and 60 Hz)

62 dB (50 Hz and 60 Hz)

85 dB (50 Hz and 60 Hz)

90 dB (50 Hz and 60 Hz)

27.27

25

20

All

16.67

¹These calculations assume a stable master clock.

²For fast settling mode, the 50 Hz/60 Hz rejection is measured in a band of 0.5 Hz around 50 Hz and/or 60 Hz. For all other modes, a region of 1 Hz around 50 Hz

and/or 60 Hz is used.

Rev. D | Page 65 of 92

AD7124-8

Data Sheet

DIAGNOSTICS

The AD7124-8 has numerous diagnostic functions on chip. Use

these features to ensure

is performed, check the status of the REF_DET_ERR bit at the

end of the calibration cycle.

The reference detect flag may be set when the device exits of

standby mode. Therefore, read the error register after exiting

standby mode to reset the flag to 0.

•

Read/write operations are to valid registers only

Only valid data is written to the on-chip registers

Appropriate decoupling is used on the LDOs

The external reference, if used, is present

The ADC modulator and filter are working within

specification

CALIBRATION, CONVERSION, AND SATURATION

ERRORS

The conversion process and calibration process can also be

monitored by the AD7124-8. These diagnostics check the

analog input used as well as the modulator and digital filter

during conversions or calibration. The functions can be enabled

using the ADC_CAL_ERR_EN, ADC_CONV_ERR_EN, and

ADC_SAT_ERR_EN bits in the ERROR_EN register. With these

functions enabled, the ADC_ CAL_ERR, ADC_CONV_ERR, and

ADC_SAT_ERR bits are set if an error occurs.

SIGNAL CHAIN CHECK

Functions such as the reference and power supply voltages can

be selected as inputs to the ADC. The AD7124-8 can therefore

check the voltages connected to the device. The AD7124-8 also

generates an internal 20 mV signal that can be applied internally to

a channel by selecting the V_20MV_P to V_20MV_M channel

in the channel register. The PGA can be checked using this

function. As the PGA setting is increased, for example, the

signal as a percent of the analog input range is reduced by a

factor of two. This allows the user to check that the PGA is

functioning correctly.

The ADC_CONV_ERR flag is set if there is an overflow or

underflow in the digital filter. The ADC conversion clamps to

all 0s or all 1s also. This flag is updated in conjunction with the

update of the data register and can be cleared only by a read of

the error register.

REFERENCE DETECT

The ADC_SAT_ERR flag is set if the modulator outputs 20

consecutive 1s or 0s. This indicates that the modulator has

saturated.

The AD7124-8 includes on-chip circuitry to detect if there is a

valid reference for conversions or calibrations when the user

selects an external reference as the reference source. This is a

valuable feature in applications such as RTDs or strain gages

where the reference is derived externally.

When an offset calibration is performed, the resulting offset

coefficient must be between 0x7FFFFF and 0xF80000. If the

coefficient is outside this range, the offset register is not updated

and the ADC_CAL_ERR flag is set. During a full-scale calibration,

overflow of the digital filter is checked. If an overflow occurs,

the error flag is set and the gain register is not updated.

COMPARATOR

REFIN (REFINx(+) – REFINx(–))

OUTPUT: 0 WHEN REFIN ≤0.7

1 WHEN REFIN <0.7

0.7V

Figure 121. Reference Detect Circuitry

OVERVOLTAGE/UNDERVOLTAGE DETECTION

This feature is enabled when the REF_DET_ERR_EN bit in the

ERROR_EN register is set to 1. If the voltage between the

selected REFINx(+) and REFINx(−) pins goes below 0.7 V, or

either the REFINx(+) or REFINx(−) inputs are open circuit, the

AD7124-8 detects that it no longer has a valid reference. In this

case, the REF_DET_ERR bit in the error register is set to 1. The

ERR bit in the status register is also set.

The overvoltage/undervoltage monitors check the absolute

voltage on the AINx analog input pins. The absolute voltage

must be within specification to meet the datasheet

specifications. If the ADC is operated outside the datasheet

limits, linearity degrades.

OVERVOLTAGE

COMPARATOR

AV

+ 40mV

If the AD7124-8 is performing normal conversions and the

REF_DET_ERR bit becomes active, the conversion results

revert to all 1s. Therefore, it is not necessary to continuously

monitor the status of the REF_DET_ERR bit when performing

conversions. It is only necessary to verify its status if the

conversion result read from the ADC data register is all 1s.

DD

AINx_OV_ERR: SET IF AINx IS

40mV ABOVE AV

DD

AINx

UNDERVOLTAGE

COMPARATOR

AINx_UV_ERR: SET IF AINx IS

40mV ABOVE AV

SS

AV – 40mV

SS

If the AD7124-8 is performing either offset or full-scale

calibrations and the REF_DET_ERR bit becomes active, the

updating of the respective calibration register is inhibited to

avoid loading incorrect coefficients to the register, and the

REF_DET_ERR bit is set. If the user is concerned about

verifying that a valid reference is in place every time a calibration

NOTE: AINx IS AINP OR AINM

Figure 122. Analog Input Overvoltage/Undervoltage Monitors

Rev. D | Page 66 of 92

Data Sheet

AD7124-8

The positive (AINP) and negative (AINM) analog inputs can be

separately checked for overvoltages and undervoltages. The

AINP_OV_ERR_EN and AINP_UV_ERR_EN bits in the

ERROR_EN register enable the overvoltage/undervoltage

diagnostics respectively. An overvoltage is flagged when the

voltage on AINP exceeds AV_DDwhile an undervoltage is flagged

when the voltage on AINP goes below AV_SS. Similarly, an

overvoltage/undervoltage check on the negative analog input

pin is enabled using the AINM_OV_ERR_EN and AINM_UV_

ERR_EN bits in the ERROR_EN register. The error flags are

AINP_OV_ERR, AINP_UV_ERR, AINM_OV_ERR, and

AINM_UV_ERR in the error register.

The AD7124-8 can also test the circuitry used for the power

supply monitoring. When the ALDO_PSM_TRIP_TEST_EN or

DLDO_PSM_TRIP_TEST_EN bits are set, the input to the test

circuitry is tied to GND rather than the LDO output. Set the

corresponding ALDO_PSM_ERR or DLDO_PSM_ERR bit.

LDO Capacitor Detect

The analog and digital LDOs require an external decoupling

capacitor of 0.1 µF. The AD7124-8 can check for the presence of

this decoupling capacitor. Using the LDO_CAP_CHK bits in

the ERROR_EN register, the LDO being checked is turned off

and the voltage at the LDO output is monitored. If the voltage

falls, this is considered a fail and the LDO_CAP_ERR bit in the

error register is set.

When this function is enabled, the corresponding flags may be

set in the error register. Therefore, the user must read the error

register when the overvoltage/undervoltage checks are enabled

to ensure that the flags are reset to 0.

Only the analog LDO or digital LDO can be tested for the

presence of the decoupling capacitor at any one time. This test

also interferes with the conversion process.

POWER SUPPLY MONITORS

The circuitry used to check for missing decoupling capacitors

can also be tested by the AD7124-8. When the LDO_CAP_

CHK_TEST_EN bit in the ERROR_EN register is set, the

decoupling capacitor is internally disconnected from the LDO,

forcing a fault condition. Therefore, when the LDO capacitor

test is performed, a fault condition is reported, that is, the

LDO_CAP_ERR bit in the error register is set.

Along with converting external voltages, the ADC can monitor

the voltage on the AV_DDpin and the IOV_DDpin. When the

inputs of AV_DDto AV_SSor IOV_DDto DGND are selected, the

voltage (AV_DDto AV_SSor IOV_DDto DGND) is internally

attenuated by 6, and the resulting voltage is applied to the Σ-Δ

modulator. This is useful because variations in the power supply

voltage can be monitored.

MCLK COUNTER

LDO MONITORING

A stable master clock is important as the output data rate, filter

settling time, and the filter notch frequencies are dependent on

the master clock. The AD7124-8 allows the user to monitor the

master clock. When the MCLK_CNT_EN bit in the ERROR_EN

register is set, the MCLK_COUNT register increments by 1 every

131 master clock cycles. The user can monitor this register over

a fixed period of time. The master clock frequency can be

determined from the result in the MCLK_COUNT register.

The MCLK_COUNT register wraps around after it reaches its

maximum value.

There are several LDO checks included on the AD7124-8. Like

the external power supplies, the voltage generated by the analog

and digital LDOs are selectable as inputs to the ADC. In addition,

the AD7124-8 can continuously monitor the LDO voltages.

Power Supply Monitor

The voltage generated by the ALDO and DLDO can be

monitored by enabling the ALDO_PSM_ERR_EN bit and the

DLDO_PSM_ERR_EN bit, respectively, in the ERROR_EN

register. When enabled, the output voltage of the LDO is

continuously monitored. If the ALDO voltage drops below

1.6 V, the ALDO_PSM_ERR flag is asserted. If the DLDO

voltage drops below 1.55 V, the DLDO_PSM_ERR flag is

asserted. The bit remains set until the corresponding LDO

voltage recovers. However, the bit is only cleared when the

error register is read.

SPI SCLK COUNTER

The SPI SCLK counter counts the number of SCLK pulses used

in each read and write operation.

must frame every read and

CS

write operation when this function is used. All read and write

operations are multiples of eight SCLK pulses (8, 16, 32, 40, 48).

If the SCLK counter counts the SCLK pulses and the result is not a

multiple of eight, an error is flagged; the SPI_SCLK_CNT_ERR bit

in the error register is set. If a write operation is being performed

and the SCLK contains an incorrect number of SCLK pulses,

the value is not written to the addressed register and the write

operation is aborted.

OVERVOLTAGE

COMPARATOR

ALDO

SET IF ALDO OUTPUT VOLTAGE IS

LESS THAN 1.6V

1.6V

Figure 123. Analog LDO Monitor

OVERVOLTAGE

COMPARATOR

The SCLK counter is enabled by setting the SPI_SCLK_

CNT_ERR_EN bit in the ERROR_EN register.

DLDO

SET IF DLDO OUTPUT VOLTAGE IS

LESS THAN 1.55V

1.55V

Figure 124. Digital LDO Monitor

Rev. D | Page 67 of 92

AD7124-8

Data Sheet

8-BIT COMMAND

UP TO 24-BIT INPUT

8-BIT CRC

SPI READ/WRITE ERRORS

CS

Along with the SCLK counter, the AD7124-8 can also check the

read and write operations to ensure that valid registers are being

addressed. When the SPI_READ_ERR_EN bit or the SPI_

WRITE_ERR_EN bit in the ERROR_EN register are set, the

AD7124-8 checks the address of the read/write operations. If

the user attempts to write to or read from any register other

than the user registers described in this data sheet, an error is

flagged; the SPI_READ_ERR bit or the SPI_WRITE_ERR bit in

the error register is set and the read/write operation is aborted.

CS

DATA

CRC

DIN

SCLK

Figure 125. SPI Write Transaction with CRC

8-BIT COMMAND

UP TO 32-BIT OUTPUT

8-BIT CRC

CS

This function, along with the SCLK counter and the CRC,

makes the serial interface more robust. Invalid registers are not

written to or read from. An incorrect number of SCLK pulses

can cause the serial interface to go asynchronous and incorrect

registers to be accessed. The AD7124-8 protects against these

issues via the diagnostics.

CMD

DIN

DOUT/

RDY

DATA

CRC

SPI_IGNORE ERROR

SCLK

At certain times, the on-chip registers are not accessible. For

example, during power-up, the on-chip registers are set to their

default values. The user must wait until this operation is

complete before writing to registers. Also, when offset or gain

calibrations are being performed, registers cannot be accessed.

The SPI_IGNORE_ERR bit in the error register indicates when

the on-chip registers cannot be written to. This diagnostic is

enabled by default. The function can be disabled using the

SPI_IGNORE_ERR_EN bit in the ERROR_EN register.

Figure 126. SPI Read Transaction with CRC

If checksum protection is enabled when continuous read mode

is active, there is an implied read data command of 0x42 before

every data transmission that must be accounted for when

calculating the checksum value. This ensures a nonzero checksum

value even if the ADC data equals 0x000000.

MEMORY MAP CHECKSUM PROTECTION

Any write operations performed when SPI_IGNORE_ERR is

enabled are ignored.

For added robustness, a CRC calculation is performed on the

on-chip registers as well. The status register, data register, and

MCLK counter register are not included in this check as their

contents change continuously. The CRC is performed at a rate

of 1/2400 seconds. Each time that the memory map is accessed,

the CRC is recalculated. Events that cause the CRC to be

recalculated are

CHECKSUM PROTECTION

The AD7124-8 has a checksum mode that can be used to improve

interface robustness. Using the checksum ensures that only

valid data is written to a register and allows data read from a

register to be validated. If an error occurs during a register

write, the CRC_ERR bit is set in the error register. However, to

ensure that the register write was successful, read back the

register and verify the checksum.

•

A user write

An offset/full-scale calibration

When the device is operated in single conversion mode

and the ADC goes into idle mode following the completion

of the conversion

When exiting continuous read mode (the CONT_READ bit

in the ADC_CONTROL register is set to 0)

For CRC checksum calculations, the following polynomial is

always used:

•

x⁸+ x²+ x + 1

The CRC_ERR_EN bit in the ERROR_EN register enables and

disables the checksum.

The memory map CRC function is enabled by setting the MM_

CRC_ERR_EN bit in the ERROR_EN register to 1. If an error

occurs, the MM_CRC_ERR bit in the error register is set to 1.

The checksum is appended to the end of each read and write

transaction. The checksum calculation for the write transaction

is calculated using the 8-bit command word and the 8-bit to 24-bit

data. For a read transaction, the checksum is calculated using the

command word and the 8-bit to 32-bit data output. Figure 125 and

Figure 126 show SPI write and read transactions, respectively.

Rev. D | Page 68 of 92

Data Sheet

AD7124-8

CRC Calculation

ROM CHECKSUM PROTECTION

The checksum, which is 8 bits wide, is generated using the

polynomial

On power-up, all registers are set to default values. These

default values are held in read only memory (ROM). For added

robustness, a CRC calculation is performed on the ROM contents

as well. The CRC is performed on power-up.

x⁸+ x²+ x + 1

To generate the checksum, the data is left shifted by eight bits to

create a number ending in eight Logic 0s. The polynomial is

aligned so that its MSB is adjacent to the leftmost Logic 1 of the

data. An XOR (exclusive OR) function is applied to the data to

produce a new, shorter number. The polynomial is again aligned

so that its MSB is adjacent to the leftmost Logic 1 of the new result,

and the procedure is repeated. This process is repeated until the

original data is reduced to a value less than the polynomial.

This is the 8-bit checksum.

The ROM CRC function is enabled by setting the ROM_CRC_

ERR_EN bit in the ERROR_EN register to 1. If an error occurs,

the ROM_CRC_ERR bit in the error register is set to 1.

When this function is enabled, the internal master clock, if

enabled, remains active in the standby mode.

Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (8-Bit Command and 16-Bit Data)

An example of generating the 8-bit checksum using the polynomial based checksum is as follows:

Initial value

011001010100001100100001

01100101010000110010000100000000

left shifted eight bits

polynomial

x⁸+ x²+ x + 1

=

100000111

100100100000110010000100000000

100000111

XOR result

polynomial

100011000110010000100000000

100000111

XOR result

polynomial

11111110010000100000000

100000111

XOR result

polynomial value

XOR result

1111101110000100000000

100000111

polynomial value

XOR result

111100000000100000000

100000111

polynomial value

XOR result

11100111000100000000

100000111

polynomial value

XOR result

1100100100100000000

100000111

polynomial value

XOR result

100101010100000000

100000111

polynomial value

XOR result

101101100000000

100000111

polynomial value

XOR result

1101011000000

100000111

polynomial value

XOR result

101010110000

100000111

polynomial value

XOR result

1010001000

100000111

polynomial value

checksum = 0x86

10000110

Rev. D | Page 69 of 92

AD7124-8

Data Sheet

When a conversion is close to full scale, the user must check

these three cases before making a judgment. If the voltage

measured is 0 V, it may indicate that the transducer has short

circuited. For normal operation, these burnout currents are

turned off by setting the burnout bits to zero. The current

sources work over the normal absolute input voltage range

specifications with buffers on.

BURNOUT CURRENTS

The AD7124-8 contains two constant current generators that

can be programmed to 0.5 µA, 2 µA, or 4 µA. One generator

sources current from AV_DDto AINP, and one sinks current from

AINM to AV_SS. These currents enable open wire detection.

AV

DD

TEMPERATURE SENSOR

Embedded in the AD7124-8 is a temperature sensor that is

useful to monitor the die temperature. This is selected using the

AINP[4:0] and AINM[4:0] bits in the channel register. The

sensitivity is 13,584 codes/°C, approximately. The equation for

the temperature sensor is

BURNOUT

DETECT

PGA1

X-MUX

AV

SS

Temperature (°C) = ((Conversion − 0x800000)/13,584) − 272.5

The temperature sensor has an accuracy of 0.5°C typically.

1.2

Figure 127. Burnout Currents

32 UNITS

1.0

0.8

The currents are switched to the selected analog input pair.

Both currents are either on or off. The burnout bits in the

configuration register enable/disable the burnout currents along

with setting the amplitude. Use these currents to verify that an

external transducer is still operational before attempting to take

measurements on that channel. After the burnout currents are

turned on, they flow in the external transducer circuit, and a

measurement of the input voltage on the analog input channel

can be taken. If the resulting voltage measured is near full scale,

the user must verify why this is the case. A near full-scale reading

can mean that the front-end sensor is open circuit. It can also

mean that the front-end sensor is overloaded and is justified in

outputting full scale, or that the reference may be absent and the

REF_DET_ERR bit is set, thus clamping the data to all 1s.

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–40 –30 –20 –10

0

15 25 40 50 60 70 85 95 105 115 125

TEMPERATURE (°C)

Figure 128. Temperature Sensor Error vs. Temperature

Rev. D | Page 70 of 92

Data Sheet

AD7124-8

GROUNDING AND LAYOUT

The analog inputs and reference inputs are differential and,

therefore, most of the voltages in the analog modulator are

common-mode voltages. The high common-mode rejection of

the device removes common-mode noise on these inputs. The

analog and digital supplies to the AD7124-8 are independent

and separately pinned out to minimize coupling between the

analog and digital sections of the device. The digital filter

provides rejection of broadband noise on the power supplies,

except at integer multiples of the master clock frequency.

possible to provide low impedance paths and reduce glitches on

the power supply line. Shield fast switching signals like clocks

with digital ground to prevent radiating noise to other sections

of the board and never run clock signals near the analog inputs.

Avoid crossover of digital and analog signals. Run traces on

opposite sides of the board at right angles to each other. This

reduces the effects of feedthrough on the board. A microstrip

technique is by far the best but is not always possible with a

double-sided board. In this technique, the component side of

the board is dedicated to ground planes, whereas signals are

placed on the solder side.

The digital filter also removes noise from the analog and

reference inputs, provided that these noise sources do not

saturate the analog modulator. As a result, the AD7124-8 is

more immune to noise interference than a conventional high

resolution converter. However, because the resolution of the

AD7124-8 is high and the noise levels from the converter are so

low, care must be taken with regard to grounding and layout.

Good decoupling is important when using high resolution ADCs.

The AD7124-8 has two power supply pins—AV_DDand IOV_DD.

The AV_DDpin is referenced to AV_SS, and the IOV_DDpin is

referenced to DGND. Decouple AV_DDwith a 1 µF tantalum

capacitor in parallel with a 0.1 µF capacitor to AV_SSon each pin.

Place the 0.1 µF capacitor as close as possible to the device on

each supply, ideally right up against the device. Decouple IOV_DD

with a 1 µF tantalum capacitor in parallel with a 0.1 µF

capacitor to DGND. All analog inputs must be decoupled to

AV_SS. If an external reference is used, decouple the REFINx(+)

and REFINx(−) pins to AV_SS.

The PCB that houses the ADC must be designed so that the

analog and digital sections are separated and confined to

certain areas of the board. A minimum etch technique is

generally best for ground planes because it results in the best

shielding.

In any layout, the user must keep in mind the flow of currents

in the system, ensuring that the paths for all return currents are as

close as possible to the paths the currents took to reach their

destinations.

The AD7124-8 also has two on-board LDO regulators—one

that regulates the AV_DDsupply and one that regulates the IOV_DD

supply. For the REGCAPA pin, it is recommended that a 0.1 µF

capacitor to AV_SSbe used. Similarly, for the REGCAPD pin, it is

recommended that a 0.1 µF capacitor to DGND be used.

Avoid running digital lines under the device because this

couples noise onto the die and allows the analog ground plane

to run under the AD7124-8 to prevent noise coupling. The

power supply lines to the AD7124-8 must use as wide a trace as

If using the AD7124-8 with split supply operation, a separate

plane must be used for AV_SS.

Rev. D | Page 71 of 92

AD7124-8

Data Sheet

APPLICATIONS INFORMATION

The AD7124-8 offers a low cost, high resolution analog-to-

digital function. Because the analog-to-digital function is provided

by a Σ-Δ architecture, the device is more immune to noisy

environments, making it ideal for use in sensor measurement,

and industrial and process control applications.

Most conversions are read from the thermocouple, with the

cold junction being read only periodically as the cold junction

temperature is stable or slow moving. If a T-type thermocouple

is used, it can measure a temperature from −200°C to +400°C.

The voltage generated over this temperature range is −8.6 mV

to +17.2 mV. The AD7124-8 internal reference equals 2.5 V.

Therefore, the PGA is set to 128. If the thermocouple uses the

AIN0/AIN1 channel and the thermistor is connected to the

AIN12/AIN13 channel, the conversion process is as follows:

TEMPERATURE MEASUREMENT USING A

THERMOCOUPLE

Figure 129 outlines a connection from a thermocouple to the

AD7124-8. In a thermocouple application, the voltage generated

by the thermocouple is measured with respect to an absolute

reference; thus, the internal reference is used for this conversion.

The cold junction measurement uses a ratiometric configuration,

so the reference is provided externally.

1. Reset the ADC.

2. Select the power mode.

Set the CHANNEL_0 register analog input to AIN0/AIN1.

Assign Setup 0 to this channel. Configure Setup 0 to have a

gain of 128 and select the internal reference. Select the

filter type and set the output data rate.

Because the signal from the thermocouple is small, the AD7124-8

is operated with the PGA enabled to amplify the signal from the

thermocouple. As the input channel is buffered, large decoupling

capacitors can be placed on the front end to eliminate any noise

pickup that may be present in the thermocouple leads. The bias

voltage generator provides a common-mode voltage so that the

voltage generated by the thermocouple is biased up to (AV_DD

AV_SS)/2. For thermocouple voltages that are centered about ground,

the AD7124-8 can be operated with a split power supply ( 1.8 V).

3. Enable VBIAS on AIN0.

4. Set the CHANNEL_1 register analog input to AIN12/AIN13.

Assign Setup 1 to this channel. Configure Setup 1 to have a

gain of 1 and select the external reference REFIN2( ). Select

the filter type and set the output data rate.

5. Enable the excitation current (IOUTx) and select a suitable

value. Output this current to the AIN4 pin.

−

RDY

6. Enable the AIN0/AIN1 channel. Wait until

Read the conversion.

goes low.

The cold junction compensation is performed using a thermistor in

Figure 129. The on-chip excitation current supplies the thermistor.

In addition, the reference voltage for the cold junction measurement

is derived from a precision resistor in series with the thermistor.

This allows a ratiometric measurement so that variation of the

excitation current has no effect on the measurement (it is the

ratio of the precision reference resistance to the thermistor

resistance that is measured).

7. Continue to read nine further conversions from the

AIN0/AIN1 channel.

8. Disable CHANNEL_0 and enable CHANNEL_1.

RDY

9. Wait until

goes low. Read one conversion.

10. Repeat Step 5 to Step 8.

Using the linearization equation for the T-type thermocouple,

process the thermocouple voltage along with the thermistor voltage

and compute the actual temperature at the thermocouple head.

AV_DD

V_BIAS

REFIN1(+)

THERMOCOUPLE JUNCTION

R

BAND GAP

REFERENCE

AIN0

AIN1

REFERENCE

DETECT

R

AV

C

DD

DOUT/RDY

DIN

SERIAL

INTERFACE

AND

CONTROL

LOGIC

DIGITAL

FILTER

Σ-Δ

PGA

AIN12

AIN13

REFIN2(+)

X-MUX

ADC

SCLK

COLD JUNCTION

CS

REFIN2(–)

CHANNEL

SEQUENCER

TEMP

SENSOR

AV

SS

IOV

DD

R

REF

INTERNAL

CLOCK

V

DIAGNOSTICS

DD

CLK

REFIN1(–)

PSW

SYNC

AD7124-8

REGCAPA

REGCAPD

AV_SS

DGND

NOTES

1. SIMPLIFIED BLOCK DIAGRAM SHOWN.

Figure 129. Thermocouple Application

Rev. D | Page 72 of 92

Data Sheet

AD7124-8

The external antialias filter is omitted for clarity. However, such

a filter is required to reject any interference at the modulator

frequency and multiples of the modulator frequency. In addition,

some filtering may be needed for EMI purposes. Both the analog

inputs and the reference inputs can be buffered, which allows

the user to connect any RC combination to the reference or

analog input pins.

TEMPERATURE MEASUREMENT USING AN RTD

To optimize a 3-wire RTD configuration, two identically

matched current sources are required. The AD7124-8, which

contains two well matched current sources, is ideally suited to

these applications. One possible 3-wire configuration is shown

in Figure 130. In this 3-wire configuration, the lead resistances

result in errors if only one current (output at AIN0) is used, as

the excitation current flows through RL1, developing a voltage

error between AIN1 and AIN2. In the scheme outlined, the

second RTD current source (available at AIN3) compensates for

the error introduced by the excitation current flowing through

RL1. The second RTD current flows through RL2. Assuming

that RL1 and RL2 are equal (the leads are normally of the same

material and of equal length) and that the excitation currents

match, the error voltage across RL2 equals the error voltage

across RL1, and no error voltage is developed between AIN1

and AIN2. Twice the voltage is developed across RL3; however,

because this is a common-mode voltage it does not introduce

errors. The reference voltage for the AD7124-8 is also generated

using one of the matched current sources. It is developed using

a precision resistor and applied to the differential reference pins

of the ADC. This scheme ensures that the analog input voltage

span remains ratiometric to the reference voltage. Any errors in

the analog input voltage due to the temperature drift of the

excitation current are compensated by the variation of the

reference voltage.

The required power mode depends on the performance

required from the system along with the current consumption

allowance for the system. In a field transmitter, low current

consumption is essential. In this application, the low power

mode or mid power mode is most suitable. In process control

applications, power consumption is not a priority. Thus, full

power mode may be selected. The full power mode offers

higher throughput and lower noise.

The AD7124-8 on-chip diagnostics allow the user to check the

circuit connections, monitor power supply, reference, and LDO

voltages, check all conversions and calibrations for any errors, as

well as monitor any read/write operations. In thermocouple

applications, the circuit connections are verified using the

reference detect and the burnout currents. The REF_DET_ERR

flag is set if the external reference REFIN2( ) is missing. The

burnout currents (available in the configuration registers) detect an

open wire. For example, if the thermocouple is not connected

and the burnout currents are enabled on the channel, the ADC

outputs a conversion that is equal to or close to full scale. For

best performance, enable the burnout currents periodically to

check the connections but disable them as soon as the connections

are verified for they add an error to the conversions. The

decoupling capacitors on the LDOs can also be checked. The

ADC indicates if the capacitor is not present.

As an example, the PT100 measures temperature from −200°C

to +600°C. The resistance is 100 Ω typically at 0°C and 313.71 Ω

at 600°C. If the 500 µA excitation currents are used, the

maximum voltage generated across the RTD when using the full

temperature range of the RTD is

As part of the conversion process, the analog input overvoltage/

undervoltage monitors are useful for detecting any excessive

voltages on AINP and AINM. The power supply voltages and

reference voltages are selectable as inputs to the ADC. Thus, the

user can periodically check these voltages to confirm whether

they are within the system specification. Also, the user can check

that the LDO voltages are within specification. The conversion

process and calibration process can also be checked. This ensures

that any invalid conversions or calibrations are flagged to the user.

500 µA × 313.71 Ω = 156.86 mV

This is amplified to 2.51 V within the AD7124-8 if the gain is

programmed to 16.

The voltage generated across the reference resistor must be at least

2.51 V. Therefore, the reference resistor value must equal at least

2.51 V/500 µA = 5020 Ω

Therefore, a 5.11 kΩ resistor can be used.

5.11 kΩ × Excitation Current = 5.11 kΩ × 500 µA = 2.555 V

Finally, the CRC check, SCLK counter, and the SPI read/write

checks make the interface more robust as any read/write

operation that is not valid is detected. The CRC check

highlights if any bits are corrupted when being transmitted

between the processor and the ADC.

One other consideration is the output compliance. The output

compliance equals AV_DD− 0.37 V. If a 3 .3 V analog supply is

used, the voltage at AIN0 must be less than (3.3 V − 0.37 V) =

2.93 V. From the previous calculations, this specification is met

because the maximum voltage at AIN0 equals the voltage across

the reference resistor plus the voltage across the RTD, which equals

2.555 V + 156.86 mV = 2.712 V

Rev. D | Page 73 of 92

AD7124-8

Data Sheet

A typical procedure for reading the RTD is as follows:

The power mode to use depends on the performance required

from the system along with the current consumption allowance

for the system. In a field transmitter, low current consumption

is essential. In this application, the low power mode or mid power

mode is most suitable. In process control applications, power

consumption is not a priority. Thus, full power mode may be

selected. The full power mode offers higher throughput and

lower noise.

1. Reset the ADC.

2. Select the power mode.

3. Set the CHANNEL_0 register analog input to AIN1/AIN2.

Assign Setup 0 to this channel. Configure Setup 0 to have a

gain of 16 and select the reference source REFIN2( ).

Select the filter type and set the output data rate.

4. Program the excitation currents to 500 µA and output the

currents on the AIN0 and AIN3 pins.

The AD7124-8 on-chip diagnostics allow the user to check the

circuit connections, monitor the power supply, reference, and

LDO voltages, check all conversions and calibrations for any

errors, as well as monitor any read/write operations. In RTD

applications, the circuit connections are verified using the

reference detect and the burnout currents. The REF_DET_ERR

flag is set if the external reference REFIN2( ) is missing. The

burnout currents (available in the configuration registers) detect an

open wire. The decoupling capacitors on the LDOs can also be

checked. The ADC indicates if the capacitor is not present.

RDY

5. Wait until

6. Repeat Step 4.

goes low. Read the conversion value.

In the processor, implement the linearization routine for the PT100.

The external antialias filter is omitted for clarity. However, such

a filter is required to reject any interference at the modulator

frequency and multiples of the modulator frequency. Also, some

filtering may be needed for EMI purposes. Both the analog inputs

and reference inputs can be buffered, which allows the user to

connect any RC combination to the reference or analog input pins.

As part of the conversion process, the analog input overvoltage/

undervoltage monitors are useful to detect any excessive voltages

on AINP and AINM. The power supply voltages and reference

voltages are selectable as inputs to the ADC. Thus, the user can

periodically check these voltages to confirm whether they are

within the system specification. Also, the user can check that

the LDO voltages are within specification. The conversion process

and calibration process can also be checked. This ensures that

any invalid conversions or calibrations are flagged to the user.

On the AD7124-8, the excitation currents can be made available

at the input pins, for example, the AIN3 pin can function as an

analog input as well as outputting the current source. This option

allows multiple sensors to be connected to the ADC using a

minimum pin count. However, the resistor of the antialiasing

filter is in series with the RTD. This introduces an error in the

conversions as there is a voltage generated across the antialiasing

resistor. To minimize the error, minimize the resistance of the

antialiasing filter.

Finally, the CRC check, SCLK counter, and the SPI read/write

checks make the interface more robust as any read/write

operation that is not valid is detected. The CRC check highlights if

any bits are corrupted when being transmitted between the

processor and the ADC.

AV_DD

V_BIAS

REFIN1(+)

AIN0

REFERENCE

DETECT

AV

DD

REFIN2(+)

REFIN2(–)

DOUT/RDY

SERIAL

R

REF

INTERFACE

AND

DIN

DIGITAL

FILTER

Σ-Δ

PGA

X-MUX

ADC

SCLK

CONTROL

LOGIC

RL1

RL2

AIN1

AIN2

AIN3

CS

RTD

CHANNEL

SEQUENCER

TEMP

SENSOR

IOV

DD

AV

SS

INTERNAL

CLOCK

RL3

V

DIAGNOSTICS

DD

CLK

REFIN1(–)

PSW

SYNC

AD7124-8

AV_SS

DGND

REGCAPA

REGCAPD

NOTES

1. SIMPLIFIED BLOCK DIAGRAM SHOWN.

Figure 130. 3-Wire RTD Application

Rev. D | Page 74 of 92

Data Sheet

AD7124-8

A typical procedure for reading the sensors is as follows:

FLOWMETER

1. Reset the ADC.

2. Select the power mode.

Figure 131 shows the AD7124-8 being used in a flowmeter

application that consists of two pressure transducers, with the

rate of flow being equal to the pressure difference. The pressure

transducers are arranged in a bridge network and give a differential

output voltage between its OUT+ and OUT− terminals. With

rated full-scale pressure (in this case, 300 mmHg) on the trans-

ducer, the differential output voltage is 3 mV/V of the input

voltage (that is, the voltage between the IN+ and IN− terminals).

3. Set the CHANNEL_0 register analog input to AIN0/AIN1.

Assign Setup 0 to this channel. Configure Setup 0 to have a

gain of 128 and select the reference source to REFIN1( ).

Select the filter type and set the output data rate.

4. Set the CHANNEL_1 register analog input to AIN2/AIN3.

Assign Setup 0 to this channel (both channels use the same

setup).

5. Set the CHANNEL_2 register analog input to AIN4/AIN5.

Assign Setup 1 to this channel. Configure Setup 1 to have a

gain of 1 and select the reference source REFIN2( ). Select

the filter type and set the output data rate.

Assuming a 3 V excitation voltage, the full-scale output range

from the transducer is 9 mV. The excitation voltage for the

bridge can directly provide the reference for the ADC, as the

reference input range includes the supply voltage.

A second advantage of using the AD7124-8 in transducer-based

applications is that the low-side power switch can be fully utilized

in low power applications. The low-side power switch is connected

in series with the cold side of the bridges. In normal operation,

the switch is closed and measurements are taken. In applications

where power is of concern, the AD7124-8 can be placed in standby

mode, thus significantly reducing the power consumed in the

application. In addition, the low-side power switch can be opened

while in standby mode, thus avoiding unnecessary power

consumption by the front-end transducers. When the device is

taken out of standby mode, and the low-side power switch is

closed, the user must ensure that the front-end circuitry is fully

settled before attempting a read from the AD7124-8. The power

switch can be closed prior to taking the device out of standby, if

needed. This allows time for the sensor to power up and settle

before the ADC powers up and begins sampling the analog input.

6. Program the excitation current and output the current on

the AIN4 pin.

7. Enable both CHANNEL_0 and CHANNEL_1. Enable the

DATA_STATUS bit to identify the channel from which the

conversion originated. The ADC automatically sequences

through these channels.

RDY

8. Wait until

goes low. Read the conversion value.

9. Repeat Step 8 until the temperature is to be read (every 10

conversions of the pressure sensor readings, for example).

10. Disable CHANNEL_0 and CHANNEL_1. Enable

CHANNEL_2.

RDY

11. Wait until

goes low. Read the conversion.

12. Repeat Step 6 to Step 10.

In the processor, the conversion information is converted to

pressure and the flow rate can be calculated. The processor

typically contains a lookup table for each pressure sensor so its

variation with temperature can be compensated.

In the diagram, temperature compensation is performed using a

thermistor. The on-chip excitation current supplies the thermistor.

In addition, the reference voltage for the temperature measurement

is derived from a precision resistor in series with the thermistor.

This allows a ratiometric measurement so that variation of the

excitation current has no effect on the measurement (it is the

ratio of the precision reference resistance to the thermistor

resistance that is measured).

The external antialias filter is omitted for clarity. However, such

a filter is required to reject any interference at the modulator

frequency and multiples of the modulator frequency. Also,

some filtering may be needed for EMI purposes. Both the

analog inputs and reference inputs can be buffered, which

allows the user to connect any RC combination to the reference

or analog input pins.

If the sensor sensitivity is 3 mV/V and the excitation voltage is 3 V,

the maximum output from the sensor is 9 mV. The AD7124-8

PGA can be set to 128 to amplify the sensor signal.

The power mode to use depends on the performance required

from the system along with the current consumption allowance

for the system. In a field transmitter, low current consumption

is essential. In this application, low power mode or mid power

mode is most suitable. In process control applications, power

consumption is not a priority. Thus, full power mode may be

selected. Full power mode offers higher throughput and lower

noise.

The AD7124-8 PGA amplifies the signal to

9 mV × 128 = 1.152 V

This value does not exceed the reference voltage (3 V).

Rev. D | Page 75 of 92

AD7124-8

Data Sheet

The AD7124-8 on-chip diagnostics allow the user to check the

circuit connections, monitor power supply, reference, and LDO

voltages, check all conversions and calibrations for any errors, as

well as monitor any read/write operations. The REF_DET_ERR

flag is set if the external reference REFIN2( ) or REFIN1( ) is

missing. The decoupling capacitors on the LDOs can also be

checked. The ADC indicates if the capacitor is not present.

within the system specification. In addition, the user can check

that the LDO voltages are within specification. The conversion

process and calibration process can also be checked. This ensures

that any invalid conversions or calibrations are flagged to the

user.

Finally, the CRC check, SCLK counter, and the SPI read/write

checks make the interface more robust as any read/write operation

that is not valid is detected. The CRC check highlights if any bits

are corrupted when being transmitted between the processor and

the ADC.

As part of the conversion process, the analog input overvoltage/

undervoltage monitors are useful to detect any excessive voltages

on AINP and AINM. The power supply voltages and reference

voltages are selectable as inputs to the ADC. Thus, the user can

periodically check these voltages to confirm whether they are

AV

DD

AV

REFIN1(+)

DD

IN+

OUT–

V

BIAS

OUT+

AIN0

REFERENCE

DETECT

AIN1

AIN2

AV

DD

IN+

IN–

AIN3

AIN4

AIN5

REFIN2(+)

OUT–

OUT+

DOUT/RDY

SERIAL

INTERFACE

AND

DIN

DIGITAL

FILTER

Σ-Δ

ADC

PGA

X-MUX

SCLK

CONTROL

LOGIC

REFIN2(–)

CS

CHANNEL

SEQUENCER

TEMP

SENSOR

R

REF

AV

SS

IOV

DD

INTERNAL

CLOCK

VDD

DIAGNOSTICS

CLK

REFIN1(–)

PSW

SYNC

AD7124-8

AV

SS

AV

SS

DGND

REGCAPA

REGCAPD

NOTES

1. SIMPLIFIED BLOCK DIAGRAM SHOWN.

Figure 131. Flowmeter Application

Rev. D | Page 76 of 92

Data Sheet

AD7124-8

ON-CHIP REGISTERS

The ADC is controlled and configured via a number of on-chip registers that are described in the following sections. In the following

descriptions, set implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted.

Table 63. Register Summary

Addr. Name

0x00 COMMS

0x00 Status

Bit 7

WEN

RDY

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

RS[5:0]

Bit 1

Bit 0

Reset

0x00

RW

W

R/

ERROR_FLAG

0

POR_FLAG

CH_ACTIVE

CS

_EN

0x00

R

0x01 ADC_

CONTROL

RDY

CONT_READ

DATA_STATUS

REF_EN

0x0000

RW

DOUT_

DEL

_

POWER_MODE

Mode

CLK_SEL

0x02 Data

Data [23:16]

Data [15:8]

Data [7:0]

0x000000

R

0x03 IO_

CONTROL_1

GPIO_DAT4

PDSW

GPIO_DAT3

0

GPIO_DAT2

GPIO_DAT1

IOUT1

GPIO_CTRL4

GPIO_CTRL3

GPIO_CTRL2

IOUT0

GPIO_CTRL1

RW

IOUT1_CH

IOUT0_CH

0x04 IO_

CONTROL_2

VBIAS15

VBIAS7

VBIAS14

VBIAS6

VBIAS13

VBIAS5

VBIAS12

VBIAS4

VBIAS11

VBIAS3

VBIAS10

VBIAS2

VBIAS9

VBIAS1

VBIAS8

VBIAS0

0x0000

0x14

0x05 ID

DEVICE_ID

SILICON_REVISION

R

0x06 Error

0

LDO_CAP_ERR

REF_DET_ERR

ADC_CAL_ERR

ADC_CONV_

ERR

ADC_SAT_ERR 0x000000

AINP_OV_ERR

AINP_UV_ERR

AINM_OV_ERR

AINM_UV_

ERR

0

DLDO_PSM_

ERR

0

ALDO_PSM_

ERR

SPI_IGNORE_

ERR

SPI_SCLK_CNT_ SPI_READ_

ERR ERR

SPI_WRITE_

ERR

SPI_CRC_ERR

MM_CRC_ERR

ROM_CRC_ERR

0x07 ERROR_EN

0

MCLK_CNT_EN LDO_CAP_CHK_

TEST_EN

LDO_CAP_CHK

ADC_CAL_ERR_ ADC_CONV_

ADC_SAT_

ERR_EN

0x000040

RW

EN

ERR_EN

AINP_OV_ERR_ AINP_UV_ERR_ AINM_OV_ERR_ AINM_UV_

REF_DET_ERR_

EN

DLDO_PSM_

TRIP_TEST_EN

DLDO_PSM_

ERR_EN

ALDO_PSM_

TRIP_TEST_EN

EN

SPI_SCLK_CNT_ SPI_READ_

ERR_EN ERR_EN

ERR_EN

ALDO_PSM_

ERR_EN

SPI_IGNORE_

ERR_EN

SPI_WRITE_

ERR_EN

SPI_CRC_ERR_EN MM_CRC_ERR_ ROM_CRC_

EN

ERR_EN

0x08 MCLK_

COUNT

MCLK_COUNT

0x00

R

0x09 CHANNEL_0

Enable

Setup

0

AINP[4:3]

0x8001¹

RW

to

AINP[2:0]

AINM[4:0]

0x18 CHANNEL_15

0x19 CONFIG_0 to

0

Bipolar

REF_SEL

Burnout

REF_BUFP

0x0860

RW

to

CONFIG_7

REF_BUFM

AIN_BUFP

Filter

AIN_BUFM

PGA

0x20

0x21 FILTER_0 to

REJ60

POST_FILTER

SINGLE_CYCLE 0x060180

0x800000

to

FILTER_7

0

FS[10:8]

0x28

FS[7:0]

0x29 OFFSET_0 to

Offset [23:16]

Offset [15:8]

Offset [7:0]

Gain [23:16]

Gain [15:8]

Gain [7:0]

RW

to

OFFSET_7

0x30

0x31 GAIN_0 to

0x5XXXXX RW

to

GAIN_7

0x38

¹CHANNEL_0 is reset to 0x8001. All other channels are reset to 0x0000.

Rev. D | Page 77 of 92

AD7124-8

Data Sheet

communications register. This is the default state of the interface

and, on power-up or after a reset, the ADC is in this default state

waiting for a write operation to the communications register.

COMMUNICATIONS REGISTER

RS[5:0] = 0, 0, 0, 0, 0, 0

The communications register is an 8-bit, write only register. All

communications to the device must start with a write operation

to the communications register. The data written to the communi-

cations register determines whether the next operation is a read

or write operation, and to which register this operation takes

place, the RS[5:0] bits selecting the register to be accessed.

In situations where the interface sequence is lost, a write

operation of at least 64 serial clock cycles with DIN high returns

the ADC to this default state by resetting the entire device.

Table 64 outlines the bit designations for the communications

register. Bit 7 denotes the first bit of the data stream.

For read or write operations, after the subsequent read or write

operation to the selected register is complete, the interface

returns to where it expects a write operation to the

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

RS[5:0] (0)

Bit 1

Bit 0

WEN (0)

R/W (0)

Table 64. Communications Register Bit Descriptions

Bits

Bit Name

Description

7

WEN

Write enable bit. A 0 must be written to this bit so that the write to the communications register actually occurs. If

a 1 is the first bit written, the device does not clock on to subsequent bits in the register. It stays at this bit location

until a 0 is written to this bit. As soon as a 0 is written to the WEN bit, the next seven bits are loaded to the

communications register.

6

R/W

A 0 in this bit location indicates that the next operation is a write to a specified register. A 1 in this position

indicates that the next operation is a read from the designated register.

5:0

RS[5:0]

Register address bits. These address bits select which registers of the ADC are being selected during this serial

interface communication. See Table 63.

STATUS REGISTER

RS[5:0] = 0, 0, 0, 0, 0, 0

Power-On/Reset = 0x00

The status register is an 8-bit, read only register. To access the ADC status register, the user must write to the communications register,

select the next operation to be read, and set the register address bits RS[5:0] to 0.

Table 65 outlines the bit designations for the status register. Bit 7 denotes the first bit of the data stream. The number in parentheses

indicates the power-on/reset default status of that bit.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RDY (0)

ERROR_FLAG (0) 0 (0)

POR_FLAG (0)

CH_ACTIVE (0)

Table 65. Status Register Bit Descriptions

Bits

Bit Name

Description

7

RDY

Ready bit for the ADC. This bit is cleared when data is written to the ADC data register. The RDY bit is set

automatically after the ADC data register is read or a period of time before the data register is updated with a

new conversion result to indicate to the user not to read the conversion data. It is also set when the device is

placed in power-down or standby mode. The end of a conversion is also indicated by the DOUT/RDY pin. This

pin can be used as an alternative to the status register for monitoring the ADC for conversion data.

6

ERROR_FLAG

ADC error bit. This bit indicates if one of the error bits has been asserted in the error register. This bit is high if

one or more of the error bits in the error register has been set. This bit is cleared by a read of the error register.

5

4

0

This bit is set to 0.

POR_FLAG

Power-on reset flag. This bit indicates when a power-on reset occurs. A power-on reset occurs on power-up,

when the power supply voltage goes below a threshold voltage, when a reset is performed, and when coming

out of power-down mode. The status register must be read to clear the bit.

Rev. D | Page 78 of 92

Data Sheet

AD7124-8

Bits

Bit Name

Description

3:0

CH_ACTIVE

These bits indicate which channel is being converted by the ADC.

0000 = Channel 0.

0001 = Channel 1.

0010 = Channel 2.

0011 = Channel 3.

0100 = Channel 4.

0101 = Channel 5.

0110 = Channel 6.

0111 = Channel 7.

1000 = Channel 8.

1001 = Channel 9.

1010 = Channel 10.

1011 = Channel 11.

1100 = Channel 12.

1101 = Channel 13.

1110 = Channel 14.

1111 = Channel 15.

ADC_CONTROL REGISTER

RS[5:0] = 0, 0, 0, 0, 0, 1

Power-On/Reset = 0x0000

Table 66 outlines the bit designations for the register. Bit 15 is the first bit of the data stream. The number in parentheses indicates the

power-on/reset default status of that bit.

Bit 7

Bit 6

0 (0)

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0 (0)

DOUT_RDY_DEL (0)

CONT_READ (0) DATA_STATUS (0) CS_EN (0)

REF_EN (0)

POWER_MODE (0)

Mode (0)

CLK_SEL (0)

Table 66. ADC Control Register Bit Descriptions

Bits

15:13

12

Bit Name

Description

0

These bits must be programmed with a Logic 0 for correct operation.

DOUT_RDY_DEL

Controls the SCLK inactive edge to DOUT/RDY high time. When DOUT_RDY_DEL is cleared, the delay is

10 ns minimum. When DOUT_RDY_DEL is set, the delay is increased to 100 ns minimum. This function is

useful when CS is tied low (the CS_EN bit is set to 0).

11

CONT_READ

Continuous read of the data register. When this bit is set to 1 (and the data register is selected), the serial

interface is configured so that the data register can be continuously read; that is, the contents of the data

register are automatically placed on the DOUT pin when the SCLK pulses are applied after the RDY pin

goes low to indicate that a conversion is complete. The communications register does not have to be

written to for subsequent data reads. To enable continuous read, the CONT_READ bit is set. To disable

continuous read, write a read data command while the DOUT/ RDY pin is low. While continuous read is

enabled, the ADC monitors activity on the DIN line so that it can receive the instruction to disable

continuous read. Additionally, a reset occurs if 64 consecutive 1s occur on DIN; therefore, hold DIN low

until an instruction is written to the device.

10

9

DATA_STATUS

CS_EN

This bit enables the transmission of the status register contents after each data register read. When

DATA_STATUS is set, the contents of the status register are transmitted along with each data register

read. This function is useful when several channels are selected because the status register identifies the

channel to which the data register value corresponds.

This bit controls the operation of the DOUT/RDY pin during read operations.

When CS_EN is cleared, the DOUT pin returns to being a RDY pin within nanoseconds of the SCLK

inactive edge (the delay is determined by the DOUT_RDY_DEL bit).

When set, the DOUT/RDY pin continues to output the LSB of the register being read until CS is taken

high. CS must frame all read operations when CS_EN is set. CS_EN must be set to use the diagnostic

functions SPI_WRITE_ERR, SPI_READ_ERR, and SPI_SCLK_CNT_ERR.

Rev. D | Page 79 of 92

AD7124-8

Data Sheet

Bits

Bit Name

Description

8

REF_EN

Internal reference voltage enable. When this bit is set, the internal reference is enabled and available at

the REFOUT pin. When this bit is cleared, the internal reference is disabled.

7:6

POWER_MODE

Power Mode Select. These bits select the power mode. The current consumption and output data rate

ranges are dependent on the power mode.

00 = low power.

01 = mid power.

10 = full power.

11 = full power.

5:2

1:0

Mode

These bits control the mode of operation for ADC. See Table 67.

CLK_SEL

These bits select the clock source for the ADC. Either the on-chip 614.4 kHz clock can be used or an

external clock can be used. The ability to use an external clock allows several AD7124-8 devices to be

synchronized. Also, 50 Hz and 60 Hz rejection is improved when an accurate external clock drives the ADC.

00 = internal 614.4 kHz clock. The internal clock is not available at the CLK pin.

01 = internal 614.4 kHz clock. This clock is available at the CLK pin.

10 = external 614.4 kHz clock.

11 = external clock. The external clock is divided by 4 within the AD7124-8.

Table 67. Operating Modes

Mode

Value

Description

0000

Continuous conversion mode (default). In continuous conversion mode, the ADC continuously performs conversions and places

the result in the data register. RDY goes low when a conversion is complete. The user can read these conversions by placing the device

in continuous read mode whereby the conversions are automatically placed on the DOUT line when SCLK pulses are applied.

Alternatively, the user can instruct the ADC to output the conversion by writing to the communications register. After power-on,

a reset, or a reconfiguration of the ADC, the complete settling time of the filter is required to generate the first valid conversion.

Subsequent conversions are available at the selected output data rate, which is dependent on filter choice.

0001

0010

Single conversion mode. When single conversion mode is selected, the ADC powers up and performs a single conversion on the

selected channel. The conversion requires the complete settling time of the filter. The conversion result is placed in the data

register, RDY goes low, and the ADC returns to standby mode. The conversion remains in the data register and RDY remains

active (low) until the data is read or another conversion is performed.

Standby mode. In standby mode, all sections of the AD7124-8 can be powered down except the LDOs. The internal reference, on-

chip oscillator, low-side power switch, and bias voltage generator can be enabled or disabled while in standby mode. The on-

chip registers retain their contents in standby mode.

Any enabled diagnostics remain active when the ADC is in idle mode. The diagnostics can be enabled/disabled while in standby

mode. However, any diagnostics that require the master clock (reference detect, undervoltage/overvoltage detection, LDO trip

tests, memory map CRC, and MCLK counter) must be enabled when the ADC is in continuous conversion mode or idle mode;

these diagnostics do not function if enabled in standby mode.

0011

Power-down mode. In power-down mode, all the AD7124-8 circuitry is powered down, including the current sources, power

switch, burnout currents, bias voltage generator, and clock circuitry. The LDOs are also powered down. In power-down mode, the

on-chip registers do not retain their contents. Therefore, coming out of power-down mode, all registers must be reprogrammed.

0100

0101

Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks continue to be

provided.

Internal zero-scale (offset) calibration. An internal short is automatically connected to the input. RDY goes high when the

calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following a calibration.

The measured offset coefficient is placed in the offset register of the selected channel. Select only one channel when zero-scale

calibration is being performed. An internal zero-scale calibration takes a time of one settling period to be performed.

0110

Internal full-scale (gain) calibration. A full-scale input voltage is automatically connected to the selected analog input for this

calibration. RDY goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed

in idle mode following a calibration. The measured full-scale coefficient is placed in the gain register of the selected channel. A

full-scale calibration is required each time the gain of a channel is changed to minimize the full-scale error. Select only one

channel when full-scale calibration is being performed. An internal full-scale calibration takes a time of one settling period to be

performed when the gain is set to 1 and four settling periods for gains greater than one.

Internal full-scale calibrations cannot be performed in the full power mode. So, if using the full-power mode, select mid or low

power mode for the internal full-scale calibration. This calibration is valid in full power mode as the same reference and gain are

used. When performing internal zero-scale and internal full-scale calibrations, the internal full-scale calibration must be

performed before the internal zero-scale calibration. Therefore, write 0x800000 to the offset register before performing any

internal full-scale calibration, which resets the offset register to its default value.

Rev. D | Page 80 of 92

Data Sheet

AD7124-8

Mode

Value

Description

0111

System zero-scale (offset) calibration. Connect the system zero-scale input to the channel input pins of the selected channel. RDY

goes high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode

following a calibration. The measured offset coefficient is placed in the offset register of the selected channel. A system zero-

scale calibration is required each time the gain of a channel is changed. Select only one channel when full-scale calibration is

being performed. A system zero-scale calibration takes a time of one settling period to be performed.

1000

System full-scale (gain) calibration. Connect the system full-scale input to the channel input pins of the selected channel. RDY goes

high when the calibration is initiated and returns low when the calibration is complete. The ADC is placed in idle mode following

a calibration. The measured full-scale coefficient is placed in the gain register of the selected channel. A full-scale calibration is

required each time the gain of a channel is changed. Select only one channel when full-scale calibration is being performed. A

system full-scale calibration takes a time of one settling period to be performed.

1001

Reserved.

to1111

DATA REGISTER

RS[5:0] = 0, 0, 0, 0, 1, 0

Power-On/Reset = 0x000000

The conversion result from the ADC is stored in this data register. This is a read-only register. On completion of a read operation from

RDY

this register, the

bit/pin is set.

IO_CONTROL_1 REGISTER

RS[5:0] = 0, 0, 0, 0, 1, 1

Power-On/Reset = 0x000000

Table 68 outlines the bit designations for the register. Bit 23 is the first bit of the data stream. The number in parentheses indicates the

power-on/reset default status of that bit.

Bit 7

GPIO_DAT4 (0) GPIO_DAT3 (0) GPIO_DAT2 (0) GPIO_DAT1 (0) GPIO_CTRL4 (0) GPIO_CTRL3 (0) GPIO_CTRL2 (0) GPIO_CTRL1 (0)

PDSW (0) 0 (0) IOUT1 (0) IOUT0 (0)

IOUT0_CH (0)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

IOUT1_CH (0)

Table 68. IO_CONTROL_1 Register Bit Descriptions

Bits

Bit Name

Description

23

GPIO_DAT4

Digital Output P4. When GPIO_CTRL4 is set, the GPIO_DAT4 bit sets the value of the P4 general-purpose

output pin. When GPIO_DAT4 is high, the P4 output pin is high. When GPIO_DAT4 is low, the P4 output

pin is low. When the IO_CONTROL_1 register is read, the GPIO_DAT4 bit reflects the status of the P4 pin if

GPIO_CTRL4 is set.

22

21

20

19

GPIO_DAT3

GPIO_DAT2

GPIO_DAT1

GPIO_CTRL4

Digital Output P3. When GPIO_CTRL3 is set, the GPIO_DAT3 bit sets the value of the P3 general-purpose

output pin. When GPIO_DAT3 is high, the P3 output pin is high. When GPIO_DAT3 is low, the P3 output

pin is low. When the IO_CONTROL_1 register is read, the GPIO_DAT3 bit reflects the status of the P3 pin if

GPIO_CTRL3 is set.

Digital Output P2. When GPIO_CTRL2 is set, the GPIO_DAT2 bit sets the value of the P2 general-purpose

output pin. When GPIO_DAT2 is high, the P2 output pin is high. When GPIO_DAT2 is low, the P2 output

pin is low. When the IO_CONTROL_1 register is read, the GPIO_DAT2 bit reflects the status of the P2 pin if

GPIO_CTRL2 is set.

Digital Output P1. When GPIO_CTRL1 is set, the GPIO_DAT1 bit sets the value of the P1 general-purpose

output pin. When GPIO_DAT1 is high, the P1 output pin is high. When GPIO_DAT1 is low, the P1 output

pin is low. When the IO_CONTROL_1 register is read, the GPIO_DAT1 bit reflects the status of the P1 pin if

GPIO_CTRL1 is set.

Digital Output P4 enable. When GPIO_CTRL4 is set, the digital output P4 is active. When GPIO_CTRL4 is

cleared, the pin functions as analog input pin AIN5.

Rev. D | Page 81 of 92

AD7124-8

Data Sheet

Bits

Bit Name

Description

18

GPIO_CTRL3

GPIO_CTRL2

GPIO_CTRL1

PDSW

Digital Output P3 enable. When GPIO_CTRL3 is set, the digital output P3 is active. When GPIO_CTRL3 is

cleared, the pin functions as analog input pin AIN4.

17

16

15

Digital Output P2 enable. When GPIO_CTRL2 is set, the digital output P2 is active. When GPIO_CTRL2 is

cleared, the pin functions as analog input pin AIN3.

Digital Output P1 enable. When GPIO_CTRL1 is set, the digital output P1 is active. When GPIO_CTRL1 is

cleared, the pin functions as analog input pin AIN2.

Bridge power-down switch control bit. Set this bit to close the bridge power-down switch PDSW to

AGND. The switch can sink up to 30 mA. Clear this bit to open the bridge power-down switch. When the

ADC is placed in standby mode, the bridge power-down switch remains active.

14

0

This bit must be programmed with a Logic 0 for correct operation.

These bits set the value of the excitation current for IOUT1.

000 = off.

13:11

IOUT1

001 = 50 µA.

010 = 100 µA

011 = 250 µA.

100 = 500 µA.

101 = 750 µA.

110 = 1000 µA

111 = 1000 µA.

10:8

IOUT0

These bits set the value of the excitation current for IOUT0.

000 = off.

001 = 50 µA.

010 = 100 µA

011 = 250 µA.

100 = 500 µA.

101 = 750 µA.

110 = 1000 µA

111 = 1000 µA.

7:4

IOUT1_CH

Channel select bits for the excitation current for IOUT1.

0000 = IOUT1 is available on the AIN0 pin.

0001 = IOUT1 is available on the AIN1 pin.

0010 = IOUT1 is available on the AIN2 pin.

0011 = IOUT1 is available on the AIN3 pin.

0100 = IOUT1 is available on the AIN4 pin.

0101 = IOUT1 is available on the AIN5 pin.

0110 = IOUT1 is available on the AIN6 pin.

0111 = IOUT1 is available on the AIN7 pin.

1000 = IOUT1 is available on the AIN8 pin.

1001 = IOUT1 is available on the AIN9 pin.

1010 = IOUT1 is available on the AIN10 pin.

1011 = IOUT1 is available on the AIN11 pin.

1100 = IOUT1 is available on the AIN12 pin.

1101 = IOUT1 is available on the AIN13 pin.

1110 = IOUT1 is available on the AIN14 pin.

0111 = IOUT1 is available on the AIN15 pin.

Rev. D | Page 82 of 92

Data Sheet

AD7124-8

Bits

Bit Name

IOUT0_CH

Description

3:0

Channel select bits for the excitation current for IOUT0.

0000 = IOUT0 is available on the AIN0 pin.

0001 = IOUT0 is available on the AIN1 pin.

0010 = IOUT0 is available on the AIN2 pin.

0011 = IOUT0 is available on the AIN3 pin.

0100 = IOUT0 is available on the AIN4 pin.

0101 = IOUT0 is available on the AIN5 pin.

0110 = IOUT0 is available on the AIN6 pin.

0111 = IOUT0 is available on the AIN7 pin.

1000 = IOUT0 is available on the AIN8 pin.

1001 = IOUT0 is available on the AIN9 pin.

1010 = IOUT0 is available on the AIN10 pin.

1011 = IOUT0 is available on the AIN11 pin.

1100 = IOUT0 is available on the AIN12 pin.

1101 = IOUT0 is available on the AIN13 pin.

1110 = IOUT0 is available on the AIN14 pin.

1111 = IOUT0 is available on the AIN15 pin.

IO_CONTROL_2 REGISTER

RS[5:0] = 0, 0, 0, 1, 0, 0

Power-On/Reset = 0x0000

Table 69 outlines the bit designations for the register. Bit 15 is the first bit of the data stream. The number in parentheses indicates the

power-on/reset default status of that bit. The internal bias voltage can be enabled on multiple channels.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

VBIAS15 (0)

VBIAS7 (0)

VBIAS14 (0)

VBIAS6 (0)

VBIAS13 (0)

VBIAS5 (0)

VBIAS12 (0)

VBIAS4 (0)

VBIAS11 (0)

VBIAS3 (0)

VBIAS10 (0)

VBIAS2 (0)

VBIAS9 (0)

VBIAS1 (0)

VBIAS8 (0)

VBIAS0 (0)

Table 69. IO_CONTROL_2 Register Bit Descriptions

Bits

15

14

13

12

11

10

9

8

7

6

5

Bit Name

VBIAS15

VBIAS14

VBIAS13

VBIAS12

VBIAS11

VBIAS10

VBIAS9

VBIAS8

VBIAS7

VBIAS6

VBIAS5

VBIAS4

VBIAS3

VBIAS2

VBIAS1

VBIAS0

Description

Enable the bias voltage on the AIN15 channel. When set, the internal bias voltage is available on AIN15.

Enable the bias voltage on the AIN14 channel. When set, the internal bias voltage is available on AIN14.

Enable the bias voltage on the AIN13 channel. When set, the internal bias voltage is available on AIN13.

Enable the bias voltage on the AIN12 channel. When set, the internal bias voltage is available on AIN12.

Enable the bias voltage on the AIN11 channel. When set, the internal bias voltage is available on AIN11.

Enable the bias voltage on the AIN10 channel. When set, the internal bias voltage is available on AIN10.

Enable the bias voltage on the AIN9 channel. When set, the internal bias voltage is available on AIN9.

Enable the bias voltage on the AIN8 channel. When set, the internal bias voltage is available on AIN8.

Enable the bias voltage on the AIN7 channel. When set, the internal bias voltage is available on AIN7.

Enable the bias voltage on the AIN6 channel. When set, the internal bias voltage is available on AIN6.

Enable the bias voltage on the AIN5 channel. When set, the internal bias voltage is available on AIN5.

Enable the bias voltage on the AIN4 channel. When set, the internal bias voltage is available on AIN4.

Enable the bias voltage on the AIN3 channel. When set, the internal bias voltage is available on AIN3.

Enable the bias voltage on the AIN2 channel. When set, the internal bias voltage is available on AIN2.

Enable the bias voltage on the AIN1 channel. When set, the internal bias voltage is available on AIN1.

Enable the bias voltage on the AIN0 channel. When set, the internal bias voltage is available on AIN0.

4

3

2

1

0

Rev. D | Page 83 of 92

AD7124-8

Data Sheet

ID REGISTER

RS[5:0] = 0, 0, 0, 1, 0, 1

Power-On/Reset = 0x14

The identification number for the AD7124-8 is stored in the ID register. This is a read only register.

ERROR REGISTER

RS[5:0] = 0, 0, 0, 1, 1, 0

Power-On/Reset = 0x000000

Diagnostics, such as checking overvoltages and checking the SPI interface, are included on the AD7124-8. The error register contains the

flags for the different diagnostic functions. The functions are enabled and disabled using the ERROR_EN register.

Table 70 outlines the bit designations for the register. Bit 23 is the first bit of the data stream. The number in parentheses indicates the

power-on/reset default status of that bit.

Bit 7

Bit 6

Bit 5

0 (0)

Bit 4

Bit 3

LDO_CAP_ERR

(0)

Bit 2

Bit 1

Bit 0

ADC_CAL_ERR ADC_CONV_ERR ADC_SAT_ERR

(0)

AINP_OV_ERR

(0)

AINP_UV_ERR (0) AINM_OV_ERR (0)

AINM_UV_ERR REF_DET_ERR

(0) (0)

0 (0)

DLDO_PSM_ERR 0 (0)

(0)

ALDO_PSM_ERR SPI_IGNORE_ERR SPI_SCLK_CNT_ERR SPI_READ_ERR SPI_WRITE_ERR SPI_CRC_ERR

(0) (0) (0) (0) (0) (0)

MM_CRC_ERR

(0)

ROM_CRC_ERR

(0)

Table 70. Error Register Bit Descriptions

Bits

23:20

19

Bit Name

Description

0

These bits must be programmed with a Logic 0 for correct operation.

Analog/digital LDO decoupling capacitor check. This flag is set if the decoupling capacitors required for the

analog and digital LDOs are not connected to the AD7124-8.

LDO_CAP_ERR

18

ADC_CAL_ERR

Calibration check. If a calibration is initiated but not completed, this flag is set to indicate that an error

occurred during the calibration. The associated calibration register is not updated.

17

16

15

14

13

12

11

ADC_CONV_ERR

ADC_SAT_ERR

AINP_OV_ERR

AINP_UV_ERR

AINM_OV_ERR

AINM_UV_ERR

REF_DET_ERR

This bit indicates whether a conversion is valid. This flag is set if an error occurs during a conversion.

ADC saturation flag. This flag is set if the modulator is saturated during a conversion.

Overvoltage detection on AINP.

Undervoltage detection on AINP.

Overvoltage detection on AINM.

Undervoltage detection on AINM.

Reference detection. This flag indicates when the external reference being used by the ADC is open circuit or

less than 0.7 V.

10

9

8

7

6

0

This bit must be programmed with a Logic 0 for correct operation.

Digital LDO error. This flag is set if an error is detected with the digital LDO.

This bit must be programmed with a Logic 0 for correct operation.

Analog LDO error. This flag is set if an error is detected with the analog LDO voltage.

When a CRC check of the internal registers is being performed, the on-chip registers cannot be written to.

User write instructions are ignored by the ADC. This bit is set when the CRC check of the registers is

occurring. The bit is cleared when the check is complete; write operations can only be performed then.

DLDO_PSM_ERR

0

ALDO_PSM_ERR

SPI_IGNORE_ERR

5

SPI_SCLK_CNT_ERR All serial communications are some multiple of eight bits. This bit is set when the number of SCLK cycles is

not a multiple of eight.

4

3

2

1

SPI_READ_ERR

SPI_WRITE_ERR

SPI_CRC_ERR

MM_CRC_ERR

This bit is set when an error occurs during an SPI read operation.

This bit is set when an error occurs during an SPI write operation.

This bit is set if an error occurs in the CRC check of the serial communications.

Memory map error. A CRC calculation is performed on the memory map each time that the registers are

written to. Following this, periodic CRC checks are performed on the on-chip registers. If the register

contents have changed, the MM_CRC_ERR bit is set.

0

ROM_CRC_ERR

ROM error. A CRC calculation is performed on the ROM contents (contains the default register values) on

power-up. If the contents have changed, the ROM_CRC_ERR bit is set.

Rev. D | Page 84 of 92

Data Sheet

AD7124-8

ERROR_EN REGISTER

RS[5:0] = 0, 0, 0, 1, 1, 1

Power-On/Reset = 0x000040

All the diagnostic functions can be enabled or disabled by setting the appropriate bits in this register.

Table 71 outlines the bit designations for the register. Bit 23 is the first bit of the data stream. The number in parentheses indicates the

power-on/reset default status of that bit.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0 (0)

MCLK_CNT_

EN (0)

LDO_CAP_CHK_

TEST_EN (0)

LDO_CAP_CHK (0)

ADC_CAL_ERR_

EN (0)

ADC_CONV_ERR_

EN (0)

ADC_SAT_

ERR_EN (0)

AINP_OV_

ERR_EN (0)

AINP_UV_

ERR_EN (0)

AINM_OV_ERR_

EN (0)

AINM_UV_

ERR_EN (0)

REF_DET_ERR_

EN (0)

DLDO_PSM_

TRIP_TEST_EN (0)

DLDO_PSM_ERR_

EN (0)

ALDO_PSM_

TRIP_TEST_EN (0)

ALDO_PSM_

ERR_EN (0)

SPI_IGNORE_

ERR_EN (0)

SPI_SCLK_CNT_

ERR_EN (0)

SPI_READ_

ERR_EN (0)

SPI_WRITE_

ERR_EN (0)

SPI_CRC_ERR_

EN (0)

MM_CRC_ERR_

EN (0)

ROM_CRC_ERR_

EN (0)

Table 71. ERROR_EN Register Bit Descriptions

Bits

Bit Name

Description

23

0

This bit must be programmed with a Logic 0 for correct operation.

22

MCLK_CNT_EN

Master clock counter. When this bit is set, the master clock counter is enabled and the result is

reported via the MCLK_COUNT register. The counter monitors the master clock being used by the

ADC. If an external clock is the clock source, the MCLK counter monitors this external clock.

Similarly, if the on-chip oscillator is selected as the clock source to the ADC, the MCLK counter

monitors the on-chip oscillator.

21

LDO_CAP_CHK_TEST_EN

LDO_CAP_CHK

Test of analog/digital LDO decoupling capacitor check. When this bit is set, the decoupling

capacitor is internally disconnected from the LDO, forcing a fault condition. This allows the user to

test the circuitry that is used for the analog and digital LDO decoupling capacitor check.

20:19

Analog/digital LDO decoupling capacitor check. These bits enable the capacitor check. When a

check is enabled, the ADC checks for the presence of the external decoupling capacitor on the

selected supply. When the check is complete, the LDO_CAP_CHK bits are both reset to 0.

00 = check is not enabled.

01 = check the analog LDO capacitor.

10 = check the digital LDO capacitor.

11 = check is not enabled.

18

17

ADC_CAL_ERR_EN

When this bit is set, the calibration fail check is enabled.

ADC_CONV_ERR_EN

When this bit is set, the conversions are monitored and the ADC_CONV_ERR bit is set when a

conversion fails.

16

15

14

13

12

11

ADC_SAT_ERR_EN

AINP_OV_ERR_EN

AINP_UV_ERR_EN

AINM_OV_ERR_EN

AINM_UV_ERR_EN

REF_DET_ERR_EN

When this bit is set, the ADC modulator saturation check is enabled.

When this bit is set, the overvoltage monitor on all enabled AINP channels is enabled.

When this bit is set, the undervoltage monitor on all enabled AINP channels is enabled.

When this bit is set, the overvoltage monitor on all enabled AINM channels is enabled.

When this bit is set, the undervoltage monitor on all enabled AINM channels is enabled.

When this bit is set, any external reference being used by the ADC is continuously monitored. An

error is flagged if the external reference is open circuit or has a value of less than 0.7 V.

10

9

DLDO_PSM_TRIP_TEST_EN Checks the test mechanism that monitors the digital LDO. When this bit is set, the input to the test

circuit is tied to DGND instead of the LDO output. Set the DLDO_PSM_ERR bit in the error register.

DLDO_PSM_ERR_ERR

When this bit is set, the digital LDO voltage is continuously monitored. The DLDO_PSM_ERR bit in

the error register is set if the voltage being output from the digital LDO is outside specification.

8

ALDO_PSM_TRIP_TEST_EN Checks the test mechanism that monitors the analog LDO. When this bit is set, the input to the

test circuit is tied to AV_SSinstead of the LDO output. Set the ALDO_PSM_ERR bit in the error

register.

7

6

ALDO_PSM_ERR_EN

SPI_IGNORE_ERR_EN

When this bit is set, the analog LDO voltage is continuously monitored. The ALDO_PSM_ERR bit in

the error register is set if the voltage being output from the analog LDO is outside specification.

When a CRC check of the internal registers is being performed, the on-chip registers cannot be

written to. User write instructions are ignored by the ADC. Set this bit so that the SPI_IGNORE_ERR

bit in the error register informs the user when write operations must not be performed.

Rev. D | Page 85 of 92

AD7124-8

Data Sheet

Bits

Bit Name

Description

5

SPI_SCLK_CNT_ERR_EN

When this bit is set, the SCLK counter is enabled. All read and write operations to the ADC are

multiples of eight bits. For every serial communication, the SCLK counter counts the number of

SCLK pulses. CS must be used to frame each read and write operation. If the number of SCLK

pulses used during a communication is not a multiple of eight, the SPI_SCLK_CNT_ERR bit in the

error register is set. For example, a glitch on the SCLK pin during a read or write operation can be

interpreted as an SCLK pulse. In this case, the SPI_SCLK_CNT_ERR bit is set as there is an excessive

number of SCLK pulses detected. CS_EN in the ADC_CONTROL register must be set to 1 when the

SCLK counter function is being used.

4

3

SPI_READ_ERR_EN

SPI_WRITE_ERR_EN

When this bit is set, the SPI_READ_ERR bit in the error register is set when an error occurs during a

read operation. An error occurs if the user attempts to read from invalid addresses.

CS_EN in the ADC_CONTROL register must be set to 1 when the SPI read check function is being

used.

When this bit is set, the SPI_WRITE_ERR bit in the error register is set when an error occurs during a

write operation. An error occurs if the user attempts to write to invalid addresses or write to read-

only registers. CS_EN in the ADC_CONTROL register must be set to 1 when the SPI write check

function is being used.

2

1

0

SPI_CRC_ERR_EN

MM_CRC_ERR_EN

ROM_CRC_ERR_EN

This bit enables a CRC check of all read and write operations. The SPI_CRC_ERR bit in the error

register is set if the CRC check fails. In addition, an 8-bit CRC word is appended to all data read

from the AD7124-8.

When this bit is set, a CRC calculation is performed on the memory map each time that the

registers are written to. Following this, periodic CRC checks are performed on the on-chip

registers. If the register contents have changed, the MM_CRC_ERR bit is set.

When this bit is set, a CRC calculation is performed on the ROM contents on power-on. If the ROM

contents have changed, the ROM_CRC_ERR bit is set.

MCLK_COUNT REGISTER

RS[5:0] = 0, 0, 1, 0, 0, 0

Power-On/Reset = 0x00

The master clock frequency can be monitored using this register.

Table 72 outlines the bit designations for the register. Bit 7 is the first bit of the data stream. The number in parentheses indicates the

power-on/reset default status of that bit.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MCLK_COUNT (0)

Table 72. MCLK_COUNT Register Bit Descriptions

Bits Bit Name Description

7:0

MCLK_COUNT This register allows the user to determine the frequency of the internal/external oscillator. Internally, a clock counter

increments every 131 pulses of the sampling clock (614.4 kHz in full power mode, 153.6 kHz in mid power mode,

and 768 kHz in low power mode). The 8-bit counter wraps around on reaching its maximum value. The counter

output is read back via this register.

Rev. D | Page 86 of 92

Data Sheet

AD7124-8

CHANNEL REGISTERS

RS[5:0] = 0, 0, 1, 0, 0, 1 to 0, 1, 1, 0, 0, 0

Power-On/Reset = 0x8001 for CHANNEL_0; all other channel registers are set to 0x0001

Sixteen channel registers are included on the AD7124-8, CHANNEL_0 to CHANNEL_15. The channel registers begin at Address 0x09

(CHANNEL_0) and end at Address 0x18 (CHANNEL_15). Via each register, the user can configure the channel (AINP input and AINM

input), enable or disable the channel, and select the setup. The setup is selectable from eight different options defined by the user. When

the ADC converts, it automatically sequences through all enabled channels. This allows the user to sample some channels multiple times

in a sequence, if required. In addition, it allows the user to include diagnostic functions in a sequence also.

Table 73 outlines the bit designations for the register. Bit 15 is the first bit of the data stream. The number in parentheses indicates the

power-on/reset default status of that bit.

Bit 7

Bit 6

AINP[2:0] (000)

Table 73. Channel Register Bit Descriptions

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Enable (1)

Setup (0)

(0)

0 (0)

AINP[4:3] (00)

AINM[4:0] (00001)

Bits

Bit Name

Description

15

Enable

Channel enable bit. Setting this bit enables the device channel for the conversion sequence. By default, only the

enable bit for Channel 0 is set. The order of conversions starts with the lowest enabled channel, then cycles

through successively higher channel numbers, before wrapping around to the lowest channel again.

When the ADC writes a result for a particular channel, the four LSBs of the status register are set to the channel

number, 0 to 15. This allows the channel the data corresponds to be identified. When the DATA_STATUS bit in the

ADC_CONTROL register is set, the contents of the status register are appended to each conversion when it is

read. Use this function when several channels are enabled to determine to which channel the conversion value

read corresponds.

14:12

Setup

Setup select. These bits identify which of the eight setups are used to configure the ADC for this channel. A setup

comprises a set of four registers: analog configuration, output data rate/filter selection, offset register, and gain

register. All channels can use the same setup, in which case the same 3-bit value must be written to these bits on

all active channels. Alternatively, up to eight channels can be configured differently.

11:10

9:5

0

These bits must be programmed with a Logic 0 for correct operation.

AINP[4:0]

Positive analog input AINP input select. These bits select which of the analog inputs is connected to the positive

input for this channel.

00000 = AIN0 (default).

00001 = AIN1.

00010 = AIN2.

00011 = AIN3.

00100 = AIN4.

00101 = AIN5.

00110 = AIN6.

00111 = AIN7.

01000 = AIN8.

01001 = AIN9.

01010 = AIN10.

01011 = AIN11.

01100 = AIN12.

01101 = AIN13.

01110 = AIN14.

01111 = AIN15.

10000 = temperature sensor.

10001 = AV_SS.

10010 = internal reference.

10011 = DGND.

10100 = (AV_DD− AV_SS)/6+. Use in conjunction with (AV_DD− AV_SS)/6− to monitor supply AV_DD− AV_SS.

10101 = (AV_DD− AV_SS)/6−. Use in conjunction with (AV_DD− AV_SS)/6+ to monitor supply AV_DD− AV_SS.

10110 = (IOV_DD− DGND)/6+. Use in conjunction with (IOV_DD− DGND)/6− to monitor IOV_DD− DGND.

10111 = (IOV_DD− DGND)/6−. Use in conjunction with (IOV_DD− DGND)/6+ to monitor IOV_DD− DGND.

Rev. D | Page 87 of 92

AD7124-8

Data Sheet

Bits

Bit Name

Description

11000 = (ALDO − AV_SS)/6+. Use in conjunction with (ALDO − AV_SS)/6− to monitor the analog LDO.

11001 = (ALDO − AV_SS)/6−. Use in conjunction with (ALDO − AV_SS)/6+ to monitor the analog LDO.

11010 = (DLDO − DGND)/6+. Use in conjunction with (DLDO − DGND)/6− to monitor the digital LDO.

11011 = (DLDO − DGND)/6−. Use in conjunction with (DLDO − DGND)/6+ to monitor the digital LDO.

11100 = V_20MV_P. Use in conjunction with V_20MV_M to apply a 20 mV p-p signal to the ADC.

11101 = V_20MV_M. Use in conjunction with V_20MV_P to apply a 20 mV p-p signal to the ADC.

11110 = Reserved.

11111 = Reserved.

4:0

AINM[4:0]

Negative analog input AINM input select. These bits select which of the analog inputs is connected to the

negative input for this channel.