AD712AH/+ [ADI]
IC IC,OP-AMP,DUAL,BIPOLAR/JFET,CAN,8PIN,METAL, Operational Amplifier;
| 型号： | AD712AH/+ |
| 厂家： | 
ADI |
| 描述： | IC IC,OP-AMP,DUAL,BIPOLAR/JFET,CAN,8PIN,METAL, Operational Amplifier 运算放大器 |
| 文件： | 总20页 (文件大小：435K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual Precision, Low Cost,
High Speed BiFET Op Amp
AD712
FEATURES
CONNECTION DIAGRAM
AMPLIFIER NO. 1
AMPLIFIER NO. 2
Enhanced replacement for LF412 and TL082
AC performance
1
8
V+
OUTPUT
INVERTING
INPUT
Settles to 0.01% in 1.0 μs
OUTPUT
2
3
4
7
6
5
16 V/μs minimum slew rate (AD712J)
3 MHz minimum unity-gain bandwidth (AD712J)
DC performance
INVERTING
INPUT
NONINVERTING
INPUT
NONINVERTING
INPUT
V–
AD712
200 V/mV minimum open-loop gain (AD712K)
Figure 1. 8-Lead PDIP (N-Suffix),
SOIC_N (R-Suffix), and CERDIP (Q-Suffix)
Surface mount available in tape and reel in
accordance with the EIA-481A standard
MIL-STD-883B parts available
Single version available: AD711
Quad version: AD713
Available in PDIP, SOIC_N, and CERDIP packages
GENERAL DESCRIPTION
military temperature range of −55°C to +125°C and is available
processed to MIL-STD-883B, Rev. C.
The AD712 is a high speed, precision, monolithic operational
amplifier offering high performance at very modest prices. Its
very low offset voltage and offset voltage drift are the results of
advanced laser wafer trimming technology. These performance
benefits allow the user to easily upgrade existing designs that
use older precision BiFETs and, in many cases, bipolar op amps.
Extended reliability PLUS screening is available, specified over
the commercial and industrial temperature ranges. PLUS
screening includes 168-hour burn-in, in addition to other
environmental and physical tests.
The superior ac and dc performance of this op amp makes it
suitable for active filter applications. With a slew rate of 16 V/μs
and a settling time of 1 μs to ±±.±1%, the AD712 is ideal as a
buffer for 12-bit digital-to-analog and analog-to-digital
converters and as a high speed integrator. The settling time is
unmatched by any similar IC amplifier.
The AD712 is available in 8-lead PDIP, SOIC_N, and CERDIP
packages.
PRODUCT HIGHLIGHTS
1. The AD712 offers excellent overall performance at very
competitive prices.
The combination of excellent noise performance and low input
current also make the AD712 useful for photo diode preamps.
Common-mode rejection of 88 dB and open-loop gain of
4±± V/mV ensure 12-bit performance even in high speed
unity-gain buffer circuits.
2. The Analog Devices, Inc. advanced processing technology
and 1±±% testing guarantee a low input offset voltage (3 mV
maximum, J grade). Input offset voltage is specified in the
warmed-up condition.
The AD712 is pinned out in a standard op amp configuration
and is available in seven performance grades. The AD712J and
AD712K are rated over the commercial temperature range of
±°C to 7±°C. The AD712A is rated over the industrial tempera-
ture range of −4±°C to +85°C. The AD712S is rated over the
3. Together with precision dc performance, the AD712 offers
excellent dynamic response. It settles to ±±.±1% in 1 μs and
has a minimum slew rate of 16 V/μs. Thus, this device is ideal
for applications such as DAC and ADC buffers that require a
combination of superior ac and dc performance.
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD712
TABLE OF CONTENTS
Features .............................................................................................. 1
Guarding...................................................................................... 14
Digital-to-Analog Converter Applications ............................. 14
Noise Characteristics ................................................................. 15
Connection Diagram ....................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Settling Time ................................................................................... 11
Optimizing Settling Time.......................................................... 11
Op Amp Settling Time—A Mathematical Model.................. 12
Applications Information .............................................................. 14
Driving the Analog Input of an
Analog-to-Digital Converter .................................................... 15
Driving a Large Capacitive Load.............................................. 16
Filters................................................................................................ 17
Active Filter Applications.......................................................... 17
Second-Order Low-Pass Filter.................................................. 17
9-Pole Chebychev Filter............................................................. 18
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 2±
REVISION HISTORY
8/06—Rev. F to Rev. G
7/02—Rev. D to Rev. E
Edits to Figure 1................................................................................ 1
Change to 9-Pole Chebychev Filter Section................................ 18
Edits to Features.................................................................................1
9/01—Rev. C to Rev. D
Edits to Features.................................................................................1
Edits to General Description ...........................................................1
Edits to Connection Diagram..........................................................1
Edits to Ordering Guide ...................................................................3
Deleted Metalization Photograph ...................................................3
Edits to Absolute Maximum Ratings .............................................3
Edits to Figure 7.................................................................................9
Edits to Outline Dimensions......................................................... 15
6/06—Rev. E to Rev. F
Updated Format..................................................................Universal
Deleted B, C, and T Models...............................................Universal
Changes to General Description .................................................... 1
Changes to Product Highlights....................................................... 1
Changes to Specifications Section.................................................. 3
Changes to Figure 43...................................................................... 15
Rev. G | Page 2 of 20
AD712
SPECIFICATIONS
VS = ±15 V ꢀ TA = 25°C, unless otherwise noted. Specifications in boldface are tested on all production units at final electrical test.
Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those
shown in boldface are tested on all production units.
Table 1.
AD712J/A/S
Typ
AD712K
Typ
Parameter
INPUT OFFSET VOLTAGE1
Min
Max
Min
Max
Unit
Initial Offset
TMIN to TMAX
vs. Temp
vs. Supply
0.3
3/1/1
4/2/2
20/20/20
0.2
1.0
2.0
10
mV
mV
μV/°C
dB
dB
7
95
7
100
76
76/76/76
80
80
TMIN to TMAX
Long-Term Offset Stability
INPUT BIAS CURRENT2
VCM = 0 V
15
15
ꢀV/month
25
20
0.5
pA
nA
pA
75
1.7/4.8/77
100
75
1.7
100
VCM = 0 V @ TMAX
0.6/1.6/26
VCM
= 10 V
INPUT OFFSET CURRENT
VCM = 0 V
VCM = 0 V @ TMAX
10
5
0.1
pA
nA
25
0.6/1.6/26
25
0.6
0.3/0.7/11
MATCHING CHARACTERISTICS
Input Offset Voltage
TMIN to TMAX
Input Offset Voltage Drift
Input Bias Current
Crosstalk
3/1/1
4/2/2
20/20/20
25
1.0
2.0
10
mV
mV
ꢀV/°C
pA
25
@ f = 1 kHz
@ f = 100 kHz
120
90
120
90
dB
dB
FREQUENCY RESPONSE
Small Signal Bandwidth
Full Power Response
Slew Rate
Settling Time to 0.01%
Total Harmonic Distortion
INPUT IMPEDANCE
Differential
3.0
4.0
200
20
1.0
0.0003
3.4
4.0
200
20
1.0
0.0003
MHz
kHz
V/ꢀs
ꢀs
16
18
1.2
1.2
%
3×1012||5.5
3×1012||5.5
3×1012||5.5
3×1012||5.5
Ω||pF
Ω||pF
Common Mode
INPUT VOLTAGE RANGE
Differential3
20
20
V
V
V
Common-Mode Voltage4
+14.5, −11.5
+14.5, −11.5
TMIN to TMAX
−VS + 4
+VS − 2
−VS + 4
+VS − 2
Common-Mode Rejection
Ratio
VCM
TMIN to TMAX
VCM 11 V
=
10 V
88
84
84
80
2
45
22
18
16
88
84
84
80
2
45
22
18
16
dB
dB
dB
dB
76
76/76/76
70
80
80
76
74
=
TMIN to TMAX
70/70/70
INPUT VOLTAGE NOISE
ꢀV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
Rev. G | Page 3 of 20
AD712
AD712J/A/S
Typ
AD712K
Typ
Parameter
Min
Max
Min
Max
Unit
INPUT CURRENT NOISE
OPEN-LOOP GAIN
0.01
0.01
400
pA/√Hz
V/mV
V/mV
400
150
100/100/100
200
100
OUTPUT CHARACTERISTICS
Voltage
+13.9, −13.3
+13.8, −13.1
+25
V
V
mA
+13, −12.5
12/ 12/ 12
+13, −12.5 +13.9, −13.3
+13.8, −13.1
+25
12
Current
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
15
15
V
V
mA
4.5
18
+6.8
4.5
18
+6.0
+5.0
+5.0
1 Input offset voltage specifications are guaranteed after 5 minutes of operation at TA = 25°C.
2 Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = 25°C. For higher temperatures, the current doubles every 10°C.
3 Defined as voltage between inputs, such that neither exceeds 10 V from ground.
4 Typically exceeding −14.1 V negative common-mode voltage on either input results in an output phase reversal.
Rev. G | Page 4 of 20
AD712
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage
Internal Power Dissipation1
Input Voltage2
Output Short-Circuit Duration
Differential Input Voltage
Storage Temperature Range
Q-Suffix
N-Suffix and R-Suffix
Operating Temperature Range
AD712J/K
Stresses above those listed under Absolute Maximum Ratings
Rating
18 V
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
18 V
Indefinite
+VS and −VS
−65°C to +150°C
−65°C to +125°C
0°C to 70°C
AD712A
AD712S
−40°C to +85°C
−55°C to +125°C
Lead Temperature Range (Soldering 60 sec) 300°C
1 Thermal characteristics:
8-lead PDIP package:
8-lead CERDIP package:
8-lead SOIC package:
θJA = 165°C/W
θJC = 22°C/W; θJA = 110°C/W
θJA = 100°C/W
2 For supply voltages less than 18 V, the absolute maximum voltage is equal
to the supply voltage.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. G | Page 5 of 20
AD712
TYPICAL PERFORMANCE CHARACTERISTICS
20
6
5
4
3
2
15
10
R
= 2kΩ
L
25°C
5
0
0
5
10
SUPPLY VOLTAGE ± V
15
20
0
5
10
15
20
SUPPLY VOLTAGE ± V
Figure 2. Input Voltage Swing vs. Supply Voltage
Figure 5. Quiescent Current vs. Supply Voltage
20
15
10
6
10
10
7
8
9
+V
OUT
10
10
–V
OUT
R
= 2kΩ
L
25°C
10
11
10
10
5
0
12
10
0
5
10
SUPPLY VOLTAGE ± V
15
20
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
Figure 6. Input Bias Current vs. Temperature
Figure 3. Output Voltage Swing vs. Supply Voltage
100
10
30
25
20
15
10
5
±15V SUPPLIES
1.0
0.1
0.01
0
1k
10k
100k
1M
10M
10
100
1k
10k
FREQUENCY (Hz)
LOAD RESISTANCE (Ω)
Figure 7. Output Impedance vs. Frequency
Figure 4. Output Voltage Swing vs. Load Resistance
Rev. G | Page 6 of 20
AD712
100
75
100
80
100
MAX J GRADE LIMIT
80
60
60
40
V
= 15V
S
25°C
50
25
0
40
20
GAIN
PHASE
2kΩ
100pF
LOAD
20
0
0
–20
10M
–20
–10
–5
0
5
10
10
100
1k
10k
100k
1M
COMMON MODE VOLTAGE (V)
FREQUENCY (Hz)
Figure 8. Input Bias Current vs. Common-Mode Voltage
Figure 11. Open-Loop Gain and Phase Margin vs. Frequency
26
24
22
125
120
115
110
+ OUTPUT CURRENT
20
18
16
14
12
10
R
= 2kΩ
L
25°C
– OUTPUT CURRENT
105
100
95
–60 –40 –20
0
20
40
60
80
100 120 140
0
5
10
SUPPLY VOLTAGE ± V
15
20
AMBIENT TEMPERATURE (°C)
Figure 9. Short-Circuit Current Limit vs. Temperature
Figure 12. Open-Loop Gain vs. Supply Voltage
110
100
5.0
4.5
4.0
3.5
3.0
+ SUPPLY
– SUPPLY
80
60
40
20
V
= ±15V SUPPLIES
S
WITH 1V p-p SINEWAVE 25°C
0
10
100 1k
10k
100k
1M
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
SUPPLY MODULATION FREQUENCY (Hz)
Figure 10. Unity-Gain Bandwidth vs. Temperature
Figure 13. Power Supply Rejection vs. Frequency
Rev. G | Page 7 of 20
AD712
100
80
60
40
20
–70
–80
V
V
25°C
= ±15V
S
= 1V p-p
CM
3V rms
R
C
= 2kΩ
= 100pF
L
L
–90
–100
–110
–120
–130
0
10
100
1k
10k
100k
1M
100
1k
10k
FREQUENCY (Hz)
100k
FREQUENCY (Hz)
Figure 17. Total Harmonic Distortion vs. Frequency
Figure 14. Common-Mode Rejection vs. Frequency
30
25
20
15
10
5
1k
R
= 2kΩ
L
25°C
= ±15V
V
S
100
10
0
100k
1
1M
10M
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 18. Input Noise Voltage Spectral Density
Figure 15. Large Signal Frequency Response
10
8
25
20
15
6
4
2
1% 0.1%
ERROR 1% 0.1%
0.01%
0.01%
0
–2
10
5
–4
–6
–8
–10
0.5
0
0.6
0.7
0.8
0.9
1.0
0
100
200
300
400
500
600
700
800
900
SETTLING TIME (µs)
INPUT ERROR SIGNAL (mV)
(AT SUMMING JUNCTION)
Figure 16. Output Swing and Error vs. Settling Time
Figure 19. Slew Rate vs. Input Error Signal
Rev. G | Page 8 of 20
AD712
25
20
15
+V
8
S
0.1µF
0.1µF
–
V
C
OUT
1/2
AD712
R
2kΩ
L
+
L
V
IN
4
100pF
SQUARE
WAVE
INPUT
–V
S
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
Figure 23. Unity-Gain Follower
Figure 20. Slew Rate vs. Temperature
+V
S
0.1µF
100
90
8
+
1/2
OUTPUT
100pF
AD712
INPUT
2kΩ
–
4
0.1µF
–V
S
10
0%
1µs
5V
Figure 21. THD Test Circuit
Figure 24. Unity-Gain Follower Pulse Response (Large Signal)
V
100
90
OUT
20kΩ
2.2kΩ
+V
S
–
2
3
–
8
6
5
1/2
1/2
1
7
20V p-p
AD712
AD712
+
+
5kΩ
5kΩ
4
V
IN
CROSSTALK = 20 log
V
OUT
10V
10
–V
S
IN
0%
50mV
100ns
Figure 22. Crosstalk Test Circuit
Figure 25. Unity-Gain Follower Pulse Response (Small Signal)
Rev. G | Page 9 of 20
AD712
5kΩ
+V
8
S
0.1µF
100
90
5kΩ
–
V
IN
V
C
OUT
1/2
AD712
R
2kΩ
L
+
L
SQUARE
WAVE
INPUT
4
100pF
0.1µF
10
–V
S
0%
50mV
200ns
Figure 26. Unity-Gain Inverter
Figure 28. Unity-Gain Inverter Pulse Response (Small Signal)
100
90
10
0%
1µs
5V
Figure 27. Unity-Gain Inverter Pulse Response (Large Signal)
Rev. G | Page 10 of 20
AD712
SETTLING TIME
OPTIMIZING SETTLING TIME
In addition to a significant improvement in settling time, the
low offset voltage, low offset voltage drift, and high open-loop
gain of the AD71x family assure 12-bit accuracy over the full
operating temperature range.
Most bipolar high speed digital-to-analog converters (DACs)
have current outputs; therefore, for most applications, an
external op amp is required for a current-to-voltage conversion.
The settling time of the converter/op amp combination depends
on the settling time of the DAC and output amplifier. A good
approximation is
The excellent high speed performance of the AD712 is shown in
the oscilloscope photos in Figure 3± and Figure 31. Measure-
ments were taken using a low input capacitance amplifier
connected directly to the summing junction of the AD712 and
both figures show a worst-case situation: full-scale input
transition. The 4 kΩ [1± kΩ||8 kΩ = 4.4 kΩ] output impedance
of the DAC, together with a 1± kΩ feedback resistor, produce an
op amp noise gain of 3.25. The current output from the DAC
produces a 1± V step at the op amp output (± to −1± V shown in
Figure 3±, and −1± V to ± V shown in Figure 31).
2
tS Total =
(
tS DAC 2
)
+
(
tS AMP
)
The settling time of an op amp DAC buffer varies with the noise
gain of the circuit, the DAC output capacitance, and the amount
of external compensation capacitance across the DAC output
scaling resistor.
Settling time for a bipolar DAC is typically 1±± ns to 5±± ns.
Previously, conventional op amps have required much longer
settling times than have typical state-of-the-art DACs; therefore,
the amplifier settling time has been the major limitation to a
high speed, voltage output, digital-to-analog function. The
introduction of the AD71x family of op amps with their 1 ꢁs (to
±±.±1% of final value) settling time permits the full high speed
capabilities of most modern DACs to be realized.
Therefore, with an ideal op amp, settling to ±1/2 LSB (±±.±1%)
requires that 375 μV or less appears at the summing junction.
This means that the error between the input and output (that
voltage which appears at the AD712 summing junction) must
be less than 375 μV. As shown in Figure 3±, the total settling
time for the AD712/AD565A combination is 1.2 microseconds.
0.1µF
BIPOLAR
OFFSET ADJUST
R1
100Ω
BIPOLAR
OFF
REF
OUT
V
CC
R2
100Ω
20V
SPAN
GAIN
ADJUST
+
–
10V
5kΩ
AD565A
10pF
9.95kΩ
+15V
10V
SPAN
REF
IN
0.1µF
0.1µF
19.95kΩ
0.5mA
5kΩ
8kΩ
DAC
OUT
I
REF
–
8
DAC
1/2
REF
GND
I
OUTPUT
–10V TO +10V
O
I
I
= 4 ×
20kΩ
OUT
REF
AD712
× CODE
+
4
POWER
GND
MSB
LSB
–V
0.1µF
–15V
EE
Figure 29. 10 V Voltage Output Bipolar DAC
Rev. G | Page 11 of 20
AD712
Where
1mV
5V
ωO
2π
= unity-gain frequency of the op amp.
100
90
⎛
⎞
R
GN = noise gain of circuit
.
SUMMING
JUNCTION
⎜
⎜
⎟
⎟
1+
RO
⎝
⎠
This equation can then be solved for Cf
0V
10
2 − GN
RωO
RCXωO
+
1 − GN
)
OUTPUT
(2)
2
CX
=
+
0%
RωO
–10V
500ns
In these equations, Capacitance CX is the total capacitance
appearing at the inverting terminal of the op amp. When
modeling a DAC buffer application, the Norton equivalent
Figure 30. Settling Characteristics for AD712 with AD565A,
Full-Scale Negative Transition
circuit shown in Figure 32 can be used directly; Capacitance CX
is the total capacitance of the output of the DAC plus the input
capacitance of the op amp (because the two are in parallel).
1mV
5V
100
90
SUMMING
JUNCTION
+
1/2
V
OUT
AD712
–
R
C
L
L
C
F
0V
R
OUTPUT
10
I
R
C
X
O
O
0%
–10V
500ns
Figure 32. Simplified Model of the AD712 Used as a Current-Out DAC Buffer
Figure 31. Settling Characteristics for AD712 with AD565A,
Full-Scale Positive Transition
When RO and IO are replaced with their Thevenin VIN and RIN
equivalents, the general-purpose inverting amplifier shown in
Figure 33 is created. Note that when using this general model,
Capacitance CX is either the input capacitance of the op amp, if
a simple inverting op amp is being simulated, or the combined
capacitance of the DAC output and the op amp input if the
DAC buffer is being modeled.
OP AMP SETTLING TIME—A MATHEMATICAL
MODEL
The design of the AD712 gives careful attention to optimizing
individual circuit components; in addition, a careful trade-off
was made: the gain bandwidth product (4 MHz) and slew rate
(2± V/μs) were chosen to be high enough to provide very fast
settling time but not too high to cause a significant reduction
in phase margin (and therefore, stability). Thus designed, the
AD712 settles to ±±.±1%, with a 1± V output step, in under 1 μs,
while retaining the ability to drive a 25± pF load capacitance
when operating as a unity-gain follower.
+
1/2
V
OUT
AD712
–
R
C
L
L
C
F
R
R
IN
V
C
IN
X
If an op amp is modeled as an ideal integrator with a unity-gain
crossover frequency of ωO/2π, then Equation 1 accurately
describes the small signal behavior of the circuit of Figure 32,
consisting of an op amp connected as an I-to-V converter at the
output of a bipolar or CMOS DAC. This equation would com-
pletely describe the output of the system if not for the finite slew
rate and other nonlinear effects of the op amp.
Figure 33. Simplified Model of the AD712 Used as an Inverter
In either case, Capacitance CX causes the system to go from a
one-pole to a two-pole response; this additional pole increases
settling time by introducing peaking or ringing in the op amp
output. Because the value of CX can be estimated with reasonable
accuracy, Equation 2 can be used to choose a small capacitor
(CF) to cancel the input pole and optimize amplifier response.
Figure 34 is a graphical solution of Equation 2 for the AD712
with R = 4 kΩ.
VO
IIN
−R
GN
ωO
(1)
=
⎛
⎜
⎜
⎝
⎞
⎟
⎠
R(CX )
2
⎟
s +
+ RCf s +1
ωO
Rev. G | Page 12 of 20
AD712
60
50
40
30
20
10
0
5V
100
90
G
= 4.0
N
G
= 3.0
N
G
= 2.0
= 1.5
= 1.0
N
10
G
N
0%
G
N
5mV
500ns
0
10
20
30
40
50
60
Figure 36. Settling Characteristics 0 V to −10 V Step
Upper Trace: Output of AD712 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)
C
F
Figure 34. Value of Capacitor CF vs. Value of CX
The input of the settling time fixture is driven by a flat top pulse
generator. The error signal output from the false summing node
of A1 is clamped, amplified by A2, and then clamped again. The
error signal is thus clamped twice: once to prevent overloading
Amplifier A2 and then a second time to avoid overloading the
oscilloscope preamp. The Tektronix oscilloscope preamp type
7A26 was carefully chosen because it does not overload with
these input levels. Amplifier A2 needs to be a very high speed
FET-input op amp; it provides a gain of 1±, amplifying the error
signal output of A1.
The photos of Figure 35 and Figure 36 show the dynamic
response of the AD712 in the settling test circuit of Figure 37.
5V
100
90
10
0%
5mV
500ns
Figure 35. Settling Characteristics 0 V to +10 V Step
Upper Trace: Output of AD712 Under Test (5 V/Div)
Lower Trace: Amplified Error Voltage (0.01%/Div)
5pF
TEKTRONIX 7A26
OSCILLOSCOPE
PREAMP
INPUT SECTION
V
× 5
+
–
ERROR
1/2
205Ω
HP2835
20pF
1MΩ
HP2835
0.47µF
0.47µF
4.99kΩ
4.99kΩ
5 TO 18pF
–15V +15V
10kΩ
200Ω
DATA
DYNAMICS
5109
10kΩ
1.1kΩ
V
IN
0.2 TO 0.6pF
10kΩ
–
1/2
V
AD712
OUT
+
10pF
5kΩ
(OR EQUIVALENT
FLAT TOP PULSE
GENERATION)
0.1µF
0.1µF
+15V
–15V
Figure 37. Settling Time Test Circuit
Rev. G | Page 13 of 20
AD712
APPLICATIONS INFORMATION
Figure 39 and Figure 4± show the AD712 and AD7545 (12-bit
CMOS DAC) configured for unipolar binary (2-quadrant multi-
plication) or bipolar (4-quadrant multiplication) operation.
Capacitor C1 provides phase compensation to reduce overshoot
and ringing.
GUARDING
The low input bias current (15 pA) and low noise characteristics
of the AD712 BiFET op amp make it suitable for electrometer
applications such as photo diode preamplifiers and picoampere
current-to-voltage converters. The use of a guarding technique,
such as that shown in Figure 38, in printed circuit board layout
and construction is critical to minimize leakage currents. The
guard ring is connected to a low impedance potential at the
same level as the inputs. High impedance signal lines should
not be extended for any unnecessary length on the printed
circuit board.
V
R2A*
DD
+15V
C1A
0.1µF
33pF
R
GAIN
ADJUST
V
FB
DD
–
OUT1
1/2
AD712
V
AD7545
IN
V
V
OUTA
REF
+
R1A*
AGND
DGND
ANALOG
COMMON
PDIP (N), CERDIP (Q),
AND SOIC (R) PACKAGES.
*REFER TO
TABLE 3
DB11 TO DB0
4
5
6
7
8
R2B*
V
V
DD
3
2
C1B
33pF
GAIN
ADJUST
R
FB
OUT1
DD
–
1
1/2
V
AD7545
IN
V
V
OUTB
REF
AD712
+
Figure 38. Board Layout for Guarding Inputs
R1B*
AGND
DGND
0.1µF
DIGITAL-TO-ANALOG CONVERTER APPLICATIONS
ANALOG
COMMON
*REFER TO
TABLE 3
–15V
The AD712 is an excellent output amplifier for CMOS DACs. It
can be used to perform both 2-quadrant and 4-quadrant
operations. The output impedance of a DAC using an inverted
R-2R ladder approaches R for codes containing many 1s, and 3R
for codes containing a single 1. For codes containing all ±s, the
output impedance is infinite.
DB11 TO DB0
Figure 39. Unipolar Binary Operation
R1 and R2 calibrate the zero offset and gain error of the DAC.
Specific values for these resistors depend upon the grade of
AD7545 and are listed in Table 3.
Table 3. Recommended Trim Resistor Values vs. Grades of
the AD7545 for VDD = 5 V
Trim
For example, the output resistance of the AD7545 modulates
between 11 kΩ and 33 kΩ. Therefore, with an 11 kΩ DAC
internal feedback resistance, the noise gain varies from 2 to 4/3.
This changing noise gain modulates the effect of the input offset
voltage of the amplifier, resulting in nonlinear DAC amplifier
performance.
Resistor
R1
R2
JN/AQ
500 Ω
150 Ω
KN/BQ
200 Ω
68 Ω
LN
GLN
20 Ω
6.8 Ω
100 Ω
33 Ω
The AD712K with guaranteed 7±± ꢁV offset voltage minimizes
this effect to achieve 12-bit performance.
R2*
R4
V
DD
20kΩ 1%
+15V
C1
33pF
0.1µF
R5
20kΩ 1%
GAIN
ADJUST
R
V
FB
OUT1
DD
–
1/2
–
AD7545
V
V
REF
IN
AD712
+
1/2
AD712
R3
10kΩ 1%
R1*
AGND
DGND
V
OUT
+
DB11 TO DB0
12
0.1µF
DATA INPUT
–15V
*FOR VALUES OF
R1 AND R2 SEE TABLE 3
ANALOG
COMMON
Figure 40. Bipolar Operation
Rev. G | Page 14 of 20
AD712
Figure 41 and Figure 42 show the settling time characteristics of
the AD712 when used as a DAC output buffer for the AD7545.
DRIVING THE ANALOG INPUT OF AN
ANALOG-TO-DIGITAL CONVERTER
An op amp driving the analog input of an ADC, such as that
shown in Figure 43, must be capable of maintaining a constant
output voltage under dynamically changing load conditions. In
successive approximation converters, the input current is com-
pared to a series of switched trial currents. The comparison
point is diode clamped, but can deviate several hundred millivolts
resulting in high frequency modulation of analog-to-digital
input current. The output impedance of a feedback amplifier
is made artificially low by the loop gain. At high frequencies,
where the loop gain is low, the amplifier output impedance
can approach its open-loop value. Most IC amplifiers exhibit a
minimum open-loop output impedance of 25 Ω due to current-
limiting resistors.
1mV
100
90
10
0%
5V
500ns
Figure 41. Positive Settling Characteristics for AD712 with AD7545
12/8
CS
STS
1mV
HIGH
BITS
A
100
90
O
AD574A
R/C
CE
GAIN
ADJUST
MIDDLE
BITS
REF IN
R2
100Ω
R1
100Ω
LOW
BITS
REF OUT
BIP OFF
+15V
1/2
0.1µF
+5V
+15V
–15V
DC
10
OFFSET
ADJUST
10V
IN
–
0%
20V
AC
IN
AD712
5V
500ns
±10V
ANALOG
INPUT
+
0.1µF
Figure 42. Negative Settling Characteristics for AD712 with AD7545
ANALOG COM
–15V
NOISE CHARACTERISTICS
Figure 43. AD712 as An ADC Unity-Gain Buffer
The random nature of noise, particularly in the flicker noise
region, makes it difficult to specify in practical terms. At the
same time, designers of precision instrumentation require
certain guaranteed maximum noise levels to realize the full
accuracy of their equipment. All grades of the AD712 are sample
tested on an AQL basis to a limit of 6 μV p-p, ±.1 Hz to 1± Hz.
A few hundred microamps reflected from the change in con-
verter loading can introduce errors in instantaneous input
voltage. If the analog-to-digital conversion speed is not excessive
and the bandwidth of the amplifier is sufficient, the amplifier
output returns to the nominal value before the converter makes
its comparison. However, many amplifiers have relatively narrow
bandwidth yielding slow recovery from output transients. The
AD712 is ideally suited to drive high speed analog-to-digital
converters because it offers both wide bandwidth and high
open-loop gain.
Rev. G | Page 15 of 20
AD712
DRIVING A LARGE CAPACITIVE LOAD
1mV
PD711 BUFF
The circuit in Figure 46 uses a 1±± Ω isolation resistor that
enables the amplifier to drive capacitive loads exceeding
15±± pF; the resistor effectively isolates the high frequency
feedback from the load and stabilizes the circuit. Low frequency
feedback is returned to the amplifier summing junction via the
low-pass filter formed by the 1±± Ω series resistor and the Load
Capacitance CL. Figure 47 shows a typical transient response for
this connection.
100
90
10
0%
4.99kΩ
200ns
500mV
–10V ADC IN
30pF
+V
IN
Figure 44. ADC Input Unity Gain Buffer Recovery Times, −10 V ADC IN
0.1µF
+
–
4.99kΩ
–
1mV
PD711 BUFF
100Ω
1/2
AD712
INPUT
OUTPUT
100
90
+
TYPICAL CAPACITANCE
LIMIT FOR VARIOUS
LOAD RESISTORS
C1
R1
0.1µF
+
–
R
C UP TO
1
1
–V
2kΩ
10kΩ
20Ω
1500pF
1500pF
1000pF
IN
Figure 46. Circuit for Driving a Large Capacitive Load
10
0%
1µs
5V
200ns
500mV
–5V ADC IN
100
90
Figure 45. ADC Input Unity Gain Buffer Recovery Times, −5 V ADC IN
10
0%
Figure 47. Transient Response RL = 2 kΩ, CL = 500 pF
Rev. G | Page 16 of 20
AD712
FILTERS
ACTIVE FILTER APPLICATIONS
C1
560pF
In active filter applications using op amps, the dc accuracy of
the amplifier is critical to optimal filter performance. The
amplifier offset voltage and bias current contribute to output
error. Offset voltage is passed by the filter and can be amplified
to produce excessive output offset. For low frequency
+15V
1/2
0.1µF
R1
R2
20kΩ 20kΩ
+
C2
280pF
V
OUT
AD712
V
IN
–
0.1µF
applications requiring large value input resistors, bias currents
flowing through these resistors also generate an offset voltage.
–15V
In addition, at higher frequencies, the op amp dynamics must
be carefully considered. Here, slew rate, bandwidth, and open-
loop gain play a major role in op amp selection. The slew rate
must be fast as well as symmetrical to minimize distortion. The
amplifier bandwidth in conjunction with the filter gain dictates
the frequency response of the filter.
Figure 48. Second-Order Low-Pass Filter
An important property of filters is their out-of-band rejection.
The simple 2± kHz low-pass filter shown in Figure 48, can be
used to condition a signal contaminated with clock pulses or
sampling glitches that have considerable energy content at high
frequencies.
The use of a high performance amplifier such as the AD712
minimizes both dc and ac errors in all active filter applications.
The low output impedance and high bandwidth of the AD712
minimize high frequency feedthrough as shown in Figure 49.
The upper trace is that of another low cost BiFET op amp
showing 17 dB more feedthrough at 5 MHz.
SECOND-ORDER LOW-PASS FILTER
Figure 48 depicts the AD712 configured as a second-order,
Butterworth low-pass filter. With the values as shown, the
corner frequency is 2± kHz; however, the wide bandwidth of the
AD712 permits a corner frequency as high as several hundred
kilohertz. Equations for component selection are as follows:
REF 20.0 dBm
10dB/DIV
OFFSET .0 Hz
0dB
RANGE 15.0dBm
R1 = R2 = A user selected value (1± kΩ to 1±± kΩ, typical)
TYPICAL BIFET
1.414
C1 (in farads) =
(
2π
)
(
fcutoff
)
(
R1)
AD712
±.7±7
C2 =
(
2π
)(
fcutoff
)
(
R1
)
CENTER 5 000 000.0Hz
RBW 30kHz
SPAN 10 000 000.0Hz
ST .8 SEC
VBW 30kHz
Figure 49. High Frequency Feedthrough
Rev. G | Page 17 of 20
AD712
+15V
0.1µF
+15V
0.1µF
V
IN
+
0.001µF
2800Ω
6190Ω
6490Ω
6190Ω
2800Ω
A1
+
AD711
–
A2
V
–15
–15
–15
–15
D
OUT
4.9395E
5.9276E
5.9276E
4.9395E
AD711
–
0.1µF
A
B
C
+
+
+
+
0.1µF
4.99kΩ
4.99kΩ
–15V
*
*
*
*
–15V
100kΩ
0.001µF
124kΩ
SEE TEXT
*
Figure 50. 9-Pole Chebychev Filter
9-POLE CHEBYCHEV FILTER
+15V
+
0.1µF
Figure 5± and Figure 51 show the AD712 and its dual
counterpart, the AD711, as a 9-pole Chebychev filter using
active frequency dependent negative resistors (FDNRs). With a
cutoff frequency of 5± kHz and better than 9± dB rejection, it
can be used as an antialiasing filter for a 12-bit data acquisition
system with 1±± kHz throughput.
0.001µF
+
1/2
AD712
–
R
0.1µF
–
1/2
0.001µF
AD712
+
–15V
As shown in Figure 5±, the filter is comprised of four FDNRs
(A, B, C, D) having values of 4.9395 × 1±−15 and 5.9276 × 1±–15
farad-seconds. Each FDNR active network provides a two-pole
response for a total of eight poles. The ninth pole consists of a
±.±±1 ꢁF capacitor and a 124 kΩ resistor at Pin 3 of Amplifier A2.
Figure 51 depicts the circuits for each FDNR with the proper
selection of R. To achieve optimal performance, the ±.±±1 μF
capacitors must be selected for 1% or better matching and all
resistors should have 1% or better tolerance.
1.0kΩ
4.99kΩ
–15
R: 24.9kΩ FOR 4.9395E
29.4kΩ FOR 5.9276E
–15
Figure 51. FDNR for 9-Pole Chebychev Filter
REF 5.0dBm
10dB/DIV
MARKER 96 800.0Hz
RANGE –5.0dBm –90dBm
START.0Hz
RBW 300Hz
STOP 200 000.0Hz
ST 69.6 SEC
VBW 30Hz
Figure 52. High Frequency Response for 9-Pole Chebychev Filter
Rev. G | Page 18 of 20
AD712
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
0.005 (0.13)
MIN
0.055 (1.40)
MAX
8
5
8
1
5
4
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.310 (7.87)
0.220 (5.59)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
1
4
PIN 1
0.100 (2.54)
0.100 (2.54) BSC
0.405 (10.29) MAX
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210
(5.33)
MAX
0.320 (8.13)
0.290 (7.37)
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.150 (3.81)
MIN
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.200 (5.08)
0.125 (3.18)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
15°
0°
0.070 (1.78)
0.030 (0.76)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-001-BA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 54. 8-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-8)
Figure 53. 8-Lead Plastic Dual In-Line Package [PDIP]
(N-8)
Dimensions shown in inches and (millimeters)
Dimensions shown in inches and (millimeters)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
0.50 (0.0196)
× 45°
1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0099)
0.25 (0.0098)
0.10 (0.0040)
8°
0.51 (0.0201)
0.31 (0.0122)
0° 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 55. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. G | Page 19 of 20
AD712
ORDERING GUIDE
Model
AD712AQ
AD712JN
AD712JNZ1
Temperature Range
−40°C to +85°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
−55°C to +125°C
Package Description
8-Lead CERDIP
8-Lead PDIP
Package Option
Q-8
N-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
N-8
N-8
R-8
R-8
R-8
R-8
R-8
R-8
Q-8
8-Lead PDIP
AD712JR
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead PDIP
AD712JR-REEL
AD712JR-REEL7
AD712JRZ1
AD712JRZ-REEL1
AD712JRZ-REEL71
AD712KN
AD712KNZ1
AD712KR
8-Lead PDIP
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead CERDIP
AD712KR-REEL
AD712KR-REEL7
AD712KRZ1
AD712KRZ-REEL1
AD712KRZ-REEL71
AD712SQ/883B
1 Z = Pb-free part.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00823-0-8/06(G)
Rev. G | Page 20 of 20
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