AD713_11 [ADI]
Precision, High Speed, BiFET Quad Op Amp; 精密，高速，的BiFET四通道运算放大器
| 型号： | AD713_11 |
| 厂家： | 
ADI |
| 描述： | Precision, High Speed, BiFET Quad Op Amp |
| 文件： | 总20页 (文件大小：362K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision, High Speed, BiFET Quad Op Amp
AD713
FEATURES
CONNECTION DIAGRAMS
AC performance
1 μs settling to 0.01% for 10 V step
20 V/μs slew rate
0.0003% total harmonic distortion (THD)
4 MHz unity gain bandwidth
DC performance
1.5 mV maximum offset voltage
8 μV/°C typical drift
150 V/mV minimum open-loop gain
2 μV p-p typical noise, 0.1 Hz to 10 Hz
True 14-bit accuracy
Single version: AD711, dual version: AD712
Available in 16-lead SOIC, 14-lead PDIP and CERDIP
OUTPUT
–IN
1
2
3
4
5
6
7
14 OUTPUT
13 –IN
1
4
+IN
12 +IN
AD713
+V
S
11 –V
S
TOP VIEW
(Not to Scale)
+IN
–IN
10 +IN
9
8
–IN
2
3
OUTPUT
OUTPUT
Figure 1. 14-Lead PDIP (N) and CERDIP (Q) Packages
OUTPUT
–IN
1
2
3
4
5
6
7
8
16 OUTPUT
15 –IN
1
4
+IN
14 +IN
+V
S
13 –V
S
AD713
APPLICATIONS
+IN
–IN
12 +IN
Active filters
11 –IN
2
3
Quad output buffers for 12- and 14-bit DACs
Input buffers for precision ADCs
Photo diode preamplifier applications
OUTPUT
NC
10 OUTPUT
TOP VIEW
(Not to Scale)
9
NC
NC = NO CONNECT. DO NOT
CONNECT TO THIS PIN.
Figure 2. 16-Lead SOIC_W (RW) Package
GENERAL DESCRIPTION
The AD713 is a quad operational amplifier, consisting of four
AD711 BiFET op amps. These precision monolithic op amps
offer excellent dc characteristics plus rapid settling times, high
slew rates, and ample bandwidths. In addition, the AD713 provides
the close matching ac and dc characteristics inherent to amplifiers
sharing the same monolithic die. The single-pole response of
the AD713 provides fast settling: l μs to 0.01%. This feature,
combined with its high dc precision, makes the AD713 suitable
for use as a buffer amplifier for 12- or 14-bit DACs and ADCs.
It is also an excellent choice for use in active filters in 12-, 14-
and 16-bit data acquisition systems. Furthermore, the AD713
low total harmonic distortion (THD) level of 0.0003% and very
close matching ac characteristics make it an ideal amplifier for
many demanding audio applications. The AD713 is internally
compensated for stable operation at unity gain. The AD713J is
rated over the commercial temperature range of 0°C to 70°C.
The AD713A is rated over the industrial temperature of −40°C
to +85°C.
PRODUCT HIGHLIGHTS
1. The AD713 is a high speed BiFET op amp that offers
excellent performance at competitive prices. It upgrades
the performance of circuits using op amps such as the
TL074, TL084, LT1058, LF347, and OPA404.
2. Slew rate is 100% tested for a guaranteed minimum of
16 V/μs (J and A grades).
3. The combination of Analog Devices, Inc., advanced
processing technology, laser wafer drift trimming, and
well-matched ion-implanted JFETs provides outstanding
dc precision. Input offset voltage, input bias current and
input offset current are specified in the warmed-up
condition and are 100% tested.
4. Very close matching of ac characteristics between the four
amplifiers makes the AD713 ideal for high quality active
filter applications.
The AD713 is offered in 16-lead SOIC, 14-lead PDIP, and
14-lead CERDIP packages.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2011 Analog Devices, Inc. All rights reserved.
AD713
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 11
Measuring AD713 Settling Time ............................................. 11
Power Supply Bypassing............................................................ 11
A High Speed Instrumentation Amplifier Circuit................. 12
A High Speed 4-Op-Amp Cascaded Amplifier Circuit........ 12
High Speed Op Amp Applications and Techniques.............. 12
CMOS DAC Applications ......................................................... 14
Filter Applications...................................................................... 14
GIC and FDNR Filter Applications ......................................... 15
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 18
Applications....................................................................................... 1
Connection Diagrams...................................................................... 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Typical Performance Characteristics ............................................. 6
Test Circuits..................................................................................... 10
REVISION HISTORY
7/11—Rev. E to Rev. F
Deleted Figure 9 and Figure 10; Renumbered Sequentially ........9
Changes to Figure 23 Caption and Figure 24 Caption .............. 10
Added Test Circuits Section.......................................................... 11
Moved Figures 26, Figure 27, and Figure 28............................... 11
Changes to Figure 29...................................................................... 12
Changes to DAC Buffers (I-to-V Converters) Section.............. 13
Changes to Figure 37 and Table 5................................................. 14
Changed C1 to CL ........................................................................... 14
Changes to Figure 43 and Figure 44............................................. 15
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide.......................................................... 19
Changes to Figure 2.......................................................................... 1
6/11—Rev. D to Rev. E
Changed 8 μV/°C Maximum Drift to 8 μV/°C Typical Drift in
Features Section ................................................................................ 1
5/11—Rev. C to Rev. D
Updated Format..................................................................Universal
Changes to Features Section, General Description Section, and
Product Highlights Section ............................................................. 1
Deleted S, K, B, and T Grades Throughout................................... 1
Changes to Table 1............................................................................ 3
Changes to Table 2............................................................................ 5
Added Typical Performance Characteristics Summary .............. 6
Change to Figure 7 ........................................................................... 7
Changes to Figure 15, Figure 17, and Figure 18 ........................... 8
10/01—Rev. B to Rev. C
Edits to Features.................................................................................1
Edits to Product Description ...........................................................1
Edits to Ordering Guide ...................................................................3
Edits to Metallization Photograph ..................................................3
Rev. F | Page 2 of 20
AD713
SPECIFICATIONS
VS = 15 V at TA = 25°C, unless otherwise noted.
Table 1.
AD713J/AD713A
Typ
Parameter
INPUT OFFSET VOLTAGE1
Initial Offset
Offset
Test Conditions/Comments
Min
Max
Unit
0.3
0.5
5
1.5
2
mV
mV
μV/°C
dB
dB
μV/Month
pA
TMIN to TMAX
vs. Temp
vs. Supply
78
76
95
95
15
40
TMIN to TMAX
Long-Term Stability
INPUT BIAS CURRENT2
VCM = 0 V
150
VCM = 0 V at TMAX
3.4/9.6
200
nA
pA
VCM
=
10 V
55
10
INPUT OFFSET CURRENT
VCM = 0 V
75
pA
VCM = 0 V at TMAX
1.7/4.8
pA
MATCHING CHARACTERISTICS
Input Offset Voltage
0.5
0.7
8
1.8
2.3
mV
mV
μV/°C
pA
dB
dB
TMIN to TMAX
Input Offset Voltage Drift
Input Bias Current
Crosstalk
10
100
−130
−95
f = 1 kHz
f = 100 kHz
FREQUENCY RESPONSE
Small Signal Bandwidth
Full Power Response
Slew Rate
G = −1
VO = 20 V p-p
G = −1
3.0
16
4.0
200
20
1.0
0.0003
MHz
kHz
V/μs
μs
Settling Time to 0.01%
Total Harmonic Distortion
INPUT IMPEDANCE
Differential3
1.2
f = 1 kHz; RL ≥ 2 kΩ; VO = 3 V rms
%
3 × 1012||5.5
3 × 1012||5.5
Ω||pF
Ω||pF
Common Mode4
INPUT VOLTAGE RANGE
Differential
20
V
Common-Mode Voltage
+14.5/−11.5
V
TMIN to TMAX
VCM 10 V
TMIN to TMAX
VCM 11 V
TMIN to TMAX
0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
f = 10 kHz
−11
78
76
72
70
+13
V
dB
dB
dB
Common Mode
Rejection Ratio
=
88
84
84
80
2
45
22
18
16
0.01
400
=
dB
INPUT VOLTAGE NOISE
μV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
pA/√Hz
V/mV
V/mV
INPUT CURRENT NOISE
OPEN-LOOP GAIN
f = 1 kHz
VO = 10 V; RL ≥ 2 kΩ
TMIN to TMAX
150
100
Rev. F | Page 3 of 20
AD713
AD713J/AD713A
Typ
Parameter
Test Conditions/Comments
Min
Max
Unit
OUTPUT CHARACTERISTICS
Voltage
RL ≥ 2 kΩ
TMIN to TMAX
Short circuit
+13/−12.5
12
+13.9/−13.3
+13.8/−13.1
25
V
V
mA
Current
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
TRANSISTOR COUNT
15
V
V
mA
4.5
18
13.5
10.0
120
Number of transistors
1 Input offset voltage specifications are guaranteed after 5 minutes of operation at TA = 25°C.
2 Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = 25°C. For higher temperatures, the current doubles every 10°C.
3 Defined as the voltage between inputs, such that neither exceeds 10 V from ground.
4 Typically exceeding −14.1 V negative common-mode voltage on either input results in an output phase reversal.
Rev. F | Page 4 of 20
AD713
ABSOLUTE MAXIMUM RATINGS
Table 2.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
18 V
18 V
Supply Voltage
Input Voltage1
Output Short-Circuit Duration
(For One Amplifier)
Differential Input Voltage
Storage Temperature Range (Q)
Storage Temperature Range (N, R)
Operating Temperature Range
AD713J
Indefinite
+VS and −VS
−65°C to +150°C
−65°C to +125°C
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
0°C to 70°C
−40°C to +85°C
300°C
Table 3. Thermal Resistance
AD713A
Package Type
θJA
θJC
30
30
30
Unit
°C/W
°C/W
°C/W
Lead Temperature Range (Soldering, 60 sec)
14-Lead PDIP (N-14)
14-Lead CERDIP (Q-14)
16-Lead SOIC_W (RW-16)
100
110
100
1 For supply voltages less than 18 V, the absolute maximum input voltage is
equal to the supply voltage.
ESD CAUTION
Rev. F | Page 5 of 20
AD713
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 15 V at TA = 25°C, unless otherwise noted.
20
16
12
8
R
= 2kΩ
= 25°C
L
T
A
15
10
5
4
0
0
0
5
10
15
20
0
5
10
15
20
SUPPLY VOLTAGE (±V)
SUPPLY VOLTAGE (V)
Figure 3. Input Voltage Swing vs. Supply Voltage
Figure 6. Quiescent Current vs. Supply Voltage
20
15
10
5
–6
10
10
R
= 2kΩ
= 25°C
L
T
A
–7
–8
–9
+V
10
10
OUT
–V
OUT
–10
10
–11
–12
10
10
0
0
5
10
SUPPLY VOLTAGE (±V)
15
20
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
Figure 4. Output Voltage Swing vs. Supply Voltage
Figure 7. Input Bias Current vs. Temperature
30
25
20
15
10
100
10
1
±15V SUPPLIES
0.1
5
0
0.01
10
100
1k
10k
1k
10k
100k
1M
10M
LOAD RESISTANCE (Ω)
FREQUENCY (Hz)
Figure 5. Output Voltage Swing vs. Load Resistance
Figure 8. Output Impedance vs. Frequency, G = 1
Rev. F | Page 6 of 20
AD713
50
40
30
100
80
60
40
20
0
100
80
V
T
= ±15V
= 25°C
S
A
60
40
20
10
0
GAIN
PHASE
2kΩ||100pF LOAD
20
0
–20
10M
–20
10
–10
–5
0
5
10
100
1k
10k
100k
1M
COMMON-MODE VOLTAGE (V)
FREQUENCY (Hz)
Figure 9. Input Bias Current vs. Common Mode Voltage
+OUTPUT CURRENT
Figure 12. Open-Loop Gain and Phase Margin vs. Frequency
125
26
24
22
20
18
16
14
12
R
= 2kΩ
L
T
= 25°C
A
120
115
110
–OUTPUT CURRENT
105
100
95
10
0
5
10
15
20
–60 –40 –20
0
20
40
60
80
100 120 140
SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (°C)
Figure 13. Open-Loop Gain vs. Supply Voltage
Figure 10. Short-Circuit Current Limit vs. Temperature
5.0
110
100
+SUPPLY
4.5
4.0
3.5
3.0
80
60
40
20
–SUPPLY
V
= ±15V SUPPLIES WITH
S
1V p-p SINE WAVE 25°C
0
10
–60 –40 –20
0
20
40
60
80
100 120 140
100 1k
10k
100k
1M
TEMPERATURE (°C)
SUPPLY MODULATION FREQUENCY (Hz)
Figure 14. Power Supply Rejection vs. Frequency
Figure 11. Gain Bandwidth vs. Temperature
Rev. F | Page 7 of 20
AD713
100
70
80
V
V
= ±15V
3V RMS
S
R
C
= 2kΩ
= 100pF
= 1V p-p
L
L
CM
T
= 25°C
A
80
60
90
100
110
120
130
40
20
0
10
100
1k
10k
100k
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 18. Total Harmonic Distortion vs. Frequency
Figure 15. Common-Mode Rejection vs. Frequency
1k
100
10
30
25
20
R
= 2kΩ
= 25°C
= ±15V
L
T
A
V
S
15
10
5
1
0
100k
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
INPUT FREQUENCY (Hz)
Figure 19. Input Noise Voltage Spectral Density
Figure 16. Large Signal Frequency Response
10
25
20
15
10
5
8
6
4
2
1% 0.1%
0.01%
0
ERROR
1% 0.1%
0.01%
–2
–4
–6
–8
0
–10
0.5
0
100
200
300
400
500
600
700
800
900
0.6
0.7
0.8
0.9
1.0
INPUT ERROR SIGNAL (mV)
(AT SUMMING JUNCTION)
SETTLING TIME (µs)
Figure 17. Output Swing and Error vs. Settling Time
Figure 20. Slew Rate vs. Input Error Signal
Rev. F | Page 8 of 20
AD713
–70
–80
1
2
3
4
5
6
7
14
13
12
11
10
9
1
2
4
3
–90
100
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–110
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–140
10
100
1k
FREQUENCY (Hz)
10k
100k
5V
1µs
Figure 24. Unity Gain Inverter Pulse Response—Small Signal (see Figure 28)
Figure 21. Crosstalk vs. Frequency (see Figure 26 for Test Circuit)
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5V
1µs
50mV
200ns
Figure 22. Unity Gain Follower Pulse Response—Large Signal (see Figure 27
for Test Circuit)
Figure 25. Unity Gain Inverter Pulse Response—Small Signal (see Figure 28)
100
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Figure 23. Unity Gain Follower Pulse Response—Small Signal (see Figure 27)
Rev. F | Page 9 of 20
AD713
TEST CIRCUITS
9kΩ
AD713
PIN 4
+V
1kΩ
S
+V
4
S
+
+
0.1µF
0.1µF
1µF
1µF
1/4
+
AD713
COM
1µF
0.1µF
OUTPUT
1/4
INPUT
SIGNAL
OR
ALL 4 AMPLIFIERS
ARE CONNECTED
AS SHOWN.
AD713
PIN 11
V
–V
S
OUT
AD713
1kΩ
R
C
L
L
11
V
2kΩ
10pF
IN
GROUND*
*THE SIGNAL INPUT (1kHz SINEWAVE, 2V p-p) IS APPLIED TO ONE
AMPLIFIER AT A TIME. THE OUTPUTS OF THE OTHER THREE
AMPLIFIERS ARE THEN MEASURED FOR CROSSTALK.
SQUARE
WAVE
INPUT
1µF
0.1µF
–V
+
S
Figure 26. Crosstalk Test Circuit for Figure 21
Figure 27. Unity Gain Follower Circuit for Figure 22 and Figure 23
7.5pF
2kΩ
+V
4
S
+
2kΩ
1µF
0.1µF
V
IN
1/4
V
OUT
AD713
R
2kΩ
C
L
10pF
L
SQUARE
WAVE
INPUT
11
1µF
0.1µF
+
–V
S
Figure 28. Unity Gain Inverter Circuit for Figure 24 and Figure 25
Rev. F | Page 10 of 20
AD713
THEORY OF OPERATION
The error signal is thus clamped twice: once to prevent overload-
ing amplifier A2 and then a second time to avoid overloading
the oscilloscope preamp. A Tektronix oscilloscope preamp
Type 7A26 was carefully chosen because it recovers from the
approximately 0.4 V overload quickly enough to allow accurate
measurement of the AD713 1 μs settling time. Amplifier A2 is a
very high speed FET input op amp; it provides a voltage gain of
10, amplifying the error signal output of the AD713 under test
(providing an overall gain of 5).
MEASURING AD713 SETTLING TIME
Figure 30 and Figure 31 show the dynamic response of the AD713
while operating in the settling time test circuit of Figure 29.
The input of the settling time fixture is driven by a flat-top pulse
generator. The error signal output from the false summing node
of A1, the AD713 under test, is clamped, amplified by Op Amp
A2, and then clamped again.
TO TEKTRONIX 7A26
OSCILLOSCOPE
PREAMP INPUT
SECTION (VIA LESS
THAN 1FT 50Ω
1MΩ
20pF
5V
COAXIAL CABLE)
5pF
100
90
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+
V
ERROR × 5
2 ×
HP2835
A2
206Ω
2 ×
HP2835
0.47µF
0.47µF
–V +V
S
S
10kΩ
10
NOTES
1. USE CIRCUIT BOARD
WITH GROUND PLANE.
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0%
1.1kΩ
0.2pF TO 0.8pF
4.99kΩ
5mV
500ns
4.99kΩ
10kΩ
200Ω
10kΩ
Figure 31. Settling Characteristics to –10 V Step,
Upper Trace: Output of AD713 Under Test (5 V/div),
Lower Trace: Amplified Error Voltage (0.01%/div)
FLAT-TOP
PULSE
5pF TO 18pF
*USE VERY
SHORT CABLE
OR TERMINATION
GENERATOR
V
1/4
AD713
IN
RESISTOR
*
POWER SUPPLY BYPASSING
A1
DATA
DYNAMICS
5109
The power supply connections to the AD713 must maintain a
low impedance to ground over a bandwidth of 4 MHz or more.
This is especially important when driving a significant resistive
or capacitive load because all current delivered to the load
comes from the power supplies. Multiple high quality bypass
capacitors are recommended for each power supply line in any
critical application. As shown in Figure 32, a 0.1 μF ceramic and
a 1 μF electrolytic capacitor placed as close as possible to the
amplifier (with short lead lengths to power supply common)
assures adequate high frequency bypassing in most applications.
A minimum bypass capacitance of 0.1 μF should be used for
any application.
4
5kΩ
10pF
+
11
OR
EQUIVALENT
+
1µF
0.1µF
1µF
0.1µF
+
–V +V
S
S
Figure 29. Settling Time Test Circuit
5V
100
90
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • •
+V
S
+
1µF
0.1µF
4
1/4
AD713
11
10
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • •
0%
1µF
0.1µF
+
–V
5mV
500ns
S
Figure 32. Recommended Power Supply Bypassing
Figure 30. Settling Characteristics 0 V to 10 V Step,
Upper Trace: Output of AD713 Under Test (5 V/div),
Lower Trace: Amplified Error Voltage (0.01%/div)
Rev. F | Page 11 of 20
AD713
A HIGH SPEED INSTRUMENTATION AMPLIFIER
CIRCUIT
A HIGH SPEED 4-OP-AMP CASCADED AMPLIFIER
CIRCUIT
The instrumentation amplifier circuit shown in Figure 33 can
provide a range of gains from unity up to 1000 and higher using
only a single AD713. The circuit bandwidth is 1.2 MHz at a gain
of 1 and 250 kHz at a gain of 10; settling time for the entire
circuit is less than 5 μs to within 0.01% for a 10 V step, (G = 10).
Other uses for Amplifier A4 include an active data guard and an
active sense input.
Figure 35 shows how the four amplifiers of the AD713 can be
connected in cascade to form a high gain, high bandwidth
amplifier. This gain of 100 amplifier has a −3 dB bandwidth
greater than 600 kHz.
+V
S
0.1µF
1µF
INPUT
3
2
4
1
5
6
20,000
1/4
CIRCUIT GAIN =
+ 1
7
10
9
R
AD713
G
1/4
AD713
1/4
8
12
13
1/4
AD713
14
11
3
2
*1.5pF TO 20pF
(TRIM FOR BEST SETTLING TIME)
2.15kΩ
AD713
–IN
1/4
AD713
OUTPUT
0.1µF
2.15kΩ
1
A1
2.15kΩ
1kΩ
1kΩ
2.15kΩ
1kΩ
10kΩ**
10kΩ
1kΩ
22MΩ
1µF
10kΩ**
+
SENSE
–V
9
S
–V
+V
S
7.5pF
7.5pF
S
4-OP-AMP CASCADED AMPLIFIER
GAIN = 100
BANDWIDTH (–3dB) = 632kHz
100kΩ
R
8
A3
G
10kΩ**
OPTIONAL V
OS
ADJUSTMENT
10
1/4
5pF
AD713
10kΩ**
Figure 35. High Speed 4-Op-Amp Cascaded Amplifier Circuit
10kΩ
6
5
TO SPECTRUM ANALYZER
7
13
A4
A2
ERROR SIGNAL
OUTPUT
TO BUFFERED
VOLTAGE
REFERENCE
OR REMOTE
GROUND SENSE
14
+IN
1/4
AD713
(ERROR/11)
NULL
12
1/4
AD713
1kΩ
ADJUST
100kΩ
10kΩ
10kΩ
AD713
PIN 4
+V
S
+
+V
S
0.1µF
0.1µF
1µF
*
VOLTRONICS SP20 TRIMMER CAPACITOR
OR EQUIVALENT
RATIO MATCHED 1% METAL FILM
RESISTORS
COM
+
1kΩ
+
**
1µF
0.1µF
1µF
4
AD713
PIN 11
LOW DISTORTION
SINEWAVE INPUT
1/4
–V
S
AD713
100pF
11
Figure 33. High Speed Instrumentation Amplifier Circuit
Table 4 provides a performance summary for this circuit. Figure 34
shows the pulse response of this circuit for a gain of 10.
1µF
0.1µF
+
–V
S
Figure 36. THD Test Circuit
Table 4. Performance Summary for the High Speed
Instrumentation Amplifier Circuit
HIGH SPEED OP AMP APPLICATIONS AND
TECHNIQUES
DAC Buffers (I-to-V Converters)
Gain
RG
Bandwidth
Settling Time (0.01%)
1
2
10
NC1
1.2 MHz
1.0 MHz
0.25 MHz
2 μs
2 μs
2 μs
20 kΩ
4.04 kΩ
The wide input dynamic range of JFET amplifiers makes them
ideal for use in both waveform reconstruction and digital audio
DAC applications. The AD713, in conjunction with a 16-bit
DAC, can achieve 0.0016% THD without requiring the use of a
deglitcher in digital audio applications.
1 NC = no connect.
5V
100
90
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • •
Driving the Analog Input of an Analog-to-Digital
Converter
An op amp driving the analog input of an analog-to-digital
converter (ADC), such as that shown in Figure 37, must be
capable of maintaining a constant output voltage under dynami-
cally changing load conditions. In successive approximation
converters, the input current is compared to a series of switched
trial currents. The comparison point is diode clamped but may
vary by several hundred millivolts, resulting in high frequency
modulation of the analog-to-digital input current. The output
impedance of a feedback amplifier is made artificially low by its
10
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • •
0%
2µs
Figure 34. Pulse Response of High Speed Instrumentation Amplifier,
Gain = 10
Rev. F | Page 12 of 20
AD713
loop gain. At high frequencies, where the loop gain is low, the
amplifier output impedance can approach its open-loop value.
1mV
AD713 BUFF
100
90
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
STS
LOGIC
12/8 (MSB) DB11
3
CS
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
HIGH
BITS
4
A
O
AD574A
TOP VIEW
(Not to Scale)
5
R/C
CE
6
V
7
CC
MIDDLE
BITS
8
REF OUT
AC
GAIN ADJUST
9
10
10
11
12
13
14
REF IN
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0%
+15V
0.1µF
R2 100Ω
R1 100Ω
V
EE
LOW
BITS
BIP OFF
10V
500mV
–5V ADC IN
200ns
IN
IN
(LSB) DB0
DC
4
OFFSET ADJUST
20V
±10V
ANALOG
INPUT
Figure 39. Buffer Recovery Time Sink Current = 1 mA
11
0.1µF
ANALOG COM
Driving A Large Capacitive Load
1/4
AD713
–15V
The circuit of Figure 40 uses a 100 Ω isolation resistor that
enables the amplifier to drive capacitive loads exceeding
1500 pF; the resistor effectively isolates the high frequency
feedback from the load and stabilizes the circuit. Low frequency
feedback is returned to the amplifier summing junction via the
low-pass filter formed by the 100 Ω series resistor and the load
capacitance, CL. Figure 41 shows a typical transient response for
this connection.
Figure 37. AD713 as an ADC Buffer
Most IC amplifiers exhibit a minimum open-loop output imped-
ance of 25 Ω, due to current limiting resistors. A few hundred
microamps reflected from the change in converter loading can
introduce errors in instantaneous input voltage. If the analog-
to-digital conversion speed is not excessive and the bandwidth
of the amplifier is sufficient, the amplifier output returns to
the nominal value before the converter makes its comparison.
However, many amplifiers have relatively narrow bandwidths,
yielding slow recovery from output transients. The AD713 is
ideally suited as a driver for ADCs because it offers both a wide
bandwidth and a high open-loop gain.
4.99kΩ
30pF
+V
S
0.1µF
4.99kΩ
4
INPUT
OUTPUT
100Ω
1/4
TYPICAL CAPACITANCE
LIMIT FOR VARIOUS
LOAD RESISTORS
AD713
1mV
AD713 BUFF
C
R
L
L
11
0.1µF
100
90
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • •
R
C UP TO
L
L
2kΩ 1500pF
10kΩ 1500pF
20kΩ 1000pF
–V
S
Figure 40. Circuit for Driving a Large Capacitance Load
5V
1µs
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • •
100
90
10
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • •
0%
500mV
10V ADC IN
200ns
Figure 38. Buffer Recovery Time Source Current = 2 mA
10
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• • • •
0%
Figure 41. Transient Response, RL = 2 kΩ, CL = 500 pF
Rev. F | Page 13 of 20
AD713
R2*
V
DD
CMOS DAC APPLICATIONS
+15V
0.1µF
C1
The AD713 is an excellent output amplifier for CMOS DACs. It
can be used to perform both two- and four-quadrant operation.
The output impedance of a DAC using an inverted R-2R ladder
approaches R for codes containing many 1s, 3R for codes
containing a single 1, and infinity for codes containing all 0s.
33pF
GAIN
ADJUST
18
20
V
R
FB
DD
1
4
OUT1
V
19
V
IN
REF
1/4
R1*
AD7545
V
OUT
AD713
2
AGND
11
0.1µF
DGND
3
ANALOG
COMMON
For example, the output resistance of the AD7545 modulates
between 11 kΩ and 33 kΩ. Therefore, with the DAC’s internal
feedback resistance of 11 kΩ, the noise gain varies from 2 to
4/3. This changing noise gain modulates the effect of the input
offset voltage of the amplifier, resulting in nonlinear DAC
amplifier performance. The AD713, with its guaranteed 1.5 mV
input offset voltage, minimizes this effect, achieving 12-bit
performance.
–15V
DB11 TO DB0
*REFER TO TABLE 5.
Figure 42. Unipolar Binary Operation
FILTER APPLICATIONS
A Programmable State Variable Filter
For the state variable or universal filter configuration of Figure 44
to function properly, DAC A1 and DAC B1 must control the
gain and Q of the filter characteristic, and DAC A2 and DAC B2
must accurately track for the simple expression of fC to be true.
This is readily accomplished using two AD7528 DACs and one
AD713 quad op amp. Capacitor C3 compensates for the effects
of op amp gain bandwidth limitations.
Figure 42 and Figure 43 show the AD713 and a 12-bit CMOS
DAC, the AD7545, configured for either a unipolar binary (two-
quadrant multiplication) or bipolar (four-quadrant multiplication)
operation. Capacitor C1 provides phase compensation, which
reduces overshoot and ringing.
Table 5. Recommended Trim Resistor Values vs. Grades for
AD7545 for VD = 5 V
This filter provides low-pass, high-pass, and band-pass outputs
and is ideally suited for applications where microprocessor
control of filter parameters is required. The programmable
range for component values shown is fC = 0 kHz to 15 kHz and
Q = 0.3 to 4.5.
Trim Resistor JN/AQ
KN/BQ
200 Ω
68 Ω
LN/CQ
100 Ω
33 Ω
GLN/GCQ
R1
R2
500 Ω
150 Ω
20 Ω
6.8 Ω
R2*
V
DD
R4
R5
20kΩ
1%
+15V
0.1µF
20kΩ
C1
33pF
1%
GAIN
ADJUST
18
20
R3
10kΩ
1%
V
R
FB
DD
1
OUT1
AGND
4
V
19
V
IN
REF
1/4
R1*
AD7545
AD713
1/4
2
V
OUT
AD713
DGND
3
11
0.1µF
12
DATA INPUT
DB11 TO DB0
ANALOG
COMMON
–15V
*REFER TO TABLE 5.
Figure 43. Bipolar Operation
Rev. F | Page 14 of 20
AD713
R5
30kΩ
+V
4
S
1µF
C1
1000pF
C2
1000pF
R4
CIRCUIT EQUATIONS
C3
33pF
30kΩ
+
R3
10kΩ
2
3
C
= C , R = R , R = R
2 1 2 4 5
1
1
6
5
9
13
12
A1
HIGH
LOW PASS
OUTPUT
7
8
14
A2
PASS
A3
A4
1/4
AD713
OUTPUT
1
10
1/4
AD713
f
=
C
11
2π R
C
1
1/4
AD713
1/4
1
AD713
+
1µF
R
R
R
F
3
Q =
×
V
V
DD
DD
R
4
FBB1
2
20
19
18
4
2
18
20
–V
S
17
4
17
BAND PASS
OUTPUT
AD7528
DAC A1
R
F
A = –
O
1
5
1
5
R
V
S
IN
DAC B1
DAC A2
R1
DAC B2
R2
AD7528
R
R
S
F
15
16
6
15
16
6
14
7
14
7
DAC EQUIVALENT RESISTANCE EQUALS
256 × (DAC LADDER RESISTANCE)
DAC DIGITAL CODE
DB0 TO
DB0 TO
DB7
DB7
CS
WR DAC A/
DACB
CS
WR DAC A/
DAC B
DATA 1
DATA 2
Figure 44. A Programmable State Variable Filter Circuit
0
GIC AND FDNR FILTER APPLICATIONS
0
–1
–2
–3
–4
The closely matched and uniform ac characteristics of the AD713
make it ideal for use in generalized impedance converter (GIC)/
gyrator and frequency dependent negative resistor (FDNR)
filter applications. Figure 47 and Figure 48 show the AD713
used in two typical active filters. The first shows a single AD713
simulating two coupled inductors configured as a one-third
octave band-pass filter. A single section of this filter meets
ANSI Class II specifications and handles a 7.07 V rms signal
with <0.002% THD (20 Hz to 20 kHz).
–10
–20
–30
–5
16 18 20 22 24
–40
–50
–60
FREQUENCY (MHz)
Figure 48 shows a seven-pole antialiasing filter for a 2× over-
sampling (88.2 kHz) digital audio application. This filter has
<0.05 dB pass-band ripple and 19.8 ꢀs 0.3 ꢀs delay, at dc to
20 kHz, and handles a 5 V rms signal (VS = 15 V) with no
overload at any internal nodes.
–70
0
10
20
30
40
50
60
70
80
90
100
FREQUENCY (MHz)
Figure 45. Output Amplitude vs. Frequency of 1/3 Octave Filter
3
OUTPUT AMPLITUDE
2
The filter of Figure 47 can be scaled for any center frequency by
using the following formula:
0
–10
–20
–30
–40
–50
1
0
–1
1.11
2πRC
200 500 1k 2k
5k 10k 20k
fC
=
18
19
20
21
22
GROUP DELAY
where all resistors and capacitors scale equally. Resistors R3 to
R8 should not be greater than 2 kꢁ in value to prevent parasitic
oscillations caused by the amplifier’s input capacitance.
–60
–70
–80
200 500 1k 2k
5k 10k 20k
If this is not practical, add small lead capacitances (10 pF to
20 pF) across R5 and R6. Figure 45 and Figure 46 show the
output amplitude vs. frequency of these filters.
–90
–100
–110
–120
10k
100k
1M
FREQUENCY (MHz)
Figure 46. Relative Output Amplitude vs. Frequency of Antialiasing Filter
Rev. F | Page 15 of 20
AD713
R1
6.19kΩ
INPUT
OUTPUT
C2
C2
6800pF
R2
6800pF
6.19kΩ
R3
1300Ω
R4
1300Ω
5
6
12
13
1/4
AD713
1/4
AD713
R5
R6
7
14
1300Ω
1300Ω
2
1/4
9
1/4
R7
1300Ω
R8
1300Ω
1
8
AD713
AD713
1.11
2πRC
3
10
f
=
C3
6800pF
C4
6800pF
C
C
R
R
R
= C = C = C = C
2 3 4
R9
1300Ω
R10
1300Ω
1
R11
5.62kΩ
= R = 4.76Ω
1
2
AD713
PIN 4
+V
S
+
= 4.32Ω
11
0.1µF
0.1µF
1µF
1µF
COM
= R = R = R = R = R = R = R = R
3
4
5
6
7
8
9
10
+
AD713
PIN 11
–V
S
Figure 47. A 1/3 Octave Filter Circuit
95.3kΩ
1/4
AD713
1/4
2
3
AD713
412Ω
1.74kΩ
1.74kΩ
330Ω
1
12
13
A1
14
INPUT
4700pF
B4
1kΩ
OUTPUT
100kΩ
130Ω
4700pF
10kΩ
36Ω
120Ω
1kΩ
4700pF
4700pF
4700pF
10
9
3
10
9
1kΩ
1kΩ
1kΩ
1kΩ
8
1
8
A3
1/4
B1
1/4
B3
1/4
2
6
13
12
6
7
14
7
A2
A4
B2
1kΩ
1kΩ
AD713
AD713
AD713
5
5
1/4
AD713
1/4
AD713
1/4
AD713
1.2kΩ
1.87kΩ
1.1kΩ
AD713
PIN 4
+V
S
+
0.1µF
1µF
1µF
4700pF
4700pF
4700pF
COM
+
0.1µF
AD713
PIN 11
–V
S
Figure 48. An Antialiasing Filter
Rev. F | Page 16 of 20
AD713
OUTLINE DIMENSIONS
0.775 (19.69)
0.750 (19.05)
0.735 (18.67)
14
1
8
7
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.110 (2.79)
0.015 (0.38)
GAUGE
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
PLANE
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.005 (0.13)
MIN
0.070 (1.78)
0.050 (1.27)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 49. 14-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-14)
Dimensions shown in inches and (millimeters)
0.098 (2.49) MAX
8
0.005 (0.13) MIN
14
0.310 (7.87)
0.220 (5.59)
1
7
PIN 1
0.100 (2.54) BSC
0.785 (19.94) MAX
0.320 (8.13)
0.290 (7.37)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.150
(3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
15°
0°
0.070 (1.78)
0.030 (0.76)
0.023 (0.58)
0.014 (0.36)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 50. 14-Lead Ceramic Dual In-Line Package [CERDIP]
(Q-14)
Dimensions shown in inches and (millimeters)
Rev. F | Page 17 of 20
AD713
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.0098)
1.27 (0.0500)
BSC
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 51. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1
AD713AQ
AD713JNZ
AD713JR-16
AD713JR-16-REEL
AD713JR-16-REEL7
AD713JRZ-16
AD713JRZ-16-REEL
AD713JRZ-16-REEL7
Temperature Range
Package Description
14-Lead CERDIP
14-Lead PDIP
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
16-Lead SOIC_W
Package Option
Q-14
N-14
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
−40°C to +85°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
1 Z = RoHS Compliant Part.
Rev. F | Page 18 of 20
AD713
NOTES
Rev. F | Page 19 of 20
AD713
NOTES
©2002–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00824-0-7/11(F)
Rev. F | Page 20 of 20
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