AD7142ACPZ-1REEL1 [ADI]
Programmable Controller for Capacitance Touch Sensors; 对于电容式触摸传感器的可编程控制器
| 型号： | AD7142ACPZ-1REEL1 |
| 厂家： | 
ADI |
| 描述： | Programmable Controller for Capacitance Touch Sensors |
| 文件： | 总73页 (文件大小：844K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Programmable Controller for
Capacitance Touch Sensors
AD7142
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
V
REF– REF+
TEST
27
Programmable capacitance-to-digital converter
36 ms update rate (@ maximum sequence length)
Better than 1 fF resolution
14 capacitance sensor input channels
No external RC tuning components required
Automatic conversion sequencer
On-chip automatic calibration logic
Automatic compensation for environmental changes
Automatic adaptive threshold and sensitivity levels
On-chip RAM to store calibration data
SPI®-compatible serial interface (AD7142)
I2C®-compatible serial interface (AD7142-1)
Separate VDRIVE level for serial interface
Interrupt output and GPIO
29 28
30
31
32
1
CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8
CIN9
CIN10
CIN11
CIN12
CIN13
POWER-ON
RESET
LOGIC
AV
CC
13
2
3
14 AGND
4
16-BIT
CALIBRATION
ENGINE
Σ-Δ
5
CDC
6
17
18
19
DV
7
CC
8
CALIBRATION
RAM
DGND1
DGND2
9
10
11
CONTROL
AND
DATA
REGISTERS
C
12
15
16
SHIELD
SRC
250kHz
EXCITATION
SOURCE
32-lead, 5 mm x 5 mm LFCSP_VQ
2.6 V to 3.6 V supply voltage
SRC
Low operating current
Full power mode: less than 1 mA
INTERRUPT
AND GPIO
LOGIC
SERIAL INTERFACE
AND CONTROL LOGIC
V
DRIVE 20
26
GPIO
Low power mode: 50 μA
22
23
24
25
21
SDO/
SDA
SDI/
ADD0
CS/
ADD1
SCLK
INT
APPLICATIONS
Figure 1.
Personal music and multimedia players
Cell phones
Digital still cameras
Smart hand-held devices
Television, A/V, and remote controls
Gaming consoles
GENERAL DESCRIPTION
The AD7142 and AD7142-1 are integrated capacitance-to-
digital converters (CDCs) with on-chip environmental
calibration for use in systems requiring a novel user input
method. The AD7142 and AD7142-1 can interface to external
capacitance sensors implementing functions such as capacitive
buttons, scroll bars, or wheels.
The AD7142 and AD7142-1 have on-chip calibration logic to
account for changes in the ambient environment. The calibration
sequence is performed automatically and at continuous intervals,
when the sensors are not touched. This ensures that there are no
false or nonregistering touches on the external sensors due to a
changing environment.
The CDC has 14 inputs channeled through a switch matrix to a
16-bit, 250 kHz sigma-delta (∑-Δ) capacitance-to-digital
converter. The CDC is capable of sensing changes in the
capacitance of the external sensors and uses this information to
register a sensor activation. The external sensors can be
arranged as a series of buttons, as a scroll bar or wheel, or as a
combination of sensor types. By programming the registers, the
user has full control over the CDC setup. High resolution
sensors require minor software to run on the host processor.
The AD7142 has an SPI-compatible serial interface, and the
AD7142-1 has an I2C-compatible serial interface. Both parts
have an interrupt output, as well as a general-purpose input/
output (GPIO).
The AD7142 and AD7142-1 are available in a 32-lead, 5 mm ×
5 mm LFCSP_VQ and operate from a 2.6 V to 3.6 V supply. The
operating current consumption is less than 1 mA, falling to
50 μA in low power mode (conversion interval of 400 ms).
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
IMPORTANT LINKS for the AD7142*
Last content update 06/27/2013 05:41 am
This product is not recommended for new designs. The AD7147 is recommended instead for new CapTouch(R) designs.
PARAMETRIC SELECTION TABLES
DESIGN TOOLS, MODELS, DRIVERS & SOFTWARE
AD714X Input CapTouch(R) Programmable Controller Linux Driver
Find Similar Products By Operating Parameters
DOCUMENTATION
EVALUATION KITS & SYMBOLS & FOOTPRINTS
Symbols and Footprints
AN-854: Sensor PCB Design Guidelines for the AD7142 and AD7143
Capacitance-to-Digital Converters
Applications
AN-929: Tuning the AD714x for CapTouch(R)
AN-857: Introduction to AD7142 Host Software Requirements
AN-858: AD7142 Sensor Board In-Line Production Test Procedure
AN-830: Factors Affecting Sensor Response
DESIGN COLLABORATION COMMUNITY
AN-829: Environmental Compensation on the AD7142: The Effects of
Temperature and Humidity on Capacitance Sensors
Collaborate Online with the ADI support team and other designers
about select ADI products.
Webcast: Design And Develop Innovative And Robust Touch Sensor
Interfaces Using Capacitive-To-Digital Converters
Follow us on Twitter: www.twitter.com/ADI_News
Like us on Facebook: www.facebook.com/AnalogDevicesInc
Capacitance Sensors for Human Interfaces to Electronic Equipment
MS-2210: Designing Power Supplies for High Speed ADC
Capacitive Sensors Can Replace Mechanical Switches for Touch
Control
Programmable Medical Infusion Pumps Offer High Reliability and
Performance
DESIGN SUPPORT
Submit your support request here:
Linear and Data Converters
Embedded Processing and DSP
Building a reliable capacitive-sensor interface
EE Times Names ACE Finalists
Programmable 16-Bit CDC Targets Handheld Touch Screen Apps
Programmable Capacitance-to-Digital Converter Includes 14
Channels
Telephone our Customer Interaction Centers toll free:
Americas:
Europe:
China:
1-800-262-5643
00800-266-822-82
4006-100-006
Capacitance-To-Digital Converter Eases Touch-Based Switch
Implementation
India:
Russia:
1800-419-0108
8-800-555-45-90
Capacitance-To-Digital Converter Simplifies Touchpad Design
ADI’s Capacitance-To-Digital Converter
Quality and Reliability
Lead(Pb)-Free Data
analogZONE Reviews The AD7142 CDC
Capacitive Touch Sensors Gain Fans
iPod’s Lesson: Please Touch
Capacitive Touch Sensors Fulfill Early Promise
Motion Sensing Devices Make Integrated Systems Easy
Visit the AD7142 Product Page for more documentation.
SAMPLE & BUY
AD7142
View Price & Packaging
Request Evaluation Board
Request Samples Check Inventory & Purchase
Find Local Distributors
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet.
Note: Dynamic changes to the content on this page (labeled 'Important Links') does not
constitute a change to the revision number of the product data sheet.
This content may be frequently modified.
AD7142
TABLE OF CONTENTS
Features .............................................................................................. 1
Capacitance Sensor Behavior with Calibration...................... 22
SLOW FIFO ................................................................................ 23
SLOW_FILTER_UPDATE_LVL.............................................. 23
Adaptive Threshold and Sensitivity ............................................. 24
Interrupt Output............................................................................. 26
CDC Conversion Complete Interrupt..................................... 26
Sensor Touch Interrupt.............................................................. 26
INT
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
SPI Timing Specifications (AD7142)......................................... 6
I2C Timing Specifications (AD7142-1) ..................................... 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 12
Capacitance Sensing Theory..................................................... 12
Operating Modes........................................................................ 13
Capacitance Sensor Input Configuration.................................... 14
CIN Input Multiplexer Setup.................................................... 14
Capacitance-to-Digital Converter................................................ 15
Oversampling the CDC Output ............................................... 15
Capacitance Sensor Offset Control.......................................... 15
Conversion Sequencer ............................................................... 15
CDC Conversion Sequence Time ............................................ 16
CDC Conversion Results........................................................... 17
Noncontact Proximity Detection ................................................. 18
Recalibration ............................................................................... 18
Proximity Sensitivity.................................................................. 18
FF_SKIP_CNT............................................................................ 20
Environmental Calibration ........................................................... 22
Capacitance Sensor Behavior Without Calibration............... 22
GPIO
Output Control ....................................................... 28
Outputs ............................................................................................ 30
Excitation Source........................................................................ 30
CSHIELD Output ............................................................................. 30
GPIO ............................................................................................ 30
Using the GPIO to turn on/off an LED................................... 30
Serial Interface ................................................................................ 31
SPI Interface................................................................................ 31
I2C Compatible Interface........................................................... 33
VDRIVE Input ................................................................................. 35
PCB Design Guidelines ................................................................. 36
Capacitive Sensor Board Mechanical Specifications............. 36
Chip Scale Packages ................................................................... 36
Power-Up Sequence ....................................................................... 37
Typical Application Circuits ......................................................... 38
Register Map ................................................................................... 39
Detailed Register Descriptions ..................................................... 40
Bank 1 Registers ......................................................................... 40
Bank 2 Registers ......................................................................... 50
Bank 3 Registers ......................................................................... 57
Outline Dimensions....................................................................... 69
Ordering Guide .......................................................................... 69
Rev. A | Page 2 of 72
AD7142
Added Slow FIFO and
REVISION HISTORY
SLOW_FILTER_UPDATE_LVL Section...................................23
Changes to Adaptive Threshold and Sensitivity Section ...........24
Inserted Figure 37 and Table 13 ....................................................25
Deleted Figure 42 ............................................................................29
Changes to CSHIELD Output Section ...............................................30
Changes to Figure 55 ......................................................................36
Changes to Power-up Sequence Section ......................................37
Changes to Figure 58 ......................................................................38
Changes to Table 21 ........................................................................42
Changes to Table 24 ........................................................................43
Changes to Table 25 ........................................................................44
Changes to Table 29 ........................................................................48
Changes to Table 31 ........................................................................49
1/07—Rev. 0 to Rev. A
Updated Format.................................................................. Universal
Changes to Data Sheet Title.............................................................1
Inserted Figure 5................................................................................8
Changes to Figure 18 ......................................................................12
Changes to Operating Modes Section..........................................13
Changes to CIN Input Multiplexer Setup Section ......................14
Changes to Table 9 and Conversion Sequencer Section ............15
Changes to Noncontact Proximity Detection Section ...............18
Changes to Recalibration Section and Table 12 ..........................18
Deleted FIFO Control Section.......................................................19
Changes to Figure 31 and Table 13 ...............................................20
Changes to Figure 32 ......................................................................21
Changes to Capacitance Sensor Behavior with
6/06—Revision 0: Initial Version
Calibration Section.....................................................................22
Rev. A | Page 3 of 72
AD7142
SPECIFICATIONS
AVCC, DVCC = 2.6 V to 3.6 V, TA = −40oC to +85°C, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max Unit
Test Conditions/Comments
CAPACITANCE-TO-DIGITAL CONVERTER
Update Rate
Resolution
CIN Input Range1
35.45
36.86
16
2
38.4 ms
12 conversion stages in sequencer, decimation rate = 256
Bit
pF
Bit
nA
No Missing Codes
16
Guaranteed by design, but not production tested
CIN Input Leakage
Total Unadjusted Error
Output Noise (Peak-to-Peak)
25
2ꢀ
%
7
3
ꢀ.8
ꢀ.5
Codes Decimation rate = 128
Codes Decimation rate = 256
Codes Decimation rate = 128
Codes Decimation rate = 256
Output Noise (RMS)
Parasitic Capacitance
4ꢀ
pF
Parasitic capacitance to ground, per CIN input
guaranteed by characterization
CBULK Offset Range1
CBULK Offset Resolution
Low Power Mode Delay Accuracy
EXCITATION SOURCE
Frequency
2ꢀ
156.25
pF
fF
%
4
% of 2ꢀꢀ ms, 4ꢀꢀ ms, 6ꢀꢀ ms, or 8ꢀꢀ ms
24ꢀ
25ꢀ
26ꢀ
AVCC
kHz
V
Output Voltage
Short-Circuit Source Current
Short-Circuit Sink Current
Maximum Output Load
CSHIELD Output Drive
2ꢀ
5ꢀ
25ꢀ
1ꢀ
AVCC/2
mA
mA
pF
μA
V
Capacitance load on source to ground
CSHIELD Bias Level
CS
LOGIC INPUTS (SDI, SCLK, , SDA, GPI TEST)
VIH Input High Voltage
VIL Input Low Voltage
IIH Input High Voltage
IIL Input Low Voltage
Hysteresis
ꢀ.7 × VDRIVE
−1
V
V
μA
μA
mV
ꢀ.4
1
VIN = VDRIVE
VIN = DGND
15ꢀ
ꢀ.1
OPEN-DRAIN OUTPUTS (SCLK, SDA, INT)
VOL Output Low Voltage
IOH Output High Leakage Current
LOGIC OUTPUTS (SDO, GPO)
VOL Output Low Voltage
VOH Output High Voltage
SDO Floating State Leakage Current
GPO Floating State Leakage Current
POWER
ꢀ.4
1
V
μA
ISINK = −1 mA
VOUT = VDRIVE
ꢀ.4
V
V
μA
μA
ISINK = 1 mA, VDRIVE = 1.65 V to 3.6 V
ISOURCE = 1 mA, VDRIVE = 1.65 V to 3.6 V
Pin three-state, leakage measured to GND and DVCC
Pin three-state, leakage measured to GND and DVCC
VDRIVE − ꢀ.6
−5
1
2
AVCC, DVCC
VDRIVE
ICC
2.6
1.65
3.3
ꢀ.9
16
3.6
3.6
1
2ꢀ
33
4.5
18
V
V
Serial interface operating voltage
In full power mode
Low power mode, converter idle, TA = 25°C
Low power mode, converter idle
Full shutdown, TA = 25°C
mA
μA
μA
μA
μA
2.25
Full shutdown
1 CIN and CBULK are defined in Figure 2.
Rev. A | Page 4 of 72
AD7142
C
IN
PLASTIC OVERLAY
SENSOR BOARD
C
BULK
CAPACITIVE SENSOR
Figure 2.
SRC
Table 2. Typical Average Current in Low Power Mode, AVCC, DVCC = 3.6 V, T= 25°C, Load of 50 pF on SRC Pin, No Load on
Number of Conversion Stages (Current Values Expressed in ꢀA)
Low Power Mode
Delay
Decimation
Rate
1
2
3
4
5
6
7
8
9
10
11
12
2ꢀꢀ ms
4ꢀꢀ ms
6ꢀꢀ ms
8ꢀꢀ ms
128
256
128
256
128
256
128
256
26.4
35.6
21.3
26
33.3
49.1
24.8
32.9
21.9
27.4
2ꢀ.5
24.6
4ꢀ.1
62.2
28.3
39.7
24.3
32
46.9
74.9
31.7
46.5
26.6
36.6
24
53.5
87.3
35.2
53.1
28.9
41.1
25.7
35
6ꢀ
66.5
111
42
66.1
33.5
5ꢀ
72.8
79.1
85.2
91.3
97.3
99.3
38.6
59.6
31.2
45.6
27.5
38.4
122.3 133.4 144.2 154.7 164.9
45.4
72.4
35.8
54.4
31
48.7
78.7
38.1
58.8
32.7
48.5
52
55.3
91
58.6
97
84.9
4ꢀ.4
63.1
34.4
51.8
19.6
22.7
18.7
21.1
42.6
67.4
36.1
55.1
44.8
71.6
37.8
58.4
22.2
28.1
29.2
41.8
31.5
45.2
SRC
Table 3. Maximum Average Current in Low Power Mode, AVCC, DVCC = 3.6 V, Load of 50 pF on SRC Pin, No Load on
Number of Conversion Stages (Current Values Expressed in ꢀA)
Low Power Mode Decimation
Delay
Rate
128
256
128
256
128
256
128
256
1
2
3
4
5
6
7
8
9
10
11
12
2ꢀꢀ ms
45.4
56.2
39.5
45
53.6
72
61.5
87.2
47.7
61.1
43
52.1
4ꢀ.7
47.5
69.4
1ꢀ2
51.8
68.9
45.8
57.4
42.7
51.5
77.1
84.7
92.2
99.6
1ꢀ6.8 113.9 121
127.9
116.3 13ꢀ.2 143.7 156.8 169.5 181.8 193.8 2ꢀ5.5
4ꢀꢀ ms
6ꢀꢀ ms
8ꢀꢀ ms
43.6
53.1
4ꢀ.3
46.7
38.6
43.4
55.8
76.7
48.5
62.7
44.8
55.6
59.8
84.3
51.2
67.9
46.8
59.5
63.7
91.8
53.9
73.1
48.8
63.5
67.6
99.1
56.5
78.2
5ꢀ.9
67.4
71.5
75.4
79.2
83
1ꢀ6.4 113.6 12ꢀ.6 127.5
37.5
41.2
36.5
39.3
59.2
83.3
52.9
71.3
61.8
88.3
54.9
75.2
64.5
93.3
56.9
79
67.1
98.2
58.9
82.8
Rev. A | Page 5 of 72
AD7142
SPI TIMING SPECIFICATIONS (AD7142)
TA = −40°C to +85°C; VDRIVE = 1.65 V to 3.6 V; AVCC, DVCC = 2.6 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure
compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V.
Table 4. SPI Timing Specifications
Parameter
Limit at TMIN, TMAX
Unit
Description
fSCLK
t1
5
5
MHz max
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
CS falling edge to first SCLK falling edge
SCLK high pulse width
SCLK low pulse width
SDI setup time
SDI hold time
SDO access time after SCLK falling edge
CS rising edge to SDO high impedance
SCLK rising edge to CS high
t2
t3
t4
t5
t6
t7
2ꢀ
2ꢀ
15
15
2ꢀ
16
15
t8
CS
t1
t2
t8
t3
15
15
1
2
3
16
1
2
16
SCLK
t4
t5
LSB
MSB
SDI
t6
t7
SDO
MSB
LSB
Figure 3. SPI Detailed Timing Diagram
Rev. A | Page 6 of 72
AD7142
I2C TIMING SPECIFICATIONS (AD7142-1)
TA = −40°C to +85°C; VDRIVE = 1.65 V to 3.6 V; AVCC, DVCC = 2.6 V to 3.6 V, unless otherwise noted. Sample tested at 25°C to ensure
compliance. All input signals timed from a voltage level of 1.6 V.
Table 5. I2C Timing Specifications1
Parameter
Limit
4ꢀꢀ
ꢀ.6
1.3
ꢀ.6
1ꢀꢀ
3ꢀꢀ
ꢀ.6
ꢀ.6
1.3
Unit
Description
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
kHz max
μs min
μs min
μs min
ns min
ns min
μs min
μs min
μs min
ns max
ns max
Start condition hold time, tHD; STA
Clock low period, tLOW
Clock high period, tHIGH
Data setup time, tSU; DAT
Data hold time, tHD; DAT
Stop condition setup time, tSU; STO
Start condition setup time, tSU; STA
Bus free time between stop and start conditions, tBUF
Clock/data rise time
tR
tF
3ꢀꢀ
3ꢀꢀ
Clock/data fall time
1 Guaranteed by design, not production tested.
tR
tF
t1
t2
SCLK
t3
t7
t1
t6
t5
t4
SDATA
t8
STOP START
START
STOP
Figure 4. I2C Detailed Timing Diagram
Rev. A | Page 7 of 72
AD7142
ABSOLUTE MAXIMUM RATINGS
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 6.
Parameter
Rating
AVCC to AGND, DVCC to DGND
Analog Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Input Current to Any Pin Except
Supplies1
−ꢀ.3 V to +3.6 V
−ꢀ.3 V to AVCC + ꢀ.3 V
−ꢀ.3 V to VDRIVE + ꢀ.3 V
−ꢀ.3V to VDRIVE + ꢀ.3 V
1ꢀ mA
ESD Rating (Human Body Model)
Operating Temperature Range
Storage Temperature Range
Junction Temperature
LFCSP_VQ
Power Dissipation
2.5 kV
200µA
I
OL
−4ꢀ°C to +15ꢀ°C
−65°C to +15ꢀ°C
15ꢀ°C
TO OUTPUT
PIN
1.6V
C
50pF
L
45ꢀ mW
200µA
I
OH
θJA Thermal Impedance
IR Reflow Peak Temperature
Lead Temperature (Soldering 1ꢀ sec)
135.7°C/W
26ꢀ°C ( ꢀ.5°C)
3ꢀꢀ°C
Figure 5. Load Circuit for Digital Output Timing Specifications
ESD CAUTION
1Transient currents of up to 1ꢀꢀ mA do not cause SCR latch-up.
Rev. A | Page 8 of 72
AD7142
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8
CIN9
CIN10
1
2
3
4
5
6
7
8
24 CS
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8
CIN9
CIN10
1
2
3
4
5
6
7
8
24 ADD1
23 SCLK
22 ADD0
21 SDA
PIN 1
INDICATOR
PIN 1
INDICATOR
23 SCLK
22 SDI
21 SDO
AD7142
AD7142-1
TOP VIEW
(Not to Scale)
20
V
20
V
DRIVE
TOP VIEW
DRIVE
19 DGND2
18 DGND1
17 DV
19 DGND2
18 DGND1
17 DV
CC
CC
Figure 6. AD7142 Pin Configuration
Figure 7. AD7142-1 Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8
CIN9
CIN1ꢀ
CIN11
CIN12
CIN13
CSHIELD
AVCC
Description
1
2
3
4
5
6
7
8
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
9
1ꢀ
11
12
13
14
15
16
17
18
19
2ꢀ
21
CDC Shield Potential Output. Requires 1ꢀ nF capacitor to ground. Connect to external shield.
CDC Supply Voltage.
Analog Ground Reference Point for All CDC Circuitry. Tie to analog ground plane.
CDC Excitation Source Output.
AGND
SRC
SRC
Inverted Excitation Source Output.
DVCC
Digital Core Supply Voltage.
Digital Ground.
Digital Ground.
Serial Interface Operating Voltage Supply.
DGND1
DGND2
VDRIVE
SDO
(AD7142) SPI Serial Data Output.
SDA
SDI
ADDꢀ
SCLK
CS
(AD7142-1) I2C Serial Data Input/Output. SDA requires pull-up resistor.
(AD7142) SPI Serial Data Input.
22
(AD7142-1) I2C Address Bit ꢀ.
23
24
Clock Input for Serial Interface.
(AD7142) SPI Chip Select Signal.
ADD1
INT
(AD7142-1) I2C Address Bit 1.
General-Purpose Open-Drain Interrupt Output. Programmable polarity; requires pull-up resistor.
Programmable GPIO.
25
26
27
28
29
3ꢀ
31
32
GPIO
TEST
VREF+
Factory Test Pin. Tie to ground.
CDC Positive Reference Input. Normally tied to analog power.
CDC Negative Reference Input. Tie to analog ground.
Capacitance Sensor Input.
Capacitance Sensor Input.
Capacitance Sensor Input.
VREF−
CINꢀ
CIN1
CIN2
Rev. A | Page 9 of 72
AD7142
TYPICAL PERFORMANCE CHARACTERISTICS
1000
2.45
2.30
2.15
2.00
1.85
1.70
1.55
1.40
980
DEVICE 1
DEVICE 2
960
DEVICE 3
940
920
DEVICE 2
DEVICE 1
DEVICE 3
900
880
860
840
820
2.7
2.8
2.9
3.0
3.1
V
3.2
(V)
3.3
3.4
3.5
3.6
2.7
2.8
2.9
3.0
3.1
V
3.2
(V)
3.3
3.4
3.5
3.6
CC
CC
Figure 8. Supply Current vs. Supply Voltage
(VCC = AVCC + DVCC, ICC = AICC + DICC
Figure 11. Shutdown Supply Current vs. Supply Voltage
(VCC = AVCC + DVCC, ICC = AICC + DICC
)
)
1.10
1.05
1.00
0.95
0.90
0.85
0.80
180
DEVICE 1
LP_CONV_DELAY = 200ms
160
140
120
100
80
LP_CONV_DELAY = 400ms
DEVICE 3
DEVICE 2
LP_CONV_DELAY = 600ms
60
LP_CONV_DELAY = 800ms
40
2.7
0
50
100 150 200 250 300 350 400 450 500
CAPACITANCE LOAD ON SOURCE (pF)
2.8
2.9
3.0
3.1
V
3.2
(V)
3.3
3.4
3.5
3.6
CC
Figure 12. Supply Current vs. Capacitive Load on SRC (ICC = AICC + DICC
)
Figure 9. Low Power Supply Current vs. Supply Voltage,
Decimation Rate = 256 (VCC = AVCC + DVCC, ICC = AICC + DICC
)
120
16015
16010
16005
16000
15995
15990
15985
15980
DEVICE 1
100
80
LP_CONV_DELAY = 200ms
DEVICE 2
LP_CONV_DELAY = 400ms
LP_CONV_DELAY = 600ms
60
DEVICE 3
40
LP_CONV_DELAY = 800ms
20
2.7
2.8
2.9
3.0
3.10
V
3.2
(V)
3.3
3.4
3.5
3.6
0
50
100 150 200 250 300 350 400 450 500
CAPACITANCE LOAD ON SOURCE (pF)
CC
Figure 10. Low Power Supply Current vs. Supply Voltage
Decimation Rate = 128 (VCC = AVCC + DVCC, ICC = AICC + DICC
Figure 13. Output Code vs. Capacitive Load on SRC
)
Rev. A | Page 1ꢀ of 72
AD7142
960
940
920
900
880
860
840
820
800
780
2.5
2.0
1.5
1.0
0.5
0
100mV
200mV
300mV
400mV
500mV
3.6V
3.3V
2.7V
–40
–20
0
20
40
60
80
100
120
10
1k
100k
FREQUENCY (Hz)
10M
TEMPERATURE (°C)
Figure 14. Supply Current vs. Temperature (Supply Current = AICC + DICC
)
Figure 16. Power Supply Sine Wave Rejection
12
180
160
140
120
100
80
10
8
300mV
6
3.6V
3.3V
4
60
200mV
100mV
40
2
50mV
25mV
20
2.7V
100
0
–40
0
100
–20
0
20
40
60
80
120
1k
10k
100k
1M
10M
TEMPERATURE (°C)
SQUARE WAVE FREQUENCY (Hz)
Figure 15. Shutdown Supply Current vs. Temperature
(Supply Current = AICC + DICC
Figure 17. Power Supply Square Wave Rejection
)
Rev. A | Page 11 of 72
AD7142
THEORY OF OPERATION
CAPACITANCE SENSING THEORY
The AD7142 and AD7142-1 are capacitance-to-digital
converters (CDCs) with on-chip environmental compensation,
intended for use in portable systems requiring high resolution
user input. The internal circuitry consists of a 16-bit, ∑-Δ con-
verter that converts a capacitive input signal into a digital value.
There are 14 input pins on the AD7142 and AD7142-1, CIN0 to
CIN13. A switch matrix routes the input signals to the CDC.
The result of each capacitance-to-digital conversion is stored in
on-chip registers. The host subsequently reads the results over
the serial interface. The AD7142 contains an SPI interface and
the AD7142-1 has an I2C interface ensuring that the parts are
compatible with a wide range of host processors. Because the
AD7142 and AD7142-1 are identical parts, with the exception of
the serial interface, AD7142 refers to both the AD7142 and
AD7142-1 throughout this data sheet.
The AD7142 uses a method of sensing capacitance known as
the shunt method. Using this method, an excitation source is
connected to a transmitter generating an electric field to a
receiver. The field lines measured at the receiver are translated
into the digital domain by a ∑-Δ converter. When a finger, or
other grounded object, interferes with the electric field, some of
the field lines are shunted to ground and do not reach the
receiver (see Figure 18). Therefore, the total capacitance
measured at the receiver decreases when an object comes close
to the induced field.
The AD7142 interfaces with up to 14 external capacitance
sensors. These sensors can be arranged as buttons, scroll bars,
wheels, or as a combination of sensor types. The external
sensors consist of electrodes on a single or multiple layer PCB
that interfaces directly to the AD7142.
PLASTIC COVER
PCB LAYER 1
Tx
Rx
The AD7142 can be set up to implement any set of input
sensors by programming the on-chip registers. The registers can
also be programmed to control features such as averaging,
offsets, and gains for each of the external sensors. There is a
sequencer on-chip to control how each of the capacitance
inputs is polled.
16-BIT
DATA
EXCITATION
SIGNAL
250kHz
Σ-Δ
ADC
AD7142
Figure 18. Sensing Capacitance Method
The AD7142 has on-chip digital logic and 528 words of RAM
that are used for environmental compensation. The effects of
humidity, temperature, and other environmental factors can
effect the operation of capacitance sensors. Transparent to the
user, the AD7142 performs continuous calibration to compen-
sate for these effects, allowing the AD7142 to give error-free
results at all times.
In practice, the excitation source and ∑-Δ ADC are implemented
on the AD7142, and the transmitter and receiver are constructed
on a PCB that makes up the external sensor.
Registering a Sensor Activation
When a sensor is approached, the total capacitance associated
with that sensor, measured by the AD7142, changes. When the
capacitance changes to such an extent that a set threshold is
exceeded, the AD7142 registers this as a sensor touch.
The AD7142 requires some minor companion software that
runs on the host or other microcontroller to implement high
resolution sensor functions such as a scroll bar or wheel.
However, no companion software is required to implement
buttons, including 8-way button functionality. Button sensors
are implemented completely in digital logic on-chip.
Preprogrammed threshold levels are used to determine if a
change in capacitance is due to a button being activated. If the
capacitance exceeds one of the threshold limits, the AD7142
registers this as a true button activation. The same thresholds
principle is used to determine if other types of sensors, such as
sliders or scroll wheels, are activated.
The AD7142 can be programmed to operate in either full power
mode, or in low power automatic wake-up mode. The
automatic wake-up mode is particularly suited for portable
devices that require low power operation giving the user
significant power savings coupled with full functionality.
INT
The AD7142 has an interrupt output,
, to indicate when
INT
new data has been placed into the registers.
is used to
interrupt the host on sensor activation. The AD7142 operates
from a 2.6 V to 3.6 V supply, and is available in a 32-lead, 5 mm ×
5 mm LFCSP_VQ.
Rev. A | Page 12 of 72
AD7142
Complete Solution for Capacitance Sensing
Low Power Mode
Analog Devices, Inc. provides a complete solution for
capacitance sensing. The two main elements to the solution are
the sensor PCB and the AD7142.
When in low power mode, the AD7142 POWER_MODE bits
are set to 10 upon device initialization. If the external sensors
are not touched, the AD7142 reduces its conversion frequency,
thereby greatly reducing its power consumption. The part
remains in a reduced power state when the sensors are not
touched. Every LP_CONV_DELAY ms (200, 400, 600 or 800 ms),
the AD7142 performs a conversion and uses this data to update
the compensation logic. When an external sensor is touched,
the AD7142 begins a conversion sequence every 36 ms to read
back data from the sensors. In low power mode, the total
current consumption of the AD7142 is an average of the current
used during a conversion, and the current used when the
AD7142 is waiting for the next conversion to begin. For
example, when LP_CONV_DELAY l is 400 ms, the AD7142
typically uses 0.9 mA current for 36 ms, and 15 ꢀA for 400 ms
of the conversion interval. Note that these conversion timings
can be altered through the register settings. See the CDC
Conversion Sequence Time section for more information.
If the application requires high resolution sensors, such as scroll
bars or wheels, software is required that runs on the host
processor. (No software is required for button sensors.) The
memory requirements for the host depend on the sensor, and
are typically 10 kB of code and 600 bytes of data memory.
SENSOR PCB
HOST PROCESSOR
1 MIPS
2
SPI OR I C
AD7142
10kB ROM
600 BYTES RAM
Figure 19. Three Part Capacitance Sensing Solution
Analog Devices supplies the sensor PCB footprint design
libraries to the customer based on the customer’s specifications,
and supplies any necessary software on an open-source basis.
AD7142 SETUP
AND INITIALIZATION
POWER_MODE = 10
OPERATING MODES
The AD7142 has three operating modes. Full power mode,
where the device is always fully powered, is suited for applications
where power is not a concern (for example, game consoles that
have an ac power supply). Low power mode, where the part
automatically powers down, is tailored to give significant power
savings over full power mode, and is suited for mobile applications
where power must be conserved. In shutdown mode, the part
shuts down completely.
ANY
YES
NO
SENSOR
TOUCHED?
CONVERSION SEQUENCE
EVERY LP_CONV_DELAY ms
UPDATE COMPENSATION
LOGIC DATA PATH
CONVERSION SEQUENCE
EVERY 36ms FOR
SENSOR READBACK
YES
ANY SENSOR
TOUCHED?
The POWER_MODE bits (Bit 0 and Bit 1) of the control
register set the operating mode on the AD7142. The control
register is at Address 0x000. Table 8 shows the POWER_MODE
settings for each operating mode. To put the AD7142 into
shutdown mode, set the POWER_MODE bits to either 01 or 11.
NO
TIMEOUT
PROXIMITY TIMER
COUNT DOWN
Figure 20. Low Power Mode Operation
Table 8. POWER_MODE Settings
The time taken for the AD7142 to go from a full power state to
a reduced power state, once the user stops touching the external
sensors, is configurable. The PWR_DWN_TIMEOUT bits, in
Ambient Compensation Ctrl 0 Register, at Address 0x002,
control the length of time the AD7142 takes before going into
the reduced power state, once the sensors are not touched.
POWER_MODE Bits
Operating Mode
ꢀꢀ
ꢀ1
1ꢀ
11
Full power mode
Full shutdown mode
Low power mode
Full shutdown mode
The power-on default setting of the POWER_MODE bits is 00,
full power mode.
Full Power Mode
In full power mode, all sections of the AD7142 remain fully
powered at all times. When a sensor is being touched, the
AD7142 processes the sensor data. If no sensor is touched, the
AD7142 measures the ambient capacitance level and uses this
data for the on-chip compensation routines. In full power
mode, the AD7142 converts at a constant rate. See the CDC
Conversion Sequence Time section for more information.
Rev. A | Page 13 of 72
AD7142
CAPACITANCE SENSOR INPUT CONFIGURATION
Each input connection from the external capacitance sensors to
the AD7142 converter can be uniquely configured by using the
registers in Table 45 and Table 46. These registers are used to
configure input pin connection setups, sensor offsets, sensor
sensitivities, and sensor limits for each stage. Each sensor can be
individually optimized. For example, a button sensor connected
to STAGE0 can have different sensitivity and offset values than
a button with a different function that is connected to a
different stage.
CDC, or it can be left floating. Each input can also be internally
connected to the CSHIELD signal to help prevent cross coupling. If
an input is not used, always connect it to CSHIELD.
Connecting a CINx input pin to the positive CDC input results
in a decrease in CDC output code when the corresponding
sensor is activated. Connecting a CINx input pin to the negative
CDC input results in an increase in CDC output code when the
corresponding sensor is activated.
The multiplexer settings for each conversion sequence can be
unique and different for each of the input pins, CIN0 to CIN13.
For example, CIN0 is connected to the negative CDC input for
conversion STAGE1, left floating for sequencer STAGE1, and so
on for all twelve conversion stages.
CIN INPUT MULTIPLEXER SETUP
The CIN_CONNECTION_SETUP registers in Table 45 list the
different options that are provided for connecting the sensor
input pin to the CDC.
Two bits in each sequence stage register control the mux setting for
the input pin.
The AD7142 has an on-chip multiplexer to route the input
signals from each pin to the input of the converter. Each input
pin can be tied to either the negative or the positive input of the
CIN0
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8
CIN9
CIN10
CIN11
CIN12
CIN13
CIN_CONNECTION
_SETUP BITS
CIN SETTING
00
01
CINX FLOATING
CINX CONNECTED TO
NEGATIVE CDC INPUT
+
–
CDC
10
11
CINX CONNECTED TO
POSITIVE CDC INPUT
CINX CONNECTED TO
C
SHIELD
Figure 21. Input Mux Configuration Options
Rev. A | Page 14 of 72
AD7142
CAPACITANCE-TO-DIGITAL CONVERTER
7
+DAC
The capacitance-to-digital converter on the AD7142 has a Σ-ꢁ
architecture with 16-bit resolution. There are 14 possible inputs to
the CDC that are connected to the input of the converter through a
switch matrix. The sampling frequency of the CDC is 250 kHz.
POS_AFE_OFFSET
(20pF RANGE)
POS_AFE_OFFSET_SWAP BIT
OVERSAMPLING THE CDC OUTPUT
CIN
+
_
16
16-BIT
CDC
The decimation rate, or oversampling ratio, is determined by
Bits[9:8] of the control register, as listed in Table 9.
NEG_AFE_OFFSET_SWAP BIT
Table 9. CDC Decimation Rate
CDC Output Rate
Decimation Bit Value Decimation Rate Per Stage
SRC
7
–DAC
(20pF RANGE)
ꢀꢀ
ꢀ1
1ꢀ1
111
256
128
–
3.ꢀ72 ms
1.536 ms
–
–
NEG_AFE_OFFSET
CIN_CONNECTION_SETUP
REGISTER
–
Figure 23. Analog Front-End Offset Control
1 Do not use this setting.
CONVERSION SEQUENCER
The decimation process on the AD7142 is an averaging process
where a number of samples are taken and the averaged result is
output. Due to the architecture of the digital filter employed, the
amount of samples taken (per stage) is equal to 3 times the
decimation rate. So 3 × 256 or 3 × 128 samples are averaged to
obtain each stage result.
The AD7142 has an on-chip sequencer to implement
conversion control for the input channels. Up to 12 conversion
stages can be performed in one sequence. Each of the 12
conversion stages can measure the input from a different sensor. By
using the Bank 2 registers, each stage can be uniquely configured to
support multiple capacitance sensor interface requirements. For
example, a slider sensor can be assigned to STAGE1 through
STAGE8, with a button sensor assigned to STAGE0.
The decimation process reduces the amount of noise present in
the final CDC result. However, the higher the decimation rate,
the lower the output rate per stage, thus, a trade-off is possible
between a noise-free signal and speed of sampling.
The AD7142 on-chip sequence controller provides conversion
control beginning with STAGE0. Figure 24 shows a block diagram of
the CDC conversion stages and CIN inputs. A conversion sequence is
defined as a sequence of CDC conversions starting at STAGE0 and
ending at the stage determined by the value programmed in the
SEQUENCE_STAGE_NUM register. Depending on the number and
type of capacitance sensors that are used, not all conversion stages are
required. Use the SEQUENCE_STAGE_NUM register to set the
number of conversions in one sequence, depending on the sensor
interface requirements. For example, this register would be set to 5 if
the CIN inputs were mapped to only six stages. In addition, set the
STAGE_CAL_EN registers according to the number of stages that
are used.
CAPACITANCE SENSOR OFFSET CONTROL
There are two programmable DACs on board the AD7142 to
null any capacitance sensor offsets. These offsets are associated
with printed circuit board capacitance or capacitance due to any
other source, such as connectors. In Figure 22, CIN is the
capacitance of the input sensors, and CBULK is the capacitance
between layers of the sensor PCB. CBULK can be offset using the
on-board DACs.
C
IN
PLASTIC OVERLAY
SENSOR BOARD
C
BULK
CAPACITIVE SENSOR
Figure 22. Capacitances Around the Sensor PCB
A simplified block diagram in Figure 23 shows how to apply the
STAGE_OFFSET registers to null the offsets. The 7-bit
POS_AFE_OFFSET and NEG_AFE_OFFSET registers program
the offset DAC to provide 0.16 pF resolution offset adjustment
over a range of 20 pF. Apply the positive and negative offsets
to either the positive or the negative CDC input using the
NEG_AFE_OFFSET register and POS_AFE_OFFSET register.
This process is only required once during the initial capacitance
sensor characterization.
Rev. A | Page 15 of 72
AD7142
STAGE11
STAGE10
STAGE9
STAGE8
STAGE7
The 8-way switch is made from two pairs of differential buttons.
It, therefore, requires two conversion stages, one for each of the
differential button pairs. It also requires a stage to measure
whether the sensor is active. The buttons are orientated so that
one pair makes up the top and bottom portions of the 8-way
switch; the other pair makes up the left and right portions of the
8-way switch.
STAGE6
STAGE5
STAGE4
STAGE3
STAGE2
STAGE1
STAGE0
CIN0
CDC CONVERSION SEQUENCE TIME
CIN1
CIN2
The time required for one complete measurement for all 12 stages
by the CDC is defined as the CDC conversion sequence time. The
SEQUENCE_STAGE_NUM register and DECIMATION register
determine the conversion time as listed in Table 10.
CIN3
CIN4
CIN5
Σ-Δ
16-BIT
ADC
E
CIN6
CIN7
C
N
UE
CIN8
CIN9
Q
Table 10. CDC Conversion Times for Full Power Mode
E
S
N
Conversion Time (ms)
CIN10
O
I
RS
CIN11
CIN12
CIN13
E
DECIMATION
= 128
DECIMATION
= 256
NV
SEQUENCE_STAGE_NUM
O
C
ꢀ
1
2
3
1.536
3.ꢀ72
4.6ꢀ8
6.144
7.68
3.ꢀ72
6.144
9.216
12.288
15.36
Figure 24. CDC Conversion Stages
The number of required conversion stages depends completely
on the number of sensors attached to the AD7142. Figure 25
shows how many conversion stages are required for each sensor,
and how many inputs each sensor requires to the AD7142.
4
5
6
7
8
9
1ꢀ
11
9.216
1ꢀ.752
12.288
13.824
15.36
16.896
18.432
18.432
21.5ꢀ4
24.576
27.648
3ꢀ.72
AD7142 SEQUENCER
STAGEX
+
CDC
–
8-ELEMENT SLIDER
STAGEX
+
33.792
36.864
CDC
–
STAGEX
+
AD7142 SEQUENCER
CDC
BUTTONS
–
For example, operating with a decimation rate of 128, if the
SEQUENCE_STAGE_NUM register is set to 5 for the
conversion of six stages in a sequence, the conversion sequence
time is 9.216 ms.
STAGEX
+
–
S1
STAGEX
CDC
+
CDC
–
STAGEX
S2
S3
+
STAGEX
CDC
–
+
CDC
–
Full Power Mode CDC Conversion Sequence Time
STAGEX
SRC
+
The full power mode CDC conversion sequence time for all 12
stages is set by configuring the SEQUENCE_STAGE_NUM
register, and DECIMATION register as outlined in Table 10.
CDC
–
STAGEX
+
CDC
–
Figure 26 shows a simplified timing diagram of the full power
CDC conversion time. The full power mode CDC conversion
time, tCONV_FP, is set using Table 10.
SRC
STAGEX
+
CDC
–
Figure 25. Sequencer Setup for Sensors
tCONV_FP
A button sensor generally requires one sequencer stage;
however, it is possible to configure two button sensors to
operate differentially. Only one button from the pair can be
activated at a time; pressing both buttons together results in
neither button being activated. This configuration requires one
conversion stage, and is shown in Figure 25, B2 and B3.
CONVERSION
SEQUENCE N SEQUENCE N+1 SEQUENCE N+2
CONVERSION
CONVERSION
CDC
CONVERSION
NOTES
1. tCONV_FP = VALUE SET FROM TABLE 10.
Figure 26. Full Power Mode CDC Conversion Sequence Time
A scroll bar or slider sensor requires eight stages. The result from
each stage is used by the host software to determine the user’s
position on the scroll bar. The algorithm that performs this process
is available from Analog Devices free of charge, on signing a
software license. Scroll wheels also require eight stages.
Rev. A | Page 16 of 72
AD7142
tCONV_LP
Low Power Mode CDC Conversion Sequence Time with
Delay
t
CONV_FP
CDC
CONVERSION
SEQUENCE N
CONVERSION
SEQUENCE N+1
The frequency of each CDC conversion operating in the low
power automatic wake-up mode is controlled by using the
LP_CONV_DELAY register located at Address 0x000[3:2], in
addition to the registers listed in Table 10. This feature provides
some flexibility for optimizing the conversion time to meet
system requirements vs. AD7142 power consumption.
LP_CONV_DELAY
CONVERSION
Figure 27. Low Power Mode CDC Conversion Sequence Time
CDC CONVERSION RESULTS
Certain high resolution sensors require the host to read back
the CDC conversion results for processing. The registers
required for host processing are located in the Bank 3 registers.
The host processes the data readback from these registers using
a software algorithm, to determine position information.
For example, maximum power savings is achieved when the
LP_CONV_DELAY register is set to 3. With a setting of 3, the
AD7142 automatically wakes up, performing a conversion
every 800 ms.
In addition to the results registers in the Bank 3 registers, the
AD7142 provides the 16-bit CDC output data directly, starting
at Address 0x00B of Bank 1. Reading back the CDC 16-bit
conversion data register allows for customer-specific application
data processing.
Table 11. LP_CONV_DELAY Settings
LP_CONV_DELAY Bits
Delay Between Conversions
ꢀꢀ
ꢀ1
1ꢀ
11
2ꢀꢀ ms
4ꢀꢀ ms
6ꢀꢀ ms
8ꢀꢀ ms
Figure 27 shows a simplified timing example of the low power
CDC conversion time. As shown, the low power CDC conversion
time is set by tCONV_FP and the LP_CONV_DELAY register.
Rev. A | Page 17 of 72
AD7142
NONCONTACT PROXIMITY DETECTION
The AD7142 internal signal processing continuously monitors
all capacitance sensors for noncontact proximity detection. This
feature provides the ability to detect when a user is approaching
a sensor, at which time all internal calibration is immediately
disabled and the AD7142 is automatically configured to detect a
valid contact.
determined by PROXIMITY_RECAL_LVL, for a set period of
time known as the recalibration timeout. In full power mode, the
recalibration timeout is controlled by FP_PROXIMITY_RECAL,
and in low power mode, by LP_PROXIMITY_RECAL.
Recalibration timeout in full power mode =
FP_PROXIMITY_RECAL × Time taken for one conversion
sequence in full power mode
The proximity control register bits are described in Table 12.
The FP_PROXIMITY_CNT register bits and
Recalibration timeout in low power mode =
LP_PROXIMITY_RECAL × Time taken for one conversion
sequence in low power mode
LP_PROXIMITY_CNT register bits control the length of the
calibration disable period after the user leaves the sensor and
proximity is no longer active, in full and low power modes. The
calibration is disabled during this time and enabled again at the
end of this period provided that the user is no longer
approaching, or in contact with, the sensor. Figure 28 and
Figure 29 show examples of how these registers are used to set
the full and low power mode calibration disable periods.
Figure 30 and Figure 31 show examples of how the
FP_PROXIMITY_RECAL and LP_PROXIMITY_RECAL
register bits control the timeout period before a recalibration,
operating in the full and low power modes. These figures show a
user approaching a sensor followed by the user leaving the sensor
and the proximity detection remains active after the user leaves the
sensor. The measured CDC value exceeds the stored ambient value
by the amount set in the PROXIMITY_RECAL_LVL bits, for the
entire timeout period. The sensor is automatically recalibrated
at the end of the timeout period. The forced recalibration takes
two interrupt cycles, therefore, it should not be set again during
this interval.
Calibration disable period in full power mode =
FP_PROXIMITY_CNT × 16 × Time taken for one conversion
sequence in full power mode
Calibration disable period in low power mode =
LP_PROXIMITY_CNT × 4 × Time taken for one conversion
sequence in low power mode
RECALIBRATION
PROXIMITY SENSITIVITY
In certain situations, the proximity flag can be set for a long
period, for example when a user hovers over a sensor for a long
time. The environmental calibration on the AD7142 is
suspended when proximity is detected, but changes may occur
to the ambient capacitance level during the proximity event.
This means the ambient value stored on the AD7142 no longer
represents the actual ambient value. In this case, even when the
user has left the sensor, the proximity flag may still be set. This
situation could occur if the user interaction creates some
moisture on the sensor causing the new sensor ambient value to
be different from the expected value. In this situation, the
AD7142 automatically forces a recalibration internally. This
ensures that the ambient values are recalibrated regardless of
how long the user hovers over a sensor. A recalibration ensures
maximum AD7142 sensor performance.
The fast filter in Figure 32 is used to detect when someone is
close to the sensor (proximity). Two conditions set the internal
proximity detection signal using Comparator 1 and
Comparator 2. Comparator 1 detects when a user is
approaching a sensor. The PROXIMITY_DETECTION_RATE
register controls the sensitivity of Comparator 1. For example, if
PROXIMITY_DETECTION_RATE is set to 4, the Proximity 1
signal is set when the absolute difference between WORD1 and
WORD3 exceeds four LSB codes. Comparator 2 detects when a
user hovers over a sensor or approaches a sensor very slowly.
The PROXIMITY_RECAL_LVL register (Address 0x003)
controls the sensitivity of Comparator 2. For example, if
PROXIMITY_RECAL_LVL is set to 75, the Proximity 2 signal
is set when the absolute difference between the fast filter
average value and the ambient value exceeds 75 LSB codes.
The AD7142 recalibrates automatically when the measured
CDC value exceeds the stored ambient value by an amount
Table 12. Proximity Control Registers (See Figure 32)
Register
Length Register Address
Description
FP_PROXIMITY_CNT
LP_PROXIMITY_CNT
FP_PROXIMITY_RECAL
LP_PROXIMITY_RECAL
PROXIMITY_RECAL_LVL
4 bits
4 bits
8 bits
6 bits
8 bits
ꢀxꢀꢀ2 [7:4]
ꢀxꢀꢀ2 [11:8]
ꢀxꢀꢀ4 [9:ꢀ]
ꢀxꢀꢀ4 [15:1ꢀ]
ꢀxꢀꢀ3 [13:8]
ꢀxꢀꢀ3 [7:ꢀ]
Calibration disable time in full power mode
Calibration disable time in low power mode
Full power mode proximity recalibration time
Low power mode proximity recalibration time
Proximity recalibration level
PROXIMITY_DETECTION_RATE 6 bits
Proximity detection rate
Rev. A | Page 18 of 72
AD7142
USER APPROACHES
SENSOR HERE
USER LEAVES SENSOR
AREA HERE
tCONV_FP
1
2
3
4 5 6 7 8 9 1011 1213 1415 16
CDC CONVERSION SEQUENCE
(INTERNAL)
tCALDIS
PROXIMITY DETECTION
(INTERNAL)
CALIBRATION
(INTERNAL)
CALIBRATION DISABLED
CALIBRATION ENABLED
Figure 28. Full Power Mode Proximity Detection Example with FP_PROXIMITY_CNT = 1
USER
APPROACHES
SENSOR HERE
USER LEAVES
SENSOR
AREA HERE
tCONV_LP
1
2
3
4 5
6
7
8 9 1011 1213 1415 16 1718 19 20 21222324
tCALDIS
CDC CONVERSION SEQUENCE
(INTERNAL)
PROXIMITY DETECTION
(INTERNAL)
CALIBRATION
(INTERNAL)
CALIBRATION DISABLED
CALIBRATION ENABLED
NOTES
1. SEQUENCE CONVERSION TIME tCONV_LP
=
tCONV_FP + LP_CONV_DELAY
2. PROXIMITY IS SET WHEN USER APPROACHES THE SENSOR AT WHICH TIME THE INTERNAL CALIBRATION IS DISABLED.
3. tCALDIS = (tCONV_LP × LP_PROXIMITY_CNT × 4)
Figure 29. Low Power Mode Proximity Detection with LP_PROXIMITY_CNT = 4
USER APPROACHES
SENSOR HERE
tRECAL
MEASURED CDC VALUE > STORED AMBIENT
BY PROXIMITY_RECAL _LVL
USER LEAVES SENSOR
AREA HERE
tCONV_FP
70
16
30
CDC CONVERSION SEQUENCE
(INTERNAL)
tCALDIS
PROXIMITY DETECTION
(INTERNAL)
CALIBRATION
(INTERNAL)
CALIBRATION DISABLED
RECALIBRATION TIME-OUT
tRECAL_TIMEOUT
CALIBRATION ENABLED
RECALIBRATION COUNTER
(INTERNAL)
NOTES
1. SEQUENCE CONVERSION TIME tCONV_FP DETERMINED FROM TABLE 10
2. tCALDIS tCONV_FP × FP_PROXIMITY_CNT ×16
3. tRECAL_TIMEOUT tCONV_FP × FP_PROXIMITY_RECAL
4. tRECAL = 2 × tCONV_FP
=
=
Figure 30. Full Power Mode Proximity Detection with Forced Recalibration Example with FP_PROXIMITY_CNT = 1 and FP_PROXIMITY_RECAL = 40
Rev. A | Page 19 of 72
AD7142
USER APPROACHES
SENSOR HERE
tRECAL
USER LEAVES SENSOR
AREA HERE
MEASURED CDC VALUE > STORED AMBIENT
BY PROXIMITY_RECAL _LVL
tCONV_LP
16
30
70
CDC CONVERSION SEQUENCE
(INTERNAL)
PROXIMITY DETECTION
(INTERNAL)
tCALDIS
CALIBRATION
(INTERNAL)
RECALIBRATION TIME-OUT
tRECAL_TIMEOUT
CALIBRATION ENABLED
CALIBRATION DISABLED
RECALIBRATION
(INTERNAL)
NOTES
1. SEQUENCE CONVERSION TIME tCONV_LP
2. tCALDIS tCONV_LP × LP_PROXIMITY_CNT × 4
3. tRECAL_TIMEOUT tCONV_FP × LP_PROXIMITY_RECAL
4. tRECAL = 2 × tCONV_LP
=
tCONV_FP + LP_CONV_DELAY
=
=
Figure 31. Low Power Mode Proximity Detection with Forced Recalibration Example with LP_PROXIMITY_CNT = 4 and LP_PROXIMITY_RECAL = 40
FF_SKIP_CNT
The proximity detection fast FIFO is used by the on-chip logic to determine if proximity is detected. The fast FIFO expects to receive
samples from the converter at a set rate. FF_SKIP_CNT is used to normalize the frequency of the samples going into the FIFO, regardless
of how many conversion stages are in a sequence. In Register 0x02, Bits[3:0] are the fast filter skip control, FF_SKIP_CNT. This value
determines which CDC samples are not used (skipped) in the proximity detection fast FIFO.
Determining the FF_SKIP_CNT value is required only once during the initial setup of the capacitance sensor interface. Table 13 shows
how FF_SKIP_CNT controls the update rate to the fast FIFO. Recommended value for this setting when using all 12 conversion stages on
the AD7142 is FF_SKIP_CNT = 0000 = no samples skipped.
Table 13. FF_SKIP_CNT Settings
FAST FIFO Update Rate
FF_SKIP_CNT
DECIMATION = 128
DECIMATION = 256
0
1.536 × (SEQUENCE_STAGE_NUM + 1) ms
3.072 × (SEQUENCE_STAGE_NUM + 1) ms
4.608 × (SEQUENCE_STAGE_NUM + 1) ms
6.144 × (SEQUENCE_STAGE_NUM + 1) ms
7.68 × (SEQUENCE_STAGE_NUM + 1) ms
9.216 × (SEQUENCE_STAGE_NUM + 1) ms
10.752 × (SEQUENCE_STAGE_NUM + 1) ms
12.288 × (SEQUENCE_STAGE_NUM + 1) ms
13.824 × (SEQUENCE_STAGE_NUM + 1) ms
15.36 × (SEQUENCE_STAGE_NUM + 1) ms
16.896 × (SEQUENCE_STAGE_NUM + 1) ms
18.432 × (SEQUENCE_STAGE_NUM + 1) ms
19.968 × (SEQUENCE_STAGE_NUM + 1) ms
21.504 × (SEQUENCE_STAGE_NUM + 1) ms
23.04 × (SEQUENCE_STAGE_NUM + 1) ms
24.576 × (SEQUENCE_STAGE_NUM + 1) ms
3.072 × (SEQUENCE_STAGE_NUM + 1) ms
6.144 × (SEQUENCE_STAGE_NUM + 1) ms
9.216 × (SEQUENCE_STAGE_NUM + 1) ms
12.288 × (SEQUENCE_STAGE_NUM + 1) ms
15.36 × (SEQUENCE_STAGE_NUM + 1) ms
18.432 × (SEQUENCE_STAGE_NUM + 1) ms
21.504 × (SEQUENCE_STAGE_NUM + 1) ms
24.576 × (SEQUENCE_STAGE_NUM + 1) ms
27.648 × (SEQUENCE_STAGE_NUM + 1) ms
30.72 × (SEQUENCE_STAGE_NUM + 1) ms
33.792 × (SEQUENCE_STAGE_NUM + 1) ms
36.864 × (SEQUENCE_STAGE_NUM + 1) ms
39.936 × (SEQUENCE_STAGE_NUM + 1) ms
43.008 × (SEQUENCE_STAGE_NUM + 1) ms
46.08 × (SEQUENCE_STAGE_NUM + 1) ms
49.152 × (SEQUENCE_STAGE_NUM + 1) ms
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Rev. A | Page 20 of 72
AD7142
16
CDC
FP_PROXIMITY_CNT
REGISTER 0x002
LP_PROXIMITY_CNT
REGISTER 0X002
STAGE_FF_WORD0
STAGE_FF_WORD1
STAGE_FF_WORD2
STAGE_FF_WORD3
STAGE_FF_WORD4
STAGE_FF_WORD5
STAGE_FF_WORD6
STAGE_FF_WORD7
PROXIMITY
COMPARATOR 1
WORD0 – WORD3
PROXIMITY 1
PROXIMITY TIMING
CONTROL LOGIC
PROXIMITY_DETECTION_RATE
REGISTER 0x003
FP_PROXIMITY_RECAL
REGISTER 0x004
LP_PROXIMITY_RECAL
REGISTER 0X004
BANK 3 REGISTERS
7
WORD(N)
STAGE_FF_AVG
BANK 3 REGISTERS
Σ
N = 0
8
STAGE_FF_WORDX
COMPARATOR 2
AVERAGE – AMBIENT
PROXIMITY
SW1
SLOW_FILTER_EN
PROXIMITY_RECAL_LVL
REGISTER 0x003
AMBIENT VALUE
STAGE_SF_WORD0
STAGE_SF_WORD1
STAGE_SF_WORD2
STAGE_SF_WORD3
STAGE_SF_WORD4
STAGE_SF_WORD5
STAGE_SF_WORD6
STAGE_SF_WORD7
COMPARATOR 2
WORD0 – WORD3
STAGE_SF_WORDX
SENSOR
CONTACT
STAGE_SF_AMBIENT
BANK 3 REGISTERS
SLOW_FILTER_UPDATE_LVL
REGISTER 0x003
TIME
BANK 3 REGISTERS
NOTES
|STAGE_SF_
|
WORD 0–STAGE_SF_WORD 1 EXCEEDS THE VALUE PROGRAMMED IN THE SLOW_FILTER_UPDATE_LVL REGISTER
1. SLOW FILTER EN IS SET AND SW1 IS CLOSED WHEN
PROVIDING PROXIMITY IS NOT SET.
|STAGE_FF_
|
2. PROXIMITY 1 IS SET WHEN
WORD 0– STAGE_FF_WORD 3 EXCEEDS THE VALUE PROGRAMMED IN THE PROXIMITY_DETECTION_RATE REGISTER.
|
|
3. PROXIMITY 2 IS SET WHEN AVERAGE–AMBIENT EXCEEDS THE VALUE PROGRAMMED IN THE PROXIMITY_RECAL_LVL REGISTER.
4. DESCRIPTION OF COMPARATOR FUNCTIONS:
COMPARATOR 1: USED TO DETECT WHEN A USER IS APPROACHING OR LEAVING A SENSOR.
COMPARATOR 2: USED TO DETECT WHEN A USER IS HOVERING OVER A SENSOR, OR APPROACHING A SENSOR VERY SLOWLY.
ALSO USED TO DETECT IF THE SENSOR AMBIENT LEVEL HAS CHANGED AS A RESULT OF THE USER INTERACTION.
FOR EXAMPLE, HUMIDITY OR DIRT LEFT BEHIND ON SENSOR.
COMPARATOR 3: USED TO ENABLE THE SLOW FILTER UPDATE RATE. THE SLOW FILTER IS UPDATED WHEN SLOW FILTER EN IS SET AND PROXIMITY IS NOT SET.
Figure 32. AD7142 Proximity Detection and Environmental Calibration
Rev. A | Page 21 of 72
AD7142
ENVIRONMENTAL CALIBRATION
The AD7142 provides on-chip capacitance sensor calibration to
automatically adjust for environmental conditions that have an
effect on the capacitance sensor ambient levels. Capacitance
sensor output levels are sensitive to temperature, humidity, and
in some cases, dirt. The AD7142 achieves optimal and reliable
sensor performance by continuously monitoring the CDC
ambient levels and correcting for any changes by adjusting the
STAGE_HIGH_THRESHOLD and STAGE_LOW_ THRESHOLD
register values, as described in Equation 1 and Equation 2. The
CDC ambient level is defined as the capacitance sensor output
level during periods when the user is not approaching or in
contact with the sensor.
CAPACITANCE SENSOR BEHAVIOR WITHOUT
CALIBRATION
Figure 34 shows the typical behavior of a capacitance sensor
with no applied calibration. This figure shows ambient levels
drifting over time as environmental conditions change. The
ambient level drift has resulted in the detection of a missed user
contact on Sensor 2. This is a result of the initial low offset level
remaining constant when the ambient levels drifted upward
beyond the detection range.
The Capacitance Sensor Behavior with Calibration section
describes how the AD7142 adaptive calibration algorithm
prevents errors such as this from occurring.
The compensation logic runs automatically on every conversion
after configuration when the AD7142 is not being touched. This
allows the AD7142 to account for rapidly changing environ-
mental conditions.
SENSOR 1 INT
ASSERTED
STAGE_HIGH_THRESHOLD
CDC AMBIENT
VALUE DRIFTING
The ambient compensation control registers give the host access
to general setup and controls for the compensation algorithm.
The RAM stores the compensation data for each conversion
stage, as well as setup information specific to each stage.
STAGE_LOW_THRESHOLD
Figure 33 shows an example of an ideal capacitance sensor
behavior where the CDC ambient level remains constant
regardless of the environmental conditions. The CDC output
shown is for a pair of differential button sensors, where one
sensor caused an increase, and the other a decrease in measured
capacitance when activated. The positive and negative sensor
threshold levels are calculated as a percentage of the
STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW values
based on the threshold sensitivity settings and the ambient
value. These values are sufficient to detect a sensor contact,
SENSOR 2 INT
NOT ASSERTED
t
CHANGING ENVIRONMENTAL CONDITIONS
Figure 34. Typical Sensor Behavior Without Calibration Applied
CAPACITANCE SENSOR BEHAVIOR WITH
CALIBRATION
The AD7142 on-chip adaptive calibration algorithm prevents
sensor detection errors such as the one shown in Figure 34. This
is achieved by monitoring the CDC ambient levels and
readjusting the initial STAGE_OFFSET_HIGH and
INT
resulting with the AD7142 asserting the
threshold levels are exceeded.
output when the
STAGE_OFFSET_LOW values according to the amount of
ambient drift measured on each sensor. The internal
STAGE_HIGH_THRESHOLD and STAGE_LOW_THRESHOLD
values described in Equation 1 and Equation 2 are automatically
updated based on the new STAGE_OFFSET_HIGH and
STAGE_OFFSET_LOW values. This closed-loop routine
ensures the reliability and repeatable operation of every sensor
connected to the AD7142 under dynamic environmental
conditions. Figure 35 shows a simplified example of how the
AD7142 applies the adaptive calibration process resulting in no
interrupt errors under changing CDC ambient levels due to
environmental conditions.
SENSOR 1 INT
ASSERTED
STAGE_HIGH_THRESHOLD
CDC AMBIENT VALUE
STAGE_LOW_THRESHOLD
SENSOR 2 INT
ASSERTED
t
CHANGING ENVIRONMENTAL CONDITIONS
Figure 33. Ideal Sensor Behavior with a Constant Ambient Level
Rev. A | Page 22 of 72
AD7142
SENSOR 1 INT
ASSERTED
capacitance value tracks the measured capacitance value read by
the converter.
3
STAGE_HIGH_THRESHOLD
(POST CALIBRATED
REGISTER VALUE)
2
1
Slow FIFO update rate in full power mode = AVG_FP_SKIP ×
[(3 × Decimation Rate) × (SEQUENCE_STAGE_NUM +1) ×
(FF_SKIP_CNT +1) × 4 × 10-7]
CDC AMBIENT
VALUE DRIFTING
Slow FIFO update rate in low power mode = (AVG_LP_SKIP +1) ×
[(3 × Decimation Rate) × (SEQUENCE_STAGE_NUM +1) ×
(FF_SKIP_CNT +1) × 4 × 10-7] / [(FF_SKIP_CNT +1 ) +
LP_CONV_DELAY]
6
5
STAGE_LOW_THRESHOLD
(POST CALIBRATED
REGISTER VALUE)
4
SENSOR 2 INT
ASSERTED
The slow FIFO is used by the on-chip logic to track the ambient
capacitance value. The slow FIFO expects to receive samples
from the converter at a rate of 33 ms to 40 ms. AVG_FP_SKIP
and AVG_LP_SKIP are used to normalize the frequency of the
samples going into the FIFO, regardless of how many
conversion stages are in a sequence.
t
CHANGING ENVIRONMENTAL CONDITIONS
NOTES
1. INITIAL STAGE_OFFSET_HIGH REGISTER VALUE
2. POST CALIBRATED REGISTER STAGE_HIGH_THRESHOLD
3. POST CALIBRATED REGISTER STAGE_HIGH_THRESHOLD
4. INITIAL STAGE_LOW_THRESHOLD
5. POST CALIBRATED REGISTER STAGE_LOW_THRESHOLD
6. POST CALIBRATED REGISTER STAGE_LOW_THRESHOLD
Determining the AVG_FP_SKIP and AVG_LP_SKIP value is
only required once during the initial setup of the capacitance
sensor interface. Recommended values for these settings when
using all 12 conversion stages on the AD7142 are:
Figure 35. Typical Sensor Behavior with Calibration Applied on the Data Path
SLOW FIFO
As shown in Figure 32, there are a number of FIFOs
implemented on the AD7142. These FIFOs are located in
Bank 3 of the on-chip memory. The slow FIFOs are used by the
on-chip logic to monitor the ambient capacitance level from
each sensor.
AVG_FP_SKIP = 00 = skip 3 samples
AVG_LP_SKIP = 00 = skip 0 samples
SLOW_FILTER_UPDATE_LVL
The SLOW_FILTER_UPDATE_LVL controls whether the most
recent CDC measurement goes into the Slow FIFO (slow filter)
or not. The slow filter is updated when the difference between
the current CDC value and last value pushed into the slow FIFO
> SLOW_FILTER_UPDATE_LVL. This variable is in Ambient
Control Register 1, at Address 0x003.
AVG_FP_SKIP and AVG_LP_SKIP
In Register 0x001, Bits[13:12] are the slow FIFO skip control for
full power mode, AVG_FP_SKIP. Bits[15:14] in the same
register are the slow FIFO skip control for low power mode,
AVG_LP_SKIP. These values determine which CDC samples
are not used (skipped) in the slow FIFO. Changing theses values
slows down or speeds up the rate at which the ambient
⎛
⎜
STAGE _ OFFSET _ HIGH
⎞
⎟
⎛
⎜
⎝
⎞
⎟
⎠
STAGE _ OFFSET _ HIGH −
STAGE _ OFFSET _ HIGH
4
⎛
⎝
⎞
⎟
⎠
⎜
⎜
⎜
⎝
⎟
⎟
⎟
⎠
STAGE _ HIGH _ THRESHOLD = STAGE _ SF _ AMBIENT +
+
× POS _ THRESHOLD _ SENSITIVITY
⎜
4
16
Equation 1. On-Chip Logic Stage High Threshold Calculation
⎛
STAGE _ OFFSET _ LOW
⎞
⎟
⎛
⎜
⎝
⎞
⎟
⎠
STAGE _ OFFSET _ LOW −
⎜
STAGE _ OFFSET _ LOW
4
⎛
⎜
⎝
⎞
⎟
⎠
⎜
⎜
⎜
⎝
⎟
⎟
⎟
⎠
STAGE _ LOW _ THRESHOLD = STAGE _ SF _ AMBIENT +
+
× NEG _ THRESHOLD _ SENSITIVITY
4
16
Equation 2. On-Chip Logic Stage Low Threshold Calculation
Rev. A | Page 23 of 72
AD7142
ADAPTIVE THRESHOLD AND SENSITIVITY
The AD7142 provides an on-chip self-learning adaptive
threshold and sensitivity algorithm. This algorithm continu-
ously monitors the output levels of each sensor and automatically
rescales the threshold levels proportionally to the sensor area
covered by the user. As a result, the AD7142 maintains optimal
threshold and sensitivity levels for all types of users regardless
of their finger sizes.
a large average maximum or minimum value, and a small finger
gives smaller values. When the average maximum or minimum
value changes, the threshold levels are rescaled to ensure that
the threshold levels are appropriate for the current user. Figure 37
shows how the minimum and maximum sensor responses are
tracked by the on-chip logic.
Reference A in Figure 36 shows an undersensitive threshold
level for a small finger user, demonstrating the disadvantages of
a fixed threshold level.
The threshold level is always referenced from the ambient level
and is defined as the CDC converter output level that must be
exceeded for a valid sensor contact. The sensitivity level is
defined as how sensitive the sensor is before a valid contact
is registered.
By enabling the adaptive threshold and sensitivity algorithm,
the positive and negative threshold levels are determined by the
POS_THRESHOLD_SENSITIVITY and NEG_THRESHOLD_
SENSITIVITY register values and the most recent average
maximum sensor output value. These registers can be used to
select 16 different positive and negative sensitivity levels
ranging between 25% and 95.32% of the most recent average
maximum output level referenced from the ambient value. The
smaller the sensitivity percentage setting, the easier it is to
trigger a sensor activation. Reference B shows that the positive
adaptive threshold level is set at almost mid-sensitivity with a
62.51% threshold level by setting POS_THRESHOLD_
SENSITIVITY = 1000. Figure 36 also provides a similar
example for the negative threshold level with NEG_
Figure 36 provides an example of how the adaptive threshold and
sensitivity algorithm works. The positive and negative sensor
threshold levels are calculated as a percentage of the STAGE_
OFFSET_HIGH and STAGE_OFFSET_LOW values based on
the threshold sensitivity settings and the ambient value. On
configuration, initial estimates are supplied for both
STAGE_OFFSET_HIGH and STAGE_OFFSET_LOW after
which the calibration engine automatically adjusts the
STAGE_HIGH_THRESHOLD and STAGE_LOW_
THRESHOLD values for sensor response.
The AD7142 tracks the average maximum and minimum values
measured from each sensor. These values give an indication of
how the user is interacting with the sensor. A large finger gives
.
THRESHOLD_SENSITIVITY = 0001.
AVERAGE MAX VALUE
95.32%
STAGE_OFFSET_HIGH
IS UPDATED
AVERAGE MAX VALUE
62.51% = POS ADAPTIVE
THRESHOLD LEVEL
A
STAGE_OFFSET_HIGH
95.32%
25%
STAGE_OFFSET_HIGH
IS UPDATED HERE
62.51% = POS
ADAPTIVE
THRESHOLD LEVEL
25%
B
AMBIENT LEVEL
25%
NEG ADAPTIVE THRESHOLD LEVEL = 39.08%
STAGE_OFFSET_LOW
IS UPDATED HERE
25%
STAGE_OFFSET_LOW
NEG ADAPTIVE THRESHOLD LEVEL = 39.08%
95.32%
STAGE_OFFSET_LOW
IS UPDATED HERE
95.32%
SENSOR CONTACTED
BY LARGE FINGER
SENSOR CONTACTED
BY SMALL FINGER
Figure 36. Threshold Sensitivity Example with POS_THRESHOLD_SENSITIVITY = 1000 and NEG_THRESHOLD_SENSITIVITY = 0011
Rev. A | Page 24 of 72
AD7142
STAGE_MAX_WORD0
STAGE_MAX_WORD1
STAGE_MAX_WORD2
STAGE_MAX_WORD3
BANK 3
REGISTERS
Σ-Δ
16-BIT
CDC
16
MAX LEVEL
DETECTION
LOGIC
STAGE_MAX_AVG
BANK 3 REGISTERS
STAGE_MAX_TEMP
BANK 3 REGISTERS
STAGE_HIGH_THRESHOLD
BANK 3 REGISTERS
STAGE_MIN_WORD0
STAGE_MIN_WORD1
STAGE_MIN_WORD2
STAGE_MIN_WORD3
BANK 3
REGISTERS
MIN LEVEL
DETECTION
LOGIC
STAGE_MIN_AVG
BANK 3 REGISTER3
STAGE_MIN_TEMP
BANK 3 REGISTERS
STAGE_LOW_THRESHOLD
BANK 3 REGISTERS
Figure 37. Tracking the Minimum and Maximum Average Sensor Values
Table 13. Additional Information about Environmental Calibration and Adaptive Threshold Registers
Register
Register
Location Description
NEG_THRESHOLD_SENSITIVITY
NEG_PEAK_DETECT
Bank 2
Bank 2
Used in Equation 2. This value is programmed once at start up.
Used by internal adaptive threshold logic only.
The NEG_PEAK_DETECT is set to a percentage of the difference between the ambient
CDC value, and the min average CDC value. If the output of the CDC gets within the
NEG_PEAK_DETECT percentage of the min average, only then is the min average value
updated.
POS_THRESHOLD_SENSITIVITY
POS_PEAK_DETECT
Bank 2
Bank 2
Used in Equation 1. This value is programmed once at start up.
Used by internal adaptive threshold logic only.
The POS_PEAK_DETECT is set to a percentage of the difference between the ambient
CDC value, and the max average CDC value. If the output of the CDC gets within the
POS_PEAK_DETECT percentage of the min average, only then is the max average value
updated.
STAGE_OFFSET_LOW
Bank 2
Bank 2
Bank 2
Used in Equation 2. An initial value (based on sensor characterization) is programmed
into this register at start up. The AD7142 on chip calibration algorithm automatically
updates this register based on the amount of sensor drift due to changing ambient
conditions. Set to 8ꢀ% of the STAGE_OFFSET_LOW_CLAMP value.
Used in Equation 1. An initial value (based on sensor characterization) is programmed
into this register at start up. The AD7142 on chip calibration algorithm automatically
updates this register based on the amount of sensor drift due to changing ambient
conditions. Set to 8ꢀ% of the STAGE_OFFSET_HIGH_CLAMP value.
Used by internal environmental calibration and adaptive threshold algorithms only.
An initial value (based on sensor characterization) is programmed into this register at
start up. The value in this register prevents a user from causing a sensor’s output value
to exceed the expected nominal value.
STAGE_OFFSET_HIGH
STAGE_OFFSET_HIGH_CLAMP
Set to the maximum expected sensor response, maximum change in CDC output code .
STAGE_OFFSET_LOW_CLAMP
STAGE_SF_AMBIENT
Bank 2
Bank 3
Used by internal environmental calibration and adaptive threshold algorithms only.
An initial value (based on sensor characterization) is programmed into this register at
start up. The value in this register prevents a user from causing a sensor’s output value
to exceed the expected nominal value.
Set to the minimum expected sensor response, minimum change in CDC output code .
Used in Equation 1 and Equation 2. This is the ambient sensor output, when the sensor
is not touched, as calculated using the slow FIFO.
STAGE_HIGH_THRESHOLD
STAGE_LOW_THRESHOLD
Bank 3
Bank 3
Equation 1 value.
Equation 2 value.
Rev. A | Page 25 of 72
AD7142
INTERRUPT OUTPUT
The AD7142 has an interrupt output that triggers an interrupt
SENSOR TOUCH INTERRUPT
INT
service routine on the host processor. The
signal is on
Use the sensor touch interrupt mode to interrupt the host
processor only when the sensor is activated.
Pin 25, and is an open-drain output. There are three types of
interrupt events on the AD7142: a CDC conversion complete
interrupt, a sensor threshold interrupt, and a GPIO interrupt.
Each interrupt has enable and status registers. The conversion
complete and sensor threshold interrupts can be enabled on a
per conversion stage basis. The status registers indicate what
Configuring the AD7142 into this mode results in the interrupt
being asserted when the user makes contact with the sensor and
again when the user lifts off the sensor. The second interrupt is
required to alert the host processor that the user is no longer
contacting the sensor.
INT
type of interrupt triggered the
pin. Status registers are
The registers located at Address 0x005 and Address 0x006 are
used to enable the interrupt output for each stage. The registers
located at Address 0x008 and Address 0x009 are used to read
back the interrupt status for each stage.
INT
cleared, and the
signal is reset high, during a read
operation. The signal returns high as soon as the read address
has been set up.
CDC CONVERSION COMPLETE INTERRUPT
Figure 38 shows the interrupt output timing during contact with
one of the sensors connected to STAGE0 when operating in the
sensor touch interrupt mode. For a low limit configuration, the
interrupt output is asserted as soon as the sensor is contacted and
again after the user has stopped contacting the sensor.
The AD7142 interrupt signal asserts low to indicate the
completion of a conversion stage, and new conversion result
data is available in the registers.
The interrupt can be independently enabled for each conversion
stage. Each conversion stage complete interrupt can be enabled via
the STAGE_COMPLETE_EN register (Address 0x007). This
register has a bit that corresponds to each conversion stage. Setting
this bit to 1 enables the interrupt for that stage. Clearing this bit to 0
disables the conversion complete interrupt for that stage.
Note: The interrupt output remains low until the host processor
reads back the interrupt status registers located at Address 0x008
and Address 0x009.
The interrupt output is asserted when there is a change in the
threshold status bits. This could indicate that a user is now
touching the sensor(s) for the first time, the number of sensors
being touched has changed, or the user is no longer touching
the sensor(s). Reading the status bits in the interrupt status
register shows the current sensor activations.
In normal operation, the AD7142 interrupt is enabled only for the
last stage in a conversion sequence. For example, if there are five
conversion stages, the conversion complete interrupt for STAGE4 is
INT
enabled.
only asserts when all five conversion stages are
complete, and the host can read new data from all five result
registers. The interrupt is cleared by reading the STAGE_
COMPLETE_STATUS_INT register located at Address 0x00A.
CONVERSION
STAGE0
STAGE1
STAGE
2
4
Register 0x00A is the conversion complete interrupt status
register. Each bit in this register corresponds to a conversion
stage. If a bit is set, it means that the conversion complete
interrupt for the corresponding stage was triggered. This
register is cleared on a read, provided the underlying condition
that triggered the interrupt has gone away.
SERIAL
READBACK
INT OUTPUT
NOTES:
1. USER TOUCHING DOWN ON SENSOR
2. ADDRESS 0X008 READ BACK TO CLEAR INTERRUPT
3. USER LIFTING OFF OF SENSOR
4. ADDRESS 0X008 READ BACK TO CLEAR INTERRUPT
Figure 38. Example of Sensor Touch Interrupt
Rev. A | Page 26 of 72
AD7142
STAGE0
STAGE1
STAGE2
STAGE3
STAGE4
STAGE5
STAGE6
STAGE7
STAGE8
STAGE9
STAGE10
STAGE11
CONVERSIONS
INT
1
2
3
SERIAL
READS
NOTES
THIS IS AN EXAMPLE OF A CDC CONVERSION COMPLETE INTERRUPT.
THIS TIMING EXAMPLE SHOWS THAT THE INTERRUPT OUTPUT HAS BEEN ENABLED TO BE ASSERTED AT THE END OF A CONVERSION CYCLE FOR
STAGE0, STAGE5, AND STAGE9. THE INTERRUPTS FOR ALL OTHER STAGES HAVE BEEN DISABLED.
STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE0, STAGE5, AND STAGE9 (x = 0, 5, 9)
STAGEx_LOW_INT_EN (ADDRESS 0x005) = 0
STAGEx_HIGH_INT_EN (ADDRESS 0x006) = 0
STAGEx_COMPLETE_EN (ADDRESS 0x007) = 1
STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE1 THROUGH STAGE8, STAGE10, AND STAGE11 (x = 1, 2, 3, 4, 5, 6, 7, 8, 10, 11)
STAGEx_LOW_INT_EN (ADDRESS 0x005) = 0
STAGEx_HIGH_INT_EN (ADDRESS 0x006) = 0
STAGEx_COMPLETE_EN (ADDRESS 0x007) = 0
SERIAL READBACK REQUIREMENTS FOR STAGE0, STAGE5 AND STAGE9. THIS READBACK OPERATION IS REQUIRED TO CLEAR THE INTERRUPT OUTPUT.
1. READ THE STAGE0_COMPLETE_STATUS_INT (ADDRESS 0x00A) REGISTER
2. READ THE STAGE5_COMPLETE_STATUS_INT (ADDRESS 0x00A) REGISTER
3. READ THE STAGE9_COMPLETE_STATUS_INT (ADDRESS 0x00A) REGISTER
Figure 39. Example of Configuring the Registers for End of Conversion Interrupt Setup
CONVERSIONS
STAGE0
STAGE1
STAGE2
STAGE3
STAGE4
STAGE5
STAGE6
STAGE7
STAGE8
STAGE9
STAGE10
STAGE11
INT
1
4
2
SERIAL
READS
NOTES
THIS IS AN EXAMPLE OF A SENSOR THRESHOLD INTERRUPT FOR A CASE WHERE THE LOW THRESHOLD LEVELS WERE EXCEEDED.
FOR EXAMPLE: THE SENSOR CONNECTED TO STAGE0 AND STAGE9 WERE CONTACTED AND THE LOW THRESHOLD LEVELS WERE EXCEEDED RESULTING
IN THE INTERRUPT BEING ASSERTED. THE STAGE6 INTERRUPT WAS NOT ASSERTED BECAUSE THE USER DID NOT CONTACT THE SENSOR CONNECTED TO
STAGE6.
STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE0, STAGE6, AND STAGE9 (x = 0, 6, 9)
STAGEx_LOW_INT_EN (ADDRESS 0x005) = 1
STAGEx_HIGH_INT_EN (ADDRESS 0x006) = 0
STAGEx_COMPLETE_EN (ADDRESS 0x007) = 0
STAGEx CONFIGURATION PROGRAMMING NOTES FOR STAGE1 THROUGH STAGE7, STAGE8, STAGE10, AND STAGE11 (x = 1, 2, 3, 4, 5, 6, 7, 8, 10, 11)
STAGEx_LOW_INT_EN (ADDRESS 0x005) = 0
STAGEx_HIGH_INT_EN (ADDRESS 0x006) = 0
STAGEx_COMPLETE_EN (ADDRESS 0x007) = 0
SERIAL READBACK REQUIREMENTS FOR STAGE0 AND STAGE9. THIS READBACK OPERATION IS REQUIRED TO CLEAR THE INTERRUPT OUTPUT.
1. READ THE STAGE0_LOW_LIMIT_INT (ADDRESS 0x008) REGISTER
2. READ THE STAGE5_LOW_LIMIT_INT (ADDRESS 0x008) REGISTER
Figure 40. Example of Configuring the Registers for Sensor Interrupt Setup
Rev. A | Page 27 of 72
AD7142
GPIO INT OUTPUT CONTROL
INT
The GPIO interrupt can be set to trigger on a rising edge, falling
edge, high level, or low level at the GPIO input pin. Table 14
shows how the settings of the GPIO_INPUT_CONFIG bits in
The
output signal can be controlled by the GPIO pin when
the GPIO is configured as an input. The GPIO is configured as
an input by setting the GPIO_SETUP bits in the interrupt
configuration register to 01. See the GPIO section for more
information on how to configure the GPIO.
INT
the interrupt enable register affect the behavior of
.
Figure 41 to Figure 44 show how the interrupt output is cleared on
a read from the CDC conversion complete interrupt status register.
Enable the GPIO interrupt by setting the GPIO_INT_EN bit in
Register 0x007 to 1, or disable the GPIO interrupt by clearing this
bit to 0. The GPIO status bit in the conversion complete interrupt
status register reflects the status of the GPIO interrupt. This bit is
INT
set to 1 when the GPIO has triggered
. The bit is cleared on
readback from the register, provided the condition that caused
the interrupt has gone away.
1
1
SERIAL
SERIAL
READBACK
READBACK
GPIO INPUT HIGH WHEN REGISTER IS READ BACK
GPIO INPUT HIGH WHEN REGISTER IS READ BACK
GPIO
INPUT
GPIO
INPUT
INT
INT
OUTPUT
OUTPUT
GPIO INPUT LOW WHEN REGISTER IS READ BACK
GPIO INPUT LOW WHEN REGISTER IS READ BACK
GPIO
INPUT
GPIO
INPUT
INT
INT
OUTPUT
OUTPUT
NOTES
NOTES
1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT.
1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT.
INT
Figure 42.
Output Controlled by the GPIO Input Example,
INT
Figure 41.
Output Controlled by the GPIO Input Example,
GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 01
GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 00
Rev. A | Page 28 of 72
AD7142
1
1
SERIAL
SERIAL
READBACK
READBACK
GPIO INPUT LOW WHEN REGISTER IS READ BACK
GPIO INPUT LOW WHEN REGISTER IS READ BACK
GPIO
GPIO
INPUT
INPUT
INT
INT
OUTPUT
OUTPUT
GPIO INPUT HIGH WHEN REGISTER IS READ BACK
GPIO INPUT HIGH WHEN REGISTER IS READ BACK
GPIO
GPIO
INPUT
INPUT
INT
INT
OUTPUT
OUTPUT
NOTES
NOTES
1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT.
1. READ GPIO_STATUS REGISTER TO RESET INT OUTPUT.
INT
Figure 44.
Output Controlled by the GPIO Input Example,
INT
GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 11
Figure 43.
Output Controlled by the GPIO Input Example,
GPIO_SETUP = 01, GPIO_INPUT_CONFIG = 10
Table 14. GPIO Interrupt Behavior
INT
INT Behavior
GPIO_INPUT_CONFIG
GPIO Pin
GPIO_STATUS
ꢀꢀ = Negative Level Triggered
ꢀꢀ = Negative Level Triggered
ꢀ1 = Positive Edge Triggered
ꢀ1 = Positive Edge Triggered
1ꢀ = Negative Edge Triggered
1ꢀ = Negative Edge Triggered
11 = Positive Level Triggered
11 = Positive Level Triggered
1
ꢀ
1
ꢀ
1
ꢀ
1
ꢀ
ꢀ
1
1
ꢀ
ꢀ
1
1
ꢀ
1
ꢀ
ꢀ
1
1
ꢀ
ꢀ
1
Not triggered
Asserted when signal on GPIO pin is low
Pulses low at low-to-high GPIO transition
Not triggered
Pulses low at high-to-low GPIO transition
Not triggered
Asserted when signal on GPIO pin is high
Not triggered
Rev. A | Page 29 of 72
AD7142
OUTPUTS
EXCITATION SOURCE
GPIO
The AD7142 has one GPIO pin located at Pin 26. It can be
configured as an input or an output. The GPIO_SETUP
Bits[13:12] in the interrupt enable register determine how the
GPIO pin is configured.
The excitation source onboard the AD7142 is a square wave
source with a frequency of 250 kHz. This excitation source
forms the electric field between the transmitter and receiver in
the external capacitance sensor PCB. The source is output from
SRC
the AD7142 on two pins, the SRC pin and the
pin (outputs
SRC
Table 15. GPIO_SETUP Bits
an inverted version of the source square wave). The signal
is not used in the
GPIO_SETUP
GPIO Configuration
GPIO disabled
Input
Output low
Output high
SRC
offsets large external sensor capacitances.
majority of applications.
ꢀꢀ
ꢀ1
1ꢀ
11
The source output can be disabled from both output pins
separately by writing to the control register bits (Address
0x000[13:12]). Setting Bit 12 in this register to 1 disables the
source output on the SRC pin. Setting Bit 13 in this register to 1
When the GPIO is configured as an output, the voltage level on
the pin is set to either a low level or a high level, as defined by
the GPIO_SETUP bits shown in Table 15.
SRC
disables the inverted source output on the
pin.
CSHIELD OUTPUT
When the GPIO is configured as an input, the
GPIO_INPUT_CONFIG bits in the interrupt enable register
determine the response of the AD7142 to a signal on the GPIO
pin. The GPIO can be configured as either active high or active
low, as well as either edge-triggered or level-triggered, as listed
in Table 16.
To prevent leakage from the external capacitance sensors, the
sensor traces can be shielded. The AD7142 has a voltage output
that can be used as the potential for any shield traces, CSHIELD
The CSHIELD voltage is equal to AVDD/2.
.
The CSHIELD potential is derived from the output of the AD7142
internal amplifier, and is of equal potential to the CIN input
lines. Because the shield is at the same potential as the sensor
traces, no leakage to ground occurs. To eliminate any ringing on
the CSHIELD output, connect a 10 nF capacitor between the
CSHIELD pin and ground. This capacitor is required, whether
Table 16. GPIO_INPUT_CONFIG Bits
GPIO_INPUT_CONFIG
GPIO Configuration
ꢀꢀ
ꢀ1
1ꢀ
11
Triggered on negative level (active low)
Triggered on positive edge (active high)
Triggered on negative edge (active low)
Triggered on positive level (active high)
CSHIELD is used in the application or not.
For most applications, CSHIELD is not used, and a ground plane is
used instead around the sensors.
When GPIO is configured as an input, it triggers the interrupt
output on the AD7142. Table 14 lists the interrupt output
behavior for each of the GPIO configuration setups.
USING THE GPIO TO TURN ON/OFF AN LED
The GPIO on the AD7142 can be used to turn on and off LEDs
by setting the GPIO as either output high or low. Setting the
GPIO output high turns on the LED; setting the GPIO output
low turns off the LED. The GPIO pin connects to a transistor
that provides the drive current for the LED. Suitable transistors
include the KTC3875.
V
CC
KTC3875
OR SIMILAR
AD7142
GPIO
Figure 45. Controlling LEDs Using the GPIO
Rev. A | Page 3ꢀ of 72
AD7142
Bits[15:11] of the command word must be set to 11100 to
successfully begin a bus transaction.
SERIAL INTERFACE
The AD7142 is available with an SPI serial interface. The
AD7142-1 is available with an I2C-compatible interface. Both
parts are the same, with the exception of the serial interface.
Bit 10 is the read/write bit; 1 indicates a read, and 0 indicates a
write.
Bits[9:0] contain the target register address. When reading or
writing to more than one register, this address indicates the
address of the first register to be written to or read from.
SPI INTERFACE
The AD7142 has a 4-wire serial peripheral interface (SPI). The
SPI has a data input pin (SDI) for inputting data to the device, a
data output pin (SDO) for reading data back from the device,
and a data clock pin (SCLK) for clocking data into and out of
Writing Data
Data is written to the AD7142 in 16-bit words. The first word
written to the device is the command word, with the read/write
bit set to 0. The master then supplies the 16-bit input data-word
on the SDI line. The AD7142 clocks the data into the register
addressed in the command word. If there is more than one
word of data to be clocked in, the AD7142 automatically incre-
ments the address pointer, and clocks the next data-word into
the next register.
CS
the device. A chip select pin ( ) enables or disables the serial
CS
interface.
is required for correct operation of the SPI
interface. Data is clocked out of the AD7142 on the negative
edge of SCLK, and data is clocked into the device on the
positive edge of SCLK.
SPI Command Word
All data transactions on the SPI bus begin with the master
The AD7142 continues to clock in data on the SDI line until
CS
taking
from high to low and sending out the command
CS
either the master finishes the write transition by pulling
word. This indicates to the AD7142 whether the transaction is a
read or a write, and gives the address of the register from which
to begin the data transfer. The following bit map shows the SPI
command word.
high, or the address pointer reaches its maximum value. The
AD7142 address pointer does not wrap around. When it
reaches its maximum value, any data provided by the master on
the SDI line is ignored by the AD7142.
MSB
15
1
LSB
14 13 12 11 10
R/W
9:0
1
1
ꢀ
ꢀ
Register address
16-BIT COMMAND WORD
ENABLE WORD
R/W
REGISTER ADDRESS
16-BIT DATA
CW
15
CW
14
CW
13
CW
12
CW
11
CW
10
CW
9
CW
7
CW
6
CW
5
CW
4
CW
3
CW
2
CW
1
CW
0
CW
8
SDI
D15 D14 D13
D2
D1
D0
t2
t4
t5
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
30
31
t8
32
t1
t
3
CS
NOTES
1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. ALL 32 BITS MUST BE WRITTEN: 16 BITS FOR CONTROL WORD AND 16 BITS FOR DATA.
3. 16-BIT COMMAND WORD SETTINGS FOR SERIAL WRITE OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 0 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS)
Figure 46. Single Register Write SPI Timing
Rev. A | Page 31 of 72
AD7142
16-BIT COMMAND WORD
R/W STARTING REGISTER ADDRESS
DATA FOR STARTING
REGISTER ADDRESS
DATA FOR NEXT
REGISTER ADDRESS
ENABLE WORD
CW CW CW CW CW CW CW CW CW CW
15 14 13 12 11 10
CW CW
CW
3
CW CW CW
SDI
D15 D14
D1
D0
D15
D1
D0
D14
D15
49
9
8
7
6
5
4
2
1
0
SCLK
CS
1
2
3
4
11
12
13
14
5
6
7
8
9
10
15
16
17
18
31
32
33
34
47
48
NOTES
1. MULTIPLE SEQUENTIAL REGISTERS CAN BE LOADED CONTINUOUSLY.
2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 16-BIT DATA-WORDS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD (ALL 16 BITS MUST BE WRITTEN).
4. CS IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.
5. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL WRITE OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 0 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS)
Figure 47. Sequential Register Write SPI Timing
16-BIT COMMAND WORD
ENABLE WORD
R/W
REGISTER ADDRESS
CW
15
CW
14
CW
13
CW
12
CW
11
CW
10
CW
9
CW
7
CW
6
CW
5
CW
4
CW
3
CW
2
CW
1
CW
0
CW
8
SDI
X
X
X
X
X
X
t2
t4
t5
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
30
31
t8
32
t1
t3
CS
t6
D15 D14 D13
16-BIT READBACK DATA
t7
SDO
D2
D1
D0
XXX
XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX
NOTES
1. SDI BITS ARE LATCHED ON SCLK RISING EDGES. SCLK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.
3. THE REGISTER DATA IS READ BACK ON THE SDO PIN.
4. X DENOTES DON’T CARE.
5. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.
6. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.
7. 16-BIT COMMAND WORD SETTINGS FOR SINGLE READBACK OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 1 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (10-BIT MSB JUSTIFIED REGISTER ADDRESS)
Figure 48. Single Register Readback SPI Timing
Reading Data
The AD7142 continues to clock out data on the SDO line
provided the master continues to supply the clock signal on
SCLK. The read transaction finishes when the master takes
A read transaction begins when the master writes the command
word to the AD7142 with the read/write bit set to 1. The master
then supplies 16 clock pulses per data-word to be read, and the
AD7142 clocks out data from the addressed register on the SDO
line. The first data-word is clocked out on the first falling edge
of SCLK following the command word, as shown in Figure 48.
CS
high. If the AD7142 address pointer reaches its maximum
value, then the AD7142 repeatedly clocks out data from the
addressed register. The address pointer does not wrap around.
Rev. A | Page 32 of 72
AD7142
16-BIT COMMAND WORD
R/W REGISTER ADDRESS
ENABLE WORD
CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW CW
15 14 13 12 11 10
SDI
X
X
X
X
X
X
X
X
X
9
8
7
6
5
4
3
2
1
0
SCLK
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
31
32
33
34
47
48
49
SDO
XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX D15 D14
D1
D0 D15 D14
D1
D0 D15
READBACK DATA FOR
NEXT REGISTER ADDRESS
READBACK DATA FOR
STARTING REGISTER ADDRESS
NOTES
1. MULTIPLE REGISTERS CAN BE READ BACK CONTINUOUSLY.
2. THE 16-BIT CONTROL WORD MUST BE WRITTEN ON SDI: 5 BITS FOR ENABLE WORD, 1 BIT FOR R/W, AND 10 BITS FOR REGISTER ADDRESS.
3. THE ADDRESS AUTOMATICALLY INCREMENTS WITH EACH 16-BIT DATA-WORD BEING READ BACK ON THE SDO PIN.
4. CS IS HELD LOW UNTIL ALL REGISTER BITS HAVE BEEN READ BACK.
5. X DENOTES DON’T CARE.
6. XXX DENOTES HIGH IMPEDANCE THREE-STATE OUTPUT.
7. 16-BIT COMMAND WORD SETTINGS FOR SEQUENTIAL READBACK OPERATION:
CW[15:11] = 11100 (ENABLE WORD)
CW[10] = 1 (R/W)
CW[9:0] = [AD9, AD8, AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0] (STARTING MSB JUSTIFIED REGISTER ADDRESS)
Figure 49. Sequential Register Read back SPI Timing
All slave peripherals connected to the serial bus respond to the
start condition and shift in the next eight bits, consisting of a
I2C COMPATIBLE INTERFACE
The AD7142-1 supports the industry standard 2-wire I2C serial
interface protocol. The two wires associated with the I2C timing are
the SCLK and the SDA inputs. The SDA is an I/O pin that allows
both register write and register readback operations. The AD7142-1
is always a slave device on the I2C serial interface bus.
W
7-bit address (MSB first) plus a R/ bit that determines the
direction of the data transfer. The peripheral whose address
corresponds to the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as the
acknowledge bit. All other devices on the bus now remain idle
when the selected device waits for data to be read from, or
It has a 7-bit device address, Address 0101 1XX. The lower two
bits are set by tying the ADD0 and ADD1 pins high or low. The
AD7142-1 responds when the master device sends its device
address over the bus. The AD7142-1 cannot initiate data
transfers on the bus.
W
written to it. If the R/ bit is a 0, the master writes to the slave
W
device. If the R/ bit is a 1, the master reads from the slave device.
Data is sent over the serial bus in a sequence of nine clock
pulses, eight bits of data followed by an acknowledge bit from
the slave device. Transitions on the data line must occur during
the low period of the clock signal and remain stable during the
high period, since a low-to-high transition when the clock is
high can be interpreted as a stop signal. The number of data
bytes transmitted over the serial bus in a single read or write
operation is limited only by what the master and slave devices
can handle.
Table 17. AD7142-1 I2C Device Address
ADD1
ADD0
I2C Address
ꢀ1ꢀ1 1ꢀꢀ
ꢀ1ꢀ1 1ꢀ1
ꢀ1ꢀ1 11ꢀ
ꢀ1ꢀ1 111
ꢀ
ꢀ
1
1
ꢀ
1
ꢀ
1
Data Transfer
When all data bytes are read or written, a stop condition is
established. A stop condition is defined by a low-to-high
transition on SDA when SCLK remains high. If the AD7142
encounters a stop condition, it returns to its idle condition, and
the address pointer register resets to Address 0x00.
Data is transferred over the I2C serial interface in 8-bit bytes.
The master initiates a data transfer by establishing a start con-
dition, defined as a high-to-low transition on the serial data
line, SDA, when the serial clock line, SCLK, remains high. This
indicates that an address/data stream follows.
Rev. A | Page 33 of 72
AD7142
START
AD7142 DEVICE ADDRESS
REGISTER ADDRESS[A15:A8]
REGISTER ADDRESS[A7:A0]
SDA
DEV DEV DEV DEV DEV DEV DEV
R/W ACK A15
A14
A9
A8 ACK A7
A6
A1
A0
A6
A5
A4
A3
A2
A1
A0
t1
t3
SCLK
1
2
3
4
11
16
5
6
7
8
9
10
17
18
19
20
25
26
t2
STOP
START
REGISTER DATA[D15:D8]
ACK D15 D14 D9
REGISTER DATA[D7:D0]
D1
AD7142 DEVICE ADDRESS
DEV DEV DEV
t8
D8 ACK
t4
D7
D0
ACK
45
D6
A6
A5
A4
t6
t7
t5
1
2
3
27
28
29
34
35
36
37
38
43
44
46
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
3. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE X ARE DON'T CARE BITS.
4. 16-BIT REGISTER ADDRESS[A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE X ARE DON’T CARE BITS.
5. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
6. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
Figure 50. Example of I2C Timing for Single Register Write Operation
Writing Data over the I2C Bus
The process for writing to the AD7142-1 over the I2C bus is
shown in Figure 50 and Figure 52. The device address is sent
Any data written to the AD7142-1 after the address pointer has
reached its maximum value is discarded.
All registers on the AD7142-1 are 16-bit. Two consecutive 8-bit
data bytes are combined and written to the 16-bit registers. To
avoid errors, all writes to the device must contain an even
number of data bytes.
W
over the bus followed by the R/ bit set to 0. This is followed
by two bytes of data that contain the 10-bit address of the
internal data register to be written. The following bit map shows
the upper register address bytes. Note that Bit 7 to Bit 2 in the
upper address byte are don’t care bits. The address is contained
in the 10 LSBs of the register address bytes.
To finish the transaction, the master generates a stop condition
on SDO, or generates a repeat start condition if the master is to
maintain control of the bus.
Reading Data over the I2C Bus
MSB
7
LSB
6
5
4
3
2
1
0
To read from the AD7142-1, the address pointer register must
first be set to the address of the required internal register. The
master performs a write transaction, and writes to the AD7142-1
to set the address pointer. The master then outputs a repeat start
condition to keep control of the bus, or if this is not possible, ends
the write transaction with a stop condition. A read transaction is
X
X
X
X
X
X
Register Register
Address Address
Bit 9
Bit 8
The following bit map shows the lower register address bytes.
MSB
7
LSB
6
5
4
3
2
1
0
W
initiated, with the R/ bit set to 1.
Reg.
Reg.
Reg.
Reg.
Reg.
Reg.
Reg.
Reg.
The AD7142-1 supplies the upper eight bits of data from the
addressed register in the first readback byte, followed by the
lower eight bits in the next byte. This is shown in Figure 51 and
Figure 52.
Addr. Addr. Addr. Addr. Addr. Addr. Addr. Addr.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit ꢀ
The third data byte contains the 8 MSBs of the data to be
written to the internal register. The fourth data byte contains
the 8 LSBs of data to be written to the internal register.
Because the address pointer automatically increases after each
read, the AD7142-1 continues to output readback data until the
master puts a no acknowledge and stop condition on the bus. If
the address pointer reaches its maximum value, and the master
continues to read from the part, the AD7142-1 repeatedly sends
data from the last register addressed.
The AD7142-1 address pointer register automatically increments
after each write. This allows the master to sequentially write to all
registers on the AD7142-1 in the same write transaction. However,
the address pointer register does not wrap around after the last
address.
Rev. A | Page 34 of 72
AD7142
START
AD7142-1 DEVICE ADDRESS
REGISTER ADDRESS[A15:A8]
REGISTER ADDRESS[A7:A0]
SDA
DEV DEV DEV DEV DEV DEV DEV
R/W ACK A15 A14
A9
A8 ACK A7
A6
A1
A0
ACK
27
A6
A5
A4
A3
A2
A1
A0
t1
t3
SCLK
1
2
3
4
5
6
7
8
9
10
11
16
17
18
19
20
25
26
t2
P
AD7142-1 DEVICE ADDRESS
REGISTER DATA[D7:D0]
D1
D6
t5
39
SR
t8
AD7142 DEVICE ADDRESS
DEV DEV DEV
DEV DEV
A6 A5
DEV DEV
D7
D0
ACK
ACK
R/W
A1
A0
A6
A5
A4
USING
REPEATED START
t4
t6
t7
1
34
35
36
37
38
44
45
46
2
3
28
29
30
AD7142-1 DEVICE ADDRESS
REGISTER DATA[D7:D0]
D6
D1
t5
39
P
P
S
DEV DEV
A6 A5
DEV DEV
D7
D0
ACK
46
ACK
R/W
A1
A0
t4
SEPARATE READ AND
WRITE TRANSACTIONS
34
35
36
37
38
44
45
28
29
30
NOTES
1. A START CONDITION AT THE BEGINNING IS DEFINED AS A HIGH-TO-LOW TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
2. A STOP CONDITION AT THE END IS DEFINED AS A LOW-TO-HIGH TRANSITION ON SDA WHILE SCLK REMAINS HIGH.
3. THE MASTER GENERATES THE ACK AT THE END OF THE READBACK TO SIGNAL THAT IT DOES NOT WANT ADDITIONAL DATA.
4. 7-BIT DEVICE ADDRESS [DEV A6:DEV A0] = [0 1 0 1 1 X X], WHERE THE TWO LSB X's ARE DON'T CARE BITS.
5. 16-BIT REGISTER ADDRESS[A15:A0] = [X, X, X, X, X, X, A9, A8, A7, A6, A5, A4, A3, A2, A1, A0], WHERE THE UPPER LSB X’s ARE DON’T CARE BITS.
6. REGISTER ADDRESS [A15:A8] AND REGISTER ADDRESS [A7:A0] ARE ALWAYS SEPARATED BY A LOW ACK BITS.
7. REGISTER DATA [D15:D8] AND REGISTER DATA [D7:D0] ARE ALWAYS SEPARATED BY A LOW ACK BIT.
8. THE R/W BIT IS SET TO A1 TO INDICATE A READBACK OPERATION.
Figure 51. Example of I2C Timing for Single Register Readback Operation
WRITE
6-BIT DEVICE
REGISTER ADDR
[15:8]
REGISTER ADDR
[7:0]
WRITE DATA
HIGH BYTE [15:8]
WRITE DATA
LOW BYTE [7:0]
WRITE DATA
HIGH BYTE [15:8]
WRITE DATA
LOW BYTE [7:0]
S
P
W
ADDRESS
READ (USING REPEATED START)
READ DATA
LOW BYTE [7:0]
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
6-BIT DEVICE
ADDRESS
REGISTER ADDR
HIGH BYTE
REGISTER ADDR
LOW BYTE
6-BIT DEVICE
ADDRESS
READ DATA
HIGH BYTE [15:8]
P
ACK
S
W
READ (WRITE TRANSACTION SETS UP REGISTER ADDRESS)
6-BIT DEVICE
ADDRESS
REGISTER ADDR
HIGH BYTE
REGISTER ADDR
LOW BYTE
READ DATA
LOW BYTE [7:0]
READ DATA
HIGH BYTE [15:8]
READ DATA
LOW BYTE [7:0]
6-BIT DEVICE
ADDRESS
READ DATA
HIGH BYTE [15:8]
P
P
S
ACK
S
W
OUTPUT FROM MASTER
OUTPUT FROM AD7142
S = START BIT
P = STOP BIT
SR = REPEATED START BIT
ACK = ACKNOWLEDGE BIT
ACK = NO ACKNOWLEDGE BIT
Figure 52. Example of Sequential I2C Write and Readback Operation
This allows the AD7142 to be connected directly to processors
whose supply voltage is less than the minimum operating
voltage of the AD7142 without the need for external level-
shifters. The VDRIVE pin can be connected to voltage supplies as
VDRIVE INPUT
The supply voltage to all pins associated with both the I2C and
CS
SPI serial interfaces (SDO, SDI, SCLK, SDA, and ) is separate
from the main VCC supplies and is connected to the VDRIVE pin.
low as 1.65 V and as high as DVCC
.
Rev. A | Page 35 of 72
AD7142
PCB DESIGN GUIDELINES
CAPACITIVE SENSOR BOARD MECHANICAL SPECIFICATIONS
Table 18.
Parameter
Symbol
Min
0.1
0
Typ
Max
Unit
mm
mm
mm
Distance from Edge of Any Sensor to Edge of Grounded Metal Object
Distance Between Sensor Edges1
Distance Between Bottom of Sensor Board and Controller Board or Grounded
Metal Casing2
D1
D2 = D3 = D4
D5
1.0
1 The distance is dependent on the application and the positioning of the switches relative to each other and with respect to the user’s finger positioning and handling.
Adjacent sensors, with 0 minimum space between them, are implemented differentially.
2 The 1.0 mm specification is meant to prevent direct sensor board contact with any conductive material. This specification does not guarantee no EMI coupling from
the controller board to the sensors. Address potential EMI coupling issues by placing a grounded metal shield between the capacitive sensor board and the main
controller board as shown in Figure 55.
CAPACITIVE SENSOR BOARD
METAL OBJECT
D
5
GROUNDED METAL SHIELD
CAPACITIVE SENSOR
PRINTED CIRCUIT
8-WAY
SWITCH
CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING
Figure 55. Capacitive Sensor Board with Grounded Shield
D
4
CHIP SCALE PACKAGES
SLIDER
The lands on the chip scale package (CP-32-3) are rectangular.
The printed circuit board pad for these should be 0.1 mm
longer than the package land length, and 0.05 mm wider than
the package land width. Center the land on the pad to maximize
the solder joint size.
BUTTONS
D
3
D
2
The bottom of the chip scale package has a central thermal pad.
The thermal pad on the printed circuit board should be at least
as large as this exposed pad. To avoid shorting, provide a
clearance of at least 0.25 mm between the thermal pad and the
inner edges of the land pattern on the printed circuit board.
D
1
Figure 53. Capacitive Sensor Board Mechanicals Top View
Thermal vias can be used on the printed circuit board thermal
pad to improve thermal performance of the package. If vias are
used, they should be incorporated in the thermal pad at a
1.2 mm pitch grid. The via diameter should be between 0.3 mm
and 0.33 mm, and the via barrel should be plated with 1 oz.
copper to plug the via.
CAPACITIVE SENSOR BOARD
D
5
CONTROLLER PRINTED CIRCUIT BOARD OR METAL CASING
Figure 54. Capacitive Sensor Board Mechanicals Side View
Connect the printed circuit board thermal pad to GND.
Rev. A | Page 36 of 72
AD7142
POWER-UP SEQUENCE
When the AD7142 is powered up, the following sequence is
recommended when initially developing the AD7142 and ꢀP
serial interface:
Address 0x003 = 0x14C8
Address 0x004 = 0x0832
Address 0x005 = 0x0000
Address 0x006 = 0x0000
1. Turn on the power supplies to the AD7142.
2. Write to the Bank 2 registers at Address 0x080 through
Address 0x0DF. These registers are contiguous so a
sequential register write sequence can be applied.
Address 0x007 = 0x0001 (The AD7142 interrupt is asserted
approximately every 36 ms.)
4. Write to the Bank 1 register, Address 0x001 = 0x0FFF.
Note: The Bank 2 register values are unique for each
application. Register values are provided by Analog
Devices after the sensor board has been developed.
5. Read back the corresponding interrupt status register at
Address 0x008, Address 0x009, or Address 0x00A. This is
determined by the interrupt output configuration as
explained in the Interrupt Output section.
3. Write to the Bank 1 registers at Address 0x000 through
Address 0x007 as follows. These registers are contiguous so
a sequential register write sequence can be applied (see
Figure 47 and Figure 52).
Note: The specific registers required to be read back
depend on each application. Analog Devices provides this
information after the sensor board has been developed.
Caution: At this time, Address 0x001 must remain set to
default value 0x0000 during this contiguous write
operation.
INT
6. Repeat Step 5 every time
is asserted.
Register values:
Address 0x000 = 0x00B2
Address 0x001 = 0x0000
Address 0x002 = 0x3230
CONVERSION
STAGE
1
2
3
4
5
6
7
8
9
10 11
0
1
2
9
10 11
0
1
2
9
10 11
0
1
0
CONVERSION STAGES DISABLED
SECOND CONVERSION
SEQUENCE
THIRD CONVERSION
SEQUENCE
FIRST CONVERSION SEQUENCE
Figure 56. Recommended Start-Up Sequence
Rev. A | Page 37 of 72
AD7142
TYPICAL APPLICATION CIRCUITS
V
DRIVE
AV
DV
CC
CC,
2.2kΩ
HOST
WITH
SPI
INT
SS
BUTTON
BUTTON
INTERFACE
CS
1
2
3
4
5
24
23
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8
CIN9
CIN10
SCLK
SCK
SDI 22
MOSI
MISO
SCROLL WHEEL
SDO
21
20
19
AD7142
V
HOST
BUTTON
V
DRIVE
BUTTON
DGND2
DGND1
6
1.8V
7
8
18
17
SENSOR PCB
DV
CC
AV
DV 2.7V TO 3.6V
CC
CC,
1µF TO 10µF
(OPTIONAL)
0.1µF
10nF
Figure 57. Typical Application Circuit with SPI Interface
V
DRIVE
V
DRIVE
V
DRIVE
2.2kΩ
AV
DV
CC
CC,
2.2kΩ
2.2kΩ
HOST
WITH
I C
INT
2
INTERFACE
SLIDER
24
1
2
3
4
5
CIN3
CIN4
CIN5
CIN6
CIN7
CIN8
ADD1
BUTTON
23
22
21
20
SCK
SDO
SCLK
ADD0
BUTTON
BUTTON
SDA
AD7142-1
V
DRIVE
DGND2
19
6
CIN9
18
17
7
8
DGND1
CIN10
DV
CC
AV
DV 2.7V TO 3.6V
CC
CC,
0.1µF
1µF TO 10µF
(OPTIONAL)
10nF
Figure 58. Typical Application Circuit with I2C Interface
Rev. A | Page 38 of 72
AD7142
REGISTER MAP
The AD7142 address space is divided into three different register
banks, referred to as Bank 1, Bank 2, and Bank 3. Figure 59
shows the division of these three banks.
Bank 3 registers contain the results of each conversion stage.
These registers automatically update at the end of each conversion
sequence. Although these registers are primarily used by the
AD7142 internal data processing, they are accessible by the host
processor for additional external data processing, if desired.
Bank 1 contains control registers, CDC conversion control
registers, interrupt enable registers, interrupt status registers,
CDC 16-bit conversion data registers, device ID registers, and
proximity status registers.
Default values are undefined for Bank 2 registers and Bank 3
registers until after power-up and configuration of the Bank 2
registers.
Bank 2 contains the configuration registers used for uniquely
configuring the CIN inputs for each conversion stage. Initialize
the Bank 2 configuration registers immediately after power-up
to obtain valid CDC conversion result data.
REGISTER BANK 1
REGISTER BANK 2
REGISTER BANK 3
ADDR 0x000
ADDR 0x001
ADDR 0x080
ADDR 0x088
ADDR 0x0E0
ADDR 0x088
STAGE0 RESULTS
(36 REGISTERS)
STAGE0 CONFIGURATION
(8 REGISTERS)
SET UP CONTROL
(1 REGISTER)
STAGE1 RESULTS
(36 REGISTERS)
STAGE1 CONFIGURATION
(8 REGISTERS)
CALIBRATION AND SET UP
(4 REGISTERS)
ADDR 0x090
ADDR 0x090
STAGE2 RESULTS
(36 REGISTERS)
STAGE2 CONFIGURATION
(8 REGISTERS)
ADDR 0x005
ADDR 0x098
ADDR 0x0A0
ADDR 0x0A8
ADDR 0x098
ADDR 0x0A0
ADDR 0x0A8
STAGE3 RESULTS
(36 REGISTERS)
STAGE3 CONFIGURATION
(8 REGISTERS)
INTERRUPT ENABLE
(3 REGISTERS)
STAGE4 RESULTS
(36 REGISTERS)
STAGE4 CONFIGURATION
(8 REGISTERS)
ADDR 0x008
ADDR 0x00B
INTERRUPT STATUS
(3 REGISTERS)
STAGE5 RESULTS
(36 REGISTERS)
STAGE5 CONFIGURATION
(8 REGISTERS)
ADDR 0x0B0
ADDR 0x0B8
ADDR 0x0B0
ADDR 0x0B8
CDC 16-BIT CONVERSION DATA
(12 REGISTERS)
STAGE6 RESULTS
(36 REGISTERS)
STAGE6 CONFIGURATION
(8 REGISTERS)
ADDR 0x017
ADDR 0x018
ADDR 0x042
STAGE7 RESULTS
(36 REGISTERS)
STAGE7 CONFIGURATION
(8 REGISTERS)
DEVICE ID REGISTER
ADDR 0x0C0
ADDR 0x0C8
ADDR 0x0C0
ADDR 0x0C8
INVALID DO NOT ACCESS
STAGE8 RESULTS
(36 REGISTERS)
STAGE8 CONFIGURATION
(8 REGISTERS)
PROXIMITY STATUS REGISTER
STAGE9 RESULTS
(36 REGISTERS)
STAGE9 CONFIGURATION
(8 REGISTERS)
ADDR 0x043
ADDR 0x0D0
ADDR 0x0D8
ADDR 0x0D0
ADDR 0x28F
STAGE10 CONFIGURATION
(8 REGISTERS)
STAGE10 RESULTS
(36 REGISTERS)
INVALID DO NOT ACCESS
STAGE11 CONFIGURATION
(8 REGISTERS)
STAGE11 RESULTS
(36 REGISTERS)
ADDR 0x7F0
Figure 59. Layout of Bank 1 Registers, Bank 2 Registers, and Bank 3 Registers
Rev. A | Page 39 of 72
AD7142
DETAILED REGISTER DESCRIPTIONS
BANK 1 REGISTERS
All addresses and default values are expressed in hexadecimal.
Table 19. PWR_CONTROL Register
Address Data Bit
DefaultValue
Type Name
R/W POWER_MODE
Description
ꢀxꢀꢀꢀ
[1:ꢀ]
ꢀ
Operating modes
ꢀꢀ = full power mode (normal operation, CDC
conversions approximately every 36 ms)
ꢀ1 = full shutdown mode (no CDC conversions)
1ꢀ = low power mode (automatic wake up operation)
11 = full shutdown mode (no CDC conversions)
Low power mode conversion delay
ꢀꢀ = 2ꢀꢀ ms
ꢀ1 = 4ꢀꢀ ms
1ꢀ = 6ꢀꢀ ms
11 = 8ꢀꢀ ms
[3:2]
[7:4]
ꢀ
ꢀ
LP_CONV_DELAY
SEQUENCE_STAGE_NUM Number of stages in sequence (N + 1)
ꢀꢀꢀꢀ = 1 conversion stage in sequence
ꢀꢀꢀ1 = 2 conversion stages in sequence
Maximum value = 1ꢀ11 = 12 conversion stages per
sequence
[9:8]
ꢀ
DECIMATION
ADC decimation factor
ꢀꢀ = decimate by 256
ꢀ1 = decimate by 128
1ꢀ = do not use this setting
11 = do not use this setting
Software reset control (self-clearing)
1 = resets all registers to default values
Interrupt polarity control
ꢀ = active low
[1ꢀ]
[11]
ꢀ
ꢀ
SW_RESET
INT_POL
1 = active high
[12]
ꢀ
ꢀ
ꢀ
EXCITATION_SOURCE
SRC
Excitation source control for Pin 15
ꢀ = enable output
1 = disable output
Excitation source control for Pin 16
ꢀ = enable output
1 = disable output
[13]
[15:14]
CDC_BIAS
CDC bias current control
ꢀꢀ = normal operation
ꢀ1 = normal operation + 2ꢀ%
1ꢀ = normal operation + 35%
11 = normal operation + 5ꢀ%
Rev. A | Page 4ꢀ of 72
AD7142
Table 20. STAGE_CAL_EN Register
Address
Data Bit DefaultValue Type
Name
Description
ꢀxꢀꢀ1
[ꢀ]
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
R/W
STAGEꢀ_CAL_EN
STAGEꢀ calibration enable
ꢀ = disable
1 = enable
STAGE1 calibration enable
ꢀ = disable
1 = enable
STAGE2 calibration enable
ꢀ = disable
1 = enable
STAGE3 calibration enable
ꢀ = disable
1 = enable
STAGE4 calibration enable
ꢀ = disable
1 = enable
STAGE5 calibration enable
ꢀ = disable
1 = enable
STAGE6 calibration enable
ꢀ = disable
1 = enable
STAGE7 calibration enable
ꢀ = disable
1 = enable
STAGE8 calibration enable
ꢀ = disable
1 = enable
STAGE9 calibration enable
ꢀ = disable
1 = enable
STAGE1ꢀ calibration enable
ꢀ = disable
1 = enable
STAGE11 calibration enable
ꢀ = disable
1 = enable
Full power mode skip control
ꢀꢀ = skip 3 samples
ꢀ1 = skip 7 samples
1ꢀ = skip 15 samples
11 = skip 31 samples
Low power mode skip control
ꢀꢀ = use all samples
ꢀ1 = skip 1 sample
1ꢀ = skip 2 samples
11 = skip 3 samples
[1]
STAGE1_CAL_EN
STAGE2_CAL_EN
STAGE3_CAL_EN
STAGE4_CAL_EN
STAGE5_CAL_EN
STAGE6_CAL_EN
STAGE7_CAL_EN
STAGE8_CAL_EN
STAGE9_CAL_EN
STAGE1ꢀ_CAL_EN
STAGE11_CAL_EN
AVG_FP_SKIP
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[1ꢀ]
[11]
[13:12]
[15:14]
ꢀ
AVG_LP_SKIP
Rev. A | Page 41 of 72
AD7142
Table 21. AMB_COMP_CTRL0 Register
Address
Data Bit DefaultValue Type
Name
Description
ꢀxꢀꢀ2
[3:ꢀ]
ꢀ
R/W
FF_SKIP_CNT
Fast filter skip control (N+1)
ꢀꢀꢀꢀ = no sequence of results are skipped
ꢀꢀꢀ1 = one sequence of results is skipped for every
one allowed into fast FIFO
ꢀꢀ1ꢀ = two sequences of results are skipped for every
one allowed into fast FIFO
1ꢀ11 = maximum value = 12 sequences of results are
skipped for every one allowed into Fast FIFO
[7:4]
F
F
ꢀ
FP_PROXIMITY_CNT
LP_PROXIMITY_CNT
PWR_DOWN_TIMEOUT
Calibration disable period in full power mode =
FP_PROXIMITY_CNT × 16 × Time taken for one
conversion sequence in full power mode
Calibration disable period in low power mode =
LP_PROXIMITY_CNT × 4 × Time taken for one
conversion sequence in low power mode
Full power to low power mode timeout control
ꢀꢀ = 1.25 × (FP_PROXIMITY_CNT)
ꢀ1 = 1.5ꢀ × (FP_PROXIMITY_CNT)
1ꢀ = 1.75 × (FP_PROXIMITY_CNT)
11 = 2.ꢀꢀ × (FP_PROXIMITY_CNT)
Forced calibration control
[11:8]
[13:12]
[14]
[15]
ꢀ
ꢀ
FORCED_CAL
CONV_RESET
ꢀ = normal operation
1 = forces all conversion stages to recalibrate
Conversion reset control (self-clearing)
ꢀ = normal operation
1 = resets the conversion sequence back to STAGEꢀ
Table 22. AMB_COMP_CTRL1 Register
Default
Data Bit Value
Address
Type
Name
Description
ꢀxꢀꢀ3
[7:ꢀ]
[13:8]
[15:14]
64
1
ꢀ
R/W
PROXIMITY_RECAL_LVL
PROXIMITY_DETECTION_RATE
SLOW_FILTER_UPDATE_LVL
Proximity recalibration level
Proximity detection rate
Slow filter update level
Table 23. AMB_COMP_CTRL2 Register
Default
Data Bit Value
Address
Type
Name
Description
ꢀxꢀꢀ4
[9:ꢀ]
[15:1ꢀ]
3FF
3F
R/W
FP_PROXIMITY_RECAL
LP_PROXIMITY_RECAL
Full power mode proximity recalibration time control
Low power mode proximity recalibration time control
Rev. A | Page 42 of 72
AD7142
Table 24. STAGE_LOW_INT_EN Register
Address Data Bit DefaultValue Type
R/W
Name
Description
ꢀxꢀꢀ5
[ꢀ]
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
STAGEꢀ_LOW_INT_EN
STAGEꢀ low interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGEꢀ low threshold is exceeded
STAGE1 low interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGE1 low threshold is exceeded
STAGE2 low interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGE2 low threshold is exceeded
STAGE3 low interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGE3 low threshold is exceeded
STAGE4 low interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGE4 low threshold is exceeded
STAGE5 low interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGE5 low threshold is exceeded
STAGE6 low interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGE6 low threshold is exceeded
STAGE7 low interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGE7 low threshold is exceeded
STAGE8 low interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGE8 low threshold is exceeded
STAGE9 low interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGE9 low threshold is exceeded
STAGE1ꢀ low interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGE1ꢀ low threshold is exceeded
STAGE11 low interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGE11 low threshold is exceeded
GPIO setup
[1]
STAGE1_LOW_INT_EN
STAGE2_LOW_INT_EN
STAGE3_LOW_INT_EN
STAGE4_LOW_INT_EN
STAGE5_LOW_INT_EN
STAGE6_LOW_INT_EN
STAGE7_LOW_INT_EN
STAGE8_LOW_INT_EN
STAGE9_LOW_INT_EN
STAGE1ꢀ_LOW_INT_EN
STAGE11_LOW_INT_EN
GPIO_SETUP
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[1ꢀ]
[11]
[13:12]
ꢀꢀ = disable GPIO pin
ꢀ1 = configure GPIO as an input
1ꢀ = configure GPIO as an active low output
11 = configure GPIO as an active high output
GPIO input configuration
[15:14]
ꢀ
GPIO_INPUT_CONFIG
ꢀꢀ = triggered on negative level
ꢀ1 = triggered on positive edge
1ꢀ = triggered on negative edge
11 = triggered on positive level
Rev. A | Page 43 of 72
AD7142
Table 25. STAGE_HIGH_INT_EN Register
Address Data Bit
DefaultValue Type
Name
Description
ꢀxꢀꢀ6
[ꢀ]
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
R/W
STAGEꢀ_HIGH_INT_EN
STAGEꢀ high interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGEꢀ high threshold is exceeded
STAGE1 high interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGE1 high threshold is exceeded
STAGE2 high interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGE2 high threshold is exceeded
STAGE3 high interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGE3 high threshold is exceeded
STAGE4 high interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGE4 high threshold is exceeded
STAGE5 high interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGE5 high threshold is exceeded
STAGE6 high interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGE6 high threshold is exceeded
STAGE7 high interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGE7 high threshold is exceeded
STAGE8 high interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGE8 high threshold is exceeded
STAGE9 sensor high interrupt enable l
ꢀ = interrupt source disabled
1 = INT asserted if STAGE9 high threshold is exceeded
STAGE1ꢀ high interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGE1ꢀ high threshold is exceeded
STAGE11 high interrupt enable
ꢀ = interrupt source disabled
1 = INT asserted if STAGE11 high threshold is exceeded
Set unused register bits = ꢀ
[1]
STAGE1_HIGH_INT_EN
STAGE2_HIGH_INT_EN
STAGE3_HIGH_INT_EN
STAGE4_HIGH_INT_EN
STAGE5_HIGH_INT_EN
STAGE6_HIGH_INT_EN
STAGE7_HIGH_INT_EN
STAGE8_HIGH_INT_EN
STAGE9_HIGH_INT_EN
STAGE1ꢀ_HIGH_INT_EN
STAGE11_HIGH_INT_EN
Unused
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[1ꢀ]
[11]
[15:12]
Rev. A | Page 44 of 72
AD7142
Table 26. STAGE_COMPLETE_INT_EN Register
Address Data Bit DefaultValue Type
R/W
Name
Description
ꢀxꢀꢀ7
[ꢀ]
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
STAGEꢀ_COMPLETE_EN
STAGEꢀ conversion interrupt control
ꢀ = interrupt source disabled
1 = INT asserted at completion of STAGEꢀ conversion
STAGE1 conversion interrupt control
ꢀ = interrupt source disabled
1 = INT asserted at completion of STAGE1 conversion
STAGE2 conversion interrupt control
ꢀ = interrupt source disabled
1 = INT asserted at completion of STAGE2 conversion
STAGE3 conversion interrupt control
ꢀ = interrupt source disabled
1 = INT asserted at completion of STAGE3 conversion
STAGE4 conversion interrupt control
ꢀ = interrupt source disabled
1 = INT asserted at completion of STAGE4 conversion
STAGE5 conversion interrupt control
ꢀ = interrupt source disabled
1 = INT asserted at completion of STAGE5 conversion
STAGE6 conversion interrupt control
ꢀ = interrupt source disabled
1 = INT asserted at completion of STAGE6 conversion
STAGE7 conversion interrupt control
ꢀ = interrupt source disabled
1 = INT asserted at completion of STAGE7 conversion
STAGE8 conversion complete interrupt control
ꢀ = interrupt source disabled
1 = INT asserted at completion of STAGE8 conversion
STAGE9 conversion interrupt control
ꢀ = interrupt source disabled
1 = INT asserted at completion of STAGE9 conversion
STAGE1ꢀ conversion interrupt control
ꢀ = interrupt source disabled
1 = INT asserted at completion of STAGE1ꢀ conversion
STAGE11 conversion interrupt control
ꢀ = interrupt source disabled
1 = INT asserted at completion of STAGE11 conversion
Interrupt control when GPIO input pin changes level
ꢀ = disabled
[1]
STAGE1_COMPLETE_EN
STAGE2_COMPLETE_EN
STAGE3_COMPLETE_EN
STAGE4_COMPLETE_EN
STAGE5_COMPLETE_EN
STAGE6_COMPLETE_EN
STAGE7_COMPLETE_EN
STAGE8_COMPLETE_EN
STAGE9_COMPLETE_EN
STAGE1ꢀ_COMPLETE_EN
STAGE11_COMPLETE_EN
GPIO_INT_EN
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[1ꢀ]
[11]
[12]
[15:13]
1 = enabled
Set unused register bits = ꢀ
Unused
Rev. A | Page 45 of 72
AD7142
Table 27. STAGE_LOW_LIMIT_INT Register1
Address Data Bit
DefaultValue Type
Name
Description
ꢀxꢀꢀ8
[ꢀ]
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
R
STAGEꢀ_LOW_LIMIT_INT
STAGEꢀ CDC conversion low limit interrupt result
1 = indicates STAGEꢀ_LOW_THRESHOLD value was
exceeded
STAGE1 CDC conversion low limit interrupt result
1 = indicates STAGE1_LOW_THRESHOLD value was
exceeded
STAGE2 CDC conversion low limit interrupt result
1 = indicates STAGE2_LOW_THRESHOLD value was
exceeded
STAGE3 CDC conversion low limit interrupt result
1 = indicates STAGE3_LOW_THRESHOLD value was
exceeded
STAGE4 CDC conversion low limit interrupt result
1 = indicates STAGE4_LOW_THRESHOLD value was
exceeded
STAGE5 CDC conversion low limit interrupt result
1 = indicates STAGE5_LOW_THRESHOLD value was
exceeded
STAGE6 CDC conversion low limit interrupt result
1 = indicates STAGE6_LOW_THRESHOLD value was
exceeded
STAGE7 CDC conversion low limit interrupt result
1 = indicates STAGE7_LOW_THRESHOLD value was
exceeded
STAGE8 CDC conversion low limit interrupt result
1 = indicates STAGE8_LOW_THRESHOLD value was
exceeded
STAGE9 CDC conversion low limit interrupt result
1 = indicates STAGE9_LOW_THRESHOLD value was
exceeded
STAGE1ꢀ CDC Conversion Low Limit Interrupt result
1 = indicates STAGE1ꢀ_LOW_THRESHOLD value was
exceeded
STAGE11 CDC conversion low limit interrupt result
1 = indicates STAGE11_LOW_THRESHOLD value was
exceeded
[1]
STAGE1_LOW_LIMIT_INT
STAGE2_LOW_LIMIT_INT
STAGE3_LOW_LIMIT_INT
STAGE4_LOW_LIMIT_INT
STAGE5_LOW_LIMIT_INT
STAGE6_LOW_LIMIT_INT
STAGE7_LOW_LIMIT_INT
STAGE8_LOW_LIMIT_INT
STAGE9_LOW_LIMIT_INT
STAGE1ꢀ_LOW_LIMIT_INT
STAGE11_LOW_LIMIT_INT
Unused
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[1ꢀ]
[11]
[15:12]
Set unused register bits = ꢀ
1 Registers self-clear to ꢀ after readback, provided that the limits are not exceeded.
Rev. A | Page 46 of 72
AD7142
Table 28. STAGE_HIGH_LIMIT_INT Register1
Address Data Bit DefaultValue
Type
Name
Description
ꢀxꢀꢀ9
[ꢀ]
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
R
STAGEꢀ_HIGH_LIMIT_INT
STAGEꢀ CDC conversion high limit interrupt result
1 = indicates STAGEꢀ_HIGH_THRESHOLD value was
exceeded
STAGE1 CDC conversion high limit interrupt result
1 = indicates STAGE1_HIGH_THRESHOLD value was
exceeded
Stage2 CDC conversion high limit interrupt result
1 = indicates STAGE2_HIGH_THRESHOLD value was
exceeded
STAGE3 CDC conversion high limit interrupt result
1 = indicates STAGE3_HIGH_THRESHOLD value was
exceeded
STAGE4 CDC conversion high limit interrupt result
1 = indicates STAGE4_HIGH_THRESHOLD value was
exceeded
STAGE5 CDC conversion high limit interrupt result
1 = indicates STAGE5_HIGH_THRESHOLD value was
exceeded
STAGE6 CDC conversion high limit interrupt result
1 = indicates STAGE6_HIGH_THRESHOLD value was
exceeded
STAGE7 CDC conversion high limit interrupt result
1 = indicates STAGE7_HIGH_THRESHOLD value was
exceeded
STAGE8 CDC conversion high limit interrupt result
1 = indicates STAGE8_HIGH_THRESHOLD value was
exceeded
STAGE9 CDC conversion high limit interrupt result
1 = indicates STAGE9_HIGH_THRESHOLD value was
exceeded
STAGE1ꢀ CDC conversion high limit interrupt result
1 = indicates STAGE1ꢀ_HIGH_THRESHOLD value was
exceeded
STAGE11 CDC conversion high limit interrupt result
1 = indicates STAGE11_HIGH_THRESHOLD value was
exceeded
[1]
STAGE1_HIGH_LIMIT_INT
STAGE2_HIGH_LIMIT_INT
STAGE3_HIGH_LIMIT_INT
STAGE4_HIGH_LIMIT_INT
STAGE5_HIGH_LIMIT_INT
STAGE6_HIGH_LIMIT_INT
STAGE7_HIGH_LIMIT_INT
STAGE8_HIGH_LIMIT_INT
STAGE9_HIGH_LIMIT_INT
STAGE1ꢀ_HIGH_LIMIT_INT
STAGE11_HIGH_LIMIT_INT
Unused
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[1ꢀ]
[11]
[15:12]
Set unused register bits = ꢀ
1 Registers self-clear to ꢀ after readback, provided that the limits are not exceeded.
Rev. A | Page 47 of 72
AD7142
Table 29. STAGE_COMPLETE_LIMIT_INT Register1
Default
Value
Address Data Bit
Type
Name
Description
ꢀxꢀꢀA
[ꢀ]
ꢀ
R
STAGEꢀ_COMPLETE_STATUS_INT STAGEꢀ conversion complete register interrupt status
1 = indicates STAGEꢀ conversion completed
[1]
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
STAGE1_COMPLETE_STATUS_INT STAGE1 conversion complete register interrupt status
1 = indicates STAGE1 conversion completed
STAGE2_COMPLETE_STATUS_INT STAGE2 conversion complete register interrupt status
1 = indicates STAGE2 conversion completed
STAGE3_COMPLETE_STATUS_INT STAGE3 conversion complete register interrupt status
1 = indicates STAGE3 conversion completed
STAGE4_COMPLETE_STATUS_INT STAGE4 conversion complete register interrupt status
1 = indicates STAGE4 conversion completed
STAGE5_COMPLETE_STATUS_INT STAGE5 conversion complete register interrupt status
1 = indicates STAGE5 conversion completed
STAGE6_COMPLETE_STATUS_INT STAGE6 conversion complete register interrupt status
1 = indicates STAGE6 conversion completed
STAGE7_COMPLETE_STATUS_INT STAGE7 conversion complete register interrupt status
1 = indicates STAGE7 conversion completed
STAGE8_COMPLETE_STATUS_INT STAGE8 conversion complete register interrupt status
1 = indicates STAGE8 conversion completed
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
STAGE9_COMPLETE_STATUS_INT STAGE9 conversion complete register interrupt status
1 = indicates STAGE9 conversion completed
STAGE1ꢀ_COMPLETE_STATUS_INT
STAGE11_COMPLETE_STATUS_INT
GPIO_STATUS
[1ꢀ]
[11]
[12]
[15:13]
STAGE1ꢀ conversion complete register interrupt status
1 = indicates STAGE1ꢀ conversion completed
STAGE11 conversion complete register interrupt status
1 = indicates STAGE11 conversion completed
GPIO input pin status
1 = indicates level on GPIO pin has changed
Set unused register bits = ꢀ
Unused
1 Registers self-clear to ꢀ after readback, provided that the limits are not exceeded.
Table 30. CDC 16-Bit Conversion Data Registers
Default
Value
Address Data Bit
Type
R
R
R
R
R
R
R
R
R
R
R
R
Name
Description
ꢀxꢀꢀB
ꢀxꢀꢀC
ꢀxꢀꢀD
ꢀxꢀꢀE
ꢀxꢀꢀF
ꢀxꢀ1ꢀ
ꢀxꢀ11
ꢀxꢀ12
ꢀxꢀ13
ꢀxꢀ14
ꢀxꢀ15
ꢀxꢀ16
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ADC_RESULT_Sꢀ
ADC_RESULT_S1
ADC_RESULT_S2
ADC_RESULT_S3
ADC_RESULT_S4
ADC_RESULT_S5
ADC_RESULT_S6
ADC_RESULT_S7
ADC_RESULT_S8
ADC_RESULT_S9
ADC_RESULT_S1ꢀ
ADC_RESULT_S11
STAGEꢀ CDC 16-bit conversion data
STAGE1 CDC 16-bit conversion data
STAGE2 CDC 16-bit conversion data
STAGE3 CDC 16-bit conversion data
STAGE4 CDC 16-bit conversion data
STAGE5 CDC 16-bit conversion data
STAGE6 CDC 16-bit conversion data
STAGE7 CDC 16-bit conversion data
STAGE8 CDC 16-bit conversion data
STAGE9 CDC 16-bit conversion data
STAGE1ꢀ CDC 16-bit conversion data
STAGE11 CDC 16-bit conversion data
Rev. A | Page 48 of 72
AD7142
Table 31. Device ID Register
Default
Value
Address Data Bit
Type
Name
Description
ꢀxꢀ17
[3:ꢀ]
[15:4]
2
E62
R
REVISION_CODE
DEVID
AD7142 revision code
AD7142 device ID = 111ꢀ ꢀ11ꢀ ꢀꢀ1ꢀ
Table 32. Proximity Status Register
Default
Value
Address Data Bit
Type
Name
Description
ꢀxꢀ42
[ꢀ]
ꢀ
R
STAGEꢀ_PROXIMITY_STATUS
STAGEꢀ proximity status register
1 = indicates proximity has been detected on STAGEꢀ
STAGE1 proximity status register
1 = indicates proximity has been detected on STAGE1
STAGE2 proximity status register
1 = indicates proximity has been detected on STAGE2
STAGE3 proximity status register
1 = indicates proximity has been detected on STAGE3
STAGE4 proximity status register
1 = indicates proximity has been detected on STAGE4
STAGE5 proximity status register
1 = indicates proximity has been detected on STAGE5
STAGE6 proximity status register
1 = indicates proximity has been detected on STAGE6
STAGE7 proximity status register
1 = indicates proximity has been detected on STAGE7
STAGE8 proximity status register
1 = indicates proximity has been detected on STAGE8
STAGE9 proximity status register
1 = indicates proximity has been detected on STAGE9
STAGE1ꢀ proximity status register
1 = indicates proximity has been detected on STAGE1ꢀ
STAGE11 proximity status register
1 = indicates proximity has been detected on STAGE11
Set unused register bits = ꢀ
[1]
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
R
R
R
R
R
R
R
R
R
R
R
STAGE1_PROXIMITY_STATUS
STAGE2_PROXIMITY_STATUS
STAGE3_PROXIMITY_STATUS
STAGE4_PROXIMITY_STATUS
STAGE5_PROXIMITY_STATUS
STAGE6_PROXIMITY_STATUS
STAGE7_PROXIMITY_STATUS
STAGE8_PROXIMITY_STATUS
STAGE9_PROXIMITY_STATUS
STAGE1ꢀ_PROXIMITY_STATUS
STAGE11_PROXIMITY_STATUS
Unused
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[1ꢀ]
[11]
[15:ꢀ]
Rev. A | Page 49 of 72
AD7142
BANK 2 REGISTERS
All address values are expressed in hexadecimal.
Table 33. STAGE0 Configuration Registers
Default
Value
Address Data Bit
Type Name
Description
ꢀxꢀ8ꢀ
ꢀxꢀ81
ꢀxꢀ82
ꢀxꢀ83
ꢀxꢀ84
ꢀxꢀ85
ꢀxꢀ86
ꢀxꢀ87
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGEꢀ_CONNECTION[6:ꢀ]
STAGEꢀ CIN(6:ꢀ) connection setup (see Table 45)
STAGEꢀ CIN(13:7) connection setup (see Table 46)
STAGEꢀ AFE offset control (see Table 47)
STAGEꢀ sensitivity control (see Table 48)
STAGEꢀ initial offset low value
STAGEꢀ_CONNECTION[13:7]
STAGEꢀ_AFE_OFFSET
STAGEꢀ_SENSITIVITY
STAGEꢀ_OFFSET_LOW
STAGEꢀ_OFFSET_HIGH
STAGEꢀ initial offset high value
STAGEꢀ_OFFSET_HIGH_CLAMP STAGEꢀ offset high clamp value
STAGEꢀ_ OFFSET_LOW_CLAMP STAGEꢀ offset low clamp value
Table 34. STAGE1 Configuration Registers
Default
Address Data Bit Value
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Description
ꢀxꢀ88
ꢀxꢀ89
ꢀxꢀ8A
ꢀxꢀ8B
ꢀxꢀ8C
ꢀxꢀ8D
ꢀxꢀ8E
ꢀxꢀ8F
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
STAGE1_CONNECTION[6:ꢀ]
STAGE1_CONNECTION[13:7]
STAGE1_AFE_OFFSET
STAGE1_SENSITIVITY
STAGE1_OFFSET_LOW
STAGE1_OFFSET_HIGH
STAGE1_OFFSET_HIGH_CLAMP
STAGE1_OFFSET_LOW_CLAMP
STAGE1 CIN(6:ꢀ) connection setup (see Table 45)
STAGE1 CIN(13:7) connection setup (see Table 46)
STAGE1 AFE offset control (see Table 47)
STAGE1 sensitivity control (see Table 48)
STAGE1 initial offset low value
STAGE1 initial offset high value
STAGE1 offset high clamp value
STAGE1 offset low clamp value
Table 35. STAGE2 Configuration Registers
Default
Address Data Bit Value
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Description
ꢀxꢀ9ꢀ
ꢀxꢀ91
ꢀxꢀ92
ꢀxꢀ93
ꢀxꢀ94
ꢀxꢀ95
ꢀxꢀ96
ꢀxꢀ97
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
STAGE2_CONNECTION[6:ꢀ]
STAGE2_CONNECTION[13:7]
STAGE2_AFE_OFFSET
STAGE2_SENSITIVITY
STAGE2_OFFSET_LOW
STAGE2_OFFSET_HIGH
STAGE2_OFFSET_HIGH_CLAMP
STAGE2_OFFSET_LOW_CLAMP
STAGE2 CIN(6:ꢀ) connection setup (see Table 45)
STAGE2 CIN(13:7) connection setup (see Table 46)
STAGE2 AFE offset control (see Table 47)
STAGE2 sensitivity control (see Table 48)
STAGE2 initial offset low value
STAGE2 initial offset high value
STAGE2 offset high clamp value
STAGE2 offset low clamp value
Rev. A | Page 5ꢀ of 72
AD7142
Table 36. STAGE3 Configuration Registers
Default
Value
Address Data Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Description
ꢀxꢀ98
ꢀxꢀ99
ꢀxꢀ9A
ꢀxꢀ9B
ꢀxꢀ9C
ꢀxꢀ9D
ꢀxꢀ9E
ꢀxꢀ9F
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
STAGE3_CONNECTION[6:ꢀ]
STAGE3_CONNECTION[13:7]
STAGE3_AFE_OFFSET
STAGE3_SENSITIVITY
STAGE3_OFFSET_LOW
STAGE3_OFFSET_HIGH
STAGE3_OFFSET_HIGH_CLAMP
STAGE3_OFFSET_LOW_CLAMP
STAGE3 CIN(6:ꢀ) connection setup (see Table 45)
STAGE3 CIN(13:7) connection setup (see Table 46)
STAGE3 AFE offset control (see Table 47)
STAGE3 sensitivity control (see Table 48)
STAGE3 initial offset low value
STAGE3 initial offset high value
STAGE3 offset high clamp value
STAGE3 offset low clamp value
Table 37. STAGE4 Configuration Registers
Default
Value
Address Data Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Description
ꢀxꢀAꢀ
ꢀxꢀA1
ꢀxꢀA2
ꢀxꢀA3
ꢀxꢀA4
ꢀxꢀA5
ꢀxꢀA6
ꢀxꢀA7
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
STAGE4_CONNECTION[6:ꢀ]
STAGE4_CONNECTION[13:7]
STAGE4_AFE_OFFSET
STAGE4_SENSITIVITY
STAGE4_OFFSET_LOW
STAGE4_OFFSET_HIGH
STAGE4_OFFSET_HIGH_CLAMP
STAGE4_OFFSET_LOW_CLAMP
STAGE4 CIN(6:ꢀ) connection setup (see Table 45)
STAGE4 CIN(13:7) connection setup (see Table 46)
STAGE4 AFE offset control (see Table 47)
STAGE4 sensitivity control (see Table 48)
STAGE4 initial offset low value
STAGE4 initial offset high value
STAGE4 offset high clamp value
STAGE4 offset low clamp value
Table 38. STAGE5 Configuration Registers
Default
Value
Address Data Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Description
ꢀxꢀA8
ꢀxꢀA9
ꢀxꢀAA
ꢀxꢀAB
ꢀxꢀAC
ꢀxꢀAD
ꢀxꢀAE
ꢀxꢀAF
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
STAGE5_CONNECTION[6:ꢀ]
STAGE5_CONNECTION[13:7]
STAGE5_AFE_OFFSET
STAGE5_SENSITIVITY
STAGE5_OFFSET_LOW
STAGE5_OFFSET_HIGH
STAGE5_OFFSET_HIGH_CLAMP
STAGE5_OFFSET_LOW_CLAMP
STAGE5 CIN(6:ꢀ) connection setup (see Table 45)
STAGE5 CIN(13:7) connection setup (see Table 46)
STAGE5 AFE offset control (see Table 47)
STAGE5 sensitivity control (see Table 48)
STAGE5 initial offset low value
STAGE5 initial offset high value
STAGE5 offset high clamp value
STAGE5 offset low clamp value
Rev. A | Page 51 of 72
AD7142
Table 39. STAGE6 Configuration Registers
Default
Value
Address Data Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Description
ꢀxꢀBꢀ
ꢀxꢀB1
ꢀxꢀB2
ꢀxꢀB3
ꢀxꢀB4
ꢀxꢀB5
ꢀxꢀB6
ꢀxꢀB7
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
STAGE6_CONNECTION[6:ꢀ]
STAGE6_CONNECTION[13:7]
STAGE6_AFE_OFFSET
STAGE6_SENSITIVITY
STAGE6_OFFSET_LOW
STAGE6_OFFSET_HIGH
STAGE6_OFFSET_HIGH_CLAMP
STAGE6_OFFSET_LOW_CLAMP
STAGE6 CIN(6:ꢀ) connection setup (see Table 45)
STAGE6 CIN(13:7) connection setup (see Table 46)
STAGE6 AFE offset control (see Table 47)
STAGE6 sensitivity control (see Table 48)
STAGE6 initial offset low value
STAGE6 initial offset high value
STAGE6 offset high clamp value
STAGE6 offset low clamp value
Table 40. STAGE7 Configuration Registers
Default
Value
Address Data Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Description
ꢀxꢀB8
ꢀxꢀB9
ꢀxꢀBA
ꢀxꢀBB
ꢀxꢀBC
ꢀxꢀBD
ꢀxꢀBE
ꢀxꢀBF
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
STAGE7_CONNECTION[6:ꢀ]
STAGE7_CONNECTION[13:7]
STAGE7_AFE_OFFSET
STAGE7_SENSITIVITY
STAGE7_OFFSET_LOW
STAGE7_OFFSET_HIGH
STAGE7_OFFSET_HIGH_CLAMP
STAGE7_OFFSET_LOW_CLAMP
STAGE7 CIN(6:ꢀ) connection setup (see Table 45)
STAGE7 CIN(13:7) connection setup (see Table 46)
STAGE7 AFE offset control (see Table 47)
STAGE7 sensitivity control (see Table 48)
STAGE7 initial offset low value
STAGE7 initial offset high value
STAGE7 offset high clamp value
STAGE7 offset low clamp value
Table 41. STAGE8 Configuration Registers
Default
Value
Address Data Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Description
ꢀxꢀCꢀ
ꢀxꢀC1
ꢀxꢀC2
ꢀxꢀC3
ꢀxꢀC4
ꢀxꢀC5
ꢀxꢀC6
ꢀxꢀC7
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
STAGE8_CONNECTION[6:ꢀ]
STAGE8_CONNECTION[13:7]
STAGE8_AFE_OFFSET
STAGE8_SENSITIVITY
STAGE8_OFFSET_LOW
STAGE8_OFFSET_HIGH
STAGE8_OFFSET_HIGH_CLAMP
STAGE8_OFFSET_LOW_CLAMP
STAGE8 CIN(6:ꢀ) connection setup (see Table 45)
STAGE8 CIN(13:7) connection setup (see Table 46)
STAGE8 AFE offset control (see Table 47)
STAGE8 sensitivity control (see Table 48)
STAGE8 initial offset low value
STAGE8 initial offset high value
STAGE8 offset high clamp value
STAGE8 offset low clamp value
Rev. A | Page 52 of 72
AD7142
Table 42. STAGE9 Configuration Registers
Default
Value
Address Data Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Description
ꢀxꢀC8
ꢀxꢀC9
ꢀxꢀCA
ꢀxꢀCB
ꢀxꢀCC
ꢀxꢀCD
ꢀxꢀCE
ꢀxꢀCF
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
STAGE9_CONNECTION[6:ꢀ]
STAGE9_CONNECTION[13:7]
STAGE9_AFE_OFFSET
STAGE9_SENSITIVITY
STAGE9_OFFSET_LOW
STAGE9_OFFSET_HIGH
STAGE9_OFFSET_HIGH_CLAMP
STAGE9_OFFSET_LOW_CLAMP
STAGE9 CIN(6:ꢀ) connection setup (see Table 45)
STAGE9 CIN(13:7) connection setup (see Table 46)
STAGE9 AFE offset control (see Table 47)
STAGE9 sensitivity control (see Table 48)
STAGE9 initial offset low value
STAGE9 initial offset high value
STAGE9 offset high clamp value
STAGE9 offset low clamp value
Table 43. STAGE10 Configuration Registers
Default
Value
Address Data Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Description
ꢀxꢀDꢀ
ꢀxꢀD1
ꢀxꢀD2
ꢀxꢀD3
ꢀxꢀD4
ꢀxꢀD5
ꢀxꢀD6
ꢀxꢀD7
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
STAGE1ꢀ_CONNECTION[6:ꢀ]
STAGE1ꢀ_CONNECTION[13:7]
STAGE1ꢀ_AFE_OFFSET
STAGE1ꢀ_SENSITIVITY
STAGE1ꢀ_OFFSET_LOW
STAGE1ꢀ_OFFSET_HIGH
STAGE1ꢀ_OFFSET_HIGH_CLAMP
STAGE1ꢀ_OFFSET_LOW_CLAMP
STAGE1ꢀ CIN(6:ꢀ) connection setup (see Table 45)
STAGE1ꢀ CIN(13:7) connection setup (see Table 46)
STAGE1ꢀ AFE offset control (see Table 47)
STAGE1ꢀ sensitivity control (see Table 48)
STAGE1ꢀ initial offset low value
STAGE1ꢀ initial offset high value
STAGE1ꢀ offset high clamp value
STAGE1ꢀ offset low clamp value
Table 44. STAGE11 Configuration Registers
Default
Value
Address Data Bit
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Name
Description
ꢀxꢀD8
ꢀxꢀD9
ꢀxꢀDA
ꢀxꢀDB
ꢀxꢀDC
ꢀxꢀDD
ꢀxꢀDE
ꢀxꢀDF
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
STAGE11_CONNECTION[6:ꢀ]
STAGE11_CONNECTION[13:7]
STAGE11_AFE_OFFSET
STAGE11_SENSITIVITY
STAGE11_OFFSET_LOW
STAGE11_OFFSET_HIGH
STAGE11_OFFSET_HIGH_CLAMP
STAGE11_OFFSET_LOW_CLAMP
STAGE11 CIN(6:ꢀ) connection setup (see Table 45)
STAGE11 CIN(13:7) connection setup (see Table 46)
STAGE11 AFE offset control (see Table 47)
STAGE11 sensitivity control (see Table 48)
STAGE11 initial offset low value
STAGE11 initial offset high value
STAGE11 offset high clamp value
STAGE11 offset low clamp value
Rev. A | Page 53 of 72
AD7142
Table 45. STAGEX Detailed CIN (0:6) Connection Setup Description (X = 0 to 11)
Default
Value
Data Bit
Type
Name
Description
[1:ꢀ]
X
R/W
CINꢀ_CONNECTION_SETUP
CINꢀ connection setup
ꢀꢀ = CINꢀ not connected to CDC inputs
ꢀ1 = CINꢀ connected to CDC negative input
1ꢀ = CINꢀ connected to CDC positive input
11 = CINꢀ connected to BIAS (connect unused CIN inputs)
CIN1 connection setup
ꢀꢀ = CIN1 not connected to CDC inputs
ꢀ1 = CIN1 connected to CDC negative input
1ꢀ = CIN1 connected to CDC positive input
11 = CIN1 connected to BIAS (connect unused CIN inputs)
CIN2 connection setup
ꢀꢀ = CIN2 not connected to CDC inputs
ꢀ1 = CIN2 connected to CDC negative input
1ꢀ = CIN2 connected to CDC positive input
11 = CIN2 connected to BIAS (connect unused CIN inputs)
CIN3 connection setup
ꢀꢀ = CIN3 not connected to CDC inputs
ꢀ1 = CIN3 connected to CDC negative input
1ꢀ = CIN3 connected to CDC positive input
11 = CIN3 connected to BIAS (connect unused CIN inputs)
CIN4 connection setup
ꢀꢀ = CIN4 not connected to CDC inputs
ꢀ1 = CIN4 connected to CDC negative input
1ꢀ = CIN4 connected to CDC positive input
11 = CIN4 connected to BIAS (connect unused CIN inputs)
CIN5 connection setup
ꢀꢀ = CIN5 not connected to CDC inputs
ꢀ1 = CIN5 connected to CDC negative input
1ꢀ = CIN5 connected to CDC positive input
11 = CIN5 connected to BIAS (connect unused CIN inputs)
CIN6 connection setup
ꢀꢀ = CIN6 not connected to CDC inputs
ꢀ1 = CIN6 connected to CDC negative input
1ꢀ = CIN6 connected to CDC positive input
11 = CIN6 connected to BIAS (connect unused CIN inputs)
Set unused register bits = ꢀ
[3:2]
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
CIN1_CONNECTION_SETUP
CIN2_CONNECTION_SETUP
CIN3_CONNECTION_SETUP
CIN4_CONNECTION_SETUP
CIN5_CONNECTION_SETUP
CIN6_CONNECTION_SETUP
Unused
[5:4]
[7:6]
[9:8]
[11:1ꢀ]
[13:12]
[15:14]
Rev. A | Page 54 of 72
AD7142
Table 46. STAGEX Detailed CIN (7:13) Connection Setup Description (X = 0 to 11)
Data Bit
Default Value
Type Name
Description
[1:ꢀ]
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CIN7_CONNECTION_SETUP
CIN7 connection setup
ꢀꢀ = CIN7 not connected to CDC inputs
ꢀ1 = CIN7 connected to CDC negative input
1ꢀ = CIN7 connected to CDC positive input
11 = CIN7 connected to BIAS (connect unused CIN inputs)
CIN8 connection setup
ꢀꢀ = CIN8 not connected to CDC inputs
ꢀ1 = CIN8 connected to CDC negative input
1ꢀ = CIN8 connected to CDC positive input
11 = CIN8 connected to BIAS (connect unused CIN inputs)
CIN9 connection setup
ꢀꢀ = CIN9 not connected to CDC inputs
ꢀ1 = CIN9 connected to CDC negative input
1ꢀ = CIN9 connected to CDC positive input
11 = CIN9 connected to BIAS (connect unused CIN inputs)
CIN1ꢀ connection setup
ꢀꢀ = CIN1ꢀ not connected to CDC inputs
ꢀ1 = CIN1ꢀ connected to CDC negative input
1ꢀ = CIN1ꢀ connected to CDC positive input
11 = CIN1ꢀ connected to BIAS (connect unused CIN inputs)
CIN11 connection setup
ꢀꢀ = CIN11 not connected to CDC inputs
ꢀ1 = CIN11 connected to CDC negative input
1ꢀ = CIN11 connected to CDC positive input
11 = CIN11 connected to BIAS (connect unused CIN inputs)
CIN12 connection setup
ꢀꢀ = CIN12 not connected to CDC inputs
ꢀ1 = CIN12 connected to CDC negative input
1ꢀ = CIN12 connected to CDC positive input
11 = CIN12 connected to BIAS (connect unused CIN inputs)
CIN13 connection setup
[3:2]
X
X
X
X
X
X
CIN8_CONNECTION_SETUP
CIN9_CONNECTION_SETUP
CIN1ꢀ_CONNECTION_SETUP
CIN11_CONNECTION_SETUP
CIN12_CONNECTION_SETUP
CIN13_CONNECTION_SETUP
[5:4]
[7:6]
[9:8]
[11:1ꢀ]
[13:12]
ꢀꢀ = CIN13 not connected to CDC inputs
ꢀ1 = CIN13 connected to CDC negative input
1ꢀ = CIN13 connected to CDC positive input
11 = CIN13 connected to BIAS (connect unused CIN inputs)
Negative AFE offset enable control
[14]
[15]
X
X
NEG_AFE_OFFSET_DISABLE
POS_AFE_OFFSET_DISABLE
ꢀ = enable
1 = disable
Positive AFE offset enable control
ꢀ = enable
1 = disable
Rev. A | Page 55 of 72
AD7142
Table 47. STAGEX Detailed Offset Control Description (X = 0 to 11)
Default
Value
Data Bit
Type
Name
Description
[6:ꢀ]
X
R/W
NEG_AFE_OFFSET
Negative AFE offset setting (2ꢀ pF range)
1 LSB value = ꢀ.16 pF of offset
[7]
X
R/W
NEG_AFE_OFFSET_SWAP
Negative AFE offset swap control
ꢀ = NEG_AFE_OFFSET applied to CDC negative input
1 = NEG_AFE_OFFSET applied to CDC positive input
Positive AFE offset setting (2ꢀ pF range)
1 LSB value = ꢀ.16 pF of offset
[14:8]
[15]
X
X
R/W
R/W
POS_AFE_OFFSET
POS_AFE_OFFSET_SWAP
Positive AFE offset swap control
ꢀ = POS_AFE_OFFSET applied to CDC positive input
1 = POS_AFE_OFFSET applied to CDC negative input
Table 48. STAGEX Detailed Sensitivity Control Description (X = 0 to 11)
Default
Value
Data Bit
Type
Name
Description
[3:ꢀ]
X
R/W
NEG_THRESHOLD_SENSITIVITY
Negative threshold sensitivity control
ꢀꢀꢀꢀ = 25%, ꢀꢀꢀ1 = 29.73%, ꢀꢀ1ꢀ = 34.4ꢀ%, ꢀꢀ11 = 39.ꢀ8%
ꢀ1ꢀꢀ = 43.79%, ꢀ1ꢀ1 = 48.47%, ꢀ11ꢀ = 53.15%
ꢀ111 = 57.83%, 1ꢀꢀꢀ = 62.51%, 1ꢀꢀ1 = 67.22%
1ꢀ1ꢀ = 71.9ꢀ%, 1ꢀ11 = 76.58%, 11ꢀꢀ = 81.28%
11ꢀ1 = 85.96%, 111ꢀ = 9ꢀ.64%, 1111 = 95.32%
Negative peak detect setting
[6:4]
X
R/W
NEG_PEAK_DETECT
ꢀꢀꢀ = 4ꢀ% level, ꢀꢀ1 = 5ꢀ% level, ꢀ1ꢀ = 6ꢀ% level
ꢀ11 = 7ꢀ% level, 1ꢀꢀ = 8ꢀ% level, 1ꢀ1 = 9ꢀ% level
Set unused register bits = ꢀ
[7]
X
X
R/W
R/W
Unused
[11:8]
POS_THRESHOLD_SENSITIVITY
Positive threshold sensitivity control
ꢀꢀꢀꢀ = 25%, ꢀꢀꢀ1 = 29.73%, ꢀꢀ1ꢀ = 34.4ꢀ%, ꢀꢀ11 = 39.ꢀ8%
ꢀ1ꢀꢀ = 43.79%, ꢀ1ꢀ1 = 48.47%, ꢀ11ꢀ = 53.15%
ꢀ111 = 57.83%, 1ꢀꢀꢀ = 62.51%, 1ꢀꢀ1 = 67.22%
1ꢀ1ꢀ = 71.9ꢀ%, 1ꢀ11 = 76.58%, 11ꢀꢀ = 81.28%
11ꢀ1 = 85.96%, 111ꢀ = 9ꢀ.64%, 1111 = 95.32%
Positive peak detect setting
ꢀꢀꢀ = 4ꢀ% level, ꢀꢀ1 = 5ꢀ% level, ꢀ1ꢀ = 6ꢀ% level
ꢀ11 = 7ꢀ% level, 1ꢀꢀ = 8ꢀ% level, 1ꢀ1 = 9ꢀ% level
Set unused register bits = ꢀ
[14:12]
[15]
X
X
R/W
R/W
POS_PEAK_DETECT
Unused
Rev. A | Page 56 of 72
AD7142
BANK 3 REGISTERS
All address values are expressed in hexadecimal.
Table 49. STAGE0 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
ꢀxꢀEꢀ
[15:ꢀ]
X
R/W
STAGEꢀ_CONV_DATA
STAGEꢀ CDC 16-bit conversion data
(copy of data in STAGEꢀ_CONV_DATA register)
ꢀxꢀE1
ꢀxꢀE2
ꢀxꢀE3
ꢀxꢀE4
ꢀxꢀE5
ꢀxꢀE6
ꢀxꢀE7
ꢀxꢀE8
ꢀxꢀE9
ꢀxꢀEA
ꢀxꢀEB
ꢀxꢀEC
ꢀxꢀED
ꢀxꢀEE
ꢀxꢀEF
ꢀxꢀFꢀ
ꢀxꢀF1
ꢀxꢀF2
ꢀxꢀF3
ꢀxꢀF4
ꢀxꢀF5
ꢀxꢀF6
ꢀxꢀF7
ꢀxꢀF8
ꢀxꢀF9
ꢀxꢀFA
ꢀxꢀFB
ꢀxꢀFC
ꢀxꢀFD
ꢀxꢀFE
ꢀxꢀFF
ꢀx1ꢀꢀ
ꢀx1ꢀ1
ꢀx1ꢀ2
ꢀx1ꢀ3
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGEꢀ_FF_WORDꢀ
STAGEꢀ_FF_WORD1
STAGEꢀ_FF_WORD2
STAGEꢀ_FF_WORD3
STAGEꢀ_FF_WORD4
STAGEꢀ_FF_WORD5
STAGEꢀ_FF_WORD6
STAGEꢀ_FF_WORD7
STAGEꢀ_SF_WORDꢀ
STAGEꢀ_SF_WORD1
STAGEꢀ_SF_WORD2
STAGEꢀ_SF_WORD3
STAGEꢀ_SF_WORD4
STAGEꢀ_SF_WORD5
STAGEꢀ_SF_WORD6
STAGEꢀ_SF_WORD7
STAGEꢀ_SF_AMBIENT
STAGEꢀ_FF_AVG
STAGEꢀ_PEAK_DETECT_WORDꢀ
STAGEꢀ_PEAK_DETECT_WORD1
STAGEꢀ_MAX_WORDꢀ
STAGEꢀ_MAX_WORD1
STAGEꢀ_MAX_WORD2
STAGEꢀ_MAX_WORD3
STAGEꢀ_MAX_AVG
STAGEꢀ_HIGH_THRESHOLD
STAGEꢀ_MAX_TEMP
STAGEꢀ_MIN_WORDꢀ
STAGEꢀ_MIN_WORD1
STAGEꢀ_MIN_WORD2
STAGEꢀ_MIN_WORD3
STAGEꢀ_MIN_AVG
STAGEꢀ fast FIFO WORDꢀ
STAGEꢀ fast FIFO WORD1
STAGEꢀ fast FIFO WORD2
STAGEꢀ fast FIFO WORD3
STAGEꢀ fast FIFO WORD4
STAGEꢀ fast FIFO WORD5
STAGEꢀ fast FIFO WORD6
STAGEꢀ fast FIFO WORD7
STAGEꢀ slow FIFO WORDꢀ
STAGEꢀ slow FIFO WORD1
STAGEꢀ slow FIFO WORD2
STAGEꢀ slow FIFO WORD3
STAGEꢀ slow FIFO WORD4
STAGEꢀ slow FIFO WORD5
STAGEꢀ slow FIFO WORD6
STAGEꢀ slow FIFO WORD7
STAGEꢀ slow FIFO ambient value
STAGEꢀ fast FIFO average value
STAGEꢀ peak FIFO WORDꢀ value
STAGEꢀ peak FIFO WORD1 value
STAGEꢀ maximum value FIFO WORDꢀ
STAGEꢀ maximum value FIFO WORD1
STAGEꢀ maximum value FIFO WORD2
STAGEꢀ maximum value FIFO WORD3
STAGEꢀ average maximum FIFO value
STAGEꢀ high threshold value
STAGEꢀ temporary maximum value
STAGEꢀ minimum value FIFO WORDꢀ
STAGEꢀ minimum value FIFO WORD1
STAGEꢀ minimum value FIFO WORD2
STAGEꢀ minimum value FIFO WORD3
STAGEꢀ average minimum FIFO value
STAGEꢀ low threshold value
STAGEꢀ_LOW_THRESHOLD
STAGEꢀ_MIN_TEMP
Unused
STAGEꢀ temporary minimum value
Set unused register bits = ꢀ
Rev. A | Page 57 of 72
AD7142
Table 50. STAGE1 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
ꢀx1ꢀ4
[15:ꢀ]
X
R/W
STAGE1_CONV_DATA
STAGE1 CDC 16-bit conversion data
(copy of data in STAGE1_CONV_DATA register)
ꢀx1ꢀ5
ꢀx1ꢀ6
ꢀx1ꢀ7
ꢀx1ꢀ8
ꢀx1ꢀ9
ꢀx1ꢀA
ꢀx1ꢀB
ꢀx1ꢀC
ꢀx1ꢀD
ꢀx1ꢀE
ꢀx1ꢀF
ꢀx11ꢀ
ꢀx111
ꢀx112
ꢀx113
ꢀx114
ꢀx115
ꢀx116
ꢀx117
ꢀx118
ꢀx119
ꢀx11A
ꢀx11B
ꢀx11C
ꢀx11D
ꢀx11E
ꢀx11F
ꢀx12ꢀ
ꢀx121
ꢀx122
ꢀx123
ꢀx124
ꢀx125
ꢀx126
ꢀx127
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE1_FF_WORDꢀ
STAGE1_FF_WORD1
STAGE1_FF_WORD2
STAGE1_FF_WORD3
STAGE1_FF_WORD4
STAGE1_FF_WORD5
STAGE1_FF_WORD6
STAGE1_FF_WORD7
STAGE1_SF_WORDꢀ
STAGE1_SF_WORD1
STAGE1_SF_WORD2
STAGE1_SF_WORD3
STAGE1_SF_WORD4
STAGE1_SF_WORD5
STAGE1_SF_WORD6
STAGE1_SF_WORD7
STAGE1_SF_AMBIENT
STAGE1_FF_AVG
STAGE1_CDC_WORDꢀ
STAGE1_CDC_WORD1
STAGE1_MAX_WORDꢀ
STAGE1_MAX_WORD1
STAGE1_MAX_WORD2
STAGE1_MAX_WORD3
STAGE1_MAX_AVG
STAGE1_HIGH_THRESHOLD
STAGE1_MAX_TEMP
STAGE1_MIN_WORDꢀ
STAGE1_MIN_WORD1
STAGE1_MIN_WORD2
STAGE1_MIN_WORD3
STAGE1_MIN_AVG
STAGE1 fast FIFO WORDꢀ
STAGE1 fast FIFO WORD1
STAGE1 fast FIFO WORD2
STAGE1 fast FIFO WORD3
STAGE1 fast FIFO WORD4
STAGE1 fast FIFO WORD5
STAGE1 fast FIFO WORD6
STAGE1 fast FIFO WORD7
STAGE1 slow FIFO WORDꢀ
STAGE1 slow FIFO WORD1
STAGE1 slow FIFO WORD2
STAGE1 slow FIFO WORD3
STAGE1 slow FIFO WORD4
STAGE1 slow FIFO WORD5
STAGE1 slow FIFO WORD6
STAGE1 slow FIFO WORD7
STAGE1 slow FIFO ambient value
STAGE1 fast FIFO average value
STAGE1 CDC FIFO WORDꢀ
STAGE1 CDC FIFO WORD1
STAGE1 maximum value FIFO WORDꢀ
STAGE1 maximum value FIFO WORD1
STAGE1 maximum value FIFO WORD2
STAGE1 maximum value FIFO WORD3
STAGE1 average maximum FIFO value
STAGE1 high threshold value
STAGE1 temporary maximum value
STAGE1 minimum value FIFO WORDꢀ
STAGE1 minimum value FIFO WORD1
STAGE1 minimum value FIFO WORD2
STAGE1 minimum value FIFO WORD3
STAGE1 average minimum FIFO value
STAGE1 low threshold value
STAGE1 temporary minimum value
Set unused register bits = ꢀ
STAGE1_LOW_THRESHOLD
STAGE1_MIN_TEMP
Unused
Rev. A | Page 58 of 72
AD7142
Table 51. STAGE2 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
ꢀx128
[15:ꢀ]
X
R/W
STAGE2_CONV_DATA
STAGE2 CDC 16-bit conversion data
(copy of data in STAGE2_CONV_DATA register)
ꢀx129
ꢀx12A
ꢀx12B
ꢀx12C
ꢀx12D
ꢀx12E
ꢀx12F
ꢀx13ꢀ
ꢀx131
ꢀx132
ꢀx133
ꢀx134
ꢀx135
ꢀx136
ꢀx137
ꢀx138
ꢀx139
ꢀx13A
ꢀx13B
ꢀx13C
ꢀx13D
ꢀx13E
ꢀx13F
ꢀx14ꢀ
ꢀx141
ꢀx142
ꢀx143
ꢀx144
ꢀx145
ꢀx146
ꢀx147
ꢀx148
ꢀx149
ꢀx14A
ꢀx14B
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE2_FF_WORDꢀ
STAGE2_FF_WORD1
STAGE2_FF_WORD2
STAGE2_FF_WORD3
STAGE2_FF_WORD4
STAGE2_FF_WORD5
STAGE2_FF_WORD6
STAGE2_FF_WORD7
STAGE2_SF_WORDꢀ
STAGE2_SF_WORD1
STAGE2_SF_WORD2
STAGE2_SF_WORD3
STAGE2_SF_WORD4
STAGE2_SF_WORD5
STAGE2_SF_WORD6
STAGE2_SF_WORD7
STAGE2_SF_AMBIENT
STAGE2_FF_AVG
STAGE2_CDC_WORDꢀ
STAGE2_CDC_WORD1
STAGE2_MAX_WORDꢀ
STAGE2_MAX_WORD1
STAGE2_MAX_WORD2
STAGE2_MAX_WORD3
STAGE2_MAX_AVG
STAGE2_HIGH_THRESHOLD
STAGE2_MAX_TEMP
STAGE2_MIN_WORDꢀ
STAGE2_MIN_WORD1
STAGE2_MIN_WORD2
STAGE2_MIN_WORD3
STAGE2_MIN_AVG
STAGE2 fast FIFO WORDꢀ
STAGE2 fast FIFO WORD1
STAGE2 fast FIFO WORD2
STAGE2 fast FIFO WORD3
STAGE2 fast FIFO WORD4
STAGE2 fast FIFO WORD5
STAGE2 fast FIFO WORD6
STAGE2 fast FIFO WORD7
STAGE2 slow FIFO WORDꢀ
STAGE2 slow FIFO WORD1
STAGE2 slow FIFO WORD2
STAGE2 slow FIFO WORD3
STAGE2 slow FIFO WORD4
STAGE2 slow FIFO WORD5
STAGE2 slow FIFO WORD6
STAGE2 slow FIFO WORD7
STAGE2 slow FIFO ambient value
STAGE2 fast FIFO average value
STAGE2 CDC FIFO WORDꢀ
STAGE2 CDC FIFO WORD1
STAGE2 maximum value FIFO WORDꢀ
STAGE2 maximum value FIFO WORD1
STAGE2 maximum value FIFO WORD2
STAGE2 maximum value FIFO WORD3
STAGE2 average maximum FIFO value
STAGE2 high threshold value
STAGE2 temporary maximum value
STAGE2 minimum value FIFO WORDꢀ
STAGE2 minimum value FIFO WORD1
STAGE2 minimum value FIFO WORD2
STAGE2 minimum value FIFO WORD3
STAGE2 average minimum FIFO value
STAGE2 low threshold value
STAGE2 temporary minimum value
Set unused register bits = ꢀ
STAGE2_LOW_THRESHOLD
STAGE2_MIN_TEMP
Unused
Rev. A | Page 59 of 72
AD7142
Table 52. STAGE3 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
ꢀx14C
[15:ꢀ]
X
R/W
STAGE3_CONV_DATA
STAGE3 CDC 16-bit conversion data
(copy of data in STAGE3_CONV_DATA register)
ꢀx14D
ꢀx14E
ꢀx14F
ꢀx15ꢀ
ꢀx151
ꢀx152
ꢀx153
ꢀx154
ꢀx155
ꢀx156
ꢀx157
ꢀx158
ꢀx159
ꢀx15A
ꢀx15B
ꢀx15C
ꢀx15D
ꢀx15E
ꢀx15F
ꢀx16ꢀ
ꢀx161
ꢀx162
ꢀx163
ꢀx164
ꢀx165
ꢀx166
ꢀx167
ꢀx168
ꢀx169
ꢀx16A
ꢀx16B
ꢀx16C
ꢀx16D
ꢀx16E
ꢀx16F
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE3_FF_WORDꢀ
STAGE3_FF_WORD1
STAGE3_FF_WORD2
STAGE3_FF_WORD3
STAGE3_FF_WORD4
STAGE3_FF_WORD5
STAGE3_FF_WORD6
STAGE3_FF_WORD7
STAGE3_SF_WORDꢀ
STAGE3_SF_WORD1
STAGE3_SF_WORD2
STAGE3_SF_WORD3
STAGE3_SF_WORD4
STAGE3_SF_WORD5
STAGE3_SF_WORD6
STAGE3_SF_WORD7
STAGE3_SF_AMBIENT
STAGE3_FF_AVG
STAGE3_CDC_WORDꢀ
STAGE3_CDC_WORD1
STAGE3_MAX_WORDꢀ
STAGE3_MAX_WORD1
STAGE3_MAX_WORD2
STAGE3_MAX_WORD3
STAGE3_MAX_AVG
STAGE3_HIGH_THRESHOLD
STAGE3_MAX_TEMP
STAGE3_MIN_WORDꢀ
STAGE3_MIN_WORD1
STAGE3_MIN_WORD2
STAGE3_MIN_WORD3
STAGE3_MIN_AVG
STAGE3 fast FIFO WORDꢀ
STAGE3 fast FIFO WORD1
STAGE3 fast FIFO WORD2
STAGE3 fast FIFO WORD3
STAGE3 fast FIFO WORD4
STAGE3 fast FIFO WORD5
STAGE3 fast FIFO WORD6
STAGE3 fast FIFO WORD7
STAGE3 slow FIFO WORDꢀ
STAGE3 slow FIFO WORD1
STAGE3 slow FIFO WORD2
STAGE3 slow FIFO WORD3
STAGE3 slow FIFO WORD4
STAGE3 slow FIFO WORD5
STAGE3 slow FIFO WORD6
STAGE3 slow FIFO WORD7
STAGE3 slow FIFO ambient value
STAGE3 fast FIFO average value
STAGE3 CDC FIFO WORDꢀ
STAGE3 CDC FIFO WORD1
STAGE3 maximum value FIFO WORDꢀ
STAGE3 maximum value FIFO WORD1
STAGE3 maximum value FIFO WORD2
STAGE3 maximum value FIFO WORD3
STAGE3 average maximum FIFO value
STAGE3 high threshold value
STAGE3 temporary maximum value
STAGE3 minimum value FIFO WORDꢀ
STAGE3 minimum value FIFO WORD1
STAGE3 minimum value FIFO WORD2
STAGE3 minimum value FIFO WORD3
STAGE3 average minimum FIFO value
STAGE3 low threshold value
STAGE3 temporary minimum value
Set unused register bits = ꢀ
STAGE3_LOW_THRESHOLD
STAGE3_MIN_TEMP
Unused
Rev. A | Page 6ꢀ of 72
AD7142
Table 53. STAGE4 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
ꢀx17ꢀ
[15:ꢀ]
X
R/W
STAGE4_CONV_DATA
STAGE4 CDC 16-bit conversion data
(copy of data in STAGE4_CONV_DATA register)
ꢀx171
ꢀx172
ꢀx173
ꢀx174
ꢀx175
ꢀx176
ꢀx177
ꢀx178
ꢀx179
ꢀx17A
ꢀx17B
ꢀx17C
ꢀx17D
ꢀx17E
ꢀx17F
ꢀx18ꢀ
ꢀx181
ꢀx182
ꢀx183
ꢀx184
ꢀx185
ꢀx186
ꢀx187
ꢀx188
ꢀx189
ꢀx18A
ꢀx18B
ꢀx18C
ꢀx18D
ꢀx18E
ꢀx18F
ꢀx19ꢀ
ꢀx191
ꢀx192
ꢀx193
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE4_FF_WORDꢀ
STAGE4_FF_WORD1
STAGE4_FF_WORD2
STAGE4_FF_WORD3
STAGE4_FF_WORD4
STAGE4_FF_WORD5
STAGE4_FF_WORD6
STAGE4_FF_WORD7
STAGE4_SF_WORDꢀ
STAGE4_SF_WORD1
STAGE4_SF_WORD2
STAGE4_SF_WORD3
STAGE4_SF_WORD4
STAGE4_SF_WORD5
STAGE4_SF_WORD6
STAGE4_SF_WORD7
STAGE4_SF_AMBIENT
STAGE4_FF_AVG
STAGE4_CDC_WORDꢀ
STAGE4_CDC_WORD1
STAGE4_MAX_WORDꢀ
STAGE4_MAX_WORD1
STAGE4_MAX_WORD2
STAGE4_MAX_WORD3
STAGE4_MAX_AVG
STAGE4_HIGH_THRESHOLD
STAGE4_MAX_TEMP
STAGE4_MIN_WORDꢀ
STAGE4_MIN_WORD1
STAGE4_MIN_WORD2
STAGE4_MIN_WORD3
STAGE4_MIN_AVG
STAGE4 fast FIFO WORDꢀ
STAGE4 fast FIFO WORD1
STAGE4 fast FIFO WORD2
STAGE4 fast FIFO WORD3
STAGE4 fast FIFO WORD4
STAGE4 fast FIFO WORD5
STAGE4 fast FIFO WORD6
STAGE4 fast FIFO WORD7
STAGE4 slow FIFO WORDꢀ
STAGE4 slow FIFO WORD1
STAGE4 slow FIFO WORD2
STAGE4 slow FIFO WORD3
STAGE4 slow FIFO WORD4
STAGE4 slow FIFO WORD5
STAGE4 slow FIFO WORD6
STAGE4 slow FIFO WORD7
STAGE4 slow FIFO ambient value
STAGE4 fast FIFO average value
STAGE4 CDC FIFO WORDꢀ
STAGE4 CDC FIFO WORD1
STAGE4 maximum value FIFO WORDꢀ
STAGE4 maximum value FIFO WORD1
STAGE4 maximum value FIFO WORD2
STAGE4 maximum value FIFO WORD3
STAGE4 average maximum FIFO value
STAGE4 high threshold value
STAGE4 temporary maximum value
STAGE4 minimum value FIFO WORDꢀ
STAGE4 minimum value FIFO WORD1
STAGE4 minimum value FIFO WORD2
STAGE4 minimum value FIFO WORD3
STAGE4 average minimum FIFO value
STAGE4 low threshold value
STAGE4 temporary minimum value
Set unused register bits = ꢀ
STAGE4_LOW_THRESHOLD
STAGE4_MIN_TEMP
Unused
Rev. A | Page 61 of 72
AD7142
Table 54. STAGE5 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
ꢀx194
[15:ꢀ]
X
R/W
STAGE5_CONV_DATA
STAGE5 CDC 16-bit conversion data
(copy of data in STAGE5_CONV_DATA register)
ꢀx195
ꢀx196
ꢀx197
ꢀx198
ꢀx199
ꢀx19A
ꢀx19B
ꢀx19C
ꢀx19D
ꢀx19E
ꢀx19F
ꢀx1Aꢀ
ꢀx1A1
ꢀx1A2
ꢀx1A3
ꢀx1A4
ꢀx1A5
ꢀx1A6
ꢀx1A7
ꢀx1A8
ꢀx1A9
ꢀx1AA
ꢀx1AB
ꢀx1AC
ꢀx1AD
ꢀx1AE
ꢀx1AF
ꢀx1Bꢀ
ꢀx1B1
ꢀx1B2
ꢀx1B3
ꢀx1B4
ꢀx1B5
ꢀx1B6
ꢀx1B7
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE5_FF_WORDꢀ
STAGE5_FF_WORD1
STAGE5_FF_WORD2
STAGE5_FF_WORD3
STAGE5_FF_WORD4
STAGE5_FF_WORD5
STAGE5_FF_WORD6
STAGE5_FF_WORD7
STAGE5_SF_WORDꢀ
STAGE5_SF_WORD1
STAGE5_SF_WORD2
STAGE5_SF_WORD3
STAGE5_SF_WORD4
STAGE5_SF_WORD5
STAGE5_SF_WORD6
STAGE5_SF_WORD7
STAGE5_SF_AMBIENT
STAGE5_FF_AVG
STAGE5_CDC_WORDꢀ
STAGE5_CDC_WORD1
STAGE5_MAX_WORDꢀ
STAGE5_MAX_WORD1
STAGE5_MAX_WORD2
STAGE5_MAX_WORD3
STAGE5_MAX_AVG
STAGE5_HIGH_THRESHOLD
STAGE5_MAX_TEMP
STAGE5_MIN_WORDꢀ
STAGE5_MIN_WORD1
STAGE5_MIN_WORD2
STAGE5_MIN_WORD3
STAGE5_MIN_AVG
STAGE5 fast FIFO WORDꢀ
STAGE5 fast FIFO WORD1
STAGE5 fast FIFO WORD2
STAGE5 fast FIFO WORD3
STAGE5 fast FIFO WORD4
STAGE5 fast FIFO WORD5
STAGE5 fast FIFO WORD6
STAGE5 fast FIFO WORD7
STAGE5 slow FIFO WORDꢀ
STAGE5 slow FIFO WORD1
STAGE5 slow FIFO WORD2
STAGE5 slow FIFO WORD3
STAGE5 slow FIFO WORD4
STAGE5 slow FIFO WORD5
STAGE5 slow FIFO WORD6
STAGE5 slow FIFO WORD7
STAGE5 slow FIFO ambient value
STAGE5 fast FIFO average value
STAGE5 CDC FIFO WORDꢀ
STAGE5 CDC FIFO WORD1
STAGE5 maximum value FIFO WORDꢀ
STAGE5 maximum value FIFO WORD1
STAGE5 maximum value FIFO WORD2
STAGE5 maximum value FIFO WORD3
STAGE5 average maximum FIFO value
STAGE5 high threshold value
STAGE5 temporary maximum value
STAGE5 minimum value FIFO WORDꢀ
STAGE5 minimum value FIFO WORD1
STAGE5 minimum value FIFO WORD2
STAGE5 minimum value FIFO WORD3
STAGE5 average minimum FIFO value
STAGE5 low threshold value
STAGE5 temporary minimum value
Set unused register bits = ꢀ
STAGE5_LOW_THRESHOLD
STAGE5_MIN_TEMP
Unused
Rev. A | Page 62 of 72
AD7142
Table 55. STAGE6 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
ꢀx1B8
[15:ꢀ]
X
R/W
STAGE6_CONV_DATA
STAGE6 CDC 16-bit conversion data
(copy of data in STAGE6_CONV_DATA register)
ꢀx1B9
ꢀx1BA
ꢀx1BB
ꢀx1BC
ꢀx1BD
ꢀx1BE
ꢀx1BF
ꢀx1Cꢀ
ꢀx1C1
ꢀx1C2
ꢀx1C3
ꢀx1C4
ꢀx1C5
ꢀx1C6
ꢀx1C7
ꢀx1C8
ꢀx1C9
ꢀx1CA
ꢀx1CB
ꢀx1CC
ꢀx1CD
ꢀx1CE
ꢀx1CF
ꢀx1Dꢀ
ꢀx1D1
ꢀx1D2
ꢀx1D3
ꢀx1D4
ꢀx1D5
ꢀx1D6
ꢀx1D7
ꢀx1D8
ꢀx1D9
ꢀx1DA
ꢀx1DB
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE6_FF_WORDꢀ
STAGE6_FF_WORD1
STAGE6_FF_WORD2
STAGE6_FF_WORD3
STAGE6_FF_WORD4
STAGE6_FF_WORD5
STAGE6_FF_WORD6
STAGE6_FF_WORD7
STAGE6_SF_WORDꢀ
STAGE6_SF_WORD1
STAGE6_SF_WORD2
STAGE6_SF_WORD3
STAGE6_SF_WORD4
STAGE6_SF_WORD5
STAGE6_SF_WORD6
STAGE6_SF_WORD7
STAGE6_SF_AMBIENT
STAGE6_FF_AVG
STAGE6_CDC_WORDꢀ
STAGE6_CDC_WORD1
STAGE6_MAX_WORDꢀ
STAGE6_MAX_WORD1
STAGE6_MAX_WORD2
STAGE6_MAX_WORD3
STAGE6_MAX_AVG
STAGE6_HIGH_THRESHOLD
STAGE6_MAX_TEMP
STAGE6_MIN_WORDꢀ
STAGE6_MIN_WORD1
STAGE6_MIN_WORD2
STAGE6_MIN_WORD3
STAGE6_MIN_AVG
STAGE6 fast FIFO WORDꢀ
STAGE6 fast FIFO WORD1
STAGE6 fast FIFO WORD2
STAGE6 fast FIFO WORD3
STAGE6 fast FIFO WORD4
STAGE6 fast FIFO WORD5
STAGE6 fast FIFO WORD6
STAGE6 fast FIFO WORD7
STAGE6 slow FIFO WORDꢀ
STAGE6 slow FIFO WORD1
STAGE6 slow FIFO WORD2
STAGE6 slow FIFO WORD3
STAGE6 slow FIFO WORD4
STAGE6 slow FIFO WORD5
STAGE6 slow FIFO WORD6
STAGE6 slow FIFO WORD7
STAGE6 slow FIFO ambient value
STAGE6 fast FIFO average value
STAGEꢀ CDC FIFO WORDꢀ
STAGE6 CDC FIFO WORD1
STAGE6 maximum value FIFO WORDꢀ
STAGE6 maximum value FIFO WORD1
STAGE6 maximum value FIFO WORD2
STAGE6 maximum value FIFO WORD3
STAGE6 average maximum FIFO value
STAGE6 high threshold value
STAGE6 temporary maximum value
STAGE6 minimum value FIFO WORDꢀ
STAGE6 minimum value FIFO WORD1
STAGE6 minimum value FIFO WORD2
STAGE6 minimum value FIFO WORD3
STAGE6 average minimum FIFO value
STAGE6 low threshold value
STAGE6 temporary minimum value
Set unused register bits = ꢀ
STAGE6_LOW_THRESHOLD
STAGE6_MIN_TEMP
Unused
Rev. A | Page 63 of 72
AD7142
Table 56. STAGE7 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
ꢀx1DC
[15:ꢀ]
X
R/W
STAGE7_CONV_DATA
STAGE7 CDC 16-bit conversion data
(copy of data in STAGE7_CONV_DATA register)
ꢀx1DD
ꢀx1DE
ꢀx1DF
ꢀx1Eꢀ
ꢀx1E1
ꢀx1E2
ꢀx1E3
ꢀx1E4
ꢀx1E5
ꢀx1E6
ꢀx1E7
ꢀx1E8
ꢀx1E9
ꢀx1EA
ꢀx1EB
ꢀx1EC
ꢀx1ED
ꢀx1EE
ꢀx1EF
ꢀx1Fꢀ
ꢀx1F1
ꢀx1F2
ꢀx1F3
ꢀx1F4
ꢀx1F5
ꢀx1F6
ꢀx1F7
ꢀx1F8
ꢀx1F9
ꢀx1FA
ꢀx1FB
ꢀx1FC
ꢀx1FD
ꢀx1FE
ꢀx1FF
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE7_FF_WORDꢀ
STAGE7_FF_WORD1
STAGE7_FF_WORD2
STAGE7_FF_WORD3
STAGE7_FF_WORD4
STAGE7_FF_WORD5
STAGE7_FF_WORD6
STAGE7_FF_WORD7
STAGE7_SF_WORDꢀ
STAGE7_SF_WORD1
STAGE7_SF_WORD2
STAGE7_SF_WORD3
STAGE7_SF_WORD4
STAGE7_SF_WORD5
STAGE7_SF_WORD6
STAGE7_SF_WORD7
STAGE7_SF_AMBIENT
STAGE7_FF_AVG
STAGE7_CDC_WORDꢀ
STAGE7_CDC_WORD1
STAGE7_MAX_WORDꢀ
STAGE7_MAX_WORD1
STAGE7_MAX_WORD2
STAGE7_MAX_WORD3
STAGE7_MAX_AVG
STAGE7_HIGH_THRESHOLD
STAGE7_MAX_TEMP
STAGE7_MIN_WORDꢀ
STAGE7_MIN_WORD1
STAGE7_MIN_WORD2
STAGE7_MIN_WORD3
STAGE7_MIN_AVG
STAGE7 fast FIFO WORDꢀ
STAGE7 fast FIFO WORD1
STAGE7 fast FIFO WORD2
STAGE7 fast FIFO WORD3
STAGE7 fast FIFO WORD4
STAGE7 fast FIFO WORD5
STAGE7 fast FIFO WORD6
STAGE7 fast FIFO WORD7
STAGE7 slow FIFO WORDꢀ
STAGE7 slow FIFO WORD1
STAGE7 slow FIFO WORD2
STAGE7 slow FIFO WORD3
STAGE7 slow FIFO WORD4
STAGE7 slow FIFO WORD5
STAGE7 slow FIFO WORD6
STAGE7 slow FIFO WORD7
STAGE7 slow FIFO ambient value
STAGE7 fast FIFO average value
STAGE7 CDC FIFO WORDꢀ
STAGE7 CDC FIFO WORD1
STAGE7 maximum value FIFO WORDꢀ
STAGE7 maximum value FIFO WORD1
STAGE7 maximum value FIFO WORD2
STAGE7 maximum value FIFO WORD3
STAGE7 average maximum FIFO value
STAGE7 high threshold value
STAGE7 temporary maximum value
STAGE7 minimum value FIFO WORDꢀ
STAGE7 minimum value FIFO WORD1
STAGE7 minimum value FIFO WORD2
STAGE7 minimum value FIFO WORD3
STAGE7 average minimum FIFO value
STAGE7 low threshold value
STAGE7 temporary minimum value
Set unused register bits = ꢀ
STAGE7_LOW_THRESHOLD
STAGE7_MIN_TEMP
Unused
Rev. A | Page 64 of 72
AD7142
Table 57. STAGE8 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
ꢀx2ꢀꢀ
[15:ꢀ]
X
R/W
STAGE8_CONV_DATA
STAGE8 CDC 16-bit conversion data
(copy of data in STAGE8_CONV_DATA register)
ꢀx2ꢀ1
ꢀx2ꢀ2
ꢀx2ꢀ3
ꢀx2ꢀ4
ꢀx2ꢀ5
ꢀx2ꢀ6
ꢀx2ꢀ7
ꢀx2ꢀ8
ꢀx2ꢀ9
ꢀx2ꢀA
ꢀx2ꢀB
ꢀx2ꢀC
ꢀx2ꢀD
ꢀx2ꢀE
ꢀx2ꢀF
ꢀx21ꢀ
ꢀx211
ꢀx212
ꢀx213
ꢀx214
ꢀx215
ꢀx216
ꢀx217
ꢀx218
ꢀx219
ꢀx21A
ꢀx21B
ꢀx21C
ꢀx21D
ꢀx21E
ꢀx21F
ꢀx22ꢀ
ꢀx221
ꢀx222
ꢀx223
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE8_FF_WORDꢀ
STAGE8_FF_WORD1
STAGE8_FF_WORD2
STAGE8_FF_WORD3
STAGE8_FF_WORD4
STAGE8_FF_WORD5
STAGE8_FF_WORD6
STAGE8_FF_WORD7
STAGE8_SF_WORDꢀ
STAGE8_SF_WORD1
STAGE8_SF_WORD2
STAGE8_SF_WORD3
STAGE8_SF_WORD4
STAGE8_SF_WORD5
STAGE8_SF_WORD6
STAGE8_SF_WORD7
STAGE8_SF_AMBIENT
STAGE8_FF_AVG
STAGE8_CDC_WORDꢀ
STAGE8_CDC_WORD1
STAGE8_MAX_WORDꢀ
STAGE8_MAX_WORD1
STAGE8_MAX_WORD2
STAGE8_MAX_WORD3
STAGE8_MAX_AVG
STAGE8_HIGH_THRESHOLD
STAGE8_MAX_TEMP
STAGE8_MIN_WORDꢀ
STAGE8_MIN_WORD1
STAGE8_MIN_WORD2
STAGE8_MIN_WORD3
STAGE8_MIN_AVG
STAGE8 fast FIFO WORDꢀ
STAGE8 fast FIFO WORD1
STAGE8 fast FIFO WORD2
STAGE8 fast FIFO WORD3
STAGE8 fast FIFO WORD4
STAGE8 fast FIFO WORD5
STAGE8 fast FIFO WORD6
STAGE8 fast FIFO WORD7
STAGE8 slow FIFO WORDꢀ
STAGE8 slow FIFO WORD1
STAGE8 slow FIFO WORD2
STAGE8 slow FIFO WORD3
STAGE8 slow FIFO WORD4
STAGE8 slow FIFO WORD5
STAGE8 slow FIFO WORD6
STAGE8 slow FIFO WORD7
STAGE8 slow FIFO ambient value
STAGE8 fast FIFO average value
STAGE8 CDC FIFO WORDꢀ
STAGE8 CDC FIFO WORD1
STAGE8 maximum value FIFO WORDꢀ
STAGE8 maximum value FIFO WORD1
STAGE8 maximum value FIFO WORD2
STAGE8 maximum value FIFO WORD3
STAGE8 average maximum FIFO value
STAGE8 high threshold value
STAGE8 temporary maximum value
STAGE8 minimum value FIFO WORDꢀ
STAGE8 minimum value FIFO WORD1
STAGE8 minimum value FIFO WORD2
STAGE8 minimum value FIFO WORD3
STAGE8 average minimum FIFO value
STAGE8 low threshold value
STAGE7 temporary minimum value
Set unused register bits = ꢀ
STAGE8_LOW_THRESHOLD
STAGE8_MIN_TEMP
Unused
Rev. A | Page 65 of 72
AD7142
Table 58. STAGE9 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
ꢀx224
[15:ꢀ]
X
R/W
STAGE9_CONV_DATA
STAGE9 CDC 16-bit conversion data
(copy of data in STAGE9_CONV_DATA register)
ꢀx225
ꢀx226
ꢀx227
ꢀx228
ꢀx229
ꢀx22A
ꢀx22B
ꢀx22C
ꢀx22D
ꢀx22E
ꢀx22F
ꢀx23ꢀ
ꢀx231
ꢀx232
ꢀx233
ꢀx234
ꢀx235
ꢀx236
ꢀx237
ꢀx238
ꢀx239
ꢀx23A
ꢀx23B
ꢀx23C
ꢀx23D
ꢀx23E
ꢀx23F
ꢀx24ꢀ
ꢀx241
ꢀx242
ꢀx243
ꢀx244
ꢀx245
ꢀx246
ꢀx247
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE9_FF_WORDꢀ
STAGE9_FF_WORD1
STAGE9_FF_WORD2
STAGE9_FF_WORD3
STAGE9_FF_WORD4
STAGE9_FF_WORD5
STAGE9_FF_WORD6
STAGE9_FF_WORD7
STAGE9_SF_WORDꢀ
STAGE9_SF_WORD1
STAGE9_SF_WORD2
STAGE9_SF_WORD3
STAGE9_SF_WORD4
STAGE9_SF_WORD5
STAGE9_SF_WORD6
STAGE9_SF_WORD7
STAGE9_SF_AMBIENT
STAGE9_FF_AVG
STAGE9_CDC_WORDꢀ
STAGE9_CDC_WORD1
STAGE9_MAX_WORDꢀ
STAGE9_MAX_WORD1
STAGE9_MAX_WORD2
STAGE9_MAX_WORD3
STAGE9_MAX_AVG
STAGE9_HIGH_THRESHOLD
STAGE9_MAX_TEMP
STAGE9_MIN_WORDꢀ
STAGE9_MIN_WORD1
STAGE9_MIN_WORD2
STAGE9_MIN_WORD3
STAGE9_MIN_AVG
STAGE9 fast FIFO WORDꢀ
STAGE9 fast FIFO WORD1
STAGE9 fast FIFO WORD2
STAGE9 fast FIFO WORD3
STAGE9 fast FIFO WORD4
STAGE9 fast FIFO WORD5
STAGE9 fast FIFO WORD6
STAGE9 fast FIFO WORD7
STAGE9 slow FIFO WORDꢀ
STAGE9 slow FIFO WORD1
STAGE9 slow FIFO WORD2
STAGE9 slow FIFO WORD3
STAGE9 slow FIFO WORD4
STAGE9 slow FIFO WORD5
STAGE9 slow FIFO WORD6
STAGE9 slow FIFO WORD7
STAGE9 slow FIFO ambient value
STAGE9 fast FIFO average value
STAGE9 CDC FIFO WORDꢀ
STAGE9 CDC FIFO WORD1
STAGE9 maximum value FIFO WORDꢀ
STAGE9 maximum value FIFO WORD1
STAGE9 maximum value FIFO WORD2
STAGE9 maximum value FIFO WORD3
STAGE9 average maximum FIFO value
STAGE9 high threshold value
STAGE9 temporary maximum value
STAGE9 minimum value FIFO WORDꢀ
STAGE9 minimum value FIFO WORD1
STAGE9 minimum value FIFO WORD2
STAGE9 minimum value FIFO WORD3
STAGE9 average minimum FIFO value
STAGE9 low threshold value
STAGE9 temporary minimum value
Set unused register bits = ꢀ
STAGE9_LOW_THRESHOLD
STAGE9_MIN_TEMP
Unused
Rev. A | Page 66 of 72
AD7142
Table 59. STAGE10 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
ꢀx248
[15:ꢀ]
X
R/W
STAGE1ꢀ_CONV_DATA
STAGE1ꢀ CDC 16-bit conversion data
(copy of data in STAGE1ꢀ_CONV_DATA register)
ꢀx249
ꢀx24A
ꢀx24B
ꢀx24C
ꢀx24D
ꢀx24E
ꢀx24F
ꢀx25ꢀ
ꢀx251
ꢀx252
ꢀx253
ꢀx254
ꢀx255
ꢀx256
ꢀx257
ꢀx258
ꢀx259
ꢀx25A
ꢀx25B
ꢀx25C
ꢀx25D
ꢀx25E
ꢀx25F
ꢀx26ꢀ
ꢀx261
ꢀx262
ꢀx263
ꢀx264
ꢀx265
ꢀx266
ꢀx267
ꢀx268
ꢀx269
ꢀx26A
ꢀx26B
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE1ꢀ_FF_WORDꢀ
STAGE1ꢀ_FF_WORD1
STAGE1ꢀ_FF_WORD2
STAGE1ꢀ_FF_WORD3
STAGE1ꢀ_FF_WORD4
STAGE1ꢀ_FF_WORD5
STAGE1ꢀ_FF_WORD6
STAGE1ꢀ_FF_WORD7
STAGE1ꢀ_SF_WORDꢀ
STAGE1ꢀ_SF_WORD1
STAGE1ꢀ_SF_WORD2
STAGE1ꢀ_SF_WORD3
STAGE1ꢀ_SF_WORD4
STAGE1ꢀ_SF_WORD5
STAGE1ꢀ_SF_WORD6
STAGE1ꢀ_SF_WORD7
STAGE1ꢀ_SF_AMBIENT
STAGE1ꢀ_FF_AVG
STAGE1ꢀ_CDC_WORDꢀ
STAGE1ꢀ_CDC_WORD1
STAGE1ꢀ_MAX_WORDꢀ
STAGE1ꢀ_MAX_WORD1
STAGE1ꢀ_MAX_WORD2
STAGE1ꢀ_MAX_WORD3
STAGE1ꢀ_MAX_AVG
STAGE1ꢀ_HIGH_THRESHOLD
STAGE1ꢀ_MAX_TEMP
STAGE1ꢀ_MIN_WORDꢀ
STAGE1ꢀ_MIN_WORD1
STAGE1ꢀ_MIN_WORD2
STAGE1ꢀ_MIN_WORD3
STAGE1ꢀ_MIN_AVG
STAGE1ꢀ fast FIFO WORDꢀ
STAGE1ꢀ fast FIFO WORD1
STAGE1ꢀ fast FIFO WORD2
STAGE1ꢀ fast FIFO WORD3
STAGE1ꢀ fast FIFO WORD4
STAGE1ꢀ fast FIFO WORD5
STAGE1ꢀ fast FIFO WORD6
STAGE1ꢀ fast FIFO WORD7
STAGE1ꢀ slow FIFO WORDꢀ
STAGE1ꢀ slow FIFO WORD1
STAGE1ꢀ slow FIFO WORD2
STAGE1ꢀ slow FIFO WORD3
STAGE1ꢀ slow FIFO WORD4
STAGE1ꢀ slow FIFO WORD5
STAGE1ꢀ slow FIFO WORD6
STAGE1ꢀ slow FIFO WORD7
STAGE1ꢀ slow FIFO ambient value
STAGE1ꢀ fast FIFO average value
STAGE1ꢀ CDC FIFO WORDꢀ
STAGE1ꢀ CDC FIFO WORD1
STAGE1ꢀ maximum value FIFO WORDꢀ
STAGE1ꢀ maximum value FIFO WORD1
STAGE1ꢀ maximum value FIFO WORD2
STAGE1ꢀ maximum value FIFO WORD3
STAGE1ꢀ average maximum FIFO value
STAGE1ꢀ high threshold value
STAGE1ꢀ temporary maximum value
STAGE1ꢀ minimum value FIFO WORDꢀ
STAGE1ꢀ minimum value FIFO WORD1
STAGE1ꢀ minimum value FIFO WORD2
STAGE1ꢀ minimum value FIFO WORD3
STAGE1ꢀ average minimum FIFO value
STAGE1ꢀ low threshold value
STAGE1ꢀ temporary minimum value
Set unused register bits = ꢀ
STAGE1ꢀ_LOW_THRESHOLD
STAGE1ꢀ_MIN_TEMP
Unused
Rev. A | Page 67 of 72
AD7142
Table 60. STAGE11 Results Registers
Default
Value
Address Data Bit
Type
Name
Description
ꢀx26C
[15:ꢀ]
X
R/W
STAGE11_CONV_DATA
STAGE11 CDC 16-bit conversion data
(copy of data in STAGE11_CONV_DATA register)
ꢀx26D
ꢀx26E
ꢀx26F
ꢀx27ꢀ
ꢀx271
ꢀx272
ꢀx273
ꢀx274
ꢀx275
ꢀx276
ꢀx277
ꢀx278
ꢀx279
ꢀx27A
ꢀx27B
ꢀx27C
ꢀx27D
ꢀx27E
ꢀx27F
ꢀx28ꢀ
ꢀx281
ꢀx282
ꢀx283
ꢀx284
ꢀx285
ꢀx286
ꢀx287
ꢀx288
ꢀx289
ꢀx28A
ꢀx28B
ꢀx28C
ꢀx28D
ꢀx28E
ꢀx28F
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
[15:ꢀ]
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STAGE11_FF_WORDꢀ
STAGE11_FF_WORD1
STAGE11_FF_WORD2
STAGE11_FF_WORD3
STAGE11_FF_WORD4
STAGE11_FF_WORD5
STAGE11_FF_WORD6
STAGE11_FF_WORD7
STAGE11_SF_WORDꢀ
STAGE11_SF_WORD1
STAGE11_SF_WORD2
STAGE11_SF_WORD3
STAGE11_SF_WORD4
STAGE11_SF_WORD5
STAGE11_SF_WORD6
STAGE11_SF_WORD7
STAGE11_SF_AMBIENT
STAGE11_FF_AVG
STAGE11_CDC_WORDꢀ
STAGE11_CDC_WORD1
STAGE11_MAX_WORDꢀ
STAGE11_MAX_WORD1
STAGE11_MAX_WORD2
STAGE11_MAX_WORD3
STAGE11_MAX_AVG
STAGE11_HIGH_THRESHOLD
STAGE11_MAX_TEMP
STAGE11_MIN_WORDꢀ
STAGE11_MIN_WORD1
STAGE11_MIN_WORD2
STAGE11_MIN_WORD3
STAGE11_MIN_AVG
STAGE11 fast FIFO WORDꢀ
STAGE11 fast FIFO WORD1
STAGE11 fast FIFO WORD2
STAGE11 fast FIFO WORD3
STAGE11 fast FIFO WORD4
STAGE11 fast FIFO WORD5
STAGE11 fast FIFO WORD6
STAGE11 fast FIFO WORD7
STAGE11 slow FIFO WORDꢀ
STAGE11 slow FIFO WORD1
STAGE11 slow FIFO WORD2
STAGE11 slow FIFO WORD3
STAGE11 slow FIFO WORD4
STAGE11 slow FIFO WORD5
STAGE11 slow FIFO WORD6
STAGE11 slow FIFO WORD7
STAGE11 slow FIFO ambient value
STAGE11 fast FIFO average value
STAGE11 CDC FIFO WORDꢀ
STAGE11 CDC FIFO WORD1
STAGE11 maximum value FIFO WORDꢀ
STAGE11 maximum value FIFO WORD1
STAGE11 maximum value FIFO WORD2
STAGE11 maximum value FIFO WORD3
STAGE11 average maximum FIFO value
STAGE11 high threshold value
STAGE11 temporary maximum value
STAGE11 minimum value FIFO WORDꢀ
STAGE11 minimum value FIFO WORD1
STAGE11 minimum value FIFO WORD2
STAGE11 minimum value FIFO WORD3
STAGE11 average minimum FIFO value
STAGE11 low threshold value
STAGE11 temporary minimum value
Set unused register bits = ꢀ
STAGE11_LOW_THRESHOLD
STAGE11_MIN_TEMP
Unused
Rev. A | Page 68 of 72
AD7142
OUTLINE DIMENSIONS
5.00
BSC SQ
0.60 MAX
0.60 MAX
PIN 1
INDICATOR
25
24
32
1
PIN 1
INDICATOR
0.50
BSC
TOP
VIEW
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
4.75
BSC SQ
0.50
0.40
0.30
17
16
8
9
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
0.05 MAX
0.02 NOM
1.00
0.85
0.80
0.30
0.23
0.18
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 60. 32-Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature Range
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
–4ꢀ°C to +85°C
Serial Interface Description
SPI Interface
Package Description
32-Lead LFCSP_VQ
32-Lead LFCSP_VQ
32-Lead LFCSP_VQ
32-Lead LFCSP_VQ
Evaluation Board
Package Option
CP-32-2
CP-32-2
CP-32-2
CP-32-2
AD7142ACPZ-REEL1
AD7142ACPZ-5ꢀꢀRL71
AD7142ACPZ-1REEL1
AD7142ACPZ-15ꢀꢀRL71
EVAL-AD7142EBZ1
EVAL-AD7142-1EBZ1
SPI Interface
I2C Interface
I2C Interface
SPI Interface
I2C Interface
Evaluation Board
1 Z = Pb-free part.
Rev. A | Page 69 of 72
AD7142
NOTES
Rev. A | Page 7ꢀ of 72
AD7142
NOTES
Rev. A | Page 71 of 72
AD7142
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05702-0-1/07(A)
Rev. A | Page 72 of 72
相关型号：
AD7147A-1ACBZ500R7
CapTouch® Programmable Controller for Single-Electrode Capacitance Sensors
ADI
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