AD7224TQ [ADI]
LC2MOS 8-Bit DAC with Output Amplifiers; LC2MOS 8位DAC，输出放大器
| 型号： | AD7224TQ |
| 厂家： | 
ADI |
| 描述： | LC2MOS 8-Bit DAC with Output Amplifiers |
| 文件： | 总8页 (文件大小：231K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2
LC MOS
a
8-Bit DAC with Output Amplifiers
AD7224
FEATURES
FUNCTIO NAL BLO CK D IAGRAM
8-Bit CMOS DAC w ith Output Am plifiers
Operates w ith Single or Dual Supplies
Low Total Unadjusted Error:
Less Than 1 LSB Over Tem perature
Extended Tem perature Range Operation
P-Com patible w ith Double Buffered Inputs
Standard 18-Pin DIPs, and 20-Term inal Surface
Mount Package and SOIC Package
GENERAL D ESCRIP TIO N
P RO D UCT H IGH LIGH TS
T he AD7224 is a precision 8-bit voltage-output, digital-to-
analog converter, with output amplifier and double buffered
interface logic on a monolithic CMOS chip. No external trims
are required to achieve full specified performance for the part.
1. DAC and Amplifier on CMOS Chip
T he single-chip design of the 8-bit DAC and output amplifier
is inherently more reliable than multi-chip designs. CMOS
fabrication means low power consumption (35 mW typical
with single supply).
T he double buffered interface logic consists of two 8-bit regis-
ters–an input register and a DAC register. Only the data held in
the DAC registers determines the analog output of the con-
verter. T he double buffering allows simultaneous update in a
system containing multiple AD7224s. Both registers may be
made transparent under control of three external lines, CS, WR
and LDAC. With both registers transparent, the RESET line
functions like a zero override; a useful function for system cali-
bration cycles. All logic inputs are T T L and CMOS (5 V) level
compatible and the control logic is speed compatible with most
8-bit microprocessors.
2. Low T otal Unadjusted Error
T he fabrication of the AD7224 on Analog Devices Linear
Compatible CMOS (LC2MOS) process coupled with a novel
DAC switch-pair arrangement, enables an excellent total un-
adjusted error of less than 1 LSB over the full operating tem-
perature range.
3. Single or Dual Supply Operation
T he voltage-mode configuration of the AD7224 allows opera-
tion from a single power supply rail. T he part can also be op-
erated with dual supplies giving enhanced performance for
some parameters.
Specified performance is guaranteed for input reference voltages
from +2 V to +12.5 V when using dual supplies. T he part is also
specified for single supply operation using a reference of +10 V.
T he output amplifier is capable of developing +10 V across a
2 kΩ load.
4. Versatile Interface Logic
T he high speed logic allows direct interfacing to most micro-
processors. Additionally, the double buffered interface en-
ables simultaneous update of the AD7224 in multiple DAC
systems. T he part also features a zero override function.
T he AD7224 is fabricated in an all ion-implanted high speed
Linear Compatible CMOS (LC2MOS) process which has been
specifically developed to allow high speed digital logic circuits
and precision analog circuits to be integrated on the same chip.
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD7224–SPECIFICATIONS
(V = 11.4 V to 16.5 V, V = –5 V ؎ 10%; AGND = DGND = O V; V = +2 V to (V – 4 V)1 unless otherwise noted.
DD
SS
REF
DD
DUAL SUPPLY
All specifications TMIN to TMAX unless otherwise noted.)
K, B, T
L, C, U
P aram eter
Versions2
Versions2
Units
Conditions/Com m ents
ST AT IC PERFORMANCE
Resolution
8
8
Bits
T otal Unadjusted Error
Relative Accuracy
Differential Nonlinearity
Full-Scale Error
Full-Scale T emperature Coefficient
Zero Code Error
Zero Code Error T emperature Coefficient
±2
±1
±1
±3/2
±20
±30
±50
±1
±1/2
±1
LSB max
LSB max
LSB max
LSB max
ppm/°C max
mV max
VDD = +15 V ± 5%, VREF = +10 V
Guaranteed Monotonic
±1
±20
±20
±30
VDD = 14 V to 16.5 V, VREF = +10 V
µV/°C typ
REFERENCE INPUT
Voltage Range
2 to (VDD – 4)
8
100
2 to (VDD – 4)
8
100
V min to V max
kΩ min
pF max
Input Resistance
Input Capacitance3
Occurs when DAC is loaded with all 1s.
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current
Input Capacitance3
Input Coding
2.4
0.8
±1
2.4
0.8
±1
V min
V max
µA max
pF max
VIN = 0 V or VDD
8
8
Binary
Binary
DYNAMIC PERFORMANCE
Voltage Output Slew Rate3
Voltage Output Settling T ime3
Positive Full-Scale Change
Negative Full-Scale Change
Digital Feedthrough
2.5
2.5
V/µs min
5
7
50
2
5
7
50
2
µs max
µs max
nV secs typ
kΩ min
VREF = +10 V; Settling T ime to ±1/2 LSB
VREF = +10 V; Settling T ime to ±1/2 LSB
VREF = 0 V
Minimum Load Resistance
VOUT = +10 V
POWER SUPPLIES
VDD Range
VSS Range
IDD
11.4/16.5
4.5/5.5
11.4/16.5
4.5/5.5
V min/V max
V min/V max
For Specified Performance
For Specified Performance
@ 25°C
T MIN to T MAX
4
6
4
6
mA max
mA max
Outputs Unloaded; VIN = VINL or VINH
Outputs Unloaded; VIN = VINL or VINH
ISS
@ 25°C
T MIN to T MAX
3
5
3
5
mA max
mA max
Outputs Unloaded; VIN = VINL or VINH
Outputs Unloaded; VIN = VINL or VINH
SWIT CHING CHARACT ERIST ICS3, 4
t1
@ 25°C
T MIN to T MAX
t2
@ 25°C
T MIN to T MAX
t3
90
90
90
90
ns min
ns min
Chip Select/Load DAC Pulse Width
Write/Reset Pulse Width
90
90
90
90
ns min
ns min
@ 25°C
T MIN to T MAX
t4
@ 25°C
T MIN to T MAX
t5
@ 25°C
T MIN to T MAX
t6
0
0
0
0
ns min
ns min
Chip Select/Load DAC to Write Setup T ime
Chip Select/Load DAC to Write Hold T ime
Data Valid to Write Setup T ime
0
0
0
0
ns min
ns min
90
90
90
90
ns min
ns min
@ 25°C
T MIN to T MAX
10
10
10
10
ns min
ns min
Data Valid to Write Hold T ime
NOT ES
1Maximum possible reference voltage.
2T emperature ranges are as follows:
K, L Versions: –40°C to +85°C
B, C Versions: –40°C to +85°C
T , U Versions: –55°C to +125°C
3Sample T ested at 25°C by Product Assurance to ensure compliance.
4Switching characteristics apply for single and dual supply operation.
Specifications subject to change without notice.
–2–
REV. B
AD7224
1
(V = +15 V ؎ 5%; V = AGND = DGND = O V; V = +10 V unless otherwise noted.
DD
SS
REF
SINGLE SUPPLY
All specifications TMIN to TMAX unless otherwise noted.)
K, B, T
L, C, U
P aram eter
Versions2
Versions2
Units
Conditions/Com m ents
ST AT IC PERFORMANCE
Resolution
8
8
Bits
T otal Unadjusted Error
Differential Nonlinearity
±2
±1
±2
±1
LSB max
LSB max
Guaranteed Monotonic
REFERENCE INPUT
Input Resistance
8
100
8
100
kΩ min
pF max
Input Capacitance3
Occurs when DAC is loaded with all 1s.
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Leakage Current
Input Capacitance3
Input Coding
2.4
0.8
±1
2.4
0.8
±1
V min
V max
µA max
pF max
VIN = 0 V or VDD
8
8
Binary
Binary
DYNAMIC PERFORMANCE
Voltage Output Slew Rate4
Voltage Output Settling T ime4
Positive Full-Scale Change
Negative Full-Scale Change
Digital Feedthrough3
2
2
V/µs min
5
5
µs max
µs max
nV secs typ
kΩ min
Settling T ime to ±1/2 LSB
Settling T ime to ±1/2 LSB
VREF = 0 V
20
50
2
20
50
2
Minimum Load Resistance
VOUT = +10 V
POWER SUPPLIES
VDD Range
IDD
14.25/15.75
14.25/15.75
V min/V max
For Specified Performance
@ 25°C
T MIN to T MAX
4
6
4
6
mA max
mA max
Outputs Unloaded; VIN = VINL or VINH
Outputs Unloaded; VIN = VINL or VINH
SWIT CHING CHARACT ERIST ICS3, 4
t1
@ 25°C
T MIN to T MAX
t2
@ 25°C
T MIN to T MAX
t3
90
90
90
90
ns min
ns min
Chip Select/Load DAC Pulse Width
Write/Reset Pulse Width
90
90
90
90
ns min
ns min
@ 25°C
T MIN to T MAX
t4
@ 25°C
T MIN to T MAX
t5
@ 25°C
T MIN to T MAX
t6
0
0
0
0
ns min
ns min
Chip Select/Load DAC to Write Setup T ime
Chip Select/Load DAC to Write Hold T ime
Data Valid to Write Setup T ime
0
0
0
0
ns min
ns min
90
90
90
90
ns min
ns min
@ 25°C
T MIN to T MAX
10
10
10
10
ns min
ns min
Data Valid to Write Hold T ime
NOT ES
1Maximum possible reference voltage.
2T emperature ranges are as follows:
AD7224KN, LN: 0°C to +70°C
AD7224BQ, CQ: –25°C to +85°C
AD7224T D, UD: –55°C to +125°C
3See T erminology.
4Sample tested at 25°C by Product Assurance to ensure compliance.
Specifications subject to change without notice.
–3–
REV. B
AD7224
ABSO LUTE MAXIMUM RATINGS1
O RD ERING GUID E
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +24 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD
Digital Input Voltage to DGND . . . . . . . –0.3 V, VDD + 0.3 V
VREF to AGND . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V
VOUT to AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW
Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C
Operating T emperature
Commercial (K, L Versions) . . . . . . . . . . . –40°C to +85°C
Industrial (B, C Versions) . . . . . . . . . . . . . –40°C to +85°C
Extended (T , U Versions) . . . . . . . . . . . . –55°C to +125°C
Storage T emperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
Total
Unadjusted
Error (LSB) O ption2
Tem perature
Range
P ackage
Model1
AD7224KN
AD7224LN
AD7224KP
AD7224LP
AD7224KR-1
AD7224LR-1
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
±2 max
±1 max
±2 max
±1 max
±2 max
±1 max
±2 max
±1 max
±2 max
±1 max
N-18
N-18
P-20A
P-20A
R-20
R-20
R-18
R-18
Q-18
Q-18
Q-18
Q-18
E-20A
E-20A
AD7224KR-18 –40°C to +85°C
AD7224LR-18 –40°C to +85°C
AD7224BQ
AD7224CQ
AD7224T Q
AD7224UQ
AD7224T E
AD7224UE
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C ±2 max
–55°C to +125°C ±1 max
–55°C to +125°C ±2 max
–55°C to +125°C ±1 max
NOT ES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2T he outputs may be shorted to AGND provided that the power dissipation of the
package is not exceeded. T ypically short circuit current to AGND is 60 mA.
NOT ES
1T o order MIL-ST D-883 processed parts, add /883B to part number.
Contact your local sales office for military data sheet.
2E = Leadless Ceramic Chip Carrier; N = Plastic DIP;
P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7224 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
P IN CO NFIGURATIO NS
D IP and SO IC
(SO IC)
(SO IC)
V
1
2
3
4
5
6
7
8
9
18
V
V
1
2
3
4
5
6
7
8
9
18
V
DD
1
2
3
20
SS
DD
SS
V
V
DD
SS
V
OUT
17 RESET
16 LDAC
15 WR
V
17 RESET
16 LDAC
15 WR
19 RESET
OUT
V
OUT
V
V
REF
REF
V
REF
18 LDAC
17 WR
AD7224
AGND
DGND
(MSB) DB7
DB6
AGND
DGND
(MSB) DB7
DB6
AD7224
AGND
4
5
6
R-18
AD7224
TOP VIEW
(Not to Scale)
R-20
14 CS
14 CS
TOP VIEW
(Not to Scale)
DGND
(MSB) DB7
DB6
16 CS
TOP VIEW
(Not to Scale)
13 DB0 (LSB)
12 DB1
13 DB0 (LSB)
12 DB1
15 DB0 (LSB)
14 DB1
7
8
DB5
11 DB2
DB5
11 DB2
DB5
DB4
13 DB2
12 DB3
11 NC
DB4
10 DB3
DB4
10 DB3
9
NC 10
LCCC
P LCC
NC = NO CONNECT
3
2
20 19
3
2
1
20 19
1
V
4
5
6
7
8
18 LDAC
REF
4
V
18
17
16
LDAC
WR
REF
AGND
DGND
17 WR
AGND 5
AD7224
TOP VIEW
(Not to Scale)
AD7224
TOP VIEW
(Not to Scale)
16 CS
CS
6
7
8
DGND
(MSB) DB7
DB6
15
14
DB0 (LSB)
DB1
(MSB) DB7
DB6
15 DB0 (LSB)
14 DB1
9
10
12 13
11
9
10 11 12 13
NC = NO CONNECT
NC = NO CONNECT
–4–
REV. B
AD7224
VOUT = D • VREF
TERMINO LO GY
TO TAL UNAD JUSTED ERRO R
where D is a fractional representation of the digital input code
T otal Unadjusted Error is a comprehensive specification which
includes full-scale error, relative accuracy and zero code error.
Maximum output voltage is VREF – 1 LSB (ideal), where 1 LSB
(ideal) is VREF/256. T he LSB size will vary over the VREF range.
Hence the zero code error, relative to the LSB size, will increase
as VREF decreases. Accordingly, the total unadjusted error,
which includes the zero code error, will also vary in terms of
LSBs over the VREF range. As a result, total unadjusted error is
specified for a fixed reference voltage of +10 V.
and can vary from 0 to 255/256.
O P -AMP SECTIO N
T he voltage-mode D/A converter output is buffered by a unity
gain noninverting CMOS amplifier. T his buffer amplifier is
capable of developing +10 V across a 2 kΩ load and can drive
capacitive loads of 3300 pF.
T he AD7224 can be operated single or dual supply resulting in
different performance in some parameters from the output am-
plifier. In single supply operation (VSS = 0 V = AGND) the sink
capability of the amplifier, which is normally 400 µA, is reduced
as the output voltage nears AGND. T he full sink capability of
400 µA is maintained over the full output voltage range by tying
VSS to –5 V. T his is indicated in Figure 2.
RELATIVE ACCURACY
Relative Accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after al-
lowing for zero code error and full-scale error and is normally
expressed in LSBs or as a percentage of full-scale reading.
500
D IFFERENTIAL NO NLINEARITY
V
= –5V
SS
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB max over
the operating temperature range ensures monotonicity.
400
300
200
100
0
V
T
= +15V
= 25°C
DD
V
= 0V
SS
A
D IGITAL FEED TH RO UGH
Digital Feedthrough is the glitch impulse transferred to the out-
put due to a change in the digital input code. It is specified in
nV secs and is measured at VREF = 0 V.
4
6
8
10
0
2
FULL-SCALE ERRO R
Full-Scale Error is defined as:
V
– Volts
OUT
Measured Value – Zero Code Error – Ideal Value
Figure 2. Variation of ISINK with VOUT
Settling-time for negative-going output signals approaching
AGND is similarly affected by VSS. Negative-going settling-time
for single supply operation is longer than for dual supply opera-
tion. Positive-going settling-time is not affected by VSS.
CIRCUIT INFO RMATIO N
D /A SECTIO N
T he AD7224 contains an 8-bit voltage-mode digital-to-analog
converter. T he output voltage from the converter has the same
polarity as the reference voltage, allowing single supply opera-
tion. A novel DAC switch pair arrangement on the AD7224 al-
lows a reference voltage range from +2 V to +12.5 V.
Additionally, the negative VSS gives more headroom to the out-
put amplifier which results in better zero code performance and
improved slew-rate at the output, than can be obtained in the
single supply mode.
T he DAC consists of a highly stable, thin-film, R-2R ladder and
eight high speed NMOS single pole, double-throw switches.
T he simplified circuit diagram for this DAC is shown in
Figure 1.
D IGITAL SECTIO N
T he AD7224 digital inputs are compatible with either T T L or
5 V CMOS levels. All logic inputs are static-protected MOS
gates with typical input currents of less than 1 nA. Internal in-
put protection is achieved by an on-chip distributed diode be-
tween DGND and each MOS gate. T o minimize power supply
currents, it is recommended that the digital input voltages be
driven as close to the supply rails (VDD and DGND) as practi-
cally possible.
R
R
R
VOUT
2R
2R
DB0
2R
DB0
2R
DB0
2R
DB0
VREF
SHOWN FOR ALL 1's ON DAC
AGND
INTERFACE LO GIC INFO RMATIO N
Figure 1. D/A Sim plified Circuit Diagram
T able I shows the truth table for AD7224 operation. T he part
contains two registers, an input register and a DAC register. CS
and WR control the loading of the input register while LDAC
and WR control the transfer of information from the input regis-
ter to the DAC register. Only the data held in the DAC register
will determine the analog output of the converter.
T he input impedance at the VREF pin is code dependent and can
vary from 8 kΩ minimum to infinity. T he lowest input imped-
ance occurs when the DAC is loaded with the digital code
01010101. T herefore, it is important that the reference presents
a low output impedance under changing load conditions. T he
nodal capacitance at the reference terminals is also code depen-
dent and typically varies from 25 pF to 50 pF.
All control signals are level-triggered and therefore either or
both registers may be made transparent; the input register by
keeping CS and WR “LOW”, the DAC register by keeping
LDAC and WR “LOW”. Input data is latched on the rising
edge of WR.
T he VOUT pin can be considered as a digitally programmable
voltage source with an output voltage of:
–5–
REV. B
AD7224
Table I. AD 7224 Truth Table
a +2.5 V bandgap reference and the AD584, a precision +10 V
reference. Note that in order to achieve an output voltage range
of 0 V to +10 V, a nominal +15 V ± 5% power supply voltage is
required by the AD7224.
RESET LDAC WR CS Function
H
H
H
H
H
H
H
L
L
L
H
X
L
g
L
g
X
L
Both Registers are T ransparent
Both Registers are Latched
Both Registers are Latched
Input Register T ransparent
Input Register Latched
DAC Register T ransparent
DAC Register Latched
Both Registers Loaded
X
H
H
H
L
X
H
L
GRO UND MANAGEMENT
AC or transient voltages between AGND and DGND can cause
noise at the analog output. T his is especially true in micropro-
cessor systems where digital noise is prevalent. T he simplest
method of ensuring that voltages at AGND and DGND are
equal is to tie AGND and DGND together at the AD7224. In
more complex systems where the AGND and DGND intertie is
on the backplane, it is recommended that two diodes be con-
nected in inverse parallel between the AD7224 AGND and
DGND pins (IN914 or equivalent).
L
H
H
X
L
X
With All Zeros
g
g
H
L
H
L
H
L
Both Register Latched With All Zeros
and Output Remains at Zero
Both Registers are T ransparent and
Output Follows Input Data
H = High State, L = Low State, X = Don’t Care.
All control inputs are level triggered.
Applying the AD7224
T he contents of both registers are reset by a low level on the
RESET line. With both registers transparent, the RESET line
functions like a zero override with the output brought to 0 V for
the duration of the RESET pulse. If both registers are latched, a
“LOW” pulse on RESET will latch all 0s into the registers and
the output remains at 0 V after the RESET line has returned
“HIGH”. T he RESET line can be used to ensure power-up to
0 V on the AD7224 output and is also useful, when used as a
zero override, in system calibration cycles. Figure 3 shows the
input control logic for the AD7224.
UNIP O LAR O UTP UT O P ERATIO N
T his is the basic mode of operation for the AD7224, with the
output voltage having the same positive polarity as VREF. T he
AD7224 can be operated single supply (VSS = AGND) or with
positive/negative supplies (see op-amp section which outlines
the advantages of having negative VSS). Connections for the uni-
polar output operation are shown in Figure 5. T he voltage at
VREF must never be negative with respect to DGND. Failure to
observe this precaution may cause parasitic transistor action and
possible device destruction. T he code table for unipolar output
operation is shown in T able II.
LDAC
DAC
REGISTER
V
V
DD
WR
REF
3
INPUT
REGISTER
DB7
CS
DATA
RESET
(8-BIT)
INPUT DATA
DB0
CS
V
DAC
OUT
Figure 3. Input Control Logic
WR
t
LDAC
RESET
1
AD7224
CS
t
t
4
3
t
t
2
2
WR
AGND
DGND
V
SS
t
t
4
3
t
1
LDAC
t
6
t
5
Figure 5. Unipolar Output Circuit
DATA
IN
DATA
VALID
Table III. Unipolar Code Table
NOTES:
1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF V
.
DD
D AC Register Contents
t
= t = 20ns OVER V
RANGE
DD
r
f
V
+ V
2
INH
INL
MSB
LSB
Analog O utput
2. TIMING MEASUREMENT REFERENCE LEVEL IS
255
+VREF
Figure 4. Write Cycle Tim ing Diagram
1 1 1 1
1 1 1 1
256
129
+VREF
SP ECIFICATIO N RANGES
1 0 0 0
0 0 0 1
256
For the DAC to maintain specified accuracy, the reference volt-
age must be at least 4 V below the VDD power supply voltage.
T his voltage differential is required for correct generation of bias
voltages for the DAC switches.
128
256
VREF
2
+VREF
+VREF
+VREF
= +
1 0 0 0
0 1 1 1
0 0 0 0
1 1 1 1
127
256
With dual supply operation, the AD7224 has an extended VDD
range from +12 V ± 5% to +15 V ± 10% (i.e., from +11.4 V to
+16.5 V). Operation is also specified for a single VDD power
supply of +15 V ± 5%.
1
256
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 0
0 V
Performance is specified over a wide range of reference voltages
from 2 V to (VDD – 4 V) with dual supplies. T his allows a range
of standard reference generators to be used such as the AD580,
1
256
Note: 1 LSB = V
2−8 = V
(
)
(
)
REF
REF
–6–
REV. B
AD7224
BIP O LAR O UTP UT O P ERATIO N
V
IN
V
V
REF
DD
T he AD7224 can be configured to provide bipolar output op-
eration using one external amplifier and two resistors. Figure 6
shows a circuit used to implement offset binary coding. In this
case
V
OUT
AGND
DAC
V
IN
R2
R1
R2
R1
VO = 1 +
With R1 = R2
• D V
(
–
• V
(
REF
)
)
REF
V
AD7224
BIAS
V
DGND
SS
VO = (2 D – 1) • VREF
where D is a fractional representation of the digital word in
the DAC register.
Figure 7. AGND Bias Circuit
Mismatch between R1 and R2 causes gain and offset errors;
therefore, these resistors must match and track over tempera-
ture. Once again, the AD7224 can be operated in single supply
or from positive/negative supplies. T able III shows the digital
code versus output voltage relationship for the circuit of Figure
6 with R1 = R2.
MICRO P RO CESSO R INTERFACE
A15
ADDRESS BUS
A8
CS
ADDRESS
8085A
DECODE
8088
LDAC
AD7224*
WR
WR
V
REF
LATCH
V
V
REF
DB7
DB0
DD
R1
EN
R2
ALE
3
DB7
AD7
+15V
ADDRESS DATA BUS
DATA
(8-BIT)
AD0
*LINEAR CIRCUITRY OMITTED FOR CLARITY
V
DB0
CS
OUT
DAC
V
Figure 8. AD7224 to 8085A/8088 Interface
OUT
+15V
WR
LDAC
RESET
A15
AD7224
R1, R2 = 10kΩ ±0.1%
ADDRESS BUS
A0
AGND
DGND
6809
6502
V
SS
CS
ADDRESS
DECODE
LDAC
EN
R/W
AD7224*
Figure 6. Bipolar Output Circuit
E OR φ2
WR
Table III. Bipolar (O ffset Binary) Code Table
D AC Register Contents
DB7
DB0
D7
D0
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
MSB
LSB
1 1 1 1
0 0 0 1
0 0 0 0
1 1 1 1
0 0 0 1
0 0 0 0
Analog O utput
127
+VREF
1 1 1 1
1 0 0 0
1 0 0 0
0 1 1 1
0 0 0 0
0 0 0 0
Figure 9. AD7224 to 6809/6502 Interface
128
1
+VREF
A15
128
ADDRESS BUS
A0
0 V
CS
Z-80
ADDRESS
DECODE
LDAC
1
–VREF
AD7224*
WR
128
WR
127
–VREF
DB7
DB0
128
D7
D0
DATA BUS
128
128
–VREF
= –VREF
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 10. AD7224 to Z-80 Interface
AGND BIAS
T he AD7224 AGND pin can be biased above system GND
(AD7224 DGND) to provide an offset “zero” analog output
voltage level. Figure 7 shows a circuit configuration to achieve
this. T he output voltage, VOUT , is expressed as:
A23
ADDRESS BUS
A1
68008
CS
ADDRESS
DECODE
LDAC
WR
VOUT = VBIAS + D • (VIN)
R/W
DTACK
AD7224*
DB7
where D is a fractional representation of the digital word in
DAC register and can vary from 0 to 255/256.
DB0
D7
D0
For a given VIN, increasing AGND above system GND will re-
duce the effective VDD–VREF which must be at least 4 V to en-
sure specified operation. Note that VDD and VSS for the AD7224
must be referenced to DGND.
DATA BUS
*LINEAR CIRCUITRY OMITTED FOR CLARITY
Figure 11. AD7224 to 68008 Interface
–7–
REV. B
AD7224
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
18-P in P lastic (Suffix N)
18-P in Cer dip (Suffix Q )
18-P in Cer am ic (Suffix D )
18-Lead SO IC
(R-18)
18
10
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
PIN 1
1
9
0.1043 (2.65)
0.4625 (11.75)
0.4469 (11.35)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
x 45
°
P LCC P ackage
P -20A
0.0500 (1.27)
0.0157 (0.40)
8
0
°
°
0.0118 (0.30)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0125 (0.32)
0.0091 (0.23)
0.0040 (0.10)
0.180 (4.57)
0.165 (4.19)
0.048 (1.21)
0.042 (1.07)
0.056 (1.42)
0.042 (1.07)
0.025 (0.63)
0.015 (0.38)
20-Lead SO IC
(R-20)
0.048 (1.21)
0.042 (1.07)
3
19
18
0.021 (0.53)
0.013 (0.33)
PIN 1
4
IDENTIFIER
0.330 (8.38)
0.290 (7.37)
0.032 (0.81)
0.050
(1.27)
BSC
TOP VIEW
0.026 (0.66)
20
11
14
8
9
13
0.2992 (7.60)
0.2914 (7.40)
0.020
(0.50)
R
0.040 (1.01)
0.025 (0.64)
0.356 (9.04)
SQ
0.350 (8.89)
0.110 (2.79)
0.085 (2.16)
0.4193 (10.65)
0.3937 (10.00)
0.395 (10.02)
0.385 (9.78)
SQ
1
10
PIN 1
LCCC P ackage
E-20A
0.1043 (2.65)
0.5118 (13.00)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
0.4961 (12.60)
x 45
°
0.200 (5.08)
BSC
0.100
0.075
(1.91)
REF
0.100 (2.54)
0.064 (1.63)
0.015 (0.38)
MIN
(2.54)
BSC
0.0500 (1.27)
0.0157 (0.40)
8
0
°
°
0.0118 (0.30)
0.0040 (0.10)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0125 (0.32)
0.0091 (0.23)
0.095 (2.41)
0.028 (0.71)
0.358 (9.09)
0.342 (8.69)
0.075 (1.90)
20
0.022 (0.56)
1
SQ
0.358
(9.09)
MAX
SQ
0.011 (0.28)
0.007 (0.18)
R TYP
BOTTOM
VIEW
0.050
(1.27)
BSC
0.075
(1.91)
REF
13
9
45
TYP
°
0.150
(3.81)
BSC
0.055 (1.40)
0.045 (1.14)
0.088 (2.24)
0.054 (1.37)
–8–
REV. B
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