AD7225BRS_技术文档

LC²MOS Quad 8-Bit DAC

with Separate Reference Inputs

AD7225

FEATURES

FUNCTIONAL BLOCK DIAGRAM

V

A V

REF

B V

REF

C V

REF

D

V

DD

REF

Four 8-bit DACs with output amplifiers

Separate reference input for each DAC

Microprocessor compatible with double-buffered inputs

Simultaneous update of all 4 outputs

Operates with single or dual supplies

Extended temperature range operation

No user trims required

INPUT

DAC

DAC A

DAC B

DAC C

DAC D

A

V

A

B

C

D

OUT

LATCH A

INPUT

LATCH B

DAC

LATCH B

B

C

D

DB7

DATA

(8-BIT)

INPUT

LATCH C

DAC

LATCH C

DB0

Skinny 24-lead PDIP, CERDIP, SOIC, and SSOP packages

28-lead PLCC package

INPUT

LATCH D

DAC

LATCH D

WR

A1

A2

AD7225

CONTROL

LOGIC

LDAC

V

AGND DGND

SS

Figure 1.

GENERAL DESCRIPTION

PRODUCT HIGHLIGHTS

The AD7225 contains four 8-bit voltage output digital-to-

analog converters, with output buffer amplifiers and interface

logic on a single monolithic chip. Each DAC has a separate

reference input terminal. No external trims are required to

achieve full specified performance for the part.

1. DACs and Amplifiers on CMOS Chip.

The single-chip design of four 8-bit DACs and amplifiers

allows a dramatic reduction in board space requirements

and offers increased reliability in systems using multiple

converters. Its pinout is aimed at optimizing board layout

with all analog inputs and outputs at one end of the

package and all digital inputs at the other.

The double-buffered interface logic consists of two 8-bit

registers per channel—an input register and a DAC register.

Control Input A0 and Control Input A1 determine which input

2. Single- or Dual-Supply Operation.

WR

The voltage-mode configuration of the AD7225 allows

single-supply operation. The part can also be operated with

dual supplies, giving enhanced performance for some

parameters.

register is loaded when

goes low. Only the data held in the

DAC registers determines the analog outputs of the converters.

The double-buffering allows simultaneous update of all four

LDAC

outputs under control of

. All logic inputs are TTL and

CMOS (5 V) level compatible, and the control logic is speed

compatible with most 8-bit microprocessors.

3. Versatile Interface Logic.

The AD7225 has a common 8-bit data bus with individual

DAC latches, providing a versatile control architecture for

simple interface to microprocessors. The double-buffered

interface allows simultaneous update of the four outputs.

Specified performance is guaranteed for input reference

voltages from 2 V to 12.5 V when using dual supplies. The part

is also specified for single-supply operation using a reference of

10 V. Each output buffer amplifier is capable of developing 10 V

across a 2 kΩ load.

4. Separate Reference Input for Each DAC.

The AD7225 offers great flexibility in dealing with input

signals, with a separate reference input provided for each

DAC and each reference having variable input voltage

capability.

The AD7225 is fabricated on an all ion-implanted, high speed,

linear-compatible CMOS (LC²MOS) process, which is

specifically developed to integrate high speed digital logic

circuits and precision analog circuitry on the same chip.

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD7225

TABLE OF CONTENTS

Features .............................................................................................. 1

Digital Inputs Section ...................................................................9

Interface Logic Information.......................................................... 10

Ground Management and Layout................................................ 11

Specification Ranges ...................................................................... 12

Unipolar Output Operation.......................................................... 13

Bipolar Output Operation............................................................. 14

AGND Bias...................................................................................... 15

AC Reference Signal....................................................................... 16

Applications Information.............................................................. 17

Programmable Transversal Filter............................................. 17

Digital Word Multiplication ..................................................... 18

Microprocesser Interface............................................................... 19

V_SSGeneration ................................................................................ 20

Outline Dimensions....................................................................... 21

Ordering Guide .......................................................................... 23

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Single Supply ................................................................................. 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ........................... 6

Typical Performance Characteristics ............................................. 7

Terminology ...................................................................................... 8

Circuit Information.......................................................................... 9

Digital-to-Analog Section........................................................... 9

Op Amp Section ........................................................................... 9

REVISION HISTORY

3/10—Rev. B to Rev. C

Updated Format..................................................................Universal

Deleted 28-Terminal Leadless Ceramic Chip Carrier

Package.................................................................................Universal

Added 24-Lead SSOP Package..........................................Universal

Changes to Features Section............................................................ 1

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 4

Changes to Table 3............................................................................ 5

Changes to Pin Configurations and Function Descriptions

Section................................................................................................ 6

Added Table 4; Renumbered Sequentially .................................... 6

Changes to Specification Ranges section .................................... 12

Changes to Programmable Transversal Filter Section and

Figure 21 .......................................................................................... 17

Updated Outline Dimensions....................................................... 21

Changes to Ordering Guide .......................................................... 23

Rev. C | Page 2 of 24

AD7225

SPECIFICATIONS

V_DD= 11.4 V to 16.5 V, V_SS= −5 V 10%; AGND = DGND = 0 V; V_REFx = +2 V to (V_DD− 4 V)¹, unless otherwise noted. All specifications

_MINto T_MAX, unless otherwise noted.

T

Table 1.

K, B

L, C

Parameter

Versions²

Unit

Conditions/Comments

STATIC PERFORMANCE

Resolution

8

Bits

Total Unadjusted Error

Relative Accuracy

Differential Nonlinearity

Full-Scale Error

Full-Scale Temperature Coefficient

Zero Code Error

±2

±±

±5

±30

±±

±±/2

±±

±±/2

±5

±20

±30

LSB max

ppm/°C typ

mV max

μV/°C typ

V_DD= ±5 V ± 5%, V_REF= ±0 V

Guaranteed monotonic

V_DD= ±4 V to ±6.5 V, V_REF= ±0 V

Zero Code Error Temperature Coefficient ±30

REFERENCE INPUT

Voltage Range

Input Resistance

Input Capacitance³

Channel-to-Channel Isolation³

AC Feedthrough³

DIGITAL INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Leakage Current

Input Capacitance³

Input Coding

2 to (V_DD− 4) 2 to (V_DD− 4)

V min to V max

kΩ min

pF max

dB min

dB max

±±

50

Occurs when each DAC is loaded with all ±s

V_REF= ±0 V p-p sine wave at ±0 kHz

60

−70

2.4

0.8

±±

2.4

0.8

±±

V min

V max

μA max

pF max

V_IN= 0 V or V_DD

8

Binary

DYNAMIC PERFORMANCE

Voltage Output Slew Rate³

Voltage Output Settling Time³

Digital Feedthrough³

Digital Crosstalk³

Minimum Load Resistance

POWER SUPPLIES

V_DDRange

2.5

4

50

2

2.5

4

50

2

V/μs min

μs max

nV sec typ

kΩ min

V_REF= ±0 V; settling time to ±½ LSB

Code transition all 0s to all ±s

V_OUT= ±0 V

±±.4/±6.5

V min to V max For specified performance

I_DD

I_SS

±0

9

±0

9

mA max

Outputs unloaded; V_IN= V_INLor V_INH

SWITCHING CHARACTERISTICS^{3, 4}

t_±

t₂

t₃

t₄

t₅

t₆

50

0

50

0

50

0

50

0

50

ns min

Write pulse width

Address to write setup time

Address to write hold time

Data valid to write setup time

Data valid to write hold time

Load DAC pulse width

^±Maximum possible reference voltage.

²Temperature range is as follows for all versions: −40°C to +85°C.

³Sample tested at 25°C to ensure compliance.

⁴Switching characteristics apply for single-supply and dual-supply operation.

Rev. C | Page 3 of 24

AD7225

SINGLE SUPPLY

V_DD= 15 V 5%; V_SS= AGND = DGND = 0 V; V_REFx = 10 V, unless otherwise noted. All specifications T_MINto T_MAX

,

unless otherwise noted.

Table 2.

Parameter

K, B Versions¹

L, C Versions¹

Unit

Conditions/Comments

STATIC PERFORMANCE

Resolution

8

Bits

Total Unadjusted Error²

Differential Nonlinearity²

REFERENCE INPUT

Voltage Range

Input Resistance

Input Capacitance³

±2

±±

LSB max

Guaranteed monotonic

2 to (V_DD− 4)

±±

50

2 to (V_DD− 4)

±±

50

60

V min to V max

kΩ min

pF max

dB min

dB max

Occurs when each DAC is loaded with all ±s

V_REF= ±0 V p-p sine wave at ±0 kHz

Channel-to-Channel Isolation^{2, 3}60

AC Feedthrough^{2, 3}

−70

DIGITAL INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Leakage Current

Input Capacitance³

2.4

0.8

±±

2.4

0.8

±±

V min

V max

μA max

pF max

V_IN= 0 V or V_DD

8

Input Coding

Binary

DYNAMIC PERFORMANCE

Voltage Output Slew Rate³

2

4

±0

2

4

±0

2

V/μs min

μs max

nV sec typ

kΩ min

Voltage Output Settling Time³

Digital Feedthrough^{2, 3}

Digital Crosstalk^{2, 3}

Minimum Load Resistance

Code transition all 0s to all ±s

V_OUT= ±0 V

POWER SUPPLIES

V_DDRange

I_DD

±4.25/±5.75

±0

±4.25/±5.75

±0

V min to V max

mA max

For specified performance

Outputs unloaded; V_IN= V_INLor V_INH

SWITCHING CHARACTERISTICS³

t_±

t₂

t₃

t₄

t₅

t₆

50

0

50

0

50

0

50

0

50

ns min

Write pulse width

Address to write setup time

Address to write hold time

Data valid to write setup time

Data valid to write hold time

Load DAC pulse width

^±Temperature range is as follows for all versions: −40°C to +85°C.

²Sample tested at 25°C to ensure compliance.

³Switching characteristics apply for single-supply and dual-supply operation.

Rev. C | Page 4 of 24

AD7225

ABSOLUTE MAXIMUM RATINGS

Table 3.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Parameter

Rating

V_DDto AGND

V_DDto DGND

V_DDto V_SS

AGND to DGND

−0.3 V, +±7 V

−0.3 V, +24 V

−0.3 V, V_DD

Digital Input Voltage to DGND

V_REFx to AGND

V_OUTx to AGND^±

−0.3 V, V_DD+ 0.3 V

V_SS, V_DD

ESD CAUTION

Power Dissipation (Any Package) to 75°C

Derates Above 75°C by

Operating Temperature

Commercial (K, L Versions)

Industrial (B, C Versions)

Storage Temperature

Lead Temperature (Soldering, ±0 sec)

500 mW

2.0 mW/°C

−40°C to +85°C

−65°C to +±50°C

300°C

^±Outputs can be shorted to any voltage in the range V_SSto V_DDprovided that

the power dissipation of the package is not exceeded. Typical short-circuit

current for a short to AGND or V_SSis 50 mA.

Rev. C | Page 5 of 24

AD7225

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

4

3

2

1

28 27 26

V

B

A

1

2

3

4

5

6

7

8

9

24

23

22

21

V

C

D

OUT

DD

OUT

PIN 1

INDENTFIER

5

6

25

24

23

22

21

20

V

B

A

V

C

D

REF

V

SS

REF

V

B

A

C

D

REF

7

AGND

NC

A0

AD7225 20

TOP VIEW

AD7225

TOP VIEW

8

NC

A1

AGND

DGND

LDAC

DB7

19 A0

(Not to Scale)

DGND

LDAC

9

18 A1

10

WR

17 WR

16 DB0

15 DB1

14 DB2

13 DB3

DB7 11

19 DB0

DB6 10

DB5 11

DB4 12

12 13 14 15 16 17 18

NC = NO CONNECT

Figure 2. PDIP, SOIC, CERDIP, and SSOP

Figure 3. PLCC

Table 4. Pin Function Descriptions

Pin No.

PDIP, SOIC,

CERDIP, SSOP

PLCC

Mnemonic

Description

±

2

3

2

3

4

V_OUT

V_SS

B

A

DAC Channel B Voltage Output.

DAC Channel A Voltage Output.

Negative Power Supply Connection.

4

5

6

7

5

6

7

9

V_REF

B

A

Reference Voltage Connection for DAC Channel B.

Reference Voltage Connection for DAC Channel A.

Analog Ground Reference Connection.

Digital Ground Reference Connection.

Active Low Load DAC Signal. DAC register data is latched on the rising edge of LDAC.

AGND

DGND

LDAC

DB7

DB6

DB5

DB4

DB3

DB2

DB±

DB0

WR

8

±0

9

±±

±2

±3

±4

±6

±7

±8

±9

Data Bit 7 (Most Significant Data Bit).

Data Bit 6.

Data Bit 5.

Data Bit 4.

Data Bit 3.

Data Bit 2.

Data Bit ±.

Data Bit 0 (Least Significant Data Bit).

Active Low Data Write Signal. Input register data is latched on the rising edge of WR.

DAC Address Select Pin.

±0

±±

±2

±3

±4

±5

±6

±7

±8

±9

20

2±

22

23

24

N/A

20

2±

23

24

25

26

27

28

A±

A0

DAC Address Select Pin.

V_REF

V_DD

V_OUT

NC

D

C

Reference Voltage Connection for DAC Channel D.

Reference Voltage Connection for DAC Channel C.

Positive Power Supply Connection.

DAC Channel D Voltage Output.

DAC Channel C Voltage Output.

No Internal Connection.

D

C

±, 8, ±5, 22

Rev. C | Page 6 of 24

AD7225

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, V_DD= 15 V, V_SS= −5 V, unless otherwise noted.

1.0

8

7

V

x = 10V

REF

6

I

DD

5

0.5

0

4

3

2

1

0

–1

–2

–3

–4

–5

–6

–7

I

–0.5

–1.0

SS

0

32

64

96

128

160

192

224

–60 –40 –20

0

20

40

60

80

100 120 140

INPUT CODE

TEMPERATURE (°C)

Figure 4. Channel-to-Channel Matching

Figure 7. Power Supply Current vs. Temperature

5

4

1.0

0.5

0

V

A

OUT

3

2

1

0

–1

–2

–3

–4

–5

V

D

OUT

V

C

OUT

–0.5

V

B

OUT

V

1

= 5V

V

= 12V

V = 15V

DD

–1.0

–60 –40 –20

0

20

40

60

80

100 120 140

TEMPERATURE (°C)

0

2

3

4

5

6

7

8

9

10 11 12 13

V

(V)

REF

Figure 5. Relative Accuracy vs. V_REF

Figure 8. Zero Code Error vs. Temperature

0.50

0.25

0

100

90

300µV

–0.25

–0.50

V

= 5V

V

= 12V

V

= 15V

DD

10

0%

0

1

2

3

4

5

6

7

8

9

10 11 12 13

1ms/DIV

V

(V)

REF

Figure 6. Differential Nonlinearity vs. V_REF

Figure 9. Broadband Noise

Rev. C | Page 7 of 24

AD7225

TERMINOLOGY

Digital Feedthrough

Total Unadjusted Error

Digital feedthrough is the glitch impulse transferred to the

output of the DAC due to a change in its digital input code. It is

specified in nV sec and is measured at V_REF= 0 V.

Total unadjusted error is a comprehensive specification that

includes full-scale error, relative accuracy, and zero code error.

Maximum output voltage is V_REF− 1 LSB (ideal), where 1 LSB

(ideal) is V_REF/256. The LSB size varies over the V_REFrange.

Therefore, the zero code error, relative to the LSB size, increases

as V_REFdecreases. Accordingly, the total unadjusted error, which

includes the zero code error, also varies in terms of LSB over the

Digital Crosstalk

Digital crosstalk is the glitch impulse transferred to the output

of one converter (not addressed) due to a change in the digital

input code to another addressed converter. It is specified in nV

sec and is measured at V_REF= 0 V.

V_REFrange. As a result, total unadjusted error is specified for a

fixed reference voltage of 10 V.

AC Feedthrough

Relative Accuracy

AC feedthrough is the proportion of reference input signal that

appears at the output of a converter when that DAC is loaded

with all 0s.

Relative accuracy or endpoint nonlinearity is a measure of the

maximum deviation from a straight line passing through the

endpoints of the DAC transfer function. It is measured after

allowing for zero code error and full-scale error and is normally

expressed in LSB or as a percentage of full-scale reading.

Channel-to-Channel Isolation

Channel-to-channel isolation is the proportion of input signal

from the reference of one DAC (loaded with all 1s) that appears

at the output of one of the other three DACs (loaded with all 0s)

The figure given is the worst case for the three other outputs

and is expressed as a ratio in dB.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured

change and the ideal 1 LSB change between any two adjacent

codes. A specified differential nonlinearity of 1 LSB maximum

over the operating temperature range ensures monotonicity.

Full-Scale Error

Full-scale error is defined as

FSE = Measured Value − Zero Code Error − Ideal Value

Rev. C | Page 8 of 24

AD7225

CIRCUIT INFORMATION

parameters that cannot be achieved with single-supply opera-

tion. In single-supply operation (V_SS= 0 V = AGND), the sink

capability of the amplifier, which is normally 400 μA, is reduced

as the output voltage nears AGND. The full sink capability of

400 μA is maintained over the full output voltage range by tying

V_SSto −5 V. This is shown in Figure 11.

DIGITAL-TO-ANALOG SECTION

The AD7225 contains four identical, 8-bit voltage mode digital-

to-analog converters. Each DAC has a separate reference input.

The output voltages from the converters have the same polarity

as the reference voltages, allowing single-supply operation. A novel

DAC switch pair arrangement on the AD7225 allows a refer-

ence voltage range from 2 V to 12.5 V on each reference input.

Settling time for negative-going output signals approaching

AGND is similarly affected by V_SS. Negative-going settling time

for single-supply operation is longer than for dual-supply opera-

tion. Positive-going settling time is not affected by V_SS.

500

Each DAC consists of a highly stable, thin-film, R-2R ladder and

eight high speed NMOS, single-pole, double-throw switches. The

simplified circuit diagram for Channel A is shown in Figure 10.

Note that AGND is common to all four DACs.

V

T

= +15V

DD

= 25°C

V

= –5V

SS

A

400

300

200

100

0

V A

OUT

R

2R 2R

DB0

2R

V

= 0V

SS

DB5

DB6

DB7

V

A

REF

AGND

SHOWN FOR ALL 1s ON DAC

Figure 10. Digital-to-Analog Simplified Circuit Diagram

The input impedance at any of the reference inputs is code

dependent and can vary from 11 kΩ minimum to infinity. The

lowest input impedance at any reference input occurs when that

DAC is loaded with Digital Code 01010101. Therefore, it is

important that the reference presents a low output impedance

under changing load conditions. The nodal capacitance at the

reference terminals is also code dependent and typically varies

from 15 pF to 35 pF.

0

2

4

6

8

10

V

(V)

OUT

Figure 11. Variation of I_SINKwith V_OUT

Additionally, the negative V_SSgives more headroom to the

output amplifiers, which results in better zero code perfor-

mance and improved slew rate at the output than can be

obtained in the single-supply mode.

Each V_OUTx pin can be considered a digitally programmable

voltage source with an output voltage of

DIGITAL INPUTS SECTION

V

_OUTX= D_X× V_REFX

The AD7225 digital inputs are compatible with either TTL or

5 V CMOS levels. All logic inputs are static protected MOS

gates with typical input currents of less than 1 nA. Internal

input protection is achieved by an on-chip distributed diode

between DGND and each MOS gate. To minimize power supply

currents, it is recommended that the digital input voltages be

driven as close to the supply rails (V_DDand DGND) as practi-

cally possible.

where D_Xis a fractional representation of the digital input code

and can vary from 0 to 255/256.

The output impedance is that of the output buffer amplifier.

OP AMP SECTION

Each voltage mode DAC output is buffered by a unity gain

noninverting CMOS amplifier. This buffer amplifier is capable

of developing 10 V across a 2 kΩ load and can drive capacitive

loads of 3300 pF.

The AD7225 can be operated single or dual supply; operating

with dual supplies results in enhanced performance in some

Rev. C | Page 9 of 24

AD7225

INTERFACE LOGIC INFORMATION

TO ALL

LDAC

A0

DAC LATCHES

The AD7225 contains two registers per DAC, an input register

and a DAC register. The A0 and A1 address lines select which

TO INPUT

LATCH A

WR

input register accepts data from the input port. When the

TO INPUT

LATCH B

signal is low, the input latches of the selected DAC are transpa-

rent. The data is latched into the addressed input register on the

A1

TO INPUT

LATCH C

WR

rising edge of

. Table 5 shows the addressing for the input

registers on the AD7225.

TO INPUT

LATCH D

WR

Table 5. AD7225 Addressing

Figure 12. Input Control Logic

A1

A0

Selected Input Register

Low

High

Low

High

Low

High

DAC A

DAC B

DAC C

DAC D

5V

0V

V

INH

INL

ADDRESS

t₂

t₃

t₁

5V

Only the data held in the DAC register determines the analog

LDAC

WR

output of the converter. The

signal is common to all four

t₆

DACs and controls the transfer of information from the input

registers to the DAC registers. Data is latched into all four DAC

t₅

LDAC

t₄

5V

0V

LDAC

registers simultaneously on the rising edge of

signal is level triggered and therefore the DAC registers can be

LDAC

. The

DATA

VALID

DATA IN

NOTES

made transparent by tying

of the converters respond to the data held in their respective

LDAC

low (in this case, the outputs

1. ALL INPUT SIGNAL RISE AND FALL TIMES MEASURED FROM

10% TO 90% OF 5V.

t_R

= t_F= 20ns OVER V RANGE.

DD

2. TIMING MEASUREMENT REFERENCE LEVEL IS

input latches).

is an asynchronous signal and is indepen-

. This is useful in many applications. However, in

LDAC

V

+ V

2

INH

INL

WR

dent of

systems where the asynchronous

write cycle (or vice versa), care must be taken to ensure that

LDAC

3. IF LDAC IS ACTIVATED PRIOR TO THE RISING EDGE OF WR,

THEN IT MUST STAY LOW FORt₆OR LONGER AFTER WR

GOES HIGH.

can occur during a

incorrect data is not latched through to the output. If

is

occurs during

WR

Figure 13. Write Cycle Timing Diagram

WR WR

(or

must stay low for t₆or longer after

activated prior to the rising edge of

LDAC LDAC

),

goes high

to ensure correct data is latched through to the output. Table 6

shows the truth table for AD7225 operation. Figure 12 shows

the input control logic for the part; the write cycle timing

diagram is given in Figure 13.

Table 6. Truth Table

WR

LDAC Function

High High

Low High

High

No operation. Device not selected.

Input register of selected DAC transparent.

Input register of selected DAC latched.

High Low

All four DAC registers Transparent (that is,

outputs respond to data held in respective

input registers). Input registers are latched.

High

All four DAC registers latched.

Low Low

DAC registers and selected input register

transparent output follows input data for

selected channel.

Rev. C | Page ±0 of 24

AD7225

GROUND MANAGEMENT AND LAYOUT

Because the AD7225 contains four reference inputs that can be

driven from ac sources (see the AC Reference Signal section),

careful layout and grounding is important to minimize analog

crosstalk between the four channels. The dynamic performance

of the four DACs depends on the optimum choice of board

layout. Figure 14 shows the relationship between input fre-

quency and channel-to-channel isolation. Figure 15 shows a

printed circuit board layout that minimizes crosstalk and

feedthrough. The four input signals are screened by AGND.

SYSTEM

GND

PIN 1

V

B

A

V

C

D

OUT

DD

OUT

V

SS

V

B

A

C

D

REF

AGND

DGND

V

_REFwas limited to between 2 V and 3.24 V to avoid slew rate

limiting effects from the output amplifier during measurements.

MSB

LSB

V

= +15V

= –5V

= 25°C

DD

SS

–80

–70

–60

–50

–40

–30

T

A

Figure 15. Suggested PCB Layout for AD7225, Component Side (Top View)

V

= 1.24V p-p

REF

20k

50k

100k

200k

500k

1M

INPUT FREQUENCY (Hz)

Figure 14. Channel-to-Channel Isolation

Rev. C | Page ±± of 24

AD7225

SPECIFICATION RANGES

code error, improved output sink capability with outputs near

AGND, and improved negative-going settling time.

For the AD7225 to operate to rated specifications, its input

reference voltage must be at least 4 V below the V_DDpower

supply voltage. This voltage differential is the overhead voltage

required by the output amplifiers.

Performance is specified over a wide range of reference voltages

from 2 V to (V_DD− 4 V) with dual supplies. This allows a range

of standard reference generators to be used, such as the AD780,

a 2.5 V band gap reference, and the AD584, a precision 10 V

reference. Note that an output voltage range of 0 V to 10 V

requires a nominal 15 V 5% power supply voltage.

The AD7225 is specified to operate over a V_DDrange from 12 V

5% to 15 V 10% (that is, from 11.4 V to 16.5 V) with a V_SS

of −5 V 10%. Operation is also specified for a single 15 V

5% V_DDsupply. Applying a V_SSof −5 V results in improved zero-

Rev. C | Page ±2 of 24

AD7225

UNIPOLAR OUTPUT OPERATION

V

A V

B V

C V

D

V

DD

REF

This is the basic mode of operation for each channel of the

AD7225, with the output voltage having the same positive

polarity as V_REFx. The AD7225 can be operated single supply

(V_SS= AGND) or with positive/negative supplies (see the Op

Amp Section, which outlines the advantages of having negative

V_SS). Connections for the unipolar output operation are shown

in Figure 16. The voltage at any of the reference inputs must

never be negative with respect to DGND. Failure to observe this

precaution may cause parasitic transistor action and possible

device destruction. The code table for unipolar output

operation is shown in Table 7.

DAC A

DAC B

DAC C

DAC D

DB7

V

A

OUT

(MSB)

DB0

(LSB)

B

C

D

OUT

WR

A1

A2

LDAC

AD7225

Note,

V

AGND

DGND

SS

1

256



_REF









1 LSB =

(

V_REF

)

(

2⁻⁸

= V

)

Figure 16. Unipolar Output Circuit

Table 7. Unipolar Code Table

DAC Latch Contents

MSB

LSB

Analog Output

255

±±±±

+V_REF

(

)

256

129

256

±000

000±

0000

V_REF

2

128

256

+V_REF

(

)

= +

127

256

0±±±

0000

±±±±

000±

0000

+V_REF

(

)

1

+V_REF

256

0 V

Rev. C | Page ±3 of 24

AD7225

BIPOLAR OUTPUT OPERATION

V

REF

Each of the DACs of the AD7225 can be individually confi-

gured to provide bipolar output operation. This is possible

using one external amplifier and two resistors per channel.

Figure 17 shows a circuit used to implement offset binary

coding (bipolar operation) with DAC A (DAC Channel A)

of the AD7225. In this case,

R1

R2

V

A

V

DD

REF

+15V

AD7225*

V

A

V

OUT

DAC A

–15V

R1, R2 = 10kΩ ± 0.1%.

*DIGITAL INPUTS OMITTED

FOR CLARITY.

R2

R1

R2

R1























V_OUT= 1+

×

(

D_AV_REF

)

−

×

(

V_REF

)



V

AGND

DGND

SS

With R1 = R2

V_OUT2D_A−1

Figure 17. Bipolar Output Circuit

=

(

)

×

(

V_REF

)

where D_Ais a fractional representation of the digital word in

Latch A (0 ≤ D_A≤ 255/256).

Table 8. Bipolar (Offset Binary) Code Table

DAC Latch Contents

Mismatch between R1 and R2 causes gain and offset errors and,

therefore, these resistors must match and track over tempera-

ture. The AD7225 can be operated in single supply or from

positive/negative supplies. Table 8 shows the digital code vs.

output voltage relationship for the circuit of Figure 17 with

R1 = R2.

MSB

LSB

Analog Output

127

±±±±

+V_REF

(

)

128

1

±000

000±

+V_REF

0 V

128

±000

0±±±

0000

±±±±

1

−V_REF

(

)

128

127

128

0000

000±

0000

−V_REF

128

= 1 −V_REF

128

Rev. C | Page ±4 of 24

AD7225

AGND BIAS

V

A

V

DD

REF

The AD7225 AGND pin can be biased above system ground

(AD7225 DGND) to provide an offset zero analog output

voltage level. Figure 18 shows a circuit configuration to achieve

this for DAC Channel A of the AD7225. The output voltage,

AD7225*

V

A

OUT

V

IN

DAC A

V_OUTA, can be expressed as:

AGND

V_OUTA = V_BIAS+ D_A(V_IN)

V

DGND

BIAS

SS

where D_Ais a fractional representation of the digital word in

DAC Latch A (0 ≤ D_A≤ 255/256).

*DIGITAL INPUTS OMITTED FOR CLARITY.

Figure 18. AGND Bias Circuit

For a given V_IN, increasing AGND above system ground reduces

the effective V_DD− V_REF, which must be at least 4 V to ensure

specified operation. Note that, because the AGND pin is

common to all four DACs, this method biases up the output

voltages of all the DACs in the AD7225. Note that V_DDand V_SS

of the AD7225 should be referenced to DGND.

Rev. C | Page ±5 of 24

AD7225

AC REFERENCE SIGNAL

+15V

15kΩ

10kΩ

In some applications, it may be desirable to have ac reference

signals. The AD7225 has multiplying capability within the

upper (V_DD− 4 V) and lower (2 V) limits of reference voltage

when operated with dual supplies. Therefore, ac signals need to

be ac-coupled and biased up before being applied to the

reference inputs. Figure 19 shows a sine wave signal applied to

+4V

REFERENCE

INPUT

+15V

–4V

V

A

V

DD

REF

AD7225*

V

A

OUT

V_REFA. For input signal frequencies up to 50 kHz, the output

DAC A

distortion typically remains less than 0.1%. The typical 3 dB

bandwidth figure for small signal inputs is 800 kHz.

V

AGND

DGND

SS

*DIGITAL INPUTS OMITTED FOR CLARITY.

Figure 19. Applying an AC Signal to the AD7225

Rev. C | Page ±6 of 24

AD7225

APPLICATIONS INFORMATION

ACCUMULATOR

OUTPUT

V

A

B

C

D

OUT

DELAYED

INPUT

FILTER

OUTPUT

INPUT

AD7820

ADC

AM29520

TLC

AD7225

AD585

SHA

+

QUAD DAC

SAMPLES

V

A

V

A

V

A

V

A

REF

h

4

1

2

3

X

1

X

n

n – 1

n – 2

n – 3

FILTER

INPUT

A

V

A

OUT

T

2

3

4

V

h

4

10V

OUT

1

2

3

AD584

REF

AM7224

DAC

AD7225

QUAD DAC

V

REF

+

FILTER

OUTPUT

y(n)

GAIN SET

TAP WEIGHT

Figure 20. Programmable Transversal Filter

0

h

= 0.117

= 0.417

1

2

3

4

PROGRAMMABLE TRANSVERSAL FILTER

–10

A discrete time filter can be described by either multiplication

in the frequency domain or by convolution in the time domain:

–20

–30

–40

–50

–60

–70

–80

–90

–100

N

Y ω = H ω X ω or y = h X

( ) ( ) ( )

n

k n−k +1

∑

k=1

The convolution sum can be implemented using the special struc-

ture known as the transversal filter (see Figure 21). It consists

of an N-stage delay line with N taps weighted by N coefficients,

the resulting products being accumulated to form the output.

The tap weights or coefficients h_kare the nonzero elements of

the impulse response and therefore determine the filter transfer

function. A particular filter frequency response is realized by

setting the coefficients to the appropriate values. This property

leads to the implementation of transversal filters whose fre-

quency response is programmable.

0

0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

NORMALIZED FREQUENCY (f/f )

S

Figure 22. Predicted (Theoretical) Response

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

X

n

n – 1

n – 2

n – N

n – N + 1

FILTER

INPUT

T

1

2

3

N –1

N

h

N

1

2

3

N – 1

h

(DAC A) = 00011110

(DAC B) = 01101011

(DAC C) = 01101011

(DAC D) = 00011110

1

2

3

4

+

FILTER

OUTPUT

N

h

X

n – k + 1

y

=

k

n

k = 1

Figure 21. Transversal Filter

A four-tap programmable transversal filter can be implemented

using the AD7225 (see Figure 20). The input signal is first sampled

and converted to allow the tapped delay line function to be

provided by the AM29520. The multiplication of delayed input

samples by fixed, programmable up weights is accomplished by

the AD7225, the four coefficients or reference inputs being set

by the digital codes stored in the AD7226. The resultant products

are accumulated to yield the convolution sum output sample,

which is held by the AD585.

0

0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50

FREQUENCY (f/f )

S

Figure 23. Actual Response

Low-pass, band-pass, and high-pass filters can be synthesized

using this arrangement. The particular up weights needed for

any desired transfer function can be obtained using the standard

Remez exchange algorithm. Figure 22 shows the theoretical

low-pass frequency response produced by a four-tap transversal

filter with the coefficients indicated. Although the theoretical

prediction does not take into account the quantization of the

input samples and the truncation of the coefficients, neverthe-

Rev. C | Page ±7 of 24

AD7225

less, there exists a good correlation with the actual performance

of the transversal filter (see Figure 23).

15V

25kΩ

50kΩ

33kΩ

50kΩ

100kΩ

V

DD

100kΩ

DIGITAL WORD MULTIPLICATION

AD7225*

V

A

V

A

B

C

D

IN

REF

OUT

Because each DAC of the AD7225 has a separate reference input,

the output of one DAC can be used as the reference input for

another. This means that multiplication of digital words can be

performed (with the result given in analog form). For example,

if the output from DAC A is applied to V_REFB, then the output

from DAC B, V_OUTB, can be expressed as:

Y

B

C

D

AGND DGND

V

SS

V_OUTB = D_A× D_B× V_REF

A

where D_Aand D_Bare the fractional representations of the digital

words in DAC Latch A and DAC Latch B, respectively.

*DIGITAL INPUTS OMITTED FOR CLARITY.

Figure 24. Complex Waveform Generation

If D_A= D_B= D, the result is D²× V_REFA.

In this manner, the four DACs can be used on their own or in

conjunction with an external summing amplifier to generate

complex waveforms. Figure 24 shows one such application.

In this case, the output waveform, Y, is represented by

Y = −(x⁴+ 2x³+ 3x²+ 2x + 4) × V_IN

where x is the digital code that is applied to all four DAC

latches.

Rev. C | Page ±8 of 24

AD7225

MICROPROCESSER INTERFACE

A15

A8

ADDRESS BUS

A8

A0

A1

A0

A1

LDAC

Z-80

8085A/

8088

ADDRESS

DECODE

LDAC

ADDRESS

DECODE

AD7225*

WR

AD7225*

EN

MREQ

WR

LATCH

EN

DB7

DB0

DB7

DB0

ALE

D7

D0

AD7

AD0

DATA BUS

*LINEAR CIRCUITRY OMITTED FOR CLARITY.

ADDRESS DATA BUS

*LINEAR CIRCUITRY OMITTED FOR CLARITY.

Figure 25. AD7225-to-8085A/8088 Interface, Double-Buffered Mode

Figure 26. AD7225-to-Z-80 Interface, Double-Buffered Mode

A23

A15

ADDRESS BUS

A0

A1

A0

A1

A0

A1

ADDRESS

DECODE

6809/

68008

AS

ADDRESS

6502

AD7225*

DECODE

LDAC

EN

AD7225*

WR

EN

R/W

DTACK

R/W

LDAC

E OR Φ2

DB7

DB0

DB7

DB0

D7

D0

D7

D0

DATA BUS

*LINEAR CIRCUITRY OMITTED FOR CLARITY.

DATA BUS

*LINEAR CIRCUITRY OMITTED FOR CLARITY.

Figure 27. AD7225-to-6809/6502 Interface, Single-Buffered Mode

Figure 28. AD7225-to-68008 Interface, Single-Buffered Mode

Rev. C | Page ±9 of 24

AD7225

V_SSGENERATION

1/6

CD4049AE

Operating the AD7225 from dual supplies results in enhanced

performance over single-supply operation on a number of

parameters as previously outlined. Some applications may

require this enhanced performance, but may only have a single

power supply rail available. The circuit of Figure 29 shows a

method of generating a negative voltage using one CD4049,

operated from a V_DDof 15 V. Two inverters of the hex inverter

chip are used as an oscillator. The other four inverters are in

parallel and used as buffers for higher output current. The

square wave output is level translated to a negative-going signal,

then rectified and filtered. The circuit configuration shown

provides an output voltage of −5.1 V for current loadings in the

range of 0.5 mA to 9 mA. This satisfies the AD7225 I_SSrequire-

ment over the commercial operating temperature range.

1/6

CD4049AE

1/6

CD4049AE

510kΩ

5.1kΩ

1/6

CD4049AE

+

0.02µF

47µF

510Ω

–V

OUT

1N4001

+

47µF

5V1

Figure 29. V_SSGeneration Circuit

Rev. C | Page 20 of 24

AD7225

OUTLINE DIMENSIONS

1.280 (32.51)

1.250 (31.75)

1.230 (31.24)

24

1

13

12

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.100 (2.54)

BSC

0.060 (1.52)

MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.210 (5.33)

MAX

0.015

(0.38)

MIN

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.015 (0.38)

GAUGE

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

PLANE

SEATING

PLANE

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

0.430 (10.92)

MAX

0.005 (0.13)

MIN

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

COMPLIANT TO JEDEC STANDARDS MS-001

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.

Figure 30. 24-Lead Plastic Dual In-Line Package [PDIP]

Narrow Body

(N-24-1)

Dimensions shown in inches and (millimeters)

0.098 (2.49)

MAX

0.005 (0.13)

MIN

0.310 (7.87)

0.220 (5.59)

24

13

12

1

PIN 1

0.060 (1.52)

0.015 (0.38)

0.320 (8.13)

0.200 (5.08)

1.280 (32.51) MAX

MAX

0.290 (7.37)

0.150 (3.81)

MIN

0.015 (0.38)

0.008 (0.20)

15°

0°

0.200 (5.08)

0.125 (3.18)

SEATING

PLANE

0.100

(2.54)

BSC

0.070 (1.78)

0.030 (0.76)

0.023 (0.58)

0.014 (0.36)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 31. 24-Lead Ceramic Dual In-Line Package [CERDIP]

Narrow Body

(Q-24-1)

Dimensions shown in inches and (millimeters)

Rev. C | Page 21 of 24

AD7225

0.180 (4.57)

0.165 (4.19)

0.048 (1.22)

0.042 (1.07)

0.056 (1.42)

0.042 (1.07)

0.020 (0.51)

MIN

4

5

26

25

0.048 (1.22)

0.042 (1.07)

0.021 (0.53)

0.013 (0.33)

PIN 1

IDENTIFIER

BOTTOM

VIEW

(PINS UP)

0.050

(1.27)

BSC

0.430 (10.92)

0.390 (9.91)

TOP VIEW

(PINS DOWN)

0.032 (0.81)

0.026 (0.66)

11

12

19

18

0.045 (1.14)

0.025 (0.64)

R

0.456 (11.582)

0.450 (11.430)

SQ

0.120 (3.04)

0.090 (2.29)

0.495 (12.57)

SQ

0.485 (12.32)

COMPLIANT TO JEDEC STANDARDS MO-047-AB

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 32. 28-Lead Plastic Leaded Chip Carrier [PLCC]

(P-28)

Dimensions shown in inches and (millimeters)

15.60 (0.6142)

15.20 (0.5984)

24

1

13

12

7.60 (0.2992)

7.40 (0.2913)

10.65 (0.4193)

10.00 (0.3937)

0.75 (0.0295)

0.25 (0.0098)

⋅

45°

2.65 (0.1043)

2.35 (0.0925)

0.30 (0.0118)

0.10 (0.0039)

8°

0°

COPLANARITY

0.10

SEATING

PLANE

0.51 (0.0201)

0.31 (0.0122)

1.27 (0.0500)ꢀ

BSC

1.27 (0.0500)

0.40 (0.0157)

0.33 (0.0130)

0.20 (0.0079)

COMPLIANT TO JEDEC STANDARDS MS-013-AD

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.

Figure 33. 24-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-24)

Dimensions shown in millimeters and (inches)

Rev. C | Page 22 of 24

AD7225

8.50

8.20

7.90

13

12

24

5.60

5.30

5.00

8.20

7.80

7.40

1

0.25

0.09

1.85

1.75

1.65

2.00 MAX

8°

4°

0°

0.95

0.75

0.55

0.38

0.22

0.05 MIN

SEATING

PLANE

COPLANARITY

0.10

0.65 BSC

COMPLIANT TO JEDEC STANDARDS MO-150-AG

Figure 34. 24-Lead Shrink Small Outline Package [SSOP]

(RS-24)

Dimensions shown in millimeters

ORDERING GUIDE

Model^{1, 2}

AD7225BQ

Temperature Range

−40°C to +85°C

Total Unadjusted Error

±2 LSB

±± LSB

±2 LSB

±± LSB

Package Description

24-Lead CERDIP

24-Lead SSOP

24-Lead PDIP

Package Option

Q-24-±

RS-24

N-24-±

P-28

AD7225BRS

AD7225BRS-REEL

AD7225BRSZ

AD7225CRS

AD7225CRS-REEL

AD7225CRSZ

AD7225CRSZ-RL

AD7225KN

AD7225KNZ

AD7225KP

AD7225KP-REEL

AD7225KPZ

AD7225KR

AD7225KR-REEL

AD7225KRZ

AD7225KRZ-REEL

AD7225LN

AD7225LNZ

AD7225LP

AD7225LP-REEL

AD7225LPZ

AD7225LPZ-REEL

AD7225LR

AD7225LR-REEL

AD7225LRZ

AD7225LRZ-REEL

24-Lead PDIP

28-Lead PLCC

24-Lead SOIC_W

24-Lead PDIP

P-28

RW-24

N-24-±

P-28

24-Lead PDIP

28-Lead PLCC

24-Lead SOIC_W

RW-24

^±To order MIL-STD-883 processed parts, add /883B to part number. Contact your local sales office for military data sheet.

²Z = RoHS Compliant Part.

Rev. C | Page 23 of 24

AD7225

NOTES

registered trademarks are the property of their respective owners.

D00986-0-3/10(C)

Rev. C | Page 24 of 24


型号：	AD7225BRS
厂家：	ADI
描述：	LC2MOS Quad 8-Bit DAC with Separate Reference Inputs LC2MOS四通道8位DAC ，具有独立的基准输入转换器光电二极管
文件：	总24页 (文件大小：400K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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