AD7228LP [ADI]

LC2MOS Octal 8-Bit DAC; LC2MOS八路8位DAC


型号：	AD7228LP
厂家：	ADI
描述：	LC2MOS Octal 8-Bit DAC LC2MOS八路8位DAC 转换器数模转换器信息通信管理
文件：	总8页 (文件大小：169K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LC MOS

Octal 8-Bit DAC

AD7228A

FEATURES

FUNCTIO NAL BLO CK D IAGRAM

Eight 8-Bit DACs w ith Output Am plifiers

Operates w ith Single +5 V, +12 V or +15 V

or Dual Supplies

␮P Com patible (95 ns WR Pulse)

No User Trim s Required

Skinny 24-Pin DlPs, SOIC, and 28-Term inal Surface

Mount Packages

GENERAL D ESCRIP TIO N

T he AD7228A contains eight 8-bit voltage-mode digital-to-

analog converters, with output buffer amplifiers and interface

logic on a single monolithic chip. No external trims are required

to achieve full specified performance for the part.

P RO D UCT H IGH LIGH TS

1. Eight DACs and Amplifiers in Small Package

T he single-chip design of eight 8-bit DACs and amplifiers al-

lows a dramatic reduction in board space requirements and

offers increased reliability in systems using multiple convert-

ers. Its pinout is aimed at optimizing board layout with all

analog inputs and outputs at one side of the package and all

digital inputs at the other.

Separate on-chip latches are provided for each of the eight D/A

converters. Data is transferred into the data latches through a

common 8-bit T T L/CMOS (5 V) compatible input port. Ad-

dress inputs A0, A1 and A2 determine which latch is loaded

when WR goes low. T he control logic is speed compatible with

most 8-bit microprocessors.

2. Single or Dual Supply Operation

Specified performance is guaranteed for input reference voltages

from +2 to +10 V when using dual supplies. T he part is also

specified for single supply +15 V operation using a reference of

+10 V and single supply +5 V operation using a reference of

+1.23 V. Each output buffer amplifier is capable of developing

+10 V across a 2 kΩ load.

T he voltage-mode configuration of the DACs allows single

supply operation of the AD7228A. T he part can also be oper-

ated with dual supplies giving enhanced performance for

some parameters.

3. Microprocessor Compatibility

T he AD7228A has a common 8-bit data bus with individual

DAC latches, providing a versatile control architecture for

simple interface to microprocessors. All latch enable signals

are level triggered and speed compatible with most high per-

formance 8-bit microprocessors.

T he AD7228A is fabricated on an all ion-implanted, high-

speed, Linear Compatible CMOS (LC²MOS) process which has

been specifically developed to integrate high-speed digital logic

circuits and precision analog circuits on the same chip.

REV. A

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 617/ 329-4700

Fax: 617/ 326-8703

AD7228A–SPECIFICATIONS

(V = 10.8 V to 16.5 V; V = –5 V ؎ 10%; GND = 0 V; V = +2 V to +10 V ; R = 2 kΩ, C = 100 pF unless otherwise

REF

noted.) All specifications T_MINto T_MAXunless otherwise noted.

DUAL SUPPLY

P aram eter

Version²

Version

Units

Conditions/Com m ents

ST AT IC PERFORMANCE

Resolution

±1

±1/2

±1

±1/2

±1

Bits

T otal Unadjusted Error³

Relative Accuracy

Differential Nonlinearity

Full-Scale Error⁴

±2

±1

±2

±1

LSB max

V_DD= +15 V ± 10%, V_REF= +10 V

Guaranteed Monotonic

T ypical tempco is 5 ppm/°C with V_REF= +10 V

±1/2

Zero Code Error

@ 25°C

T _MINto T _MAX

Minimum Load Resistance

±25

±30

±15

±20

±25

±30

±15

±20

mV max

kΩ min

T ypical tempco is 30 µV/°C

V_OUT= +10 V

REFERENCE INPUT

Voltage Range¹

Input Resistance

Input Capacitance⁵

AC Feedthrough

2 to 10

500

–70

2 to 10

500

–70

2 to 10

500

–70

2 to 10

500

–7 0

V min/V max

kΩ min

pF max

Occurs when each DAC is loaded with all 1s.

V_REF= 8 V p-p Sine Wave @ 10 kHz

dB typ

DIGIT AL INPUT S

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Leakage Current

Input Capacitance⁵

Input Coding

2.4

0.8

±1

2.4

0.8

±1

2.4

0.8

±1

2.4

0.8

±1

V min

V max

µA max

pF max

V_IN= 0 V or V_DD

Binary

DYNAMIC PERFORMANCE⁵

Voltage Output Slew Rate

Voltage Output Settling T ime

Positive Full-Scale Change

Negative Full-Scale Change

Digital Feedthrough

V/µs min

µs max

nV secs typ

V_REF= +10 V; Settling T ime to ±1/2 LSB

Code transition all 0s to all 1s. V_REF= 0 V; WR = V_DD

Code transition all 0s to all 1s. V_REF= +10 V; WR = 0 V

Digital Crosstalk⁶

POWER SUPPLIES

V_DDRange

V_SSRange

I_DD

10.8/16.5

–4.5/–5.5

10.8/16.5 10.8/16.5 10.8/16.5

–4.5/–5.5 –4.5/–5.5 –4.5/–5.5

V min/V max

For Specified Performance

Outputs Unloaded; V_IN= V_INLor V_INH

@ 25°C

T _MINto T _MAX

mA max

I_SS

Outputs Unloaded; V_IN= V_INLor V_INH

@ 25°C

T _MINto T _MAX

mA max

(V = +15 V ؎ 10%, V ; = GND = 0 V; V = +10 V, R = 2 kΩ, C = 100 pF unless otherwise noted.)

REF

SINGLE SUPPLY

AII specifications T_MINto T_MAXunless otherwise noted.

ST AT IC PERFORMANCE

Resolution

Bits

T otal Unadjusted Error³

Differential Nonlinearity

Minimum Load Resistance

±2

±1

±2

±1

LSB max

kΩ min

Guaranteed Monotonic

V_OUT= +10 V

REFERENCE INPUT

Input Resistance

500

kΩ min

pF max

Input Capacitance⁵

Occurs when each DAC is loaded with all 1s.

DIGIT AL INPUT S

As per Dual Supply Specifications

DYNAMIC PERFORMANCE⁵

Voltage Output Slew Rate

Voltage Output Settling T ime

Positive Full-Scale Change

Negative Full-Scale Change

Digital Feedthrough

V/µs min

µs max

nV secs typ

Settling T ime to ±1/2 LSB

Code transition all 0s to all 1s. V_REF= 0 V; WR = V_DD

Code transition all 0s to all 1s. V_REF= +10 V, WR = 0 V

Digital Crosstalk⁶

POWER SUPPLIES

V_DDRange

I_DD

13.5/16.5

13.5/16.5 13.5/16.5 13.5/16.5

V min/V max

For Specified Performance

Outputs Unloaded; V_IN= V_INLor V_INH

@ 25°C

T _MINto T _MAX

mA max

NOT ES

¹V_OUTmust be less than V_DDby 3.5 V to ensure correct operation.

⁵Sample tested at 25°C to ensure compliance.

²T emperature ranges are as follows:

⁶T he glitch impulse transferred to the output of one converter (not addressed) due to a

change in the digital input code to another addressed converter.

B, C Versions; –40°C to +85°C

T , U Versions; –55°C to +125°C

³T otal Unadjusted Error includes zero code error, relative accuracy and full-scale error.

⁴Calculated after zero code error has been adjusted out.

Specifications subject to change without notice.

–2–

REV. A

AD7228A

(V = +5 V ؎ 5%, V ; = 0 to –5 V ؎ 10%, GND = 0 V, V = +1.25 V, R = 2 k⍀, C = 100 pF

REF

+5 V SUPPLY OPERATION

unless otherwise noted.) AII specifications T_MINto T_MAXunless otherwise noted.

P aram eter

Version

Units

Conditions/Com m ents

ST AT IC PERFORMANCE

Resolution

Bits

Relative Accuracy

Differential Nonlinearity

Full-Scale Error

Zero Code Error

@ 25°C

±2

±1

±4

±2

±1

±2

±1

±4

±2

±1

±2

LSB max

Guaranteed Monotonic

±30

±40

±20

±30

±40

±20

±30

mV max

T _MINto T _MAX

REFERENCE INPUT

Reference Input Range

1.2

1.3

1.2

1.3

1.2

1.3

1.2

1.3

V min

V max

kΩ min

pF max

Reference Input Resistance

Reference Input Capacitance

500

POWER REQUIREMENT S

Positive Supply Range

Positive Supply Current

@ 25°C

4.75/5.25

V min/V max

For Specified Performance

µA max

T _MINto T _MAX

Negative Supply Current

@ 25°C

T _MINto T _MAX

µA max

NOT ES

All of the specifications as per Dual Supply Specifications except for negative full-scale settling-time when V_SS= 0 V.

Specifications subject to change without notice.

1, 2

SWITCHING CHARACTERISTICS

(See Figures 1, 2; V = +5 V ؎ 5% or +10.8 V to +16.5 V; V = 0 V or –5 V ؎ 10%)

Lim it at 25°C

Lim it at T_MIN, T_MAX

(B, C Versions)

Lim it at T_MIN, T_MAX

(T, U Versions)

P aram eters

All Grades

Units

Conditions/Com m ents

t₁

t₂

t₃

t₄

t₅

120

100

ns min

Address to WR Setup T ime

Address to WR Hold T ime

Data Valid to WR Setup T ime

Data Valid to WR Hold T ime

Write Pulse Width

150

NOT ES

¹Sample tested at 25°C to ensure compliance. All input rise and fall times measured from 10% to 90% of +5 V, t_R= t_F= 5 ns.

V_INH+V_INL

²T iming measurement reference level is

INTERFACE LO GIC INFO RMATIO N

Address lines A0, A1 and A2 select which DAC accepts data

from the input port. T able I shows the selection table for the

eight DACs with Figure 1 showing the input control logic.

When the WR signal is low, the input latch of the selected DAC

is transparent, and its output responds to activity on the data

bus. T he data is latched into the addressed DAC latch on the

rising edge of WR. While WR is high, the analog outputs remain

at the value corresponding to the data held in their respective

latches.

Table I. AD 7228A Truth Table

AD 7228A Control Inputs

AD 7228A

O peration

Figure 1. Input Control Logic

No Operation

Device Not Selected

DAC 1 T ransparent

DAC 1 Latched

DAC 2 T ransparent

DAC 3 T ransparent

DAC 4 T ransparent

DAC 5 T ransparent

DAC 6 T ransparent

DAC 7 T ransparent

DAC 8 T ransparent

H = High State L = Low State X = Don’t Care

Figure 2. Write Cycle Tim ing Diagram

–3–

REV. A

AD7228A

ABSO LUTE MAXIMUM RATINGS¹

Extended . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

Storage T emperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . +300°C

V_DDto GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V

V_DDto V_SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +24 V

Digital Input Voltage to GND . . . . . . . . . . . . . . . –0.3 V, V_DD

V_REFto GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3V, V_DD

V_OUTto GND². . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V_SS, V_DD

Power Dissipation (Any Package) to +75°C . . . . . . . 1000 mW

Derates above 75°C by . . . . . . . . . . . . . . . . . . . . 2.0 mW/°C

Operating T emperature

NOT ES

¹Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. T his is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

²Outputs may be shorted to any voltage in the range V_SSto V_DDprovided that the

power dissipation of the package is not exceeded. T ypical short circuit current for

a short to GND or V_SSis 50 mA.

Commercial . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

CAUTIO N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD7228A features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

P IN CO NFIGURATIO NS

D IP AND SO IC P LCC

CIRCUIT INFO RMATIO N

D /A SECTIO N

T he AD7228A contains eight identical, 8-bit, voltage-mode

digital-to-analog converters. T he output voltages from the con-

verters have the same polarity as the reference voltage, allowing

single supply operation. A novel DAC switch pair arrangement

on the AD7228A allows a reference voltage range from +2 V to

+10 V when operated from a V_DDof +15 V. Each DAC consists

of a highly stable, thin-film, R-2R ladder and eight high-speed

NMOS switches. T he simplified circuit diagram for one channel

is shown in Figure 3. Note that V_REFand GND are common to

all eight DACs.

O RD ERING GUID E

Total

Unadjusted

Error (LSB) O ption²

Tem perature

Range

P ackage

Model¹

Figure 3. D/A Sim plified Circuit Diagram

AD7228ABN

AD7228ACN

AD7228ABP

AD7228ACP

AD7228ABR

AD7228ACR

AD7228ABQ

AD7228ACQ

AD7228AT Q³

–40°C to +85°C

–55°C to +125°C

±2 max

±1 max

±2 max

±1 max

±2 max

±1 max

±2 max

±1 max

±2 max

±1 max

N-24

P-28A

R-24

Q-24

T he input impedance at the V_REFpin of the AD7228A is the

parallel combination of the eight individual DAC reference in-

put impedances. It is code dependent and can vary from 2 kΩ to

infinity. T he lowest input impedance occurs when all eight

DACs are loaded with digital code 01010101. T herefore, it is

important that the external reference source presents a low out-

put impedance to the V_REFterminal of the AD7228A under

changing load conditions. Due to transient currents at the refer-

ence input during digital code changes a 0.1 µF (or greater)

decoupling capacitor is recommended on the V_REFinput for dc

applications. T he nodal capacitance at the reference terminal is

also code dependent and typically varies from 120 pF to

350 pF.

AD7228AUQ³–55°C to +125°C

NOT ES

¹T o order MIL-ST D-883, Class B processed parts, add /883B to part number.

Contact your local sales office for military data sheet and availability.

²N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip;

R = Small Outline IC (SOIC).

Each V_OUTpin can be considered as a digitally programmable

voltage source with an output voltage:

³T hese grades will be available to /883B processing only.

V_OUTN= D_N• V_REF

where D_Nis a fractional representation of the digital input

code and can vary from 0 to 255/256.

T he output impedance is that of the output buffer amplifier as

described in the following section.

–4–

REV. A

AD7228A

O P AMP SECTIO N

SUP P LY CURRENT

Each voltage-mode D/A converter output is buffered by a unity

gain noninverting CMOS amplifier. T his buffer amplifier is

tested with a 2 kΩ and 100 pF load but will typically drive a

2 kΩ and 500 pF load.

T he AD7228A has a maximum I_DDspecification of 22 mA and

a maximum I_SSof 20 mA over the –55°C to +125°C tempera-

ture range. T his maximum current specification is actually de-

termined by the current at –55°C. Figure 6 shows a typical plot

of power supply current versus temperature.

T he AD7228A can be operated single or dual supply. Operating

the part from single or dual supplies has no effect on the positive-

going settling time. However, the negative-going settling time to

voltages near 0 V in single supply will be slightly longer than the

settling time for dual supply operation. Additionally, to ensure

that the output voltage can go to 0 V in single supply, a transis-

tor on the output acts as a passive pull-down as the output volt-

age nears 0 V. As a result, the sink capability of the amplifier is

reduced as the output voltage nears 0 V in single supply. In dual

supply operation, the full sink capability of 400 µA at 25°C is

maintained over the entire output voltage range. T he single sup-

ply output sink capability is shown in Figure 4. T he negative

V_SSalso gives improved output amplifier performance allowing

an extended input reference voltage range and giving improved

slew rate at the output.

Figure 6. Power Supply Current vs. Tem perature

AP P LYING TH IS AD 7228A

UNIP O LAR O UTP UT O P ERATIO N

T his is the basic mode of operation for each channel of the

AD7228A, with the output voltage having the same positive po-

larity as V_REF. Connections for unipolar output operation are

shown in Figure 7. T he AD7228A can be operated from single

or dual supplies as outlined earlier. T he voltage at the reference

input must never be negative with respect to GND. Failure to

observe this precaution may cause parasitic transistor action and

possible device destruction. T he code table for unipolar output

operation is shown in T able II.

Figure 4. Single Supply Sink Current

T he output broadband noise from the amplifier is 300 µV

peak-to-peak. Figure 5 shows a plot of noise spectral density

versus frequency.

Figure 5. Noise Spectral Density vs. Frequency

D IGITAL INP UTS

T he AD7228A digital inputs are compatible with either T T L or

5 V CMOS levels. All logic inputs are static-protected MOS

gates with typical input currents of less than 1 nA. Internal in-

put protection is achieved by on-chip distributed diodes.

Figure 7. Unipolar Output Circuit

–5–

REV. A

AD7228A

Table II. Unipolar Code Table

Mismatch between R1 and R2 causes gain and offset errors, and

therefore, these resistors must match and track over temperature.

D AC Latch Contents

Once again, the AD7228A can be operated from single supply

or from dual supplies. T able III shows the digital code versus

output voltage relationship for the circuit of Figure 8 with

R1 = R2.

MSB

LSB

Analog O utput

255

+V_REF

1 1 1 1

1 0 0 0

0 1 1 1

0 0 0 0

1 1 1 1

0 0 0 1

0 0 0 0

1 1 1 1

0 0 0 1

0 0 0 0

256

129

256

+V_REF

AC REFERENCE SIGNAL

V_REF

128

In some applications it may be desirable to have an ac signal ap-

plied as the reference input to the AD7228A. T he AD7228A

has multiplying capability within the upper (+10 V) and lower

(+2 V) limits of reference voltage when operated with dual sup-

plies. T herefore, ac signals need to be ac coupled and biased up

before being applied to the reference input. Figure 9 shows a

sine-wave signal applied to the reference input of the AD7228A.

For input frequencies up to 50 kHz, the output distortion typi-

cally remains less than 0.1%. T he typical 3 dB bandwidth for

small signal inputs is 800 kHz.

+V_REF

= +

256

127

256

0 V

Note: 1 LSB = (V_REF)(2^–8) = V_REF

256

BIP O LAR O UTP UT O P ERATIO N

Each of the DACs on the AD7228A can be individually config-

ured for bipolar output operation. T his is possible using one ex-

ternal amplifier and two resistors per channel. Figure 8 shows a

circuit used to implement offset binary coding (bipolar opera-

tion) with DAC1 of the AD7228A. In this case

V_OUT= 1 +

• D •V

–

• V

(

REF

(

)

REF

With R1 = R2

V_OUT= (2D₁– 1) • (V_REF

)

where D₁is a fractional representation of the digital word in

latch 1 of the AD7228A. (0 ≤ D₁≤ 255/256)

Figure 9. Applying a AC Signal to the AD7228A

TIMING D ESKEW

A common problem in AT E applications is the slowing or

“rounding-off” of signal edges by the time they reach the

pin-driver circuitry. T his problem can easily be overcome by

“squaring-up” the edge at the pin-driver. However, since each

edge will not have been “rounded-off” by the same extent, this

“squaring-up” could lead to incorrect timing relationship be-

tween signals. T his effect is shown in Figure 10a.

Figure 8. Bipolar Output Circuit

Table III. Bipolar Code Table

D AC Latch Contents

MSB

LSB

Analog O utput

Figure 10a. Tim e Skewing Due to Slowing of Edges

127

+V_REF

1 1 1 1

1 0 0 0

0 1 1 1

0 0 0 0

1 1 1 1

0 0 0 1

0 0 0 0

1 1 1 1

0 0 0 1

0 0 0 0

T he circuit of Figure 10b shows how two DACs of the

128

AD7228A can help in overcoming this problem. T he same two

signals are applied to this circuit as were applied in Figure 10b.

T he output of each DAC is applied to one input of a high-speed

comparator, and the signals are applied to the other inputs.

Varying the output voltage of the DAC effectively varies the

trigger point at which the comparator flips. T hus the timing re-

lationship between the two signals can be programmably cor-

rected (or deskewed) by varying the code to the DAC of the

AD7228A. In a typical application, the code is loaded to the

128

+V_REF

0 V

–V_REF

128

127

128

–V_REF

= –V_REF

–6–

REV. A

AD7228A

DACs for correct timing relationships during the calibration

cycle of the instrument.

Figure 12. Self-Program m able Reference

Figure 10b. AD7228A Tim ing Deskew Circuit

CO ARSE/FINE AD JUST

T he DACs on the AD7228A can be paired together to form a

coarse/fine adjust function as indicated in Figure 11. T he func-

tion is achieved using one external op amp and a few resistors

per pair of DACs.

DAC1 is the most significant or coarse DAC. Data is first

loaded to this DAC to coarsely set the output voltage. DAC2 is

then used to fine tune this output voltage. Varying the ratio of

R1 to R2 varies the relative effect of the coarse and fine DACs

on the output voltage. For the resistor values shown, DAC2 has

a resolution of 150 µV in a 10 V output range. Since each DAC

on the AD7228A is guaranteed monotonic, the coarse adjust-

ment and fine adjustment are each monotonic. One application

for this is as a set-point controller (see “Circuit Applications of

the AD7226 Quad CMOS DAC” available from Analog Devices,

Publication Number E873–15–11/84).

Figure 13. Variation of V_REFwith Feedback Configuration

MICRO P RO CESSO R INTERFACING

Figure 14. AD7228A to 8085A/Z80 Interface

Figure 11. Coarse/Fine Adjust Circuit

SELF-P RO GRAMMABLE REFERENCE

T he circuit of Figure 12 shows how one DAC of the AD7228,

in this case DAC1, may be used in a feedback configuration to

provide a programmable reference for itself and the other seven

converters. T he relationship of V_REFto V_INis expressed by

1 + G

(

)

V_REF

•V_IN

where G = R2/R1

1 + G • D

(

)

Figure 13 shows typical plots of V_REFversus digital code, D₁, for

three different values of G. With V_IN= 2.5 V and G = 3 the

voltage at the output varies between 2.5 V and 10 V giving an

effective 10-bit dynamic range to the other seven converters. For

correct operation of the circuit, V_SSshould be –5 V and R1

greater than 6.8 kΩ.

Figure 15. AD7228A to 6809/6502 Interface

–7–

REV. A

AD7228A

Figure 17. AD7228A to MCS-51 Interface

Figure 16. AD7228A to 68008 Interface

O UTLINE D IMENSIO NS

D imensions shown in inches and (mm).

P lastic D IP (N-24)

Cer dip (Q -24)

P LCC (P -28A)

SO IC (R-24)

–8–

REV. A

AD7228LP [ADI]

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