AD7242_15_技术文档

LC²MOS Dual, Complete,

12-Bit/14-Bit Serial DACs

a

AD7242/AD7244

FEATURES

FUNCTIONAL BLOCK DIAGRAM

Two 12-Bit/14-Bit DACs with Output Amplifiers

AD7242: 12-Bit Resolution

AD7244: 14-Bit Resolution

On-Chip Voltage Reference

Fast Settling Time

AD7242: 3 ␮s to ؎1/2 LSB

AD7244: 4 ␮s to ؎1/2 LSB

High Speed Serial Interface

Operates from ؎5 V Supplies

Specified Over –40؇C to +85؇C in Plastic Packages

Low Power – 130 mW typ

GENERAL DESCRIPTION

The AD7242/AD7244 is a fast, complete, dual 12-bit/14-bit

voltage output D/A converter. It consists of a 12-bit/14-bit

DAC, 3 V buried Zener reference, DAC output amplifiers and

high speed serial interface logic.

Interfacing to both DACs is serial, minimizing pin count and

allowing a small package size. Standard control signals allow

interfacing to most DSP processors and microcontrollers.

Asynchronous control of DAC updating for both DACs is made

possible with a separate LDAC input for each DAC.

PRODUCT HIGHLIGHTS

1. Complete, Dual 12-Bit/14-Bit DACs

The AD7242/AD7244 operates from ±5 V power supplies,

providing an analog output range of ±3 V. A REF OUT/REF

IN function allows the DACs to be driven from the on-chip 3 V

reference or from an external reference source.

The AD7242/AD7244 provides the complete function for

generating voltages to 12-bit/14-bit resolution. The part

features an on-chip reference, output buffer amplifiers and

two 12-bit/14-bit D/A converters.

The AD7242/AD7244 is fabricated in Linear Compatible

CMOS (LC²MOS), an advanced mixed technology process that

combines precision bipolar circuits with low power CMOS

logic. Both parts are available in a 24-pin, 0.3-inch wide, plastic

or hermetic dual-in-line package (DIP) and in a 28-pin, plastic

small outline (SOIC) package. The AD7242 and AD7244 are

available in the same pinout to allow easy upgrade from 12-bit

to 14-bit performance.

2. High Speed Serial Interface

The AD7242/AD7244 provides a high speed, easy-to-use,

serial interface allowing direct interfacing to DSP processors

and microcontrollers. A separate serial port is provided for

each DAC.

3. Small Package Size

The AD7242/AD7244 is available in a 24-pin DIP and a 28-

pin SOIC package offering considerable space saving over

comparable solutions.

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 617/329-4700

Fax: 617/326-8703

World Wide Web Site: http://www.analog.com

(V_DD= +5 V ؎ 5% V_SS= –5 V ؎ 5%, AGND = DGND = 0 V, REF INA =

AD7242/AD7244–SPECIFICATIONS _{REF INB = +3 V. V}

_OUTA, V_OUTBload to AGND: R_L= 2 k⍀, C_L= 100 pF.

All Specifications T_MINto T_MAXunless otherwise noted.)

AD7242

Parameter

J, A Versions¹

K, B Versions¹

Units

Test Conditions/Comments

DC ACCURACY

Resolution

12

±1

±5

12

Bits

Integral Nonlinearity

Differential Nonlinearity

Bipolar Zero Error

±1/2

±1

±5

LSB max

Guaranteed Monotonic

Positive Full-Scale Error²

Negative Full-Scale Error²

REFERENCE OUTPUT³

REF OUT @ +25°C

T_MINto T_MAX

REF OUT Tempco

Reference Load Change

(∆REF OUT vs. ∆I)

2.99/3.01

2.98/3.02

35

2.99/3.01

2.98/3.02

35

V min/V max

ppm/°C typ

–1

mV max

Reference Load Current Change (0 µA–500 µA)

3 V ± 5%

REFERENCE INPUTS

REF INA, REF INB Input Range

Input Current

2.85/3.15

1

2.85/3.15

1

V min/V max

µA max

LOGIC INPUTS

(LDACA, LDACB, TFSA, TFSB,

TCLKA, TCLKB, DTA, DTB)

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

2.4

0.8

±10

10

2.4

0.8

±10

10

V min

V_DD= 5 V ± 5%

V_IN= 0 V to V_DD

V max

µA max

pF max

4

Input Capacitance, C_IN

ANALOG OUTPUTS

(V_OUTA, V_OUTB

)

Output Voltage Range

DC Output Impedance

Short Circuit Current

±3

0.1

20

±3

0.1

20

V nom

Ω typ

mA typ

AC CHARACTERISTICS⁴

Voltage Output Settling Time

Positive Full-Scale Change

Negative Full-Scale Change

Digital-to-Analog Glitch Impulse

Digital Feedthrough

Settling Time to Within ±1/2 LSB of Final Value

Typically 2 µs

3

10

2

110

3

10

2

110

µs max

nV secs typ

dB typ

DAC Code Change All 1s to All 0s

Channel-to-Channel Isolation

V_OUT= 10 kHz Sine Wave

POWER REQUIREMENTS

V_DD

V_SS

I_DD

I_SS

+5

–5

27

15

195

+5

–5

27

15

195

V nom

mA max

mW max

±5% for Specified Performance

Cumulative Current from the Two V_DDPins

Cumulative Current from the Two V_SSPins

Typically 130 mW

Total Power Dissipation

NOTES

¹Temperature ranges are as follows: J, K Versions: –40°C to +85°C; A, B Versions: –40°C to +85°C.

²Measured with respect to REF IN and includes bipolar offset error.

³For capacitive loads greater than 50 pF, a series resistor is required (see Internal Reference section).

⁴Sample tested @ +25°C to ensure compliance.

Specifications subject to change without notice.

AD7242 ORDERING GUIDE

Temperature

Range

Integral

Nonlinearity

Package

Option*

Model

AD7242JN

AD7242KN

AD7242JR

AD7242KR

AD7242AQ

AD7242BQ

–40°C to +85°C

±1 LSB max

±1/2 LSB max

±1 LSB max

±1/2 LSB max

±1 LSB max

±1/2 LSB max

N-24

R-28

Q-24

*N = Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC).

–2–

REV. A

AD7242/AD7244

AD7244

Parameter

J, A Versions¹

S Version¹

Units

Test Conditions/Comments

DC ACCURACY

Resolution

14

Bits

Integral Nonlinearity

Differential Nonlinearity

Bipolar Zero Error

±2

±1

±10

±2

±1

±10

LSB max

Guaranteed Monotonic

Positive Full-Scale Error²

Negative Full-Scale Error²

REFERENCE OUTPUT³

REF OUT @ +25°C

T_MINto T_MAX

REF OUT Tempco

Reference Load Change

(∆REF OUT vs. ∆I)

2.99/3.01

2.98/3.02

35

2.99/3.01

2.98/3.02

35

V min/V max

ppm/°C typ

–1

mV max

Reference Load Current Change (0 µA–500 µA)

3 V ± 5%

REFERENCE INPUTS

REF INA, REF INB Input Range

Input Current

2.85/3.15

1

2.85/3.15

1

V min/V max

µA max

LOGIC INPUTS

(LDACA, LDACB, TFSA, TFSB,

TCLKA, TCLKB, DTA, DTB)

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

2.4

0.8

±10

10

2.4

0.8

±10

10

V min

V_DD= 5 V ± 5%

V_IN= 0 V to V_DD

V max

µA max

pF max

4

Input Capacitance, C_IN

ANALOG OUTPUTS

(V_OUTA, V_OUTB

)

Output Voltage Range

DC Output Impedance

Short Circuit Current

±3

0.1

20

±3

0.1

20

V nom

Ω typ

mA typ

AC CHARACTERISTICS⁴

Voltage Output Settling Time

Positive Full-Scale Change

Negative Full-Scale Change

Digital-to-Analog Glitch Impulse

Digital Feedthrough

Settling Time to Within ±1/2 LSB of Final Value

Typically 2.5 µs

4

10

2

110

4

10

2

110

µs max

nV secs typ

dB typ

DAC Code Change All 1s to All 0s

Channel-to-Channel Isolation

V_OUT= 10 kHz Sine Wave

POWER REQUIREMENTS

V_DD

V_SS

I_DD

I_SS

+5

–5

27

15

195

+5

–5

28

15

205

V nom

mA max

mW max

±5% for Specified Performance

Cumulative Current from the Two V_DDPins

Cumulative Current from the Two V_SSPins

Typically 130 mW

Total Power Dissipation

NOTES

¹Temperature ranges are as follows: J Version: 0°C to +70°C; A Version: –40°C to +85°C; S Version: –55°C to +125°C.

²Measured with respect to REF IN and includes bipolar offset error.

³For capacitive loads greater than 50 pF, a series resistor is required (see Internal Reference section).

⁴Sample tested @ +25°C to ensure compliance.

Specifications subject to change without notice.

AD7244 ORDERING GUIDE

Temperature

Range

Integral

Nonlinearity

Package

Option²

Model¹

AD7244JN

AD7244JR

AD7244AQ

AD7244SQ³

–40°C to +85°C

–55°C to +125°C

±2 LSB max

N-24

R-28

Q-24

NOTES

¹To order MIL-STD-883, Class B, processed parts, add /883B to part number.

Contact local sales office for military data sheet and availability.

²N = Plastic DIP; Q = Cerdip; R = Small Outline IC (SOIC).

³This grade will be available to /883B processing only.

–3–

REV. A

AD7242/AD7244

TIMING CHARACTERISTICS^{1, 2}

(V_DD= +5 V ؎ 5%, V_SS= –5 V ؎ 5%, AGND = DGND = 0 V)

Limit at T_MIN, T_MAX

Parameter

(J, K, A, B Versions)

(S Version)

Units

Conditions/Comments

t₁

t₂₃

t₃

t₄

t₅

t₆

50

75

150

30

75

40

50

ns min

TFS to TCLK Falling Edge

TCLK Falling Edge to TFS

TCLK Cycle Time

Data Valid to TCLK Setup Time

Data Valid to TCLK Hold Time

LDAC Pulse Width

100

200

40

100

40

NOTES

¹Timing specifications are sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a volt-

age level of 1.6 V.

²See Figure 6.

³TCLK Mark/Space ratio is 40/60 to 60/40.

ABSOLUTE MAXIMUM RATINGS*

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C

Power Dissipation (Any Package) to +75°C . . . . . . . 550 mW

Derates above +75°C by . . . . . . . . . . . . . . . . . . . . . 6 mW/°C

(T_A= +25°C unless otherwise noted)

V_DDto AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

_SSto AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V

AGND to DGND . . . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

_OUTto AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . V_SSto V_DD

*Stresses above those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. This is a stress rating only, functional operation

of the device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

V

REF OUT to AGND . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

REF INA, REF INB to AGND . . . . . . . –0.3 V to V_DD+ 0.3 V

Digital Inputs to DGND . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V

Operating Temperature Range

J, K Versions

AD7244 . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

AD7242 . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

A, B Versions . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

S Version . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD7242/AD7244 feature proprietary ESD protection circuitry, permanent damage

may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

PIN CONFIGURATIONS

DIP

SOIC

REV. A

–4–

AD7242/AD7244

AD7242/AD7244 PIN FUNCTION DESCRIPTION

Description

DIP

Pin No.

Mnemonic

1

LDACA

Load DAC, Logic Input. A new word is transferred into DAC Latch A from input Latch A on the fall-

ing edge of this signal. If LDACA is hard-wired low, data is transferred from input Latch A to DAC

Latch A on the sixteenth falling edge of TCLKA after TFSA goes low.

2

3

4

TFSA

DTA

Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for DACA

data with serial data expected after the falling edge of this signal.

Transmit Data, Logic Input. This is the data input which is used in conjunction with TFSA and

TCLKA to transfer serial data to input Latch A.

TCLKA

Transmit Clock, Logic Input. Serial data bits for DACA are latched on the falling edge of TCLKA

when TFSA is low.

5

6

7

8

9

DGND

TP1

Digital Ground. Both DGND pins for the device must be tied together at the device.

Test Pin 1. Used when testing the device. Do not connect anything to this pin.

V_DD

Positive Power Supply, 5 V ± 5%. Both V_DDpins for the device must be tied together at the device.

Analog Ground. Both AGND pins for the device must be tied together at the device.

AGND

V_OUTB

Analog Output Voltage from DACB. This output comes from a buffer amplifier. The range is bipolar,

±3 V with REF INB = +3 V.

10

11

12

V_SS

Negative Power Supply, –5 V ± 5%. Both V_SSpins for the device must be tied together at the device.

TP2

Test Pin 2. Used when testing the device. Do not connect anything to this pin.

REF INB

DACB Voltage Reference Input. The voltage reference for DACB is applied to this pin. It is internally

buffered before being applied to DACB. The nominal reference voltage for correct operation of the

AD7242/AD7244 is 3 V.

13

LDACB

Load DAC, Logic Input. A new word is transferred into DAC Latch B from input Latch B on the fall-

ing edge of this signal. If LDACB is hard-wired low, data is transferred from input Latch B to DAC

Latch B on the sixteenth falling edge of TCLKB after TFSB goes low.

14

15

16

TFSB

DTB

Transmit Frame Synchronization, Logic Input. This is a frame or synchronization signal for DACB

data with serial data expected after the falling edge of this signal.

Transmit Data, Logic Input. This is the data input used in conjunction with TFSB and TCLKB to

transfer serial data to input Latch B.

TCLKB

Transmit Clock, Logic Input. Serial data bits for DACB are latched on the falling edge of TCLKB

when TFSB is low.

17

18

19

20

21

DGND

TP3

Digital Ground. Both DGND pins for the device must be tied together at the device.

Test Pin 3. Used when testing the device. Do not connect anything to this pin.

V_DD

Positive Power Supply, 5 V ± 5%. Both V_DDpins for the device must be tied together at the device.

Analog Ground. Both AGND pins for the device must be tied together at the device.

AGND

V_OUTA

Analog Output Voltage from DACA. This output comes from a buffer amplifier. The range is bipolar,

±3 V with REF INA = +3 V.

22

23

V_SS

Negative Power Supply, –5 V ± 5%. Both V_SSpins for the device must be tied together at the device.

REF OUT

Voltage Reference Output. To operate the DACs with this internal reference, REF OUT should be

connected to both REF INA and REF INB. The external load capability of the reference is 500 µA.

24

REF INA

DACA Voltage Reference Input. The voltage reference for DACA is applied to this pin. It is internally

buffered before being applied to DACA. The nominal reference voltage for correct operation of the

AD7242/AD7244 is 3 V.

REV. A

–5–

AD7242/AD7244

CIRCUIT DESCRIPTION

9-bit R-2R ladder structure while on the AD7244, the 11 LSBs

switch an 11-bit R-2R ladder structure. The output voltage

from this converter has the same polarity as the reference

voltage, REF IN.

The AD7242/AD7244 contains two 12-bit/14-bit D/A convert-

ers, each with an output buffer amplifier. The part also contains

a reference input buffer amplifier for each DAC, and an on-chip

3 V reference.

The REF IN voltage is internally buffered by a unity gain

amplifier before being applied to the D/A converters and the

bipolar bias circuitry. The D/A converter is configured and

scaled for a 3 V reference, and the device is tested with 3 V

applied to REF IN. Operating the AD7242/AD7244 at refer-

ence voltages outside the ±5% tolerance range may result in

degraded performance from the part.

D/A Section

The AD7242/AD7244 contains two 12-bit/14-bit voltage mode

D/A converters, each consisting of highly stable thin-film resistors

and high speed single-pole, double-throw switches. The simplified

circuit diagram for the DAC section is shown in Figure 1. The

three MSBs of the data word are decoded to drive the seven

switches A-G. On the AD7242, the 9 LSBs switch a

Figure 1. DAC Ladder Structure

Internal Reference

The on-chip reference is a temperature-compensated buried

Zener reference that is factory trimmed for 3 V ± 10 mV. The

reference can be used to provide both the reference voltage for

the two D/A converters and the bipolar biasing circuitry. This is

achieved by connecting REF OUT to REF INA and REF INB.

The reference voltage can also be used for other components

and is capable of providing up to 500 µA to an external load.

The maximum recommended capacitance on the reference

output pin for normal operation is 50 pF. If the reference

output is required to drive a capacitive load greater than 50 pF,

a 200 Ω resistor should be placed in series with the capacitive

load. Decoupling the REF OUT pin with a series 200 Ω resistor

and a parallel combination of a 10 µF tantalum capacitor and a

0.1 µF ceramic capacitor as in Figure 2 reduces the noise

spectral density of the reference (see Figure 4). Using this

decoupling scheme to generate the reference voltage for REF

INA and REF INB gives a channel-to-channel isolation number

of 110 dB (connecting REF OUT directly to REF INA and

REF INB gives 80 dB). The channel-to-channel isolation is 110

dB using an external reference.

Figure 2. Circuit Connection for REF OUT with an External

Capacitive Load of Greater Than 50 pF

External Reference

In some applications, the user may require a system reference or

some other external reference to drive the AD7242/AD7244

reference inputs. Figure 3 shows how the AD586 reference can

be conditioned to provide the 3 V reference required by the

AD7242/AD7244 reference inputs.

Figure 3. AD586 Driving AD7242/AD7244 Reference Inputs

REV. A

–6–

AD7242/AD7244

Output Amplifier

For the AD7242, the output voltage can be expressed in terms

The outputs from each of the voltage-mode DACs are buffered

by a noninverting amplifier. The buffer amplifier is capable of

developing ±3 V across a 2 kΩ and 100 pF load to ground, and

can produce 6 V peak-to-peak sine wave signals to a frequency

of 20 kHz. The output is updated on the falling edge of the

respective LDAC input. The output voltage settling time, to

within 1/2 LSB of its final value, is typically less than 2 µs for

the AD7242 and 2.5 µs for the AD7244.

of the input code, N, using the following relationship:

2 • N • REF IN

V_OUT

=

4096

where –2048 ≤ N ≤ +2047

For the AD7244, the output voltage can be expressed in terms

of the input code, N, using the following relationship:

2 • N • REF IN

The small signal (200 mV p-p) bandwidth of the output buffer

amplifier is typically 1 MHz. The output noise from the

amplifier is low, with a figure of 30 nV/√Hz at a frequency of

1 kHz. The broadband noise from the amplifier exhibits a

typical peak-to-peak figure of 150 µV for a 1 MHz output

bandwidth. Figure 4 shows a typical plot of noise spectral

density versus frequency for the output buffer amplifier and for

the on-chip reference (including and excluding the decoupling

components).

V_OUT

=

16384

where –8192 ≤ N ≤ +8191

Table I. AD7242 Ideal Input/Output Code Table Code

DAC Latch Contents

MSB

LSB

Analog Output, V_OUT*

01 11 1111 1111

01 11 1111 1110

00 00 0000 0001

00 00 0000 0000

11 11 1111 1111

10 00 0000 0001

10 00 0000 0000

+2.998535 V

+2.99707 V

+0.001465 V

0 V

–0.001465 V

–2.998535 V

–3 V

*Assuming REF IN = +3 V.

Table II. AD7244 Ideal Input/Output Code Table Code

DAC Latch Contents

MSB

LSB

Analog Output, V_OUT*

01 1111 1111 1111

01 1111 1111 1110

00 0000 0000 0001

00 0000 0000 0000

11 1111 1111 1111

10 0000 0000 0001

10 0000 0000 0000

+2.999634 V

+2.99268 V

+0.000366 V

0 V

–0.000366 V

–2.999634 V

–3 V

Figure 4. Noise Spectral Density vs. Frequency

TRANSFER FUNCTION

The basic circuit configuration for the AD7242/AD7244 is

shown in Figure 5. Table I and Table II show the ideal input

code to output voltage relationship for the AD7242 and

AD7244 respectively. Input coding for the AD7242/AD7244 is

2s complement.

*Assuming REF IN = +3 V.

Figure 5. Basic Connection Diagram

REV. A

–7–

AD7242/AD7244

TIMING AND CONTROL

timing diagram for operation of either of the two serial input

ports on the part.

Communication with the AD7242/AD7244 is via six serial logic

inputs. These consist of separate serial clocks, word framing and

data lines for each DAC. DAC updating is controlled by two

digital inputs: LDACA for updating V_OUTAand LDACB for

updating V_OUTB. These inputs can be asserted independently of

the microprocessor by an external timer when precise updating

intervals are required. Alternatively, the LDACA and LDACB

inputs can be driven from a decoded address bus allowing the

microprocessor control over DAC updating as well as data

communication to the AD7242/AD7244 input latches.

Although 16 bits of data are clocked into the input latch, only

12 bits are transferred into the DAC latch for the AD7242 and

14 bits are transferred for the AD7244. Therefore, 4 bits in the

AD7242 data stream and 2 bits in the AD7244 data stream are

don’t cares since their value does not affect the DAC latch data.

The bit positions are the don’t cares followed by the DAC data

starting with the MSB (see Figure 6).

The respective LDAC signals control the transfer of data to the

respective DAC latches. Normally, data is loaded to the DAC

latch on the falling edge of LDAC. However, if LDAC is held

low, serial data is loaded to the DAC latch on the sixteenth

falling edge of TCLK. If LDAC goes low during the loading of

serial data to the input latch, no DAC latch update takes place

on the falling edge of LDAC. If LDAC stays low until the serial

transfer is completed, then the update takes place on the sixteenth

falling edge of TCLK. If LDAC returns high before the serial

data transfer is completed, no DAC latch update takes place.

The AD7242/AD7244 contains two latches per DAC, an input

latch and a DAC latch. Data must be loaded to the input latch

under the control of TCLKA, TFSA and DTA for input Latch

A and TCLKB, TFSB and DTB for input Latch B. Data is then

transferred from input Latch A to DAC Latch A under the control

of the LDACA signal, while LDACB controls the loading of DAC

Latch B from input Latch B. Only the data held in the DAC

latches determines the analog outputs of the AD7242/AD7244.

Data is loaded to the input latches under control of the respec-

tive TCLK, TFS and DT signals. The AD7242/AD7244

expects a 16-bit stream of serial data on its DT inputs. Data

must be valid on the falling edge of TCLK. The TFS input

provides the frame synchronization signal that tells the AD7242/

AD7244 that valid serial data will be available on the DT input

for the next 16 falling edges of TCLK. Figure 6 shows the

If seventeen or more TCLK edges occur while TFS is low, the

seventeenth (and beyond) clock edges are ignored, i.e., no

further data is clocked into the input latch after the sixteenth

TCLK edge following a falling edge on TFS.

Figure 6. AD7242/AD7244 Timing Diagram

REV. A

–8–

AD7242/AD7244

MICROPROCESSOR INTERFACING

control or address line of the ADSP-2101/ADSP-2102 could be

used to drive these inputs. Alternatively, the LDACA and

LDACB inputs of the AD7242/AD7244 could be hardwired

low; in this case the update of the DAC latches and analog

outputs takes place on the 16th falling edge of SCLK (after the

respective TFS signal goes low).

Microprocessor interfacing to the AD7242/AD7244 is via a

serial bus that uses standard protocol compatible with DSP

processors and microcontrollers. The communication interface

consists of a separate transmit section for each of the DACs.

Each section has a clock signal, a data signal and a frame or

strobe pulse.

AD7242/AD7244 to DSP56000 Interface

Figures 7 through 11 show the AD7242/AD7244 configured

for interfacing to a number of popular DSP processors and

microcontrollers.

A serial interface between the AD7242/AD7244 and the

DSP56000 is shown in Figure 8. The DSP56000 is configured

for normal mode, asynchronous operation with gated clock. It is

also set up for a 16-bit word with SCK and SC2 as outputs and

the FSL control bit set to a 0. SCK is internally generated on

the DSP56000 and applied to both the TCLKA and TCLKB

inputs of the AD7242/AD7244. Data from the DSP56000 is

valid on the falling edge of SCK. The serial data line, STD

drives the DTA and DTB serial input data lines of the

AD7242/AD7244.

AD7242/AD7244 to ADSP-2101/ADSP-2102 Interface

Figure 7 shows a serial interface between the AD7242/AD7244

and the ADSP-2101/ADSP-2102 DSP processor. The ADSP-

2101/ADSP-2102 has two serial ports and, in the interface

shown, both serial ports are used, one for each DAC. Both serial

ports do not have to be used; in the case where only one serial

port is used, an extra line (DACA/DACB as shown in the other

serial interfaces) would have to decode the one TFS line to

provide TFSA and TFSB lines for the AD7242/AD7244.

The SC2 output provides the framing pulse for valid data. This

is an active high output and is gated with a DACA/DACB

control line before being applied to the TFSA and TFSB inputs

of the AD7242/AD7244. The DACA/DACB line determines

which DAC serial data is to be transferred to, i.e., which TFS

line is active when SC2 is active.

As in the previous interface, a common LDAC input is shown

driving the LDACA and LDACB inputs of the AD7242/AD7244.

Once again, these LDAC inputs could be hardwired low, in

which case V_OUTAor V_OUTBwill be updated on the sixteenth

falling edge of SCK after the TFSA or TFSB input goes low.

Figure 7. AD7242/AD7244 to ADSP-2101/ADSP-2102

Interface

The three serial lines of the first serial port, SPORT1, of the

ADSP-2101/ADSP-2102 connect directly to the three serial

input lines of DACA of the AD7242/AD7244. The three serial

lines of SPORT2 connect directly to the three serial lines on the

DACB serial input port. Data from the ADSP-2101/ADSP-2102 is

valid on the falling edge of SCLK. A common LDAC signal is

used to drive the LDACA and LDACB inputs. This is shown to

be generated from a timer or clock recovery circuit but another

Figure 8. AD7242/AD7244 to DSP56000 Interface

REV. A

–9–

AD7242/AD7244

AD7242/AD7244 to TMS320C25 Interface

output of one of the DACs will be updated on the sixteenth

falling edge of TXD after the respective TFS signal for that

DAC has gone low. Alternatively, the scheme used in previous

interfaces, whereby the LDAC inputs are driven from a timer,

can be used.

Figure 9 shows a serial interface between the AD7242/AD7244

and the TMS320C25 DSP processor. In this interface, the

CLKX and FSX signals of the TMS320C25 are generated from

the clock/timer circuitry. The FSX pin of the TMS320C25

must be configured as an input. CLKX is used to provide both

the TCLKA and TCLKB inputs of the AD7242/AD7244. DX

of the TMS320C25 is also routed to the serial data line of each

input port of the AD7242/AD7244.

Data from the TMS32020 is valid on the falling edge of CLKX

after FSX goes low. This FSX signal is gated with the DACA/

DACB control line to determine whether TFSA or TFSB goes

low when FSX goes low.

The clock/timer circuitry also generates the LDAC signal for the

AD7242/AD7244 to synchronize the update of the outputs with

the serial transmission. As in the previous interface diagrams, a

common LDAC input is shown driving the LDACA and

LDACB inputs of the AD7242/AD7244. Once again, these

LDAC inputs could be hardwired low, in which case V_OUTAor

Figure 10. AD7242/AD7244 to 87C51 Interface

V

_OUTBwill be updated on the sixteenth falling edge of CLKX

AD7242/AD7244 to 68HC11 Interface

after the TFSA or TFSB input goes low.

Figure 11 shows a serial interface between the AD7242/AD7244

and the 68HC11 microcontroller. SCK of the 68HC11 drives

TCLKA and TCLKB of the AD7242/AD7244 while the MOSI

output drives the two serial data lines of the AD7242/AD7244.

The TFSA and TFSB signals are derived from PC6 and PC7,

respectively.

For correct operation of this interface, the 68HC11 should be

configured such that its CPOL bit is a 0 and its CPHA bit is a 1.

When data is to be transmitted to the part, PC6 (for DACA) or

PC7 (for DACB) is taken low. When the 68HC11 is configured

like this, data on MOSI is valid on the falling edge of SCK. The

68HCll transmits its serial data in 8-bit bytes with only eight

falling clock edges occurring in the transmit cycle. To load data

to the AD7242/AD7244, PC6 (for DACA) or PC7 (for DACB)

is left low after the first eight bits are transferred and a second

byte of data is then serially transferred to the AD7242/AD7244.

When the second serial transfer is complete, the PC6 line (for

DACA) or the PC7 line (for DACB) is taken high.

Figure 9. AD7242/AD7244 to TMS320C25 Interface

AD7242/AD7244 to 87C51 Interface

A serial interface between the AD7242/AD7244 and the 87C51

microcontroller is shown in Figure 10. TXD of the 87C51

drives TCLKA and TCLKB of the AD7242/AD7244 while

RXD drives the two serial data lines of the part. The TFSA and

TFSB signals are derived from P3.2 and P3.3, respectively.

The 87C51 provides the LSB of its SBUF register as the first bit

in the serial data stream. Therefore, the user will have to ensure

that the data in the SBUF register is correctly arranged so the

don’t care bits are the first to be transmitted to the AD7242/

AD7244; the last bit to be sent is the LSB of the word to be

loaded to the AD7242/AD7244. When data is to be transmitted

to the part, P3.2 (for DACA) or P3.3 (for DACB) is taken low.

Data on RXD is valid on the falling edge of TXD. The 87C51

transmits its serial data in 8-bit bytes with only eight falling

clock edges occurring in the transmit cycle. To load data to the

AD7242/AD7244, P3.2 (for DACA) or P3.3 (for DACB) is left

low after the first eight bits are transferred and a second byte of

data is then serially transferred to the AD7242/AD7244. When

the second serial transfer is complete, the P3.2 line (for DACA)

or the P3.3 line (for DACB) is taken high.

Figure 11. AD7242/AD7244 to 68HC11 Interface

Figure 11 shows both LDAC inputs of the AD7242/AD7244

hardwired low. As a result, the DAC latch and the analog

output of one of the DACs will be updated on the sixteenth

falling edge of SCK after the respective TFS signal for that

DAC has gone low. Alternatively, the scheme used in previous

interfaces, whereby the LDAC inputs are driven from a timer,

can be used.

Figure 10 shows both LDAC inputs of the AD7242/AD7244

hardwired low. As a result, the DAC latch and the analog

REV. A

–10–

AD7242/AD7244

APPLYING THE AD7242/AD7244

Low impedance analog and digital power supply common

returns are essential to low noise operation of high performance

converters. Therefore, the foil width for these tracks should be

kept as wide as possible. The use of ground planes minimizes

impedance paths and also guards the analog circuitry from

digital noise.

Good printed circuit board layout is as important as the overall

circuit design itself in achieving high speed converter perfor-

mance. The AD7242 works on an LSB size of 1.465 mV, while

the AD7244 works on an LSB size of 366 µV. Therefore, the

designer must be conscious of minimizing noise in both the

converter itself and in the surrounding circuitry. Switching

mode power supplies are not recommended as the switching

spikes can feed through to the on-chip amplifier. Other causes

of concern are ground loops and digital feedthrough from

microprocessors. These are factors that influence any high

performance converter, and a proper PCB layout that minimizes

these effects is essential for best performance.

NOISE

Keep the signal leads on the V_OUTAand V_OUTBsignals and the

signal return leads to AGND as short as possible to minimize

noise coupling. In applications where this is not possible, use a

shielded cable between the DAC outputs and their destination.

Reduce the ground circuit impedance as much as possible since

any potential difference in grounds between the DAC and its

destination device appears as an error voltage in series with the

DAC output.

LAYOUT HINTS

Ensure that the layout for the printed circuit board has separated

digital and analog lines as much as possible. Take care not to

run any digital track alongside an analog signal track. Establish a

single point analog ground (star ground) separate from the logic

system ground. Place this star ground as close as possible to the

AD7242/AD7244. Connect all analog grounds to this star

ground and also connect the AD7242/AD7244 DGND pins to

this ground. Do not connect any other digital grounds to this

analog ground point.

REV. A

–11–

AD7242/AD7244

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Plastic DIP (N-24)

Cerdip (Q-24)

SOIC (R-28)

REV. A

–12–


型号：	AD7242_15
厂家：	ADI
描述：	LC MOS Dual, Complete, 12-Bit/14-Bit Serial DACs
文件：	总12页 (文件大小：321K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7242_15 [ADI]

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