AD7245AAQ [ADI]
LC2MOS 12-Bit DACPORTs; LC2MOS 12位DACPORTs型号: | AD7245AAQ |
厂家: | ADI |
描述: | LC2MOS 12-Bit DACPORTs |
文件: | 总16页 (文件大小:308K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
2
LC MOS
12-Bit DACPORTs
a
AD7245A/AD7248A
FEATURES
AD 7245A FUNCTIO NAL BLO CK D IAGRAM
12-Bit CMOS DAC w ith Output Am plifier and
Reference
Im proved AD7245/ AD7248:
12 V to 15 V Operation
؎1/ 2 LSB Linearity Grade
Faster Interface–30 ns typ Data Setup Tim e
Extended Plastic Tem perature Range (–40؇C to +85؇C)
Single or Dual Supply Operation
Low Pow er–65 m W typ in Single Supply
Parallel Loading Structure: AD7245A
(8+4) Loading Structure: AD7248A
GENERAL D ESCRIP TIO N
T he AD7245A/AD7248A is an enhanced version of the industry
standard AD7245/AD7248. Improvements include operation
from 12 V to 15 V supplies, a ±1/2 LSB linearity grade, faster
interface times and better full scale and reference variations with
AD 7248A FUNCTIO NAL BLO CK D IAGRAM
VDD. Additional features include extended temperature range
operation for commercial and industrial grades.
T he AD7245A/AD7248A is a complete, 12-bit, voltage output,
digital-to-analog converter with output amplifier and Zener volt-
age reference on a monolithic CMOS chip. No external user
trims are required to achieve full specified performance.
Both parts are microprocessor compatible, with high speed data
latches and double-buffered interface logic. T he AD7245A ac-
cepts 12-bit parallel data which is loaded into the input latch on
the rising edge of CS or WR. T he AD7248A has an 8-bit wide
data bus with data loaded to the input latch in two write opera-
tions. For both parts, an asynchronous LDAC signal transfers
data from the input latch to the DAC latch and updates the ana-
log output. T he AD7245A also has a CLR signal on the DAC latch
which allows features such as power-on reset to be implemented.
T he on-chip 5 V buried Zener diode provides a low noise, tem-
perature compensated reference for the DAC. For single supply
operation, two output ranges of 0 V to +5 V and 0 V to +10 V
are available, while these two ranges plus an additional ±5 V
range are available with dual supplies. T he output amplifiers are
capable of developing +10 V across a 2 kΩ load to GND.
SOIC and in 28-terminal surface mount packages. T he
AD7248A is packaged in a small, 0.3" wide, 20-pin DIP and
SOIC and in 20-terminal surface mount packages.
P RO D UCT H IGH LIGH TS
1. T he AD7245A/AD7248A is a 12-bit DACPORT® on a single
chip. T his single chip design and small package size offer
considerable space saving and increased reliability over
multichip designs.
T he AD7245A/AD7248A is fabricated in linear compatible
CMOS (LC2MOS), an advanced, mixed technology process that
combines precision bipolar circuits with low power CMOS logic.
T he AD7245A is available in a small, 0.3" wide, 24-pin DIP and
2. T he improved interface times on the part allows easy, direct
interfacing to most modern microprocessors.
3. T he AD7245A/AD7248A features a wide power supply range
allowing operation from 12 V supplies.
D ACP O RT is a r egister ed tr adem ar k of Analog D evices, Inc.
REV. A
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
(V = +12 V to +15 V,1 V = O V or –12 V to –15 V,1
AGND = DGND = O V, R = 2 k⍀, C = 1OO pF. All specifications TMIN to TMAX unless otherwise noted.)
AD7245A/AD7248A–SPECIFICATIONS
DD
SS
L
L
A2
B2
T2
P aram eter
Version Version
Version Units
Test Conditions/Com m ents
ST AT IC PERFORMANCE
Resolution
12
±3/4
±1
12
12
±1/2
±3/4
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
% of FSR max
% of FSR/V max
% of FSR/V max
Relative Accuracy @ +25°C3
T MIN to T MAX
±1/2
±3/4
±1/2
±1
±3
±5
±2
±4
±2
±0.2
±0.06
±0.01
±30
T MIN to T MAX
VDD = 15 V ± 5%
Differential Nonlinearity3
Unipolar Offset Error @ +25°C3
T MIN to T MAX
±1
±3
±5
±3
±5
±2
±1
±3
±5
±2
±4
±2
±0.2
±0.06
±0.01
±40
Guaranteed Monotonic
VSS = 0 V or –12 V to –15 V4
T ypical T empco is ±3 ppm of FSR5/°C.
ROFS connected to REF OUT ; VSS = –12 V to –15 V4
T ypical T empco is ±3 ppm of FSR5/°C.
Bipolar Zero Error @ +25°C3
T MIN to T MAX
DAC Gain Error3, 6
Full-Scale Output Voltage Error7 @ +25°C ±0.2
VDD = +15 V
∆Full Scale/∆VDD
±0.06
±0.01
±30
VDD = +12 V to +15 V4
VSS = –12 V to –15 V4
∆Full Scale/∆VSS
Full-Scale T emperature Coefficient8
ppm of FSR/°C max VDD = +15 V
REFERENCE OUT PUT
REF OUT @ +25°C
∆REF OUT /∆VDD
4.99/5.01 4.99/5.01 4.99/5.01 V min/V max
VDD = +15 V
2
2
2
mV/V max
VDD = +12 V to +15 V4
Reference T emperature Coefficient
Reference Load Change
(∆REF OUT vs. ∆I)
±25
±25
±35
ppm/°C typ
–1
–1
–1
mV max
Referenee Load Current Change (0–100 µA)
DIGIT AL INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
±10
8
2.4
0.8
±10
8
2.4
0.8
±10
8
V min
V max
µA max
pF max
VIN = 0 V to VDD
Input Capacitance9
ANALOG OUT PUT S
Output Range Resistors
Output Voltage Ranges10
Output Voltage Ranges10
15/30
+5, +10 +5, +10
+5, +10, +5, +10,
15/30
15/30
+5, +10
+5, +10,
±5
kΩ min/kΩ max
V
VSS = 0 V; Pin Strappable
VSS = –12 V to –15 V;4 Pin Strappable
±5
±5
V
DC Output Impedance
0.5
0.5
0.5
Ω typ
AC CHARACT ERIST ICS9
Voltage Output Settling T ime
Positive Full-Scale Change
Negative Full-Scale Change
Output Voltage Slew Rate
Digital Feedthrough3
Settling T ime to Within ±1/2 LSB of Final Value
DAC Latch All 0s to All 1s
7
7
2
10
30
7
7
2
10
30
10
10
1.5
10
30
µs max
µs max
V/µs min
nV-s typ
nV-s typ
DAC Latch All 1s to All 0s; VSS = –12 V to –15 V4
Digital-to-Analog Glitch Impulse
POWER REQUIREMENT S
VDD
+10.8/
+16.5
–10.8/
–16.5
9
+11.4/
+15.75
–11.4/
–15.75
9
+11.4/
+15.75
–11.4/
–15.75
9
V min/
V max
V min/
V max
mA max
mA max
mA max
For Specified Performance Unless Otherwise Stated
For Specified Performance Unless Otherwise Stated
VSS
IDD @ +25°C
T MlN to T MAX
ISS (Dual Supplies)
Output Unloaded; T ypically 5 mA
Output Unloaded
Output Unloaded; T ypically 2 mA
10
3
10
3
12
5
NOT ES
1Power supply tolerance is ±10% for A Version and ±5% for B and T Versions.
2T emperature ranges are as follows: A/B Versions; –40°C to +85°C; T Version; –55°C to +125°C.
3See T erminology.
4With appropriate power supply tolerances.
5FSR means Full-Scale Range and is 5 V for the 0 V to +5 V output range and 10 V for both the 0 V to +10 V and ±5 V output ranges.
6T his error is calculated with respect to the reference voltage and is measured after the offset error has been allowed for.
7T his error is calculated with respect to an ideal 4.9988 V on rhe 0 V to +5 V and ±5 V ranges; it is calculated with respect to an ideal 9.9976 V on the
0 V to +10 V range. It includes the effects of internal voltage reference, gain and offset errors.
8Full-Scale T C = ∆FS/∆T , where ∆FS is the full-scale change from T A = +25°C to T MIN or T MAX
9Sample tested at +25°C to ensure compliance.
.
100 V to +10 V output range is available only when VDD ≥ +14.25 V.
Specifications subject to change without notice.
–2–
REV. A
AD7245A/AD7248A
1
(V = +12 V to +15 V;2 V = O V or –12 V to –15 V;2 See Figures 5 and 7.)
SWITCHING CHARACTERISTICS
DD
SS
P aram eter
A, B Versions
T Version
Units
Conditions
t1
@ +25°C
T MIN to TMAX
55
80
55
100
ns typ
ns min
Chip Select Pulse Width
t2
@ +25°C
T MIN to TMAX
40
80
40
100
ns typ
ns min
Write Pulse Width
t3
@ +25°C
T MIN to TMAX
0
0
0
0
ns min
ns min
Chip Select to Write Setup T ime
Chip Select to Write Hold T ime
Data Valid to Write Setup T ime
Data Valid to Write Hold T ime
Load DAC Pulse Width
t4
@ +25°C
T MIN to TMAX
0
0
0
0
ns min
ns min
t5
@ +25°C
T MIN to TMAX
40
80
40
80
ns typ
ns min
t6
@ +25°C
T MIN to TMAX
10
10
10
10
ns min
ns min
t7
@ +25°C
T MIN to TMAX
40
80
40
100
ns typ
ns min
t8 (AD7245A only)
@ +25°C
T MIN to TMAX
40
80
40
100
ns typ
ns min
Clear Pulse Width
NOT ES
1Sample tested at +25°C to ensure compliance.
2Power supply tolerance is ±10% for A Version and ±5% for B and T Versions.
ABSO LUTE MAXIMUM RATINGS 1
Operating T emperature
Commercial (A, B Versions) . . . . . . . . . . . –40°C to +85°C
Extended (S Version) . . . . . . . . . . . . . . . –55°C to +125°C
Storage T emperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +34 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD
Digital Input Voltage to DGND . . . . . . . . –0.3 V, VDD +0.3 V
VOUT to AGND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
NOT ES
1Stresses above those listed under “Absolute Maximum Ratings” may cause per-
manent damage to the device. T his is a stress rating only and functional opera-
tion of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2T he output may be shorted to voltages in this range provided the power dissipa-
tion of the package is not exceeded. VOUT short circuit current is typically
80 mA.
2
VOUT to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, +24 V
2
VOUT to VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –32 V, 0 V
REF OUT 2 to AGND . . . . . . . . . . . . . . . . . . . . . . . . 0 V, VDD
Power Dissipation (Any Package) to +75°C . . . . . . . . 450 mW
Derates above +75°C by . . . . . . . . . . . . . . . . . . . . 6 mW/°C
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7245A/AD7248A features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. T herefore,
proper ESD precautions are recommended to avoid performance degradation or loss of function-
ality.
WARNING!
ESD SENSITIVE DEVICE
REV. A
–3–
AD7245A/AD7248A
AD 7245A O RD ERING GUID E
D AC GAIN ERRO R
DAC Gain Error is a measure of the output error between an
ideal DAC and the actual device output with all 1s loaded after
offset error has been allowed for. It is, therefore defined as:
Tem perature
Range
Relative
Accuracy
P ackage
O ption2
Modell
Measured Value—Offset—Ideal Value
AD7245AAN
AD7245ABN
AD7245AAQ
AD7245AT Q3
AD7245AAP
AD7245AAR
AD7245ABR
AD7245AT E3
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
±3/4 LSB
±1/2 LSB
±3/4 LSB
±3/4 LSB
±3/4 LSB
±3/4 LSB
±1/2 LSB
±3/4 LSB
N-24
N-24
Q-24
Q-24
P-28A
R-24
where the ideal value is calculated relative to the actual refer-
ence value.
UNIP O LAR O FFSET ERRO R
Unipolar Offset Error is a combination of the offset errors of the
voltage mode DAC and the output amplifier and is measured
when the part is configured for unipolar outputs. It is present
for all codes and is measured with all 0s in the DAC register.
R-24
E-28A
NOT ES
BIP O LAR ZERO O FFSET ERRO R
1T o order MIL-ST D-883, Class B. processed parts, add /883B to part number.
Contact our local sales office for military data sheet and availability.
2E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip
Carrier; Q = Cerdip; R = SOIC.
Bipolar Zero Offset Error is measured when the part is config-
ured for bipolar output and is a combination of errors from the
DAC and output amplifier. It is present for all codes and is
measured with a code of 2048 (decimal) in the DAC register.
3T his grade will be available to /883B processing only.
SINGLE SUP P LY LINEARITY AND GAIN ERRO R
AD 7248A O RD ERING GUID E
T he output amplifier of the AD7245A/AD7248A can have a
true negative offset even when the part is operated from a single
positive power supply. However, because the lower supply rail
to the part is 0 V, the output voltage cannot actually go nega-
tive. Instead the output voltage sits on the lower rail and this re-
sults in the transfer function shown. T his is an offset effect and
the transfer function would have followed the dotted line if the
output voltage could have gone negative. Normally, linearity is
measured after offset and full scale have been adjusted or al-
lowed for. On the AD7245A/AD7248A the negative offset is al-
lowed for by calculating the linearity from the code which the
amplifier comes off the lower rail. T his code is given by the
negative offset specification. For example, the single supply lin-
earity specification applies between Code 3 and Code 4095 for
the 25°C specification and between Code 5 and Code 4095 over
the T MIN to TMAX temperature range. Since gain error is also
measured after offset has been allowed for, it is calculated between
the same codes as the linearity error. Bipolar linearity and gain er-
ror are measured between Code 0 and Code 4095.
Tem perature
Range
Relative
Accuracy
P ackage
O ption2
Modell
AD7248AAN
AD7248ABN
AD7248AAQ
AD7248AT Q3
AD7248AAP
AD7248AAR
AD7248ABR
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
±3/4 LSB
±1/2 LSB
±3/4 LSB
±3/4 LSB
±3/4 LSB
±3/4 LSB
±1/2 LSB
N-20
N-20
Q-20
Q-20
P-20A
R-20
R-20
NOT ES
1T o order MIL-ST D-883, Class B, processed parts, add /883B to part number.
Contact our local sales office for military data sheet and availability.
2N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = SOIC.
3T his grade will be available to /883B processing only.
TERMINO LO GY
RELATIVE ACCURACY
Relative Accuracy, or end-point nonlinearity, is a measure of the
actual deviation from a straight line passing through the end-
points of the DAC transfer function. It is measured after allow-
ing for zero and full scale and is normally expressed in LSBs or
as a percentage of full-scale reading.
OUTPUT
VOLTAGE
D IFFERENTIAL NO NLINEARITY
Differential Nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB max over
the operating temperature range ensures monotonicity.
0V
DAC CODE
NEGATIVE
OFFSET
{
D IGITAL FEED TH RO UGH
Digital Feedthrough is the glitch impulse injected from the digi-
tal inputs to the analog output when the inputs change state. It
is measured with LDAC high and is specified in nV-s.
–4–
REV. A
AD7245A/AD7248A
AD 7248A P IN FUNCTIO N D ESCRIP TIO N
(D IP P IN NUMBERS)
P in
Mnem onic D escription
P in
Mnem onic D escription
19
WR
Write Input (Active LOW). T his is used in
conjunction with CS to write data into the
input latch of the AD7245A.
l
VSS
Negative Supply Voltage (0 V for single
supply operation).
2
3
ROFS
Bipolar Offset Resistor. T his provides
access to the on-chip application resistors
and allows different output voltage ranges.
20
21
LDAC
Load DAC Input (Active LOW). T his is
an asynchronous input which when active
transfers data from the input latch to the
DAC latch.
REF OUT
Reference Output. T he on-chip reference
is provided at this pin and is used when
configuring the part for bipolar outputs.
CLR
Clear Input (Active LOW). When this in-
put is active the contents of the DAC latch
are reset to all 0s.
4
5
AGND
DB11
Analog Ground.
Data Bit 11. Most Significant Bit (MSB).
22
23
VDD
RFB
Positive Supply Voltage.
6-11 DB10-DB5 Data Bit 10 to Data Bit 5.
Feedback Resistor. T his allows access to
the amplifier’s feedback loop.
12
DGND
Digital Ground.
24
VOUT
Output Voltage. T hree different output
voltage ranges can be chosen: 0 V to +5 V,
0 V to +10 V or –5 V to +5 V.
13-16 DB4-DB1
Data Bit 4 to Data Bit 1.
Data Bit 0. Least Significant Bit (LSB).
17
18
DB0
CS
Chip Select Input (Active LOW). T he de-
vice is selected when this input is active.
AD 7245A P IN CO NFIGURATIO NS
D IP and SO IC
LCCC
P LCC
REV. A
–5–
AD7245A/AD7248A
AD 7248A P IN FUNCTIO N D ESCRIP TIO N
(ANY P ACKAGE)
P in
Mnem onic D escription
P in
Mnem onic D escription
l
VSS
Negative Supply Voltage (0 V for single
supply operation).
14
CSMSB
CSLSB
WR
Chip Select Input for MS Nibble. (Active
LOW). T his selects the upper 4 bits of the
input latch. Input data is right justified.
2
3
ROFS
Bipolar Offset Resistor. T his provides
access to the on-chip application resistors
and allows different output voltage ranges.
15
16
17
Chip Select Input for LS byte. (Active
LOW). T his selects the lower 8 bits of the
input latch.
REF OUT
Reference Output. T he on-chip reference
is provided at this pin and is used when
configuring the part for bipolar outputs.
Write Input. T his is used in conjunction
with CSMSB and CSLSB to load data
into the input latch of the AD7248A.
4
5
AGND
DB7
Analog Ground.
Data Bit 7.
LDAC
Load DAC Input (Active LOW). T his is
an asynchronous input which when active
transfers data from the input latch to the
DAC latch.
6
DB6
Data Bit 6.
7
DB5
Data Bit 5.
18
19
VDD
RFB
Positive Supply Voltage.
8
DB4
Data Bit 4.
Feedback Resistor. T his allows access to
the amplifier’s feedback loop.
9
DB3
Data Bit 3.
10
11
12
13
DGND
DB2
Digital Ground.
Data Bit 2/Data Bit 10.
Data Bit 1/Data Bit 9.
Data Bit 0 (LSB)/Data Bit 8.
20
VOUT
Output Voltage. T hree different output
voltage ranges can be chosen: 0 V to +5 V,
0 V to +10 V or –5 V to +5 V.
DB1
DB0
AD 7248A P IN CO NFIGURATIO NS
LCCC
D IP and SO IC
P LCC
–6–
REV. A
Typical Performance–AD7245A/AD7248A
Power Supply Current vs. Tem perature
Reference Voltage vs. Tem perature
Noise Spectral Density vs. Frequency
Power Supply Rejection Ration vs. Frequency
Positive-Going Settling Tim e
(VDD = +15 V, VSS = –15 V)
Negative Going Settling Tim e
(VDD = +15 V, VSS = –15 V)
REV. A
–7–
AD7245A/AD7248A
CIRCUIT INFO RMATIO N
T he small signal (200 mV p-p) bandwidth of the output buffer
amplifier is typically 1 MHz. T he output noise from the ampli-
fier is low with a figure of 25 nV/√Hz at a frequency of 1 kHz.
T he broadband noise from the amplifier has a typical peak-to-
peak figure of 150 µV for a 1 MHz output bandwidth. T here is
no significant difference in the output noise between single and
dual supply operation.
D /A SECTIO N
T he AD7245A/AD7248A contains a 12-bit voltage mode digi-
tal-to-analog converter. T he output voltage from the converter
has the same positive polarity as the reference voltage allowing
single supply operation. T he reference voltage for the DAC is
provided by an on-chip buried Zener diode.
T he DAC consists of a highly stable, thin-film, R–2R ladder and
twelve high-speed NMOS single-pole, double-throw switches.
T he simplified circuit diagram for this DAC is shown in Figure 1.
VO LTAGE REFERENCE
T he AD7245A/AD7248A contains an internal low noise buried
Zener diode reference which is trimmed for absolute accuracy
and temperature coefficient. T he reference is internally con-
nected to the DAC. Since the DAC has a variable input imped-
ance at its reference input the Zener diode reference is buffered.
T his buffered reference is available to the user to drive the cir-
cuitry required for bipolar output ranges. It can be used as a ref-
erence for other parts in the system provided it is externally
buffered. T he reference will give long-term stability comparable
with the best discrete Zener reference diodes. T he performance
of the AD7245A/AD7248A is specified with internal reference,
and all the testing and trimming is done with this reference. T he
reference should be decoupled at the REF OUT pin and recom-
mended decoupling components are 10 µF and 0.1 µF capaci-
tors in series with a 10 Ω resistor. A simplified schematic of the
reference circuitry is shown in Figure 3.
Figure 1. D/A Sim plified Circuit Diagram
T he input impedance of the DAC is code dependent and can
vary from 8 kΩ to infinity. T he input capacitance also varies
with code, typically from 50 pF to 200 pF.
O P AMP SECTIO N
T he output of the voltage mode D/A converter is buffered by a
noninverting CMOS amplifier. T he user has access to two gain
setting resistors which can be connected to allow different out-
put voltage ranges (discussed later). T he buffer amplifier is ca-
pable of developing up to 10 V across a 2 kΩ load to GND.
T he output amplifier can be operated from a single positive
power supply by tying VSS = AGND = 0 V. T he amplifier can
also be operated from dual supplies to allow a bipolar output
range of –5 V to +5 V. T he advantages of having dual supplies
for the unipolar output ranges are faster settling time to voltages
near 0 V, full sink capability of 2.5 mA maintained over the en-
tire output range and elimination of the effects of negative offset
on the transfer characteristic (outlined previously). Figure 2
shows the sink capability of the amplifier for single supply
operation.
Figure 3. Internal Reference
D IGITAL SECTIO N
T he AD7245A/AD7248A digital inputs are compatible with ei-
ther T T L or 5 V CMOS levels. All data inputs are static pro-
tected MOS gates with typical input currents of less than 1 nA.
T he control inputs sink higher currents (150 µA max) as a result
of the fast digital interfacing. Internal input protection of all
logic inputs is achieved by on-chip distributed diodes.
T he AD7245A/AD7248A features a very low digital feedthrough
figure of 10 nV-s in a 5 V output range. T his is due to the volt-
age mode configuration of the DAC. Most of the impulse is ac-
tually as a result of feedthrough across the package.
INTERFACE LO GIC INFO RMATIO N—AD 7245A
T able I shows the truth table for AD7245A operation. T he part
contains two 12-bit latches, an input latch and a DAC latch. CS
and WR control the loading of the input latch while LDAC con-
trols the transfer of information from the input latch to the
DAC latch. All control signals are level triggered; and therefore,
either or both latches may be made transparent, the input latch
by keeping CS and WR “LOW”, the DAC latch by keeping
LDAC “LOW.” Input data is latched on the rising edge of WR.
Figure 2. Typical Single Supply Sink Current vs.
Output Voltage
–8–
REV. A
AD7245A/AD7248A
T he data held in the DAC latch determines the analog output of
the converter. Data is latched into the DAC latch on the rising
edge of LDAC. T his LDAC signal is an asynchronous signal
and is independent of WR. T his is useful in many applications.
However, in systems where the asynchronous LDAC can occur
during a write cycle (or vice versa) care must be taken to ensure
that incorrect data is not latched through to the output. For ex-
ample, if LDAC goes LOW while WR is “LOW”, then the
LDAC signal must stay LOW for t7 or longer after WR goes
high to ensure correct data is latched through to the output.
Table I. AD 7245A Truth Table
CLR LDAC WR
CS
Function
H
H
H
H
H
H
H
L
L
L
L
Both Latches are T ransparent
Both Latches are Latched
Both Latches are Latched
Input Latches T ransparent
Input Latches Latched
DAC Latches T ransparent
DAC Latches Latched
DAC Latches Loaded with all 0s
DAC Latches Latched with All
0s and Output Remains at
0 V or –5 V
H
H
H
H
L
g
X
H
H
X
L
X
H
L
Figure 5. AD7245A Write Cycle Tim ing Diagram
g
L
H
H
X
H
H
H
X
H
INTERFACE LO GIC INFO RMATIO N—AD 7248A
T he input loading structure on the AD7248A is configured for
interfacing to microprocessors with an 8-bit wide data bus. T he
part contains two 12-bit latches—an input latch and a DAC
latch. Only the data held in the DAC latch determines the ana-
log output from the converter. T he truth table for AD7248A
operation is shown in T able II, while the input control logic dia-
gram is shown in Figure 6.
g
g
L
L
L
Both Latches are T ransparent
and Output Follows Input Data
H = High State L = Low State X = Don’t Care
T he contents of the DAC latch are reset to all 0s by a low level
on the CLR line. With both latches transparent, the CLR line
functions like a zero override with the output brought to 0 V in
the unipolar mode and –5 V in the bipolar mode for the dura-
tion of the CLR pulse. If both latches are latched, a “LOW”
pulse on the CLR input latches all 0s into the DAC latch and
the output remains at 0 V (or –5 V) after the CLR line has re-
turned “HIGH.” T he CLR line can be used to ensure powerup
to 0 V on the AD7245A output in unipolar operation and is also
useful, when used as a zero override, in system calibration
cycles.
Figure 4 shows the input control logic for the AD7245A and the
write cycle timing for the part is shown in Figure 5.
Figure 6. AD7248A Input Control Logic
CSMSB, CSLSB and WR control the loading of data from the
external data bus to the input latch. T he eight data inputs on
the AD7248A accept right justified data. T his data is loaded to
the input latch in two separate write operations. CSLSB and
WR control the loading of the lower 8-bits into the 12-bit wide
latch. T he loading of the upper 4-bit nibble is controlled by
CSMSB and WR. All control inputs are level triggered, and in-
put data for either the lower byte or upper 4-bit nibble is latched
into the input latches on the rising edge of WR (or either
CSMSB or CSLSB). T he order in which the data is loaded to
the input latch (i.e., lower byte or upper 4-bit nibble first) is not
important.
Figure 4. AD7245A Input Control Logic
T he LDAC input controls the transfer of 12-bit data from the
input latch to the DAC latch. T his LDAC signal is also level
triggered, and data is latched into the DAC latch on the rising
edge of LDAC. T he LDAC input is asynchronous and indepen-
dent of WR. T his is useful in many applications especially in
REV. A
–9–
AD7245A/AD7248A
the simultaneous updating of multiple AD7248A outputs. How-
ever, in systems where the asynchronous LDAC can occur dur-
ing a write cycle (or vice versa) care must be taken to ensure
that incorrect data is not latched through to the output. In other
words, if LDAC goes low while WR and either CS input are low
(or WR and either CS go low while LDAC is low), then the
LDAC signal must stay low for t7 or longer after WR returns
high to ensure correct data is latched through to the output.
T he write cycle timing diagram for the AD7248A is shown in
Figure 7.
UNIP O LAR (0 V TO +10 V) CO NFIGURATIO N
T he first of the configurations provides an output voltage range
of 0 V to +10 V. T his is achieved by connecting the bipolar off-
set resistor, ROFS, to AGND and connecting RFB to VOUT . In
this configuration the AD7245A/AD7248A can be operated
single supply (VSS = 0 V = AGND). If dual supply performance
is required, a VSS of –12 V to –15 V should be applied. Figure 8
shows the connection diagram for unipolar operation while the
table for output voltage versus the digital code in the DAC latch
is shown in T able III.
Figure 7. AD7248A Write Cycle Tim ing Diagram
Figure 8. Unipolar (0 to +10 V) Configuration
An alternate scheme for writing data to the AD7248A is to tie
the CSMSB and LDAC inputs together. In this case exercising
CSLSB and WR latches the lower 8 bits into the input latch.
T he second write, which exercises CSMSB, WR and LDAC
loads the upper 4-bit nibble to the input latch and at the same
time transfers the 12-bit data to the DAC latch. T his automatic
transfer mode updates the output of the AD7248A in two write
operations. T his scheme works equally well for CSLSB and
LDAC tied together provided the upper 4-bit nibble is loaded to
the input latch followed by a write to the lower 8 bits of the in-
put latch.
Table III. Unipolar Code Table (0 V to +10 V Range)
D AC Latch Contents
MSB
LSB
Analog O utput, VO UT
4095
1 1 1 1
1 0 0 0
1 0 0 0
0 1 1 1
1 1 1 1
0 0 0 0
0 0 0 0
1 1 1 1
1 1 1 1
0 0 0 1
0 0 0 0
1 1 1 1
+2 VREF
+2 VREF
+2 VREF
+2 VREF
+2 VREF
؋
؋
؋
؋
4096
2049
4096
Table II. AD 7248A Truth Table
2048
4096
= +VREF
CSLSB CSMSB WR LDAC Function
L
L
g
H
H
H
H
H
H
H
H
H
L
L
g
H
H
L
L
g
L
L
g
L
H
H
L
H
H
H
H
H
H
L
I.oad LS Byte into Input Latch
2047
4096
Latches LS Byte into Input Latch
Latches LS Byte into Input Latch
Loads MS Nibble into Input Latch
Latches MS Nibble into Input Latch
Latches MS Nibble into Input Latch
Loads Input Latch into DAC Latch
Latches Input Latch into DAC Latch
Loads MS Nibble into Input Latch and
1
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 0
؋
4096
0 V
g
L
1
NOT E: 1 LSB = 2
؋
VREF(2–12) = VREF Loads Input Latch into DAC Latch
No Data T ransfer Operation
2048
H
H
H
H
UNIP O LAR (0 V TO +5 V) CO NFIGURATIO N
H = High State L = Low State
T he 0 V to +5 V output voltage range is achieved by tying ROFS
RFB and VOUT together. For this output range the AD7245A/
AD7248A can be operated single supply (VSS = 0 V) or dual
supply. T he table for output voltage versus digital code is as in
T able III, with 2 • VREF replaced by VREF. Note that for this
range
,
AP P LYING TH E AD 7245A/AD 7248A
T he internal scaling resistors provided on the AD7245A/
AD7248A allow several output voltage ranges. T he part can
produce unipolar output ranges of 0 V to +5 V or 0 V to +10 V
and a bipolar output range of –5 V to +5 V. Connections for the
various ranges are outlined below.
1
.
1 LSB = VREF(2–12) = VREF
؋
4096
–10–
REV. A
AD7245A/AD7248A
BIP O LAR CO NFIGURATIO N
T he bipolar configuration for the AD7245A/AD7248A, which
gives an output voltage range from –5 V to +5 V, is achieved by
connecting the ROFS input to REF OUT and connecting RFB
and VOUT . T he AD7245A/AD7248A must be operated from
dual supplies to achieve this output voltage range. T he code
table for bipolar operation is shown in T able IV.
Table IV. Bipolar Code Table
D AC Latch Contents
MSB
LSB
Analog O utput, VO UT
2047
1 1 1 1
1 1 1 1
1 1 1 1
+VREF
+VREF
×
2048
1
Figure 9. AGND Bias Circuit
P RO GRAMMABLE CURRENT SINK
1 0 0 0
1 0 0 0
0 0 0 0
0 0 0 0
0 0 0 1
0 0 0 0
×
2048
0 V
Figure 10 shows how the AD7245A/AD7248A can be config-
ured with a power MOSFET transistor, the VN0300M, to pro-
vide a programmable current sink from VDD or VSOURCE. T he
VN0300M is placed in the feedback of the AD7245A/
AD7248A amplifier. T he entire circuit can be operated in single
supply by tying the VSS of the AD7245A/AD7248A to AGND.
T he sink current, ISINK, can be expressed as:
1
0 1 1 1
0 0 0 0
0 0 0 0
1 1 1 1
0 0 0 0
0 0 0 0
1 1 1 1
0 0 0 1
0 0 0 0
–VREF
–VREF
–VREF
×
×
×
2048
2047
2048
2048
2048
D ×VREF
= –VREF
ISINK
=
R1
1
NOT E: 1 LSB = 2 × VREF(2–11) = VREF
2048
AGND BIAS
T he AD7245A/AD7248A AGND pin can be biased above sys-
tem GND (AD7245A/AD7248A DGND) to provide an offset
“zero” analog output voltage level. With unity gain on the am-
plifier (ROFS = VOUT = RFB) the output voltage, VOUT is ex-
pressed as:
VOUT = VBIAS + D
؋
VREF where D is a fractional representation of the digital word in the
DAC latch and VBIAS is the voltage applied to the AD7245A/
AD7248A AGND pin.
Because the current flowing out of the AGND pin varies with
digital code, the AGND pin should be driven from a low imped-
ance source. A circuit configuration is outlined for AGND bias
in Figure 9 using the AD589, a +1.23 V bandgap reference.
Figure 10. Program m able Current Sink
Using the VN0300M, the voltage drop across the load can typi-
cally be as large as VSOURCE –6 V) with VOUT of the DAC at
+5 V. T herefore, for a current of 50 mA flowing in the R1 (with
all 1s in the DAC register) the maximum load is 200 Ω with
VSOURCE = +15 V. T he VN0300M can actually handle currents
up to 500 mA and still function correctly in the circuit, but in
practice the circuit must be used with larger values of VSOURCE
otherwise it requires a very small load.
If a gain of 2 is used on the buffer amplifier the output voltage,
VOUT is expressed as
VOUT = 2(VBIAS + D
؋
VREF )
In this case care must be taken to ensure that the maximum out-
put voltage is not greater than VDD –3 V. T he VDD–VOUT over-
head must be greater than 3 V to ensure correct operation of the
part. Note that VDD and VSS for the AD7245A/AD7248A must
be referenced to DGND (system GND). T he entire circuit can
be operated in single supply with the VSS pin of the AD7245A/
AD7248A connected to system GND.
Since the tolerance value on the reference voltage of the
AD7245A/AD7248A is ±0.2%, then the absolute value of ISINK
can vary by ±0.2% from device to device for a fixed value of R1.
Because the input bias current of the AD7245A/AD7248A’s op
amp is only of the order of picoamps, its effect on the sink cur-
rent is negligible. T ying the ROFS input to RFB input reduces this
effect even further and prevents noise pickup which could occur
if the ROFS pin was left unconnected.
REV. A
–11–
AD7245A/AD7248A
T he circuit of Figure 10 can be modified to provide a program-
mable current source to AGND or –VSINK (for –VSINK, dual sup-
plies are required on the AD7245A/AD7248A). T he AD7245A/
AD7248A is configured as before. T he current through R1 is
mirrored with a current mirror circuit to provide the program-
mable source current (see CMOS DAC Application Guide,
Publication No. G872-30-10/84, for suitable current mirror cir-
cuit). As before the absolute value of the source current will be
affected by the ±0.2% tolerance on VREF. In this case the per-
formance of the current mirror will also affect the value of the
source current.
MICRO P RO CESSO R INTERFACING—AD 7245
AD 7245A—8086A INTERFACE
Figure 12 shows the 8086 16-bit processor interfacing to the
AD7245A. In the setup shown the double buffering feature of
the DAC is not used and the LDAC input is tied LOW. AD0–
AD11 of the 16-bit data bus are connected to the AD7245A
data bus (DB0-DB11). T he 12-bit word is written to the
AD7245A in one MOV instruction and the analog output re-
sponds immediately. In this example the DAC address is D000.
A software routine for Figure 12 is given in T able V.
FUNCTIO N GENERATO R WITH P RO GRAMMABLE
FREQ UENCY
Figure 11 shows how the AD7245A/AD7248A with the AD537,
voltage-to-frequency converter and the AD639, trigonometric
function generator to provide a complete function generator
with programmable frequency. T he circuit provides square
wave, triwave and sine wave outputs, each output of ±10 V
amplitude.
T he AD7245A/AD7248A provides a programmable voltage to
the AD537 input. Since both the AD7245A/AD7248A and
AD537 are guaranteed monotonic, the output frequency will al-
ways increase with increasing digital code. T he AD537 provides
a square wave output which is conditioned for ±10 V by ampli-
fier A1. T he AD537 also provides a differential triwave output.
T his is conditioned by amplifiers A2 and A3 to provide the
±1.8 V triwave required at the input of the AD639. T he triwave
is further scaled by amplifier A4 to provide a ±10 V output.
Figure 12. AD7245A to 8086 Interface
Table V. Sam ple P rogram for Loading AD 7245A from 8086
ASSUME D S: D ACLO AD , CS: D ACLO AD
D ACLO AD SEGMENT AT 000
Adjusting the triwave applied to the AD639 adjust the distortion
performance of the sine wave output, (+10 V in configuration
shown). Amplitude, offset and symmetry of the triwave can af-
fect the distortion. By adjusting these, via VR1 and VR2, an
output sine wave with harmonic distortion of better than –50 dB
can be achieved at low and intermediate frequencies.
00 8CC9
MOV CS,
CS
: DEFINE DAT A SEGMENT
REGIST ER
02 8ED9
MOV DS,
CX
: EQUAL T O CODE
SEGMENT REGIST ER
Using the capacitor value shown in Figure 11 for CF (i.e.,
680 pF) the output frequency range is 0 to 100 kHz over the
digital input code range. T he step size for frequency increments
is 25 Hz. T he accuracy of the output frequency is limited to 8 or
9 bits by the AD537, but is guaranteed monotonic to 12 bits.
04 BF00D0 0MOV DI, : LOAD DI WIT H D000
# D000
07 C705
MOV MEM, : DAC LOADED WIT H WXYZ
“YZWX” # YZWX
0B EA00 00
0E 00 FF
: CONT ROL IS RET URNED T O
T HE MONIT OR PROGRAM
Figure 11. Program m able Function Generator
–12–
REV. A
AD7245A/AD7248A
In a multiple DAC system the double buffering of the AD7245A
allows the user to simultaneously update all DACs. In Figure
13, a 12-bit word is loaded to the input latches of each of the
DACs in sequence. T hen, with one instruction to the appropri-
ate address, CS4 (i.e., LDAC) is brought LOW, updating all the
DACs simultaneously.
Table Vl. Sam ple Routine for Loading AD 7245A from 68000
01000 MOVE.W
# X,D0
T he desired DAC data, X,
is loaded into Data Re-
gister 0. X may be any
value between 0 and 4094
(decimal) or 0 and OFFF
(hexadecimal).
MOVE.W
D0,$E000
T he Data X is transferred
between D0 and the
DAC Latch.
MOVE.B
T RAP
# 228,D7
# 14
Control is returned to the
System Monitor Program
using these two
instructions.
MICRO P RO CESSO R INTERFACE—AD 7248A
Figure 15 shows the connection diagram for interfacing the
AD7248A to both the 8085A and 8088 microprocessors. T his
scheme is also suited to the Z80 microprocessor, but the Z80
address/data bus does not have to be demultiplexed. Data to be
loaded to the AD7248A is right justified. T he AD7248A is
memory mapped with a separate memory address for the input
latch high byte, the input latch low byte and the DAC latch.
Data is first written to the AD7248A input latch in two write
operations. Either the high byte or the low byte data can be
written first to the AD7248A input latch. A write to the
AD7248A DAC latch address transfers the input latch data to
the DAC latch and updates the output voltage. Alternatively,
the LDAC input can be asynchronous or can be common to a
number of AD7248As for simultaneous updating of a number of
voltage channels.
Figure 13. AD7245A to 8086 Multiple DAC Interface
AD 7245A—MC68000 INTERFACE
Interfacing between the MC68000 and the AD7245A is accom-
plished using the circuit of Figure 14. Once again the AD7245A
is used in the single buffered mode. A software routine for load-
ing data to the AD7245A is given in T able VI. In this example
the AD7245A is located at address E000, and the 12-bit word is
written to the DAC in one MOVE instruction.
Figure 15. AD7248A to 8085A/8088 Interface
A connection diagram for the interface between the AD7248A
and 68008 microprocessor is shown in Figure 16. Once again
the AD7248A acts as a memory mapped device and data is right
justified. In this case the AD7248A is configured in the auto-
matic transfer mode which means that the high byte of the input
latch has the same address as the DAC latch. Data is written to
the AD7248A by first writing data to the AD7248A low byte.
Writing data to the high byte of the input latch also transfers the
input latch contents to the DAC latch and updates the output.
Figure 14. AD7245A to 68000 Interface
REV. A
–13–
AD7245A/AD7248A
Figure 18 shows a connection diagram between the AD7248A
and the 8051 microprocessor. T he AD7248A is port mapped in
this interface and is configured in the automatic transfer mode.
Data to be loaded to the input latch low byte is output to Port 1.
Output Line P3.0, which is connected to CSLSB of the
AD7248A, is pulsed to load data into the low byte of the input
latch. Pulsing the P3.1 line, after the high byte data has been set
up on Port 1, updates the output of the AD7248A. T he WR in-
put of the AD7248A can be hardwired low in this application
because spurious address strobes on CSLSB and CSMSB do not
occur.
Figure 16. AD7248A to 68008 Interface
An interface circuit for connections to the 6502 or 6809 micro-
processors is shown in Figure 17. Once again, the AD7248A is
memory mapped and data is right justified. T he procedure for
writing data to the AD7248A is as outlined for the 8085A/8088.
For the 6502 microprocessor the φ2 clock is used to generate
the WR, while for the 6809 the E signal is used.
Figure 18. AD7248A to MCS-51 Interface
Figure 17. AD7248A to 6502/6809 Interface
–14–
REV. A
AD7245A/AD7248A
MECH ANICAL INFO RMATIO N—AD 7245A
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
24-P in P lastic D IP (N-24)
24-P in SO IC (R-24) P ackage
24-P in Cer dip (Q -24)
28-Ter m inal
P lastic Leaded
Chip Car r ier (P -28A)
28-Ter m inal
Leadless Cer am ic Chip
Car r ier (E-28A)
REV. A
–15–
AD7245A/AD7248A
MECH ANICAL INFO RMATIO N —AD 7248A
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
20-P in P lastic D IP (N-20)
20-P in Cer dip (Q -20)
20-Ter m inal
P lastic Leaded
20-Lead SO IC (R-20)
Chip Car r ier (P -20A)
–16–
REV. A
相关型号:
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明