AD725ARZ-RL [ADI]
Low Cost RGB to NTSC/PAL Encoder with Luma Trap Port; 低成本RGB转NTSC / PAL编码器，亮度陷阱端口
| 型号： | AD725ARZ-RL |
| 厂家： | 
ADI |
| 描述： | Low Cost RGB to NTSC/PAL Encoder with Luma Trap Port |
| 文件： | 总20页 (文件大小：222K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Cost RGB to NTSC/PAL Encoder
with Luma Trap Port
a
AD725
FEATURES
P RO D UCT D ESCRIP TIO N
Com posite Video Output: Both NTSC and PAL
Chrom inance and Lum inance (S-Video) Outputs
Lum a Trap Port to Elim inate Cross Color Artifacts
TTL Logic Levels
Integrated Delay Line and Auto-Tuned Filters
Drives 75 ⍀ Reverse-Term inated Loads
Low Pow er +5 V Operation
T he AD725 is a very low cost general purpose RGB to NT SC/
PAL encoder that converts red, green and blue color compo-
nent signals into their corresponding luminance (baseband
amplitude) and chrominance (subcarrier amplitude and phase)
signals in accordance with either NT SC or PAL standards.
T hese two outputs are also combined on-chip to provide a
composite video output. All three outputs are available sepa-
rately at voltages of twice the standard signal levels as re-
quired for driving 75 Ω, reverse-terminated cables.
Pow er-Dow n to <1 A
Very Low Cost
T he AD725 features a luminance trap (YT RAP) pin that pro-
vides a means of reducing cross color generated by subcarrier
frequency components found in the luminance signal. For por-
table or other power-sensitive applications, the device can be
powered down to less than 1 µA of current consumption. All
logic levels are T T L compatible thus supporting the logic re-
quirements of 3 V CMOS systems.
APPLICATIONS
RGB/ VGA to NTSC/ PAL Encoding
Personal Com puters/ Netw ork Com puters
Video Gam es
Video Conference Cam eras
Digital Still Cam eras
T he AD725 is packaged in a low cost 16-lead SOIC and oper-
ates from a +5 V supply.
FUNCTIO NAL BLO CK D IAGRAM
NTSC/PAL
CSYNC
BURST
HSYNC
VSYNC
SYNC
SEPARATOR
XNOR
4FSC
CSYNC
NTSC/PAL
4FSC CLOCK
FSC 90؇C/270؇C
FSC 90
؇
C
؎
180؇C
QUADRATURE
(PAL ONLY)
4FSC
+4
FSC 0؇C
DECODER
CLOCK
AT 8FSC
CSYNC
2-POLE
LP POST-
FILTER
3-POLE
LP PRE-
FILTER
SAMPLED-
DATA
DELAY LINE
Y
DC
CLAMP
LUMINANCE
OUTPUT
RED
X2
LUMINANCE
TRAP
COMPOSITE
OUTPUT
NTSC/PAL
U
V
⌺
X2
X2
RGB-TO-YUV
ENCODING
MATRIX
U
4-POLE
LPF
DC
CLAMP
CLAMP
GREEN
BLUE
BALANCED
MODULATORS
4-POLE
LPF
CHROMINANCE
OUTPUT
V
DC
CLAMP
4-POLE
LPF
CLAMP
BURST
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
(Unless otherwise noted, V = +5, T = +25؇C, using 4FSC synchronous clock. All loads are
S
A
150 ⍀ ؎ 5% at the IC pins. Outputs are measured at the 75 ⍀ reverse terminated load.)
AD725–SPECIFICATIONS
P aram eter
Conditions
Min
Typ
Max Units
SIGNAL INPUT S (RIN, GIN, BIN)
Input Amplitude
Full Scale
714
mV p-p
V
MΩ
pF
Black Level1
0.8
5
Input Resistance2
Input Capacitance
RIN, GIN, BIN
1
LOGIC INPUTS (HSYNC, VSYNC, 4FSC, CE, STND)
Logic Low Input Voltage
T T L Logic Levels
1
V
Logic High Input Voltage
2
V
Logic Low Input Current (DC)
Logic High Input Current (DC)
1
1
µA
µA
VIDEO OUT PUT S3
Luminance (LUMA)
Bandwidth, –3 dB
NT SC
PAL
4.4
5.2
–2
0.3
279
291
1.3
MHz
MHz
%
Gain Error
Nonlinearity
Sync Level
–7
+7
max p-p
NT SC
PAL
%
252
264
310
325
mV
mV
V
DC Black Level
Luminance T rap (YT RAP)
Output Resistance
DC Black Level
1.0
1.0
kΩ
V
Chrominance (CRMA)
Bandwidth, –3 dB
NT SC
PAL
NT SC
PAL
NT SC
PAL
1.2
1.5
255
291
2.51
2.28
–4
±3
2.0
15
MHz
MHz
mV p-p
mV p-p
µs
µs
%
Degrees
V
mV p-p
Color Burst Amplitude
Color Burst Width
206
221
305
362
Chroma Level Error4
Chroma Phase Error5
DC Black Level
Chroma Feedthrough
Composite (COMP)
Absolute Gain Error
Differential Gain
Differential Phase
DC Black Level
Chroma/Luma T ime Alignment
R, G, B = 0
40
With Respect to Luma
With Respect to Chroma
With Respect to Chroma
–5
–1
+3
%
%
0.5
1.5
1.4
20
Degrees
V
ns
S-Video
POWER SUPPLIES
Recommended Supply Range
Quiescent Current—Encode Mode
Quiescent Current—Power Down
Single Supply
+4.75
+5.25
36
V
mA
µA
30
<1
NOT ES
1R, G, and B signals are inputted via an external ac coupling capacitor.
2Except during dc restore period (back porch clamp).
3All outputs measured at a 75 Ω reverse-terminated load; ac voltages at the IC output pins are twice those specified here.
4Difference between ideal and actual color bar subcarrier amplitudes.
5Difference between ideal and actual color bar subcarrier phases.
Specifications are subject to change without notice.
–2–
REV. 0
AD725
ABSO LUTE MAXIMUM RATINGS*
P IN CO NFIGURATIO N
16-Lead Wide Body (SO IC)
(R-16)
Supply Voltage, APOS to AGND . . . . . . . . . . . . . . . . . . +6 V
Supply Voltage, DPOS to DGND . . . . . . . . . . . . . . . . . . +6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Inputs . . . . . . . . . . . . . . . . . . . DGND – 0.3 to DPOS + 0.3 V
Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . . 800 mW
Operating T emperature Range . . . . . . . . . . . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . . . . . –65°C to +125°C
Lead T emperature Range (Soldering 30 sec) . . . . . . . . +230°C
16
15
1
2
HSYNC
VSYNC
DPOS
STND
AGND
4FSC
3
4
5
6
7
8
14
13
AD725
DGND
APOS
CE
TOP VIEW
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. T his is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
12 YTRAP
(Not to Scale)
RIN
GIN
BIN
11
10
9
LUMA
COMP
CRMA
T hermal Characteristics: 16-Pin SOIC Package: θJA = 100°C/W.
O RD ERING GUID E
Tem perature
Range
P ackage
D escription
P ackage
O ption
Model
AD725AR
–40°C to +85°C 16-Lead SOIC
R-16
R-16
R-16
AD725AR-Reel –40°C to +85°C 16-Lead SOIC
AD725AR-Reel7 –40°C to +85°C 16-Lead SOIC
AD725-EB
Evaluation Board
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD725 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD725
P IN D ESCRIP TIO NS
P in Mnem onic
D escription
Equivalent Circuit
1
ST ND
Encoding Standard Pin. A Logic HIGH input selects NT SC encoding.
A Logic LOW input selects PAL encoding.
T T L Logic Levels.
Circuit A
2
3
AGND
4FSC
Analog Ground Connection.
4FSC Clock Input.
Circuit A
Circuit A
For NT SC: 14.318 180 MHz.
For PAL: 17.734 475 MHz.
T T L Logic Levels.
4
5
APOS
CE
Analog Positive Supply (+5 V ± 5%).
Chip Enable. A Logic HIGH input enables the encode function.
A Logic LOW input powers down chip when not in use.
T T L Logic Levels.
6
RIN
Red Component Video Input.
0 mV to 714 mV AC-Coupled.
Circuit B
Circuit B
Circuit B
Circuit C
Circuit C
Circuit C
7
GIN
Green Component Video Input.
0 mV to 714 mV AC-Coupled.
8
BIN
Blue Component Video Input.
0 mV to 714 mV AC-Coupled.
9
CRMA
COMP
LUMA
Chrominance Output.*
Approximately 1.8 V peak-to-peak for both NT SC and PAL.
10
11
Composite Video Output.*
Approximately 2.5 V peak-to-peak for both NT SC and PAL.
Luminance plus CSYNC Output.*
Approximately 2 V peak-to-peak for both NT SC and PAL.
12
13
14
15
16
YT RAP
DGND
DPOS
Luminance Trap Filter Tap. Attach L-C resonant network to reduce cross-color artifacts. Circuit D
Digital Ground Connection.
Digital Positive Supply (+5 V ± 5%).
VSYNC
HSYNC
Vertical Sync Signal (if using external CSYNC set at > +2 V). TTL Logic Levels.
Horizontal Sync Signal (or CSYNC signal). T T L Logic Levels.
Circuit A
Circuit A
*T he Luminance, Chrominance and Composite Outputs are at twice normal levels for driving 75 Ω reverse-terminated lines.
APOS
DPOS
APOS DPOS
DPOS
DPOS
1k⍀
12
6
7
8
1
3
9
10
11
AGND
DGND
5
DGND
AGND
DGND
DGND
15
16
V
CLAMP
Circuit A
Circuit B
Circuit C
Circuit D
Figure 1. Equivalent Circuits
REV. 0
–4–
Typical Characteristics–AD725
+5V
COMPOSITE
SYNC
TEKTRONIX
TG2000
SIGNAL
GENERATION
PLATFORM
COMPOSITE
VIDEO
SONY
MONITOR
MODEL
AD725
RGB TO
NTSC/PAL
ENCODER
RGB
PVM-1354Q
3
75⍀
4FSC
GENLOCK
75⍀
FSC
(3.579545MHz
OR
4.433618MHz)
OSCILLATOR
FSC
HP3314A
؋
4 PLL TEKTRONIX
VM700A
WAVEFORM
MONITOR
Figure 2. Evaluation Setup
1.0
1.0
APL = 50.8%
525 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00V @ 6.63
APL = 50.6%
625 LINE PAL NO FILTERING
SLOW CLAMP TO 0.00V @ 6.72
s
s
100
50
0.5
0.0
0.5
0.0
0
–50
–0.5
–0.5
0
10
20
30
s
40
50
60
0
10
20
30
µs
40
50
60
Figure 5. 100% Color Bars, PAL
Figure 3. 100% Color Bars, NTSC
Figure 4. 100% Color Bars on Vector Scope, NTSC
Figure 6. 100% Color Bars on Vector Scope, PAL
–5–
REV. 0
AD725–Typical Characteristics
1.0
1.0
0.5
APL = 46.6%
APL = 33.5%
525 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00V
@ 6.63s
625 LINE PAL NO FILTERING
SLOW CLAMP TO 0.00V
@ 6.72 s
100
50
0.5
0.0
0.0
0
–50
–0.5
–0.5
0
10
20
30
40
50
60
0
10
20
30
40
50
60
s
s
Figure 7. Modulated Pulse and Bar, NTSC
Figure 9. Modulated Pulse and Bar, PAL
200mV
1s
200mV
1s
Figure 10. Zoom on Modulated Pulse, PAL
Figure 8. Zoom on Modulated Pulse, NTSC
REV. 0
–6–
AD725
1.0
1.0
APL = 48.2%
625 LINE PAL NO FILTERING
APL = 48.2%
525 LINE NTSC NO FILTERING
SLOW CLAMP TO 0.00V @ 6.63s
100
100
SLOW CLAMP TO 0.00V @ 6.72s
0.5
0.0
0.5
0.0
50
0
50
0
1MHz
2MHz
3MHz
4MHz
5MHz
6MHz
0.5MHz 1MHz 2MHz 3MHz 4MHz 5MHz
–50
–50
–0.5
–0.5
0
10
20
30
s
40
50
60
0
10
20
30
s
40
50
60
Figure 14. Multiburst, PAL
Figure 11. Multiburst, NTSC
H TIMING MEASUREMENT RS–170A (NTSC)
FIELD = 1 LINE = 22
H TIMING (PAL)
LINE = 25
9.35s
5.57s
5.67s
2.29s
9.0
CYCLES
4.90s
4.80s
273.4mV
36.1 IRE
70ns
85ns
89ns
38.0 IRE
89ns
287.7mV
AVERAGE Ն 256
AVERAGE Ն 256
Figure 12. Horizontal Tim ing, NTSC
Figure 15. Horizontal Tim ing, PAL
DG DP (NTSC)
DIFFERENTIAL GAIN (%)
0.00
0.5
0.4
0.3
Wfm —
MAX = 0.39
0.20 0.22
>
MOD 5 STEP
DG DP (PAL)
DIFFERENTIAL GAIN (%)
Wfm —> MOD 5 STEP
MIN = –0.05
–0.05
pk–pk/MAX = 0.44
0.39
MIN = –0.06 MAX = 0.43
0.15 0.23 0.43
pk–pk = 0.49
0.38
0.07
0.00
–0.06
0.5
0.4
0.3
0.2
0.2
0.1
0.1
0.0
0.0
–0.1
–0.2
–0.1
–0.2
DIFFERENTIAL PHASE (deg)
DIFFERENTIAL PHASE (deg)
MIN = –0.33
0.10
MAX = 1.17
0.70 1.05
pk–pk = 1.50
1.17
MIN = –0.44 MAX = 1.34
–0.02 0.70 1.17
pk–pk = 1.79
1.34
–0.33
–0.44
0.00
0.00
2.0
1.5
2.0
1.5
1.0
1.0
0.5
0.5
0.0
0.0
–0.5
–1.0
–0.5
–1.0
1ST
2ND
3RD
4TH
5TH
6TH
1ST
2ND
3RD
4TH
5TH
6TH
Figure 13. Com posite Output Differential Phase
and Gain, NTSC
Figure 16. Com posite Output Differential Phase
and Gain, PAL
REV. 0
–7–
AD725
Following the dc clamps, the RGB inputs are buffered and split
into two signal paths for constructing the luminance and
chrominance outputs.
TH EO RY O F O P ERATIO N
T he AD725 is a predominantly analog design, with digital logic
control of timing. T his timing logic is driven by a external fre-
quency reference at four times the color subcarrier frequency,
input into the 4FSC pin of the AD725. T his frequency should
be 14.318 180 MHz for NT SC encoding, and 17.734 475 MHz
for PAL encoding. The 4FSC input accepts standard TTL logic
levels. The duty cycle of this input clock is not critical, but a fast-
edged clock should be used to prevent excessive jitter in the timing.
Lum inance Signal P ath
T he luminance path begins with the luma (Y) matrix. T his
matrix combines the RGB inputs to form the brightness infor-
mation in the output video. T he inputs are combined by the
standard transformation
Y = 0.299 × R + 0.587 × G + 0.114 × B
T he AD725 accepts two common sync standards, composite
sync or separate horizontal and vertical syncs. T o use an exter-
nal composite sync, a logic high signal is input to the VSYNC
pin and the composite sync is input to the HSYNC pin. If sepa-
rate horizontal and vertical syncs are available, the horizontal
sync can be input to the HSYNC pin and vertical sync to the
VSYNC pin. Internally, the device XNORs the two sync inputs
to combine them into one negative-going composite sync.
T his equation describes the sensitivity of the human eye to the
individual component colors, combining them into one value of
brightness. T he equation is balanced so that full-scale RGB
inputs give a full-scale Y output.
Following the luma matrix, the composite sync is added. T he
user-supplied sync (from the HSYNC and VSYNC inputs) is
latched into the AD725 at half the master clock rate, gating a
sync pulse into the luminance signal. With the exception of
transitioning on the clock edges, the output sync timing will be
in the same format as the input sync timing. T he output sync
level will depend on the encoding standard, 286 mV (40 IRE)
for NT SC and 300 mV for PAL (voltages at the pin will be
twice these levels).
T he AD725 detects the falling sync pulse edges, and times their
width. A sync pulse of standard horizontal width will cause the
insertion of a colorburst vector into the chroma modulators at
the proper time. A sync pulse outside the detection range will
cause suppression of the color burst, and the device will enter its
vertical blanking mode. During this mode, the on-chip RC time
constants are verified using the input frequency reference, and
the filter cutoff frequencies are retuned as needed.
In order to be time-aligned with the filtered chrominance signal
path, the luma signal must be delayed before it is output. T he
AD725 uses a sampled delay line to achieve this delay.
T he component color inputs, RIN, GIN and BIN, receive ana-
log signals specifying the desired active video output. T he full-
scale range of the inputs is 0.714 mV (for either NT SC or PAL
operation). External black level is not important as these inputs
are terminated externally, and then ac coupled to the AD725.
Following the luma matrix and prior to this delay line, a prefilter
removes higher frequencies from the luma signal to prevent aliasing
by the sampled delay line. This three-pole Bessel low-pass filter has
a –3 dB frequency of 4.85 MHz for NTSC, 6 MHz for PAL.
T he AD725 contains on-chip RGB input clamps to restore the
dc level on-chip to match its single supply signal path. T his dc
restore timing is coincident with the burst flag, starting approxi-
mately 5.5 µs after the falling sync edge and lasting for 2.5 µs.
During this time, the device should be driven with a black input.
After the luma prefilter, the bandlimited luma signal is sampled
onto a set of capacitors at twice the master reference clock rate.
After an appropriate delay, the data is read off the delay line,
reconstructing the luma signal. T he 8FSC oversampling of this
delay line limits the amount of jitter in the reconstructed sync
output. T he clocks driving the delay line are reset once per
video line during the burst flag. T he output of the luma path
will remain unchanged during this period and will not respond
to changing RGB inputs.
NTSC/PAL
POWER AND GROUNDS
CSYNC
BURST
HSYNC
VSYNC
SYNC
SEPARATOR
+5V
+5V
LOGIC
XNOR
4FSC
CSYNC
ANALOG
ANALOG
LOGIC
NTSC/PAL
AGND
DGND
4FSC CLOCK
FSC 90؇C/270؇C
FSC 90
؇C
؎180؇C
NOTE:
QUADRATURE
(PAL ONLY)
4FSC
+4
THE LUMINANCE, COMPOSITE AND CHROMINANCE
OUTPUTS ARE AT TWICE NORMAL LEVELS FOR
DRIVING 75⍀ REVERSE-TERMINATED LINES.
FSC 0؇C
DECODER
CLOCK
AT 8FSC
CSYNC
2-POLE
LP POST-
FILTER
SAMPLED-
DATA
DELAY LINE
3-POLE
LP PRE-
FILTER
Y
DC
CLAMP
LUMINANCE
OUTPUT
RED
X2
LUMINANCE
TRAP
COMPOSITE
OUTPUT
NTSC/PAL
U
V
⌺
RGB-TO-YUV
ENCODING
MATRIX
X2
X2
U
4-POLE
LPF
DC
CLAMP
CLAMP
GREEN
BLUE
BALANCED
MODULATORS
4-POLE
LPF
CHROMINANCE
OUTPUT
V
DC
CLAMP
4-POLE
LPF
CLAMP
BURST
Figure 17. Functional Block Diagram
–8–
REV. 0
AD725
level during this time. T he offset cancellation occurs after each
falling sync edge, approximately 350 ns after the falling sync
edge, lasting for a period of 140 ns. If the inputs are unbalanced
during this time (for example, if a sync-on-green RGB input
were used), there will be an offset in this chrominance response
of the inputs during the remainder of the horizontal line, includ-
ing the colorburst.
T he reconstructed luma signal is then smoothed with a two pole
Bessel low-pass filter. T his filter has a –3 dB bandwidth of
5.25 MH z for NT SC, 6.5 MHz for PAL. A final buffer pro-
vides current drive for the LUMA output pin.
Chr om inance Signal P ath
T he chrominance path begins with the U and V color-difference
matrices. T he AD725 uses U and V modulation vectors for
NT SC and PAL (+U being defined as 0 degrees phase), simpli-
fying the design compared to I and Q designs. T he U and V ma-
trices combine the RGB inputs by the standard transformations:
T he U signal is sampled by the sine clock and the V signal is
sampled by the cosine clock in the modulators, after which they
are summed to form the chrominance (C) signal.
T he chrominance signal then passes through a final four-pole
modified Bessel low-pass filter to remove the harmonics of the
switching modulation. T his filter has a –3 dB frequency of
4.4 MHz for NT SC and 5.9 MHz for PAL. A final buffer pro-
vides current drive for the CRMA output pin.
U = 0.493 × (B – Y)
V = 0.877 × (R – Y)
T he Y signal in these transformations is provided by the lumi-
nance matrix.
Before modulation, the U and V signals are prefiltered to pre-
vent aliasing. T hese four-pole modified Bessel low-pass filters
have a –3 dB bandwidth of 1.2 MHz for NT SC and 1.5 MHz
for PAL.
Com posite O utput
T o provide a composite video output, the separate (S-Video)
luminance and chrominance signal paths are summed. Prior to
summing, however, a filter tap for removing cross-color artifacts
in the receiver is provided.
Between the prefilters and the modulators, the colorburst vec-
tors are added to the U and V signals. T he colorburst levels are
defined according to the encoding standard. For NT SC, the
colorburst is in the –U direction (with no V component) with a
resultant amplitude of 286 mV (40 IRE) at 180 degrees phase.
For PAL, the colorburst has equal parts of –U and ±V vectors
(changing V phase every line) for a resultant amplitude of
300 mV alternating between 135 and 225 degrees phase (volt-
ages at the pin will be twice these levels).
T he luminance path contains a resistor, output pin (YT RAP),
and buffer prior to entering the composite summer. By connecting
an inductor and capacitor on this pin, an R-L-C series-resonant
circuit can be tuned to null out the luminance frequency
response at the chrominance subcarrier frequency (3.579 545 MHz
for NT SC, 4.433 618 MHz for PAL). T he center frequency (fC)
of this filter will be determined by the external inductor and
capacitor by the equation:
T he burst gate timing is generated by waiting for a certain num-
ber of reference clock cycles following the falling sync edge. If
the sync pulse width is measured to be outside the standard
horizontal width, it is assumed that the device is in an h/2 period
(vertical blanking interval) and the burst is suppressed.
1
fC
=
2 π LC
It can be seen from this equation that the center frequency of
the trap is entirely dependent on external components.
T he U and V signals are used to modulate a pair of quadrature
clocks (sine and cosine) at one-fourth the reference frequency
input (3.579 545 MHz for NT SC, 4.433618 MHz for PAL).
For PAL operation, the phase of the cosine (V) clock is changed
after each falling sync edge is detected. T his will change the
V-vector phase in PAL mode every horizontal line. By driving
the AD725 with an odd number of sync edges per field, any
individual line will flip phase each field as required by the standard.
T he ratio of center frequency to bandwidth of the notch (Q =
fC /BW) can be described by the equation:
1
L
C
Q =
1000
When choosing the Q of the filter, it should be kept in mind that
the sharper the notch, the more critical the tolerance of the
components must be in order to target the subcarrier frequency.
Additionally, higher Q notches will exhibit a transient response
with more ringing after a luminance step. T he magnitude of this
ringing can be large enough to cause visible shadowing for Q
values much greater than 1.5.
In order to suppress the carriers in the chrominance signal, the
U and V modulators are balanced. Once per horizontal line the
offsets in the modulators are cancelled in order to minimize
residual subcarrier when the RGB inputs are equal. T his offset
cancellation also provides a dc restore for the U and V signal
paths, so it is important that the RGB inputs be held at black
REV. 0
–9–
AD725
HSYNC/VSYNC
(USER INPUTS)
tSW
RIN/GIN BIN
(USER INPUTS)
tSB
tSM
MODULATOR
RESTORE
tMW
tSR
INPUT
CLAMPS
tRW
BURST FLAG/
DELAY LINE RESET
tSD
tDW
tSS
tBY
LUMA
CRMA
tBC
tSC
Figure 18. Tim ing Diagram (Not to Scale)
Table I. Tim ing D escription (See Figure 18)
Sym bol
Nam e
D escription
Input valid sync width for burst
NTSC1
P AL2
tSW
Sync Width
Min
Max
2.8 µs
5.3 µs
Min
Max
3.3 µs
5.4 µs
insertion (user-controlled).
tSB
Sync to Blanking
End
Minimum sync to color delay
(user-controlled).
Min
8.2 µs
392 ns
140 ns
5.4 µs
2.5 µs
5.7 µs
Min
8.1 µs
298 ns
113 ns
5.6 µs
2.3 µs
5.8 µs
tSM
tMW
tSR
Sync to Modulator
Restore
Delay to modulator clamp start.
Modulator Restore
Width
Length of modulator offset clamp
(no chroma during this period).
Sync to RGB DC
Restore
Delay to input clamping start.
tRW
tSD
DC Restore Width
Length of input clamp (no RGB
response during this period).
Sync to Delay Line
Reset
Delay to start of delay line
clock reset.
tDW
Delay Line Reset
Width
Length of delay line clock reset
(no luma response during this
period), also burst gate.
2.5 µs
310 ns
340 ns
5.8 µs
360 ns
2.3 µs
265 ns
280 ns
5.9 µs
300 ns
tSS
tBY
tSC
tBC
Sync Input to Luma
Sync Output
Delay from sync input assertion
to sync in LUMA output.
typ
typ
typ
typ
typ
typ
typ
typ
Blanking End to
LUMA Start
Delay from RGB input assertion
to LUMA output response.
Sync to Colorburst
Delay from valid horizontal sync
start to CRMA colorburst output.
Blanking End to
CRMA Start
Delay from RGB input assertion
to CRMA output response.
NOT ES
1Input clock = 14.318180 MHz, ST ND pin = logic high.
2Input cock = 17.734475 MHz, ST ND pin = logic low.
REV. 0
–10–
AD725
AP P LYING TH E AD 725
Inputs
T he AD725 will operate with subcarrier frequencies that deviate
quite far from those specified by the T V standards. However,
the monitor will in general not be quite so forgiving. Most moni-
tors can tolerate a subcarrier frequency that deviates several hun-
dred Hz from the nominal standard without any degradation in
picture quality. T hese conditions imply that the subcarrier fre-
quency accuracy is a system specification and not a specification
of the AD725 itself.
RIN, BIN, GIN are analog inputs that should be terminated to
ground with 75 Ω in close proximity to the IC. When properly
terminated the peak-to-peak voltage for a maximum input level
should be 714 mV p-p. T he horizontal blanking interval should
be the most negative part of each signal.
T he inputs should be held at the input signal’s black level dur-
ing the horizontal blanking interval. T he internal dc clamps will
clamp this level during color burst to a reference that is used
internally as the black level. Any noise present on the RIN,
GIN, BIN or AGND pins during this interval will be sampled
onto the input capacitors. T his can result in varying dc levels
from line to line in all outputs, or if imbalanced, subcarrier
feedthrough in the COMP and CRMA outputs.
The STND pin is used to select between NTSC and PAL opera-
tion. Various blocks inside the AD725 use this input to program
their operation. Most of the more common variants of NTSC and
PAL are supported. There are, however, two known specific stan-
dards which are not supported by the standard AD725. These are
NTSC 4.43 and M-PAL.
Basically these two standards use most of the features of the
standard that their names imply, but use the subcarrier that is
equal to or approximately equal to the frequency of the other
standard. Because of the automatic programming of the filters in
the chrominance path and other timing considerations, a factory-
programmed special version of the AD725 is necessary to sup-
port these standards.
For increased noise rejection, larger input capacitors are desired.
A capacitor of 0.1 µF is usually adequate.
Similarly, the U and V clamps balance the modulators during an
interval shortly after the falling CSYNC input. Noise present
during this interval will be sampled in the modulators, resulting
in residual subcarrier in the COMP and CRMA outputs.
Layout Consider ations
HSYNC and VSYNC are two logic level inputs that are com-
bined internally to produce a composite sync signal. If a com-
posite sync signal is to be used, it can be input to HSYNC while
VSYNC is pulled to logic HI (> +2 V).
T he AD725 is an all CMOS mixed signal part. It has separate
pins for the analog and digital +5 V and ground power supplies.
Both the analog and digital ground pins should be tied to the
ground plane by a short, low inductance path. Each power
supply pin should be bypassed to ground by a low inductance
0.1 µF capacitor and a larger tantalum capacitor of about 10 µF.
T he form of the input sync signal(s) will determine the form of
the composite sync on the composite video (COMP) and lumi-
nance (LUMA) outputs. If no equalization or serration pulses
are included in the HSYNC input there won’t be any in the
outputs. Although sync signals without equalization and serra-
tion pulses do not technically meet the video standards’ specifi-
cations, many monitors do not require these pulses in order to
display good pictures. T he decision whether to include these
signals is a system trade-off between cost and complexity and
adhering strictly to the video standards.
T he three analog inputs (RIN, GIN, BIN) should be terminated
with 75 Ω to ground close to the respective pins. However, as
these are high impedance inputs, they can be in a loop-through
configuration. T his technique is used to drive two or more
devices with high frequency signals that are separated by some
distance. A connection is made to the AD725 with no local
termination, and the signals are run to another distant device
where the termination for these signals is provided.
T he HSYNC and VSYNC logic inputs have a small amount of
built-in hysteresis to avoid interpreting noisy input edges as
multiple sync edges. This is critical to proper device operation, as
the sync pulses are timed for vertical blanking interval detection.
T he output amplitudes of the AD725 are double that required
by the devices that it drives. T his compensates for the halving of
the signal levels by the required terminations. A 75 Ω series
resistor is required close to each AD725 output, while 75 Ω to
ground should terminate the far end of each line.
T he logic inputs have been designed for VIL < 1.0 V and VIH
> 2.0 V for the entire temperature and supply range of opera-
tion. T his allows the AD725 to directly interface to T T L or 3 V
CMOS compatible outputs, as well as 5 V CMOS outputs
where VOL is less than 1.0 V.
T he outputs have a dc bias and must be ac coupled for proper
operation. The COMP and LUMA outputs have information
down to 30 Hz for NTSC (25 MHz for PAL) that must be trans-
mitted. Each output requires a 220 µF series capacitor to work
with the 75 Ω resistance to pass these low frequencies. The CRMA
signal has information mostly up at the chroma frequency and
can use a smaller capacitor if desired, but 220 µF can be used to
minimize the number of different components used in the design.
T he NTSC specification calls for a frequency accuracy of ±10 Hz
from the nominal subcarrier frequency of 3.579545 MHz. While
maintaining this accuracy in a broadcast studio might not be a
severe hardship, it can be quite expensive in a low cost con-
sumer application.
REV. 0
–11–
AD725
D isplaying VGA O utput on a TV
system, the internal 4FSC (14.318 180 MHz) clock that drives
the VGA controller can be used for 4FSC on the AD725. This
signal is not directly accessible from outside the computer, but it
does appear on the VGA card. (A 1FSC-input encoder, the
AD724, is also available.)
T he AD725 can be used to convert the analog RGB output from a
personal computer’s VGA card to the NT SC or PAL television
standards. T o accomplish this it is important to understand that
the AD725 requires interlaced RGB video and clock rates that
are consistent with those required by the television standards.
In most computers the default output is a noninterlaced RGB
signal at a frame rate higher than used by either NT SC or PAL.
If a separate RGB monitor is also to be used, it is not possible to
simply connect it to the R, G and B signals. T he monitor pro-
vides a termination that would double terminate these signals.
T he R, G, and B signals should be buffered by three amplifiers
with high input impedances. T hese should be configured for a
gain of two, which is normalized by the divide by two termina-
tion scheme used for the RGB monitor.
Most VGA controllers support a wide variety of output modes
that are controlled by altering the contents of internal registers.
It is best to consult with the VGA controller manufacturer to
determine the exact configuration required to provide an inter-
laced output at 60 Hz (50 Hz for PAL).
T he AD8073 is a low cost triple video amplifier that can pro-
vide the buffering required in this application. However, since
the R, G and B signals go all the way to ground during horizon-
tal sync, the AD8073 will require a –5 V supply to handle these
signals. T o be able to buffer the R, G and B signals using a
single supply, a rail-to-rail amplifier is required. In this applica-
tion, the AD8051 (single) and AD8052 (dual) can be used to
provide the three required channels. T hese can be operated on a
single supply of 3 V to 5 V.
Figure 19 shows a circuit for connection to the VGA port of a
PC. T he RGB outputs are ac coupled to the respective inputs of
the AD725. T hese signals should each be terminated to ground
with 75 Ω.
T he standard 15-pin VGA connector has HSYNC on Pin 13
and VSYNC on Pin 14. T hese signals also connect directly to
the same name signals on the AD725. For a synchronous NTSC
+5V
+5V
10F
10F
0.1F
0.1F
14
4
DPOS
APOS
5
6
POWER DOWN
CE
0.1F
RIN
GIN
BIN
75⍀
0.1F
COMPOSITE
VIDEO
10
CMPS
7
0.1F
220F
AD725
8
16
15
HSYNC
VSYNC
4FSC
75⍀
75⍀
Y
11
9
LUMA
CRMA
+5V
75⍀
75⍀
75⍀
220F
220F
4FSC CLOCK
OSC
14.318180MHz (NTSC)
OR
0.1F
C
17.734475MHz (PAL)
STND
68H
9pF
47k⍀
S-VIDEO
(Y/C VIDEO)
YTRAP
NTSC/PAL
18pF
1N4148
+5V (V
)
AA
DGND
AGND
0.1F
13
2
VGA OUTPUT
CONNECTOR
75⍀
1/3
AD8073
1k⍀
1k⍀
VSYNC
HSYNC
FROM VGA PORT
75⍀
1/3
AD8073
B
75⍀
1k⍀
1k⍀
G
75⍀
75⍀
1/3
AD8073
R
75⍀
0.1F
–5V
RGB MONITOR
1k⍀
1k⍀
Figure 19. Interfacing the AD725 to the (Interlaced) VGA Port of a PC
REV. 0
–12–
AD725
Low Cost Cr ystal O scillator
to as S-video or Y/C video. Since the luminance and chromi-
nance are already separated, the monitor does not have to per-
form this function. T he S-video outputs of the AD725 can be
used to create higher quality pictures when there is an S-video
input available on the monitor.
A low cost oscillator can be made that provides a CW clock that
can be used to drive both the AD725 4FSC and other devices in
the system that require a clock at this frequency. Figure 20 shows a
circuit that uses one inverter of a 74HC04 package to create a
crystal oscillator and another inverter to buffer the oscillator
and drive other loads. T he logic family must be a CMOS type
that can support the frequency of operation, and it must NOT
be a Schmitt trigger type of inverter. Resistor R1 from input to
output of U1A linearizes the inverter’s gain such that it provides
useful gain and a 180 degree phase shift to drive the oscillator.
Flicker
In a VGA conversion application, where the software controlled
registers are correctly set, there are two techniques that are
commonly used by VGA controller manufacturers to generate
the interlaced signal. Each of these techniques introduces a
unique characteristic into the display created by the AD725.
T he artifacts described below are not due to the encoder or its
encoding algorithm as all encoders will generate the same dis-
play when presented with these inputs. T hey are due to the
method used by the controller display chip to convert a non-
interlaced output to an interlaced signal.
R1
1M⍀
TO PIN 3
OF AD725
U1A
HC04
U1B
HC04
R2
200⍀
TO OTHER
DEVICE CLOCKS
Y1
T he first interlacing technique outputs a true interlaced signal
with odd and even fields (one each to a frame Figure 21a). T his
provides the best picture quality when displaying photography,
CD video and animation (games, etc.). However, it will intro-
duce a defect commonly referred to as flicker into the display.
Flicker is a fundamental defect of all interlaced displays and is
caused by the alternating field characteristic of the interlace
technique. Consider a one pixel high black line which extends
horizontally across a white screen. T his line will exist in only
one field and will be refreshed at a rate of 30 Hz (25 Hz for
PAL). During the time that the other field is being displayed the
line will not be displayed. T he human eye is capable of detect-
ing this, and the display will be perceived to have a pulsating or
flickering black line. T his effect is highly content sensitive and
is most pronounced in applications in which text and thin
horizontal lines are present. In applications such as CD video,
photography and animation, portions of objects naturally
occur in both odd and even fields and the effect of flicker is
imperceptible.
C3
15pF
(OPT)
C1
47pF
C2
60pF
~
Figure 20. Low Cost Crystal Oscillator
T he crystal should be a parallel resonant type at the appropriate
frequency (NTSC/PAL, 4FSC). The series combination of C1
and C2 should approximately equal to the crystal manufacturer’s
specification for the parallel capacitance required for the crystal
to operate at its specified frequency. C1 will usually want to be
a somewhat smaller value because of the input parasitic capaci-
tance of the inverter. If it is desired to tune the frequency to
greater accuracy, C1 can be made still smaller and a parallel
adjustable capacitor can be used to adjust the frequency to the
desired accuracy.
Resistor R2 serves to provide the additional phase shift
required by the circuit to sustain oscillation. It can be sized by
R2 = 1/(2 × π × f × C2). Other functions of R2 are to provide a
low pass filter that suppresses oscillations at harmonics of the
fundamental of the crystal and to isolate the output of the in-
verter from the resonant load that the crystal network presents.
The second commonly used technique is to output an odd and
even field that are identical (Figure 21b). This ignores the data
that naturally occurs in one of the fields. In this case the same
one pixel high line mentioned above would either appear as a
two pixel high line, (one pixel high in both the odd and even field)
or not appear at all if it is in the data that is ignored by the control-
ler. Which of these cases occurs is dependent on the placement
of the line on the screen. T his technique provides a stable (i.e.,
nonflickering) display for all applications, but small text can be
difficult to read and lines in drawings (or spreadsheets) can
disappear. As above, graphics and animation are not particularly
affected although some resolution is lost.
T he basic oscillator described above is buffered by U1B to drive
the AD725 4FSC pin and other devices in the system. For a
system that requires both an NT SC and PAL oscillator, the
circuit can be duplicated by using a different pair of inverters
from the same package.
D ot Cr awl
T here are numerous distortions that are apparent in the presen-
tation of composite signals on T V monitors. T hese effects will
vary in degree depending on the circuitry used by the monitor
to process the signal and on the nature of the image being dis-
played. It is generally not possible to produce pictures on a
composite monitor that are as high quality as those produced by
standard quality RGB, VGA monitors.
There are methods to dramatically reduce the effect of flicker and
maintain high resolution. The most common is to ensure that
display data never exists solely in a single line. This can be accom-
plished by averaging/weighting the contents of successive/multiple
noninterlaced lines prior to creating a true interlaced output (Fig-
ure 21c). In a sense, this provides an output that will lie between
the two extremes described above. The weight or percentage of
one line that appears in another, and the number of lines used,
are variables that must be considered in developing a system of
this type. If this type of signal processing is performed, it must
be completed prior to the data being presented to the AD725
for encoding.
One well known distortion of composite video images is called
dot crawl. It shows up as a moving dot pattern at the interface
between two areas of different color. It is caused by the inability
of the monitor circuitry to adequately separate the luminance
and chrominance signals.
One way to prevent dot crawl is to use a video signal that has
separate luminance and chrominance. Such a signal is referred
REV. 0
–13–
AD725
NONINTERLACED
ODD FIELD
EVEN FIELD
Ver tical Scaling
1
2
3
4
5
6
7
1
3
5
7
In addition to converting the computer generated image from
noninterlaced to interlaced format, it is also necessary to scale
the image down to fit into NT SC or PAL format. T he most
common vertical lines/screen for VGA display are 480 and 600
lines. NT SC can only accommodate approximately 400 visible
lines/frame (200 per field), PAL can accommodate 576 lines/
frame (288 per field). If scaling is not performed, portions of
the original image will not appear in the television display.
2
4
6
=
+
a. Conversion of Noninterlace to Interlace
NONINTERLACED
ODD FIELD
EVEN FIELD
T his line reduction can be performed by merely eliminating
every Nth (6th line in converting 480 lines to NST C or every
25th line in converting 600 lines to PAL). T his risks generation
of jagged edges and jerky movement. It is best to combine the
scaling with the interpolation/averaging technique discussed
above to ensure that valuable data is not arbitrarily discarded in
the scaling process. Like the flicker reduction technique men-
tioned above, the line reduction must be accomplished prior to
the AD725 encoding operation.
1
2
3
4
5
6
7
1
3
5
7
2
4
6
=
+
b. Line Doubled Conversion Technique
NONINTERLACED
ODD FIELD
EVEN FIELD
T here is a new generation of VGA controllers on the market
specifically designed to utilize these techniques to provide a
crisp and stable display for both text and graphics oriented
applications. In addition these chips rescale the output from the
computer to fit correctly on the screen of a television. A list of
known devices is available through Analog Devices’ Applica-
tions group, but the most complete and current information will
be available from the manufacturers of graphics controller ICs.
1
2
3
4
5
6
7
1
3
5
7
2
4
6
=
+
c. Line Averaging Technique
Figure 21.
Synchr onous vs. Asynchr onous O per ation
LUMA TRAP -TH EO RY
T he source of RGB video and synchronization used as an input
to the AD725 in some systems is derived from the same clock
signal as used for the AD725 subcarrier input (4FSC). T hese
systems are said to be operating synchronously. In systems
where two different clock sources are used for these signals, the
operation is called asynchronous.
T he composite video output of the AD725 can be improved for
some types of images by incorporating a luma trap (or Y-T rap)
in the encoder circuit. T he basic configuration for such a circuit
is a notch or band elimination filter that is centered at the
subcarrier frequency. T he luma trap is only functional for the
composite video output of the AD725; it has no influence on
the S-Video (or Y/C-Video) output.
T he AD725 supports both synchronous and asynchronous
operation, but some minor differences might be noticed be-
tween them. T hese can be caused by some details of the inter-
nal circuitry of the AD725.
T he need for a luma trap arises from the method used by com-
posite video to encode the color part (chrominance or chroma)
of the video signal. T his is performed by amplitude and phase
modulation of a subcarrier. T he saturation (or lack of dilution of
a color with white) is represented in the subcarrier’s amplitude
modulation, while the hue (or color as thought of as the sections
of a rainbow) information is contained in the subcarrier’s phase
modulation. T he modulated subcarrier occupies a bandwidth
somewhat greater than 1 MHz depending on the video standard.
T here is an attempt to process all of the video and synchroniza-
tion signals totally asynchronous with respect to the subcarrier
signal. T his was achieved everywhere except for the sampled
delay line used in the luminance channel to time align the lumi-
nance and chrominance. T his delay line uses a signal at eight
times the subcarrier frequency as its clock.
T he phasing between the delay line clock and the luminance
signal (with inserted composite sync) will be constant during
synchronous operation, while the phasing will demonstrate a
periodic variation during asynchronous operation. T he jitter of
the asynchronous video output will be slightly greater due to
these periodic phase variations.
For a composite signal, the chroma is linearly added to the
luminance (luma or brightness) plus sync signal to form a single
composite signal with all of the picture information. Once this
addition is performed, it is no longer possible to ascertain which
component contributed which part of the composite signal.
At the receiver, this single composite signal must be separated
into its various parts to be properly processed. In particular, the
chroma must be separated and then demodulated into its or-
thogonal components, U and V. T hen, along with the luma
signal, the U and V signals generate the RGB signals that con-
trol the three video guns in the monitor.
A basic problem arises when the luma signal (which contains no
color information) contains frequency components that fall
REV. 0
–14–
AD725
within the chroma band. All signals in this band are processed
as chroma information since the chroma processing circuit has
no knowledge as to where these signals originated. T herefore,
the color that results from the luma signals in the chroma band
is a false color. T his effect is referred to as cross chrominance.
quality. S-video will not just eliminate cross chrominance, but
will also not have this notch in the luma response.
Im plem enting a Lum a Tr ap
T he AD725 implementation of a luma trap uses an on-chip
resistor along with an off-chip inductor and capacitor to create
an RLC notch filter. T he filter must be tuned to the center
frequency of the video standard being output by the AD725,
3.58 MHz for NT SC or 4.43 MHz for PAL.
T he cross chrominance effect is sometimes evident in white text
on a black background as a moving rainbow pattern around the
characters. T he sharp transitions from black to white (and vice
versa) that comprise the text dots contain frequency compo-
nents across the whole video band, and those in the chroma
band create cross chrominance. T his is especially pronounced
when the dot clock used to generate the characters is an integer
multiple of the chroma subcarrier frequency.
T he circuit is shown in Figure 22. T he 1 kΩ series resistor in
the composite video luma path on the AD725 works against the
impedance of the off-chip series LC to form a notch filter. T he
frequency of the filter is given by:
1
f =
Another common contributor to cross chrominance effects is
certain striped clothing patterns that are televised. At a specific
amount of zoom, the spatial frequency of vertical stripe patterns
will generate luma frequencies in the chroma band. T hese fre-
quency components will ultimately get turned into color by the
video monitor. Since the phase of these signals is not coherent
with the subcarrier, the effect shows up as random colors. If the
zoom of a T V camera is modified or there is motion of the
striped pattern, the false colors can vary quite radically and
produce a quite objectionable “moving rainbow” effect. Most
T V-savvy people have learned to adapt by just not wearing
certain patterns when appearing on T V.
2π LC
220F
75⍀
75⍀
75⍀
CRMA
COMP
LUMA
220F
220F
A
B
AD725
14.318180MHz
17.734475MHz
4FSC
1.0k⍀
A/B
LUMA
STND
YTRAP
C2
9pF
An excellent way to eliminate virtually all cross chrominance
effects is to use S-video. Since the luma and chroma are carried
on two separate circuits, there is no confusion as to which cir-
cuit should process which signals. Unfortunately, not all T Vs
that exist today, and probably still not even half of those being
sold, have a provision for S-video input.
L
68H
47k⍀
NTSC/PAL
C1
18pF
D1
1N4148
Figure 22. Lum a Trap Circuit for NTSC and PAL Video
T o ensure compatibility with the input capabilities of the major-
ity of T Vs in existence, composite video must be supplied.
Many more T Vs have a composite baseband video input port
than have an S-video port to connect cameras and VCRs.
D ual-Standar d Lum a Tr ap
For a filter that will work for both PAL and NT SC a means is
required to switch the tuning of the filter between the two
subcarrier frequencies. T he PAL standard requires a higher
frequency than NT SC. A basic filter can be made that is tuned
to the PAL subcarrier and a simple diode circuit can then be
used to switch in an extra parallel capacitor that will lower the
filter’s frequency for NT SC operation.
However, still the only common denominator for virtually all
T Vs is an RF input. T his requires modulating the baseband
video onto an RF carrier that is usually tuned to either Channel
3 or 4 (for NT SC). Most video games that can afford only a
single output use an RF interface because of its universality.
Sound can also be carried on this channel.
Figure 22 shows how the logic signal that drives ST ND (Pin 1)
can also be used to drive the circuit that selects the tuning of the
luma trap circuit. When the signal applied to ST ND (Pin 1) is
low (ground), the PAL mode is selected. T his results in a bias of
0 V across D1, which is an off condition. As a result, C2 is out
of the filter circuit and only C1 tunes the notch filter to the PAL
subcarrier frequency, 4.43 MHz.
Since it is not practical to rely exclusively on S-video to improve
the picture quality by eliminating cross chrominance, a luma
trap can be used to minimize this effect for systems that use
composite video. T he luma trap notches out or “traps” the
offending frequencies from the luma signal before it is added to
the chroma. T he cross chrominance that would be generated by
these frequencies is thereby significantly attenuated.
On the other hand, when ST ND is high (+5 V), NT SC is se-
lected and there is a forward bias across D1. T his turns the
diode on and adds C2 in parallel with C1. T he notch filter is
now tuned to the NT SC subcarrier frequency, 3.58 MHz.
T he only sacrifice that results is that the luma response has a
“hole” in it at the chroma frequency. T his will lower the lumi-
nance resolution of details whose spatial frequency causes
frequency components in the chroma band. H owever, the
attenuation of cross chrominance outweighs this in the picture
REV. 0
–15–
AD725
Measur ing the Lum a Tr ap Fr equency Response
T he frequency response of the luma trap can be measured in
two different ways. T he first involves using an RGB frequency
sweep input pattern into the AD725 and observing the compos-
ite output on a T V monitor, a T V waveform monitor or on an
oscilloscope.
tarily apply an HSYNC signal to reset the timing and perform
the dc restore. Because the inputs are high-impedance, the
droop during testing will be minimal. It is not desirable to apply
a steady pulse train of HSYNC inputs because the spectrum of
these pulses will show up in the output response.
A more stable, low noise method is shown in Figure 23. T he
RGB inputs are biased using a power supply and the source port
bias input of the network analyzer. A momentary sync input is
still applied to the device to reset its internal timing, but droop
during testing will no longer be an issue.
On a T V monitor, the composite video display will look like
vertical black and white lines that are coarsely spaced (low fre-
quency) on the left side and progress to tightly spaced (high
frequency) on the right side. Somewhere to the right of center,
there will not be discernible stripes, but rather only a gray verti-
cal area. T his is the effect of the luma trap, which filters out
luminance detail at a band of frequencies.
T he signal source is applied to the GIN input for largest output
response. T his input should be terminated through the appro-
priate termination resistor (matching the output impedance of
the network analyzer). If necessary, calibration inaccuracies can
be flattened out by reading back the input reference using a
FET probe.
At the bottom of the display are markings at each megahertz
that establish a scale of frequency vs. horizontal position. T he
location of the center of the gray area along the frequency
marker scale indicates the range of frequencies that are being
filtered out. T he gray area should be about halfway between the
3 MHz and 4 MHz markers for NT SC, and about halfway
between the 4 MHz and 5 MHz markers for PAL.
NETWORK ANALYZER
SOURCE
REF
SOURCE
BIAS
MEASURE
1V
When a horizontal line is viewed on an oscilloscope or video
waveform monitor, the notch in the response will be apparent.
T he frequency will have to be interpolated from the location of
the notch position along the H-line.
FET
PROBE
OUT
؉5V
؉5V
IN
؉
10F
؉
0.1F
0.1F
10F
1.0
4
14
APOS
DPOS
7
GIN
75⍀
100
220F
؉
75⍀
COMP
6
RIN
BIN
0.5
8
AD725
50
1V
؉5V
؉5V
15 VSYNC
9
NC
NC
CRMA
LUMA
0.0
0
11
MOMENTARY
CSYNC
10k⍀
16
HSYNC
4FSC
؉5V
5
ENCD
–50
OSC
–0.5
STND
0
10
20
30
40
50
60
s
YTRAP
NTSC/PAL
47k⍀
Figure 23. Lum inance Sweep with Trap, COMP Pin
DGND
13
AGND
68H
9pF
T he second method involves using a network analyzer to mea-
sure the frequency response of the composite signal. In order to
perform this successfully, the AD725 must be given the appro-
priate signals so that it will pass video signals through it. Figure
24 illustrates the setup used for these measurements.
2
NC = NO CONNECT
1N4148
18pF
Figure 24. Measurem ent Setup for Determ ining Lum a
Trap Frequency
T he first requirement is that the part must receive a subcarrier
clock. T his will provide clocking to the internal delay line and
enable it to pass the video signal. T he subcarrier clock should be
at the 4FSC frequency for either NT SC or PAL.
T he composite output is reverse terminated with a 50 Ω or 75 Ω
resistor and input to the measuring channel of a network analyzer.
Since only the green input is driven, this method does not yield
an absolute measurement of composite signal levels, but the
notch in the composite output will be readily discernible. T he
frequency measuring functions of the network analyzer can then
be use to accurately measure the frequency of the luma notch
filter (luma trap).
T he second requirement is that the RGB inputs are properly
biased for linear operation, and the timing logic is properly
reset. It is acceptable to ac-couple the RGB inputs and momen-
REV. 0
–16–
AD725
6
3
signal should occur at the output of an on-chip XNOR gate on
the AD725 whose two inputs are HSYNC (Pin 16) and VSYNC
(Pin 15). T here are several options for meeting these conditions.
0
LUMA PIN
T he first is to have separate signals for H SYNC and VSYNC.
Each should be mostly low and then high going during their
respective time of assertion. T his is the convention used by
RGB monitors for most PCs. The proper composite sync signal
will be produced by the on-chip XNOR gate when using these
inputs.
–3
COMP PIN
–6
–9
–12
–15
–18
–21
–24
If a composite sync signal is already available, it can be input
into HSYNC (Pin 16), while VSYNC (Pin 15) can be used to
change the polarity. (In actuality, HSYNC and VSYNC are
interchangeable since they are symmetric inputs to a two-input
gate).
0.1
1.0
FREQUENCY – MHz
10.0
If the composite sync input is mostly high and then low going
for active HSYNC time (and inverted duty cycle during VSYNC),
then it is already of the proper polarity. Pulling VSYNC high,
while inputting the composite sync signal to HSYNC will pass
this signal though the XNOR gate without inversion.
Figure 25. Lum inance Frequency Response with NTSC Trap
SYNCH RO NIZING SIGNALS
T he AD725 requires explicit horizontal and vertical synchroniz-
ing signals for proper operation. T his information cannot and
should not be incorporated in any of the RGB signals. However,
the synchronizing information can be provided as either separate
horizontal (HSYNC) and vertical (VSYNC) signals or as a
single composite sync (CSYNC) signal.
On the other hand, if the composite sync signal is the opposite
polarity as described above, pulling VSYNC low will cause the
XNOR gate to invert the signal. T his will make it the proper
polarity for use inside the AD725. T hese logic conditions are
illustrated in Figure 26.
Internally the AD725 requires a composite sync logic signal that
is mostly high and goes low during horizontal sync time. T he
vertical interval will have an inverted duty cycle from this. T his
HSYNC
VSYNC
CSYNC
Figure 26. Sync Logic Levels (Equalization and Serration Pulses Not Shown)
REV. 0
–17–
AD725
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
16-Lead Wide Body SO IC
(R-16)
0.4133 (10.50)
0.3977 (10.00)
16
9
1
8
0.1043 (2.65)
0.0291 (0.74)
0.0098 (0.25)
PIN 1
x 45°
0.0926 (2.35)
0.0118 (0.30)
0.0040 (0.10)
0.0500 (1.27)
8°
0° 0.0157 (0.40)
0.0500
(1.27)
BSC
0.0192 (0.49)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
0.0138 (0.35)
REV. 0
–18–
–19–
–20–
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