AD7265BCPZ-REEL_技术文档

Differential/Single-Ended Input, Dual

1 MSPS, 12-Bit, 3-Channel SAR ADC

AD7265

FUNCTIONAL BLOCK DIAGRAM

FEATURES

REF SELECT

D

A

AV

DV

CAP

DD

Dual 12-bit, 3-channel ADC

Throughput rate: 1 MSPS

BUF

T/H

REF

Specified for V_DDof 2.7 V to 5.25 V

Power consumption

AD7265

V

A1

A2

7 mW at 1 MSPS with 3 V supplies

17 mW at 1 MSPS with 5 V supplies

Pin-configurable analog inputs

12-channel single-ended inputs

6-channel fully differential inputs

6-channel pseudo differential inputs

70 dB SINAD at 50 kHz input frequency

Accurate on-chip reference: 2.5 V

0.2ꢀ maximum @ 25°C, 20 ppm/°C maximum

Dual conversion with read 875 ns, 16 MHz SCLK

High speed serial interface

SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible

−40°C to +125°C operation

Shutdown mode: 1 μA maximum

32-lead LFCSP and 32-lead TQFP

2 MSPS version, AD7266

12-BIT

V

A3

A4

SUCCESSIVE

APPROXIMATION

ADC

OUTPUT

DRIVERS

MUX

D

A

OUT

V

A5

A6

SCLK

CS

RANGE

SGL/DIFF

A0

CONTROL

LOGIC

A1

A2

V

B1

B2

V

DRIVE

V

B3

B4

MUX

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

OUTPUT

DRIVERS

D

B

OUT

T/H

V

B5

B6

BUF

AGND AGND AGND

D

B

DGND

CAP

GENERAL DESCRIPTION

Figure 1.

The AD7265¹is a dual, 12-bit, high speed, low power, successive

approximation ADC that operates from a single 2.7 V to 5.25 V

power supply and features throughput rates of up to 1 MSPS. The

device contains two ADCs, each preceded by a 3-channel

multiplexer, and a low noise, wide bandwidth track-and-hold

amplifier that can handle input frequencies in excess of 30 MHz.

PRODUCT HIGHLIGHTS

1. Two Complete ADC Functions Allow Simultaneous

Sampling and Conversion of Two Channels.

Each ADC has three fully/pseudo differential pairs, or six

single-ended channels, as programmed. The conversion

result of both channels is simultaneously available on

separate data lines, or in succession on one data line if only

one serial port is available.

The conversion process and data acquisition use standard

control inputs allowing easy interfacing to microprocessors or

DSPs. The input signal is sampled on the falling edge of

CS

;

conversion is also initiated at this point. The conversion time is

determined by the SCLK frequency. The AD7265 uses advanced

design techniques to achieve very low power dissipation at high

throughput rates. With 5 V supplies and a 1 MSPS throughput rate,

the part consumes 4 mA maximum. The part also offers flexible

power/throughput rate management when operating in normal

mode, because the quiescent current consumption is so low.

2. High Throughput with Low Power Consumption.

The AD7265 offers a 1 MSPS throughput rate with 9 mW

maximum power dissipation when operating at 3 V.

3. The AD7265 offers both a standard 0 V to V_REFinput range

and a 2 × V_REFinput range.

4. No Pipeline Delay.

The part features two standard successive approximation

ADCs with accurate control of the sampling instant via a

input and once off conversion control.

The analog input range for the part can be selected to be a 0 V

to V_REF(or 2 × V_REF) range, with either straight binary or twos

complement output coding. The AD7265 has an on-chip 2.5 V

reference that can be overdriven when an external reference is

preferred. This external reference range is 100 mV to V_DD. The

AD7265 is available in 32-lead LFCSP and 32-lead TQFP.

CS

¹Protected by U.S. Patent No. 6,681,332.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD7265

TABLE OF CONTENTS

Features .............................................................................................. 1

Digital Inputs .............................................................................. 18

V_DRIVE............................................................................................ 18

Modes of Operation ....................................................................... 19

Normal Mode.............................................................................. 19

Partial Power-Down Mode ....................................................... 19

Full Power-Down Mode ............................................................ 20

Power-Up Times......................................................................... 21

Power vs. Throughput Rate....................................................... 21

Serial Interface ................................................................................ 22

Microprocessor Interfacing........................................................... 23

AD7265 to ADSP218x............................................................... 23

AD7265 to ADSP-BF53x........................................................... 24

AD7265 to TMS320C541.......................................................... 24

AD7265 to DSP563xx................................................................ 25

Application Hints ........................................................................... 26

Grounding and Layout .............................................................. 26

PCB Design Guidelines for LFCSP.......................................... 26

Evaluating the AD7265 Performance...................................... 26

Outline Dimensions....................................................................... 27

Ordering Guide .......................................................................... 27

General Description......................................................................... 1

Functional Block Diagram .............................................................. 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Typical Performance Characteristics ............................................. 9

Terminology .................................................................................... 11

Theory of Operation ...................................................................... 13

Circuit Information.................................................................... 13

Converter Operation.................................................................. 13

Analog Input Structure.............................................................. 13

Analog Inputs.............................................................................. 14

Analog Input Selection .............................................................. 17

Output Coding............................................................................ 17

Transfer Functions...................................................................... 18

REVISION HISTORY

11/06—Rev. 0 to Rev. A

4/05—Revision 0: Initial Version

Changes to Format .............................................................Universal

Changes to Reference Input/Output Section................................ 4

Changes to Table 4............................................................................ 7

Changes to Terminology Section.................................................. 11

Changes to Figure 24 and Differential Mode Section................ 15

Changes to Figure 29...................................................................... 16

Changes to AD7265 to ADSP-BF53x Section............................. 24

Updated Outline Dimensions....................................................... 27

Changes to Ordering Guide .......................................................... 27

Rev. A | Page 2 of 28

AD7265

SPECIFICATIONS

T_A= T_MINto T_MAX, V_DD= 2.7 V to 5.25 V, f_SCLK= 16 MHz, f_S= 1 MSPS, V_DRIVE= 2.7 V to 5.25 V; specifications apply using internal

reference or external reference = 2.5 V 1%, unless otherwise noted.¹

Table 1.

Parameter

Specification

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio (SNR)²

71

69

dB min

f_IN= 50 kHz sine wave; differential mode

f_IN= 50 kHz sine wave; single-ended and

pseudo differential modes

Signal-to-Noise + Distortion Ratio (SINAD)²

Total Harmonic Distortion (THD)²

70

68

dB min

f_IN= 50 kHz sine wave; differential mode

f_IN= 50 kHz sine wave; single-ended and

pseudo differential modes

f_IN= 50 kHz sine wave; differential mode

f_IN= 50 kHz sine wave; single-ended and

pseudo differential modes

–77

–73

dB max

Spurious-Free Dynamic Range (SFDR)²

Intermodulation Distortion (IMD)²

Second-Order Terms

Third-Order Terms

Channel-to-Channel Isolation

–75

dB max

f_IN= 50 kHz sine wave

fa = 30 kHz, fb = 50 kHz

–88

dB typ

SAMPLE AND HOLD

Aperture Delay³

11

50

200

33/26

3.5/3

ns max

ps typ

ps max

MHz typ

Aperture Jitter³

Aperture Delay Matching³

Full Power Bandwidth

@ 3 dB, V_DD= 5 V/V_DD= 3 V

@ 0.1 dB, V_DD= 5 V/V_DD= 3 V

DC ACCURACY

Resolution

Integral Nonlinearity²

12

1

1.5

Bits

LSB max

0.5 LSB typ; differential mode

0.5 LSB typ; single-ended and pseudo

differential modes

Differential mode

Differential Nonlinearity^2,4

0.99

−0.99/+1.5

LSB max

Single-ended and pseudo differential modes

Straight Binary Output Coding

Offset Error

Offset Error Match

Gain Error

Gain Error Match

6

2

2.5

0.5

LSB max

LSB typ

LSB max

LSB typ

Twos Complement Output Coding

Positive Gain Error

Positive Gain Error Match

Zero Code Error

Zero Code Error Match

Negative Gain Error

Negative Gain Error Match

ANALOG INPUT⁵

2

0.5

5

1

2

LSB max

LSB typ

LSB max

LSB typ

LSB max

LSB typ

0.5

Single-Ended Input Range

0 V to V_REF

0 V to 2 × V_REF

0 to V_REF

2 × V_REF

V_CMV_REF/2

V_CMV_REF

V

RANGE pin low

RANGE pin high

RANGE pin low

RANGE pin high

V_CM= common-mode voltage⁷= V_REF/2

V_CM= V_REF

6

Pseudo Differential Input Range: V_IN+− V_IN−

V

Fully Differential Input Range: V_IN+and V_IN−

V_IN+and V_IN−

Rev. A | Page 3 of 28

AD7265

Parameter

Specification

Unit

Test Conditions/Comments

DC Leakage Current

Input Capacitance

1

45

10

μA max

pF typ

When in track

When in hold

REFERENCE INPUT/OUTPUT

Reference Output Voltage⁸

Long-Term Stability

Output Voltage Hysteresis²

Reference Input Voltage Range

DC Leakage Current

2.5

150

50

0.1/V_DD

2

V min/V max

ppm typ

V min/V max

μA max

0.2ꢀ max @ 25ꢁC

For 1000 hours

See Typical Performance Characteristics section

External reference applied to Pin D_CAPA/Pin D_CAP

B

Input Capacitance

25

pF typ

D_CAPA, D_CAPB Output Impedance

Reference Temperature Coefficient

10

20

10

20

Ω typ

ppm/ꢁC max

ppm/ꢁC typ

μV rms typ

V_REFNoise

LOGIC INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

2.8

0.4

15

5

V min

V max

nA typ

pF typ

V_IN= 0 V or V_DRIVE

3

Input Capacitance, C_IN

LOGIC OUTPUTS

Output High Voltage, V_OH

Output Low Voltage, V_OL

Floating State Leakage Current

Floating State Output Capacitance³

Output Coding

V_DRIVE− 0.2

0.4

1

V min

V max

μA max

pF typ

7

SGL/DIFF = 1 with 0 V to V_REFrange selected

Straight (natural) binary

Twos complement

SGL/DIFF = 0; SGL/DIFF = 1 with 0 V to 2 × V_REFrange

CONVERSION RATE

Conversion Time

14

90

110

1

SCLK cycles

ns max

MSPS max

875 ns with SCLK = 16 MHz

Full-scale step input; V_DD= 5 V

Full-scale step input; V_DD= 3 V

Track-and-Hold Acquisition Time³

Throughput Rate

POWER REQUIREMENTS

V_DD

2.7/5.25

V min/V max

V_DRIVE

I_DD

Digital I/Ps = 0 V or V_DRIVE

V_DD= 5.25 V

V_DD= 5.25 V; 3.5 mA typ

V_DD= 3.6 V; 2.7 mA typ

Static

Normal Mode (Static)

Operational, f_S= 1 MSPS

f_S= 1 MSPS

Partial Power-Down Mode

Full Power-Down Mode (V_DD)

2.3

4

3.2

500

1

mA max

μA max

T_A= −40ꢁC to +85ꢁC

T_A> 85ꢁC to 125ꢁC

2.8

Power Dissipation

Normal Mode (Operational)

Partial Power-Down (Static)

Full Power-Down (Static)

21

2.625

5.25

mW max

μW max

V_DD= 5.25 V

V_DD= 5.25 V, T_A= −40ꢁC to +85ꢁC

¹Temperature range is −40ꢁC to +125ꢁC.

²See Terminology section.

³Sample tested during initial release to ensure compliance.

⁴Guaranteed no missed codes to 12 bits.

⁵V_IN−or V_IN+must remain within GND/V_DD

.

⁶V_IN−= 0 V for specified performance. For full input range on V_IN−pin, see Figure 28 and Figure 29.

⁷For full common-mode range, see Figure 24 and Figure 25.

⁸Relates to Pin D_CAPA or Pin D_CAPB.

Rev. A | Page 4 of 28

AD7265

TIMING SPECIFICATIONS

AV_DD= DV_DD= 2.7 V to 5.25 V, V_DRIVE= 2.7 V to 5.25 V, internal/external reference = 2.5 V, T_A= T_MAXto T_MIN, unless otherwise noted¹.

Table 2.

Parameter

Limit at T_MIN, T_MAX

Unit

Description

2

f_SCLK

1

4

16

14 × t_SCLK

875

30

MHz min

MHz max

ns max

ns min

ns max

ns min

ns max

ns min

ns max

T_A= −40ꢁC to +85ꢁC

T_A> 85ꢁC to 125ꢁC

t_CONVERT

t_SCLK= 1/f_SCLK

f_SCLK= 16 MHz

t_QUIET

t₂

CS

Minimum time between end of serial read and next falling edge of

V_DD= 5 V/3 V, CS to SCLK setup time, T_A= −40ꢁC to +85ꢁC

V_DD= 5 V/3 V, CS to SCLK setup time, T_A> 85ꢁC to 125ꢁC

Delay from CS until D_OUTA and D_OUTB are three-state disabled

Data access time after SCLK falling edge, V_DD= 3 V

Data access time after SCLK falling edge, V_DD= 5 V

SCLK low pulse width

SCLK high pulse width

SCLK to data valid hold time, V_DD= 3 V

SCLK to data valid hold time, V_DD= 5 V

15/20

20/30

15

t₃

3

t₄

36

27

0.45 t_SCLK

10

t₅

t₆

t₇

5

15

t₈

CS rising edge to D_OUTA, D_OUTB, high impedance

CS rising edge to falling edge pulse width

SCLK falling edge to D_OUTA, D_OUTB, high impedance

t₉

30

t₁₀

5

50

¹Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10ꢀ to 90ꢀ of V_DD) and timed from a voltage level of 1.6 V.

All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the Serial

Interface section and Figure 41 and Figure 42.

²Minimum SCLK for specified performance; with slower SCLK frequencies, performance specifications apply typically.

³The time required for the output to cross 0.4 V or 2.4 V.

Rev. A | Page 5 of 28

AD7265

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rating

V_DDto AGND

DV_DDto DGND

V_DRIVEto DGND

V_DRIVEto AGND

AV_DDto DV_DD

AGND to DGND

Analog Input Voltage to AGND

Digital Input Voltage to DGND

Digital Output Voltage to GND

V_REFto AGND

−0.3 V to +7 V

−0.3 V to DV_DD

−0.3 V to AV_DD

−0.3 V to +0.3 V

−0.3 V to AV_DD+ 0.3 V

−0.3 V to +7 V

−0.3 V to V_DRIVE+ 0.3 V

−0.3 V to AV_DD+ 0.3 V

ESD CAUTION

Input Current to Any Pin Except

Supplies¹

10 mA

Operating Temperature Range

Storage Temperature Range

Junction Temperature

LFCSP/TQFP

−40ꢁC to +125ꢁC

−65ꢁC to +150ꢁC

150ꢁC

θ_JAThermal Impedance

108.2ꢁC/W (LFCSP)

55ꢁC/W (TQFP)

θ_JCThermal Impedance

32.71ꢁC/W (LFCSP)

Lead Temperature, Soldering

Reflow Temperature (10 sec to 30 sec) 255ꢁC

ESD

1.5 kV

¹Transient currents of up to 100 mA will not cause SCR latch up.

Rev. A | Page 6 of 28

AD7265

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

32 31 30 29 28 27 26 25

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

DGND

A1

A2

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

DGND

REF SELECT

A1

A2

SGL/DIFF

RANGE

PIN 1

REF SELECT

INDICATOR

AV

DD

SGL/DIFF

RANGE

AV

DD

A

D

A

CAP

AD7265

TOP VIEW

(Not to Scale)

AD7265

TOP VIEW

(Not to Scale)

D

AGND

D

B

CAP

AGND

D

B

AGND

CAP

V

A1

A2

B1

B2

AGND

V

B1

A1

V

B2

A2

9

10 11 12 13 14 15 16

Figure 3. 32-Lead SU-32-2

Figure 2. 32-Lead CP-32-2

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1, 29

DGND

Digital Ground. This is the ground reference point for all digital circuitry on the AD7265. Both DGND pins should

connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential

and must not be more than 0.3 V apart, even on a transient basis.

2

REF SELECT

Internal/External Reference Selection. Logic input. If this pin is tied to DGND, the on-chip 2.5 V reference is used

as the reference source for both ADC A and ADC B. In addition, Pin D_CAPA and Pin D_CAPB must be tied to

decoupling capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the

AD7265 through the D_CAPA pin and/or the D_CAPB pin.

3

AV_DD

Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7265. The

AV_DDand DV_DDvoltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a

transient basis. This supply should be decoupled to AGND.

4, 20

D_CAPA, D_CAP

AGND

B

Decoupling Capacitor Pins. Decoupling capacitors (470 nF recommended) are connected to these pins to

decouple the reference buffer for each respective ADC. Provided the output is buffered, the on-chip reference

can be taken from these pins and applied externally to the rest of a system. The range of the external reference is

dependent on the analog input range selected.

Analog Ground. Ground reference point for all analog circuitry on the AD7265. All analog input signals and any

external reference signal should be referred to this AGND voltage. All three of these AGND pins should connect

to the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must

not be more than 0.3 V apart, even on a transient basis.

5, 6, 19

7 to 12

V_A1to V_A6

Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differential

analog input channel pairs. See Table 6.

13 to 18 V_B6to V_B1

Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differential

analog input channel pairs. See Table 6.

21

22

RANGE

Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the analog

input channels. If this pin is tied to a logic low, the analog input range is 0 V to V_REF. If this pin is tied to a logic

high when CS goes low, the analog input range is 2 × V_REF. See the Analog Input Selection section for details.

SGL/DIFF

Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A

logic low selects differential operation while a logic high selects single-ended operation. See the Analog Input

Selection section for details.

23 to 25 A2 to A0

Multiplexer Select. Logic inputs. These inputs are used to select the pair of channels to be simultaneously

converted, such as Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC B, and so on. The pair

of channels selected may be two single-ended channels or two differential pairs. The logic states of these pins

need to be set up prior to the acquisition time and subsequent falling edge of CS to correctly set up the

multiplexer for that conversion. See the Analog Input Selection section for further details and Table 6 for

multiplexer address decoding.

26

27

CS

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7265

and framing the serial data transfer.

Serial Clock. Logic input. A serial clock input provides the SCLK for accessing the data from the AD7265. This

clock is also used as the clock source for the conversion process.

SCLK

Rev. A | Page 7 of 28

AD7265

Pin No. Mnemonic

Description

28, 30

D_OUTB, D_OUT

A

Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on

the falling edge of the SCLK input and 14 SCLKs are required to access the data. The data simultaneously appears

on both pins from the simultaneous conversions of both ADCs. The data stream consists of two leading zeros

followed by the 12 bits of conversion data. The data is provided MSB first. If CS is held low for 16 SCLK cycles

rather than 14, then two trailing zeros appear after the 12 bits of data. If CS is held low for a further 16 SCLK

cycles on either D_OUTA or D_OUTB, the data from the other ADC follows on the D_OUTpin. This allows data from a

simultaneous conversion on both ADCs to be gathered in serial format on either D_OUTA or D_OUTB using only one

serial port. See the Serial Interface section.

31

32

V_DRIVE

DV_DD

Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.

This pin should be decoupled to DGND. The voltage at this pin may be different than that at AV_DDand DV_DDbut

should never exceed either by more than 0.3 V.

Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD7265. The DV_DD

and AV_DDvoltages should ideally be at the same potential and must not be more than 0.3 V apart even on a

transient basis. This supply should be decoupled to DGND.

Rev. A | Page 8 of 28

AD7265

TYPICAL PERFORMANCE CHARACTERISTICS

T_A= 25°C, unless otherwise noted.

–60

4096 POINT FFT

INTERNAL REFERENCE

–10

–30

V

= 5V, V

= 3V

DD

DRIVE

F

= 1MSPS

= 26kHz

SAMPLE

–70

IN

SINAD = 71.4dB

THD = –84.42dB

DIFFERENTIAL MODE

–80

EXTERNAL REFERENCE

–50

–90

–70

–100

–110

–90

100mV p-p SINE WAVE ON AV

DD

NO DECOUPLING

SINGLE-ENDED MODE

–110

–120

0

50

100 150 200 250 300 350 400 450 500

FREQUENCY (kHz)

0

200 400 600 800 1000 1200 1400 1600 1800 2000

SUPPLY RIPPLE FREQUENCY (kHz)

Figure 7. FFT

Figure 4. PSRR vs. Supply Ripple Frequency Without Supply Decoupling

1.0

0.8

–50

V

= 5V, V

= 3V

V

= 5V

DD

DRIVE

DD

DIFFERENTIAL MODE

–55

–60

–65

–70

–75

–80

–85

–90

–95

–100

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

0

500

1000 1500 2000 2500 3000 3500 4000

CODE

0

100 200 300 400 500 600 700 800 900 1000

NOISE FREQUENCY (kHz)

Figure 5. Channel-to-Channel Isolation

Figure 8. Typical DNL

74

72

70

68

1.0

0.8

V

= 5V, V

= 3V

RANGE = 0 TO V

REF

DD

DRIVE

DIFFERENTIAL MODE

0.6

V

= 5V

DD

DIFFERENTIAL MODE

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

V

= 3V

DD

DIFFERENTIAL MODE

66

0

500

INPUT FREQUENCY (kHz)

1000

0

500

1000 1500 2000 2500 3000 3500 4000

CODE

Figure 6. SINAD vs. Analog Input Frequency for Various Supply Voltages

Figure 9. Typical INL

Rev. A | Page 9 of 28

AD7265

1.0

0.8

0.6

0.4

0.2

0

10000

9000

8000

7000

6000

5000

4000

3000

2000

1000

0

DIFFERENTIAL

MODE

V

= 3V/5V

INTERNAL

REFERENCE

DD

10000

CODES

DIFFERENTIAL MODE

POSITIVE DNL

POSITIVE INL

–0.2

NEGATIVE INL

–0.4

–0.6

–0.8

–1.0

NEGATIVE DNL

0

0.5

1.0

1.5

2.0

2.5

2046

2047

2048

2049

2050

V

(V)

CODE

REF

Figure 10. Linearity Error vs. V_REF

Figure 13. Histogram of Codes for 10k Samples in Differential Mode

12.0

10000

INTERNAL

REFERENCE

SINGLE-ENDED

MODE

9984

CODES

11.5

11.0

9000

8000

7000

6000

5000

4000

3000

2000

1000

0

V

= 5V

DD

SINGLE-ENDED MODE

10.5

10.0

9.5

V

= 3V

DD

SINGLE-ENDED MODE

9.0

8.5

V

= 3V

V

= 5V

DD

DIFFERENTIAL MODE

8.0

7.5

7.0

5 CODES

2047 2048

11 CODES

2049 2050

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

2046

V

(V)

REF

CODE

Figure 11. Effective Number of Bits vs. V_REF

Figure 14. Histogram of Codes for 10k Samples in Single-Ended Mode

2.5010

2.5005

2.5000

2.4995

2.4990

2.4985

2.4980

–60

DIFFERENTIAL MODE

V

= 3V/5V

DD

–65

–70

–75

–80

–85

–90

–95

–100

0

20

40

60

80

100 120 140 160 180 200

CURRENT LOAD (μA)

0

200

400

600

800

1000

1200

RIPPLE FREQUENCY (kHz)

Figure 12. V_REFvs. Reference Output Current Drive

Figure 15. CMRR vs. Common-Mode Ripple Frequency

Rev. A | Page 10 of 28

AD7265

TERMINOLOGY

Differential Nonlinearity (DNL)

Signal-to-(Noise + Distortion) Ratio (SINAD)

Differential nonlinearity is the difference between the measured

and the ideal 1 LSB change between any two adjacent codes in

the ADC.

SINAD is the measured ratio of signal-to-(noise + distortion)

at the output of the ADC. The signal is the rms amplitude of the

fundamental. Noise is the sum of all non-fundamental signals

up to half the sampling frequency (f_S/2), excluding dc. The ratio

is dependent on the number of quantization levels in the

digitization process; the more levels, the smaller the quantization

noise. The theoretical signal-to-(noise + distortion) ratio for an

ideal N-bit converter with a sine wave input is given by

Integral Nonlinearity (INL)

Integral nonlinearity is the maximum deviation from a straight

line passing through the endpoints of the ADC transfer function.

The endpoints of the transfer function are zero scale with a

single (1) LSB point below the first code transition, and full scale

with a 1 LSB point above the last code transition.

Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB

Offset Error

Therefore, for a 12-bit converter, this is 74 dB.

Offset error applies to straight binary output coding. It is the

deviation of the first code transition (00 . . . 000) to (00 . . . 001)

from the ideal (AGND + 1 LSB).

Total Harmonic Distortion (THD)

Total harmonic distortion is the ratio of the rms sum of

harmonics to the fundamental. For the AD7265, it is defined as

Offset Error Match

Offset error match is the difference in offset error across all

12 channels.

2

V₂+V₃+V₄+V₅+V₆

THD(dB) = 20 log

V₁

where:

V₁is the rms amplitude of the fundamental.

Gain Error

Gain error applies to straight binary output coding. It is the

deviation of the last code transition (111 . . . 110) to (111 . . .

111) from the ideal (VREF − 1 LSB) after the offset error is

adjusted out. Gain error does not include reference error.

V₂, V₃, V₄, V₅, and V₆are the rms amplitudes of the second

through the sixth harmonics.

Peak Harmonic or Spurious Noise

Gain Error Match

Gain error match is the difference in gain error across all

12 channels.

Peak harmonic, or spurious noise, is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to f_S/2, excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is

determined by the largest harmonic in the spectrum, but for

ADCs where the harmonics are buried in the noise floor, it is a

noise peak.

Zero Code Error

Zero code error applies when using twos complement output

coding with, for example, the 2 × VREF input range as −VREF

to +VREF biased about the VREF point. It is the deviation of

the midscale transition (all 1s to all 0s) from the ideal VIN

voltage (VREF).

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of

crosstalk between channels. It is measured by applying a full-

scale (2 × V_REFwhen V_DD= 5 V , and V_REFwhen V_DD= 3 V),

10 kHz sine wave signal to all unselected input channels and

determining how much that signal is attenuated in the selected

channel with a 50 kHz signal (0 V to V_REF). The result obtained

is the worst-case across all 12 channels for the AD7265.

Zero Code Error Match

Zero code error match refers to the difference in zero code error

across all 12 channels.

Positive Gain Error

This applies when using twos complement output coding with,

for example, the 2 × V_REFinput range as −V_REFto +V_REFbiased

about the V_REFpoint. It is the deviation of the last code transition

(011…110) to (011…111) from the ideal (+V_REF− 1 LSB) after

the zero code error is adjusted out.

Intermodulation Distortion

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities creates distortion

products at sum, and difference frequencies of mfa nfb where

m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms

are those for which neither m nor n are equal to zero. For

example, the second-order terms include (fa + fb) and (fa − fb),

while the third-order terms include (2fa + fb), (2fa − fb),

(fa + 2fb), and (fa − 2fb).

Track-and-Hold Acquisition Time

The track-and-hold amplifier returns to track mode after the

end of conversion. Track-and-hold acquisition time is the time

required for the output of the track-and-hold amplifier to reach

its final value, within 1/2 LSB, after the end of conversion.

Rev. A | Page 11 of 28

AD7265

The AD7265 is tested using the CCIF standard where two input

frequencies near the top end of the input bandwidth are used.

In this case, the second-order terms are usually distanced in

frequency from the original sine waves, while the third-order

terms are usually at a frequency close to the input frequencies.

As a result, the second-order and third-order terms are

specified separately. The calculation of the intermodulation

distortion is as per the THD specification, where it is the ratio

of the rms sum of the individual distortion products to the rms

amplitude of the sum of the fundamentals expressed in dBs.

Thermal Hysteresis

Thermal hysteresis is defined as the absolute maximum change

of reference output voltage after the device is cycled through

temperature from either

T_HYS+ = +25°C to T_MAXto +25°C

or

T_HYS− = +25°C to T_MINto +25°C

It is expressed in ppm by

V

_REF(25°C)−V_REF(T _ HYS)

V_HYS(ppm) =

×10⁶

Common-Mode Rejection Ratio (CMRR)

V_REF(25°C)

CMRR is defined as the ratio of the power in the ADC output at

full-scale frequency, f, to the power of a 100 mV p-p sine wave

applied to the common-mode voltage of V_IN+and V_IN−of

frequency f_Sas

where:

V

_REF(25°C) is V_REFat 25°C.

_REF(T_HYS) is the maximum change of V_REFat T_HYS+ or

T_HYS−.

CMRR (dB) = 10 log(Pf/Pf_S)

where:

Pf is the power at frequency f in the ADC output.

Pf_Sis the power at frequency f_Sin the ADC output.

Power Supply Rejection Ratio (PSRR)

Variations in power supply affect the full-scale transition but

not the converter’s linearity. PSRR is the maximum change in

the full-scale transition point due to a change in power supply

voltage from the nominal value (see Figure 4).

Rev. A | Page 12 of 28

AD7265

THEORY OF OPERATION

When the ADC starts a conversion (see Figure 17), SW3 opens

and SW1 and SW2 move to Position B, causing the comparator

to become unbalanced. Both inputs are disconnected once the

conversion begins. The control logic and the charge redistribution

DACs are used to add and subtract fixed amounts of charge

from the sampling capacitor arrays to bring the comparator

back into a balanced condition. When the comparator is

rebalanced, the conversion is complete. The control logic

generates the ADC output code. The output impedances of the

sources driving the V_IN+and V_IN−pins must be matched;

otherwise, the two inputs will have different settling times,

resulting in errors.

CIRCUIT INFORMATION

The AD7265 is a fast, micropower, dual, 12-bit, single-supply,

ADC that operates from a 2.7 V to a 5.25 V supply. When

operated from either a 3 V or a 5 V supply, the AD7265 is

capable of throughput rates of 1 MSPS when provided with a

16 MHz clock.

The AD7265 contains two on-chip, differential track-and-hold

amplifiers, two successive approximation ADCs, and a serial

interface with two separate data output pins. It is housed in a

32-lead LFCSP or a 32-lead TQFP, offering the user

considerable space-saving advantages over alternative solutions.

The serial clock input accesses data from the part, but also

provides the clock source for each successive approximation

ADC. The analog input range for the part can be selected to be

a 0 V to V_REFinput or a 2 × V_REFinput, configured with either

single-ended or differential analog inputs. The AD7265 has an

on-chip 2.5 V reference that can be overdriven when an external

reference is preferred. If the internal reference is to be used

elsewhere in a system, then the output needs to be buffered first.

CAPACITIVE

DAC

COMPARATOR

C

B

A

S

V

IN+

SW1

SW2

CONTROL

LOGIC

SW3

S

A

B

IN–

V

REF

CAPACITIVE

DAC

The AD7265 also features power-down options to allow power

saving between conversions. The power-down feature is

implemented via the standard serial interface, as described in

the Modes of Operation section.

Figure 17. ADC Conversion Phase

ANALOG INPUT STRUCTURE

Figure 18 shows the equivalent circuit of the analog input

structure of the AD7265 in differential/pseudo differential

modes. In single-ended mode, V_IN−is internally tied to AGND.

The four diodes provide ESD protection for the analog inputs.

Care must be taken to ensure that the analog input signals never

exceed the supply rails by more than 300 mV. This causes these

diodes to become forward-biased and starts conducting into the

substrate. These diodes can conduct up to 10 mA without

causing irreversible damage to the part.

CONVERTER OPERATION

The AD7265 has two successive approximation ADCs, each

based around two capacitive DACs. Figure 16 and Figure 17

show simplified schematics of one of these ADCs in acquisition

and conversion phase, respectively. The ADC is comprised of

control logic, a SAR, and two capacitive DACs. In Figure 16 (the

acquisition phase), SW3 is closed, SW1 and SW2 are in Position A,

the comparator is held in a balanced condition, and the sampling

capacitor arrays acquire the differential signal on the input.

The C1 capacitors in Figure 18 are typically 4 pF and can

primarily be attributed to pin capacitance. The resistors are

lumped components made up of the on resistance of the

switches. The value of these resistors is typically about 100 Ω.

The C2 capacitors are the ADC’s sampling capacitors with a

capacitance of 45 pF typically.

CAPACITIVE

DAC

COMPARATOR

C

B

A

S

V

IN+

SW1

SW2

CONTROL

LOGIC

SW3

S

A

B

IN–

For ac applications, removing high frequency components from

the analog input signal is recommended by the use of an RC

low-pass filter on the relevant analog input pins with optimum

values of 47 Ω and 10 pF. In applications where harmonic

distortion and signal-to-noise ratio are critical, the analog input

should be driven from a low impedance source. Large source

impedances significantly affect the ac performance of the ADC

and may necessitate the use of an input buffer amplifier. The

choice of the op amp is a function of the particular application.

V

REF

CAPACITIVE

DAC

Figure 16. ADC Acquisition Phase

Rev. A | Page 13 of 28

AD7265

V

DD

Figure 21 shows a graph of the THD vs. the analog input

frequency for various supplies while sampling at 1 MSPS. In this

case, the source impedance is 47 Ω.

D

C2

R1

V

IN+

–50

C1

F

= 1MSPS

SAMPLE

V

= 3V/5V

DD

–55

–60

–65

–70

–75

–80

–85

–90

RANGE = 0 TO V

REF

V

DD

D

V

= 3V

C2

DD

R1

SINGLE-ENDED MODE

V

IN–

C1

V

= 3V

DD

DIFFERENTIAL MODE

Figure 18. Equivalent Analog Input Circuit,

Conversion Phase—Switches Open, Track Phase—Switches Closed

V

= 5V

DD

When no amplifier is used to drive the analog input, the source

impedance should be limited to low values. The maximum source

impedance depends on the amount of THD that can be toler-

ated. The THD increases as the source impedance increases and

performance degrades. Figure 19 shows a graph of the THD vs.

the analog input signal frequency for different source impedances

in single-ended mode, while Figure 20 shows the THD vs. the

analog input signal frequency for different source impedances

in differential mode.

V

= 5V

DD

DIFFERENTIAL MODE

SINGLE-ENDED MODE

100 200 300

INPUT FREQUENCY (kHz)

0

400

500

600

Figure 21. THD vs. Analog Input Frequency for Various Supply Voltages

ANALOG INPUTS

The AD7265 has a total of 12 analog inputs. Each on-board

ADC has six analog inputs that can be configured as six single-

ended channels, three pseudo differential channels, or three

fully differential channels. These can be selected as described in

the Analog Input Selection section.

–50

F

V

= 1MSPS

SAMPLE

= 3V

R

= 300Ω

SOURCE

DD

–55

–60

RANGE = 0V TO V

REF

Single-Ended Mode

The AD7265 can have a total of 12 single-ended analog input

channels. In applications where the signal source has high

impedance, it is recommended to buffer the analog input before

applying it to the ADC. The analog input range can be pro-

–65

–70

R

SOURCE

= 0Ω

R

= 100Ω

SOURCE

–75

–80

–85

–90

grammed to be either 0 to V_REFor 0 to 2 × V_REF

.

R

= 47Ω

SOURCE

If the analog input signal to be sampled is bipolar, the internal

reference of the ADC can be used to externally bias up this

signal to make it correctly formatted for the ADC. Figure 22

shows a typical connection diagram when operating the ADC

in single-ended mode.

R

= 10Ω

SOURCE

0

100

200

300

400

500

600

INPUT FREQUENCY (kHz)

Figure 19. THD vs. Analog Input Frequency for

Various Source Impedances, Single-Ended Mode

+2.5V

R

+1.25V

0V

–60

–65

–70

–75

–80

–85

–90

R

F

V

= 1MSPS

SAMPLE

= 3V

0V

V

IN

R

= 300Ω

3R

AD7265¹

SOURCE

DD

RANGE = 0V TO V

V

A1

–1.25V

REF

R

= 0Ω

SOURCE

D

A/D

B

CAP

B6

CAP

R

= 100Ω

SOURCE

0.47µF

R

= 47Ω

SOURCE

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 22. Single-Ended Mode Connection Diagram

R

= 10Ω

SOURCE

0

100

200

300

400

500

600

INPUT FREQUENCY (kHz)

Figure 20. THD vs. Analog Input Frequency for

Various Source Impedances, Differential Mode

Rev. A | Page 14 of 28

AD7265

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

Differential Mode

T

= 25°C

A

The AD7265 can have a total of six differential analog

input pairs.

Differential signals have some benefits over single-ended

signals, including noise immunity based on the device’s

common-mode rejection and improvements in distortion

performance. Figure 23 defines the fully differential analog

input of the AD7265.

V

p-p

V

IN+

REF

AD7265¹

COMMON

MODE

VOLTAGE

V

p-p

V

REF

IN–

0

0.5

1.0

1.5

2.0

2.5

(V)

3.0

3.5

4.0

4.5

5.0

V

REF

Figure 24. Input Common-Mode Range vs. V_REF(0 to V_REFRange, V_DD= 5 V)

1

ADDITIONAL PINS OMITTED FOR CLARITY.

5.0

T

= 25°C

A

Figure 23. Differential Input Definition

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

The amplitude of the differential signal is the difference

between the signals applied to the V_IN+and V_IN−pins in each

differential pair (V_IN+− V_IN−). V_IN+and V_IN−should be

simultaneously driven by two signals each of amplitude V_REF(or

2 × V_REF, depending on the range chosen) that are 180° out of

phase. The amplitude of the differential signal is therefore

(assuming the 0 to V_REFrange is selected) −V_REFto +V_REFpeak-

to-peak (2 × V_REF), regardless of the common mode (CM).

The common mode is the average of the two signals

(V_IN++ V_IN−)/2

0

0.5

1.0

1.5

2.0

2.5

V

(V)

REF

and is therefore the voltage on which the two inputs are

centered.

Figure 25. Input Common-Mode Range vs. V_REF(2 × V_REFRange, V_DD= 5 V)

This results in the span of each input being CM

V_REF/2. This

Driving Differential Inputs

voltage has to be set up externally, and its range varies with the

reference value, V_REF. As the value of V_REFincreases, the common-

mode range decreases. When driving the inputs with an amplifier,

the actual common-mode range is determined by the amplifier’s

output voltage swing.

Differential operation requires that V_IN+and V_IN−be

simultaneously driven with two equal signals that are 180° out

of phase. The common mode must be set up externally. The

common-mode range is determined by V_REF, the power supply,

and the particular amplifier used to drive the analog inputs.

Differential modes of operation with either an ac or dc input

provide the best THD performance over a wide frequency

range. Because not all applications have a signal preconditioned

for differential operation, there is often a need to perform

single-ended-to-differential conversion.

Figure 24 and Figure 25 show how the common-mode range

typically varies with V_REFfor a 5 V power supply using the 0 to

V_REFrange or 2 × V_REFrange, respectively. The common mode

must be in this range to guarantee the functionality of the AD7265.

When a conversion takes place, the common mode is rejected,

resulting in a virtually noise-free signal of amplitude −V_REFto

+V_REFcorresponding to the digital codes of 0 to 4096. If the

2 × V_REFrange is used, then the input signal amplitude extends

from −2 V_REFto +2 V_REFafter conversion.

Rev. A | Page 15 of 28

AD7265

Using an Op Amp Pair

Pseudo Differential Mode

An op amp pair can be used to directly couple a differential

signal to one of the analog input pairs of the AD7265. The

circuit configurations illustrated in Figure 26 and Figure 27

show how a dual op amp can be used to convert a single-ended

signal into a differential signal for both a bipolar and unipolar

input signal, respectively.

The AD7265 can have a total of six pseudo differential pairs. In

this mode, V_IN+is connected to the signal source that must have

an amplitude of V_REF(or 2 × V_REF, depending on the range

chosen) to make use of the full dynamic range of the part. A dc

input is applied to the V_IN−pin. The voltage applied to this input

provides an offset from ground or a pseudo ground for the V_IN+

input. The benefit of pseudo differential inputs is that they

separate the analog input signal ground from the ADC’s ground

allowing dc common-mode voltages to be cancelled. The typical

voltage range for the V_IN−pin, while in pseudo differential

mode, is shown in Figure 28 and Figure 29. Figure 30 shows a

connection diagram for pseudo differential mode.

The voltage applied to Point A sets up the common-mode

voltage. In both diagrams, it is connected in some way to the

reference, but any value in the common-mode range can be

input here to set up the common mode. The AD8022 is a

suitable dual op amp that can be used in this configuration to

provide differential drive to the AD7265.

1.0

T

= 25°C

A

Take care when choosing the op amp; the selection depends on

the required power supply and system performance objectives.

The driver circuits in Figure 26 and Figure 27 are optimized for

dc coupling applications requiring best distortion performance.

0.8

0.6

0.4

0.2

0

The circuit configuration shown in Figure 26 converts a

unipolar, single-ended signal into a differential signal.

The differential op amp driver circuit shown in Figure 27 is

configured to convert and level shift a single-ended, ground-

referenced (bipolar) signal to a differential signal centered at the

–0.2

–0.4

V_REFlevel of the ADC.

3.75V

2.5V

2 × V

REF

p-p

220Ω

V+

0

0.5

1.0

1.5

2.0

2.5

3.0

V

(V)

REF

440Ω

1.25V

V

REF

27Ω

AD7265¹

V

Figure 28. V_IN−Input Voltage Range vs. V_REFin

Pseudo Differential Mode with V_DD= 3 V

IN+

GND

V–

220Ω

V+

2.5

2.0

1.5

1.0

0.5

0

T

= 25°C

A

3.75V

2.5V

1.25V

27Ω

D

A/D

B

CAP

IN–

CAP

A

V–

10kΩ

0.47µF

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 26. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal

into a Differential Signal

3.75V

2.5V

2 × V

REF

p-p

220Ω

V+

–0.5

0

0.5

1.0

1.5

2.0

2.5

V (V)

REF

3.0

3.5

4.0

4.5

5.0

440Ω

1.25V

GND

27Ω

AD7265¹

V

IN+

Figure 29. V_IN−Input Voltage Range vs. V_REFin

Pseudo Differential Mode with V_DD= 5 V

V–

220Ω

V+

220kΩ

3.75V

2.5V

V

REF

p–p

AD7265¹

V

IN+

1.25V

27Ω

V

D

A/D

B

CAP

IN–

CAP

A

V–

V

10kΩ

IN–

V

DC INPUT

VOLTAGE

0.47µF

REF

20kΩ

0.47µF

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 27. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal

into a Differential Unipolar Signal

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 30. Pseudo Differential Mode Connection Diagram

Rev. A | Page 16 of 28

AD7265

The channels used for simultaneous conversions are selected via

the multiplexer address input pins, A0 to A2. The logic states of

these pins also need to be established prior to the acquisition

time; however, they may change during the conversion time,

provided that the mode is not changed. If the mode is changed

from fully differential to pseudo-differential, for example, then

the acquisition time would start again from this point. The

selected input channels are decoded as shown in Table 6.

ANALOG INPUT SELECTION

The analog inputs of the AD7265 can be configured as single-

ended or true differential via the SGL/

DIFF

logic pin, as shown

in Figure 31. If this pin is tied to a logic low, the analog input

channels to each on-chip ADC are set up as three true differen-

tial pairs. If this pin is at logic high, the analog input channels to

each on-chip ADC are set up as six single-ended analog inputs.

The required logic level on this pin needs to be established prior

to the acquisition time and remain unchanged during the con-

version time until the track-and-hold has returned to track. The

track-and-hold returns to track on the 13^thrising edge of SCLK

The analog input range of the AD7265 can be selected as 0 V to

V

_REFor 0 V to 2 × V_REFvia the RANGE pin. This selection is

DIFF

made in a similar fashion to that of the SGL/

pin by setting

the logic state of the RANGE pin a time t_acqprior to the falling

CS

after the

falling edge (see Figure 41). If the level on this pin

CS

edge of . Subsequent to this, the logic level on this pin can be

is changed, it is recognized by the AD7265; therefore, it is

necessary to keep the same logic level during acquisition and

conversion to avoid corrupting the conversion in progress.

altered after the third falling edge of SCLK. If this pin is tied to a

logic low, the analog input range selected is 0 V to V_REF. If this

pin is tied to a logic high, the analog input range selected is 0 V

DIFF

For example, in Figure 31, the SGL/

for the duration of both the acquisition and conversion times

so the analog inputs are configured as single ended for that

pin is set at logic high

to 2 × V_REF

.

OUTPUT CODING

DIFF

conversion (Sampling Point A). The logic level of the SGL/

changed to low after the track-and-hold returned to track and

prior to the required acquisition time for the next sampling

instant at Point B; therefore, the analog inputs are configured as

differential for that conversion.

The AD7265 output coding is set to either twos complement or

straight binary, depending on which analog input configuration

is selected for a conversion. Table 5 shows which output coding

scheme is used for each possible analog input configuration.

Table 5. AD7265 Output Coding

A

B

t_ACQ

DIFF

Range

Output Coding

CS

SGL/

DIFF

SGL

1

14

1

14

0 V to V_REF

0 V to 2 × V_REF

0 V to V_REF

Twos complement

Straight binary

SCLK

SGL/DIFF

SGL

PSEUDO DIFF

0 V to 2 × V_REF

0 V to V_REF

0 V to 2 × V_REF

Twos complement

Straight binary

Twos complement

Figure 31. Selecting Differential or Single-Ended Configuration

Table 6. Analog Input Type and Channel Selection

ADC A

V_IN−

ADC B

V_IN−

DIFF

V_IN+

Comment

A2

0

1

0

1

A1

0

1

0

1

0

A0

0

1

0

1

0

1

0

1

0

1

0

1

SGL/

1

0

V_A1

V_A2

V_A3

V_A4

V_A5

V_A6

V_A1

V_A3

V_A5

AGND

V_B1

V_B2

V_B3

V_B4

V_B5

V_B6

V_B1

V_B3

V_B5

AGND

V_B2

V_B4

V_B6

Single ended

Fully differential

Pseudo differential

Fully differential

Pseudo differential

Fully differential

Pseudo differential

AGND

V_A2

V_A4

V_A6

V_B6

Rev. A | Page 17 of 28

AD7265

TRANSFER FUNCTIONS

DIGITAL INPUTS

The designed code transitions occur at successive integer LSB

values (1 LSB, 2 LSB, and so on). In single-ended mode, the LSB

size is V_REF/4096 when the 0 V to V_REFrange is used, and the LSB

size is 2 × V_REF/4096 when the 0 V to 2 × V_REFrange is used. In

differential mode, the LSB size is 2 × V_REF/4096 when the 0 V to

The digital inputs applied to the AD7265 are not limited by the

maximum ratings that limit the analog inputs. Instead, the

digital inputs can be applied up to 7 V and are not restricted by

the V_DD+ 0.3 V limit, as are the analog inputs. See the Absolute

Maximum Ratings section for more information. Another

V_REFrange is used, and the LSB size is 4 × V_REF/4096 when the

CS

advantage of the SCLK, RANGE, A0 to A2, and pins not

0 V to 2 × V_REFrange is used. The ideal transfer characteristic

for the AD7265 when straight binary coding is output is shown

in Figure 32, and the ideal transfer characteristic for the AD7265

when twos complement coding is output is shown (with the 2 ×

being restricted by the V_DD+ 0.3 V limit is that power supply

sequencing issues are avoided. If one of these digital inputs is

applied before V_DD, there is no risk of latch-up, as there would

be on the analog inputs if a signal greater than 0.3 V were

applied prior to V_DD.

V_REFrange) in Figure 33.

V_DRIVE

111...111

111...110

The AD7265 also has a V_DRIVEfeature to control the voltage at

which the serial interface operates. V_DRIVEallows the ADC to

easily interface to both 3 V and 5 V processors. For example, if

the AD7265 was operated with a V_DDof 5 V, the V_DRIVEpin

could be powered from a 3 V supply, allowing a large dynamic

range with low voltage digital processors. Therefore, the

AD7265 could be used with the 2 × V_REFinput range, with a V_DD

of 5 V while still being able to interface to 3 V digital parts.

111...000

011...111

1LSB = V

/4096

REF

000...010

000...001

000...000

V

– 1LSB

1LSB

REF

0V

ANALOG INPUT

NOTE

1. V

IS EITHER V

REF

OR 2 × V .

REF

Figure 32. Straight Binary Transfer Characteristic

1LSB = 2

×

V

/4096

REF

011...111

011...110

000...001

000...000

111...111

100...010

100...001

100...000

–V

+ 1LSB V

– 1LSB

+V

– 1 LSB

REF

ANALOG INPUT

Figure 33. Twos Complement Transfer Characteristic with

V_REFV_REFInput Range

Rev. A | Page 18 of 28

AD7265

MODES OF OPERATION

The mode of operation of the AD7265 is selected by controlling

the (logic) state of the signal during a conversion. There are

Once 32 SCLK cycles have elapsed, the D_OUTline returns to

nd

CS

three-state on the 32 SCLK falling edge. If

is brought high

prior to this, the D_OUTline returns to three-state at that point.

CS

three possible modes of operation: normal mode, partial power-

down mode, and full power-down mode. After a conversion is

Therefore,

may idle low after 32 SCLK cycles until it is

CS

initiated, the point at which

power-down mode, if any, the device enters. Similarly, if already

in a power-down mode, can control whether the device

is pulled high determines which

brought high again sometime prior to the next conversion

CS

returns to three-state upon completion of the dual result read.

(effectively idling

low), if so desired, because the bus still

CS

returns to normal operation or remains in power-down. These

modes of operation are designed to provide flexible power

management options. These options can be chosen to optimize

the power dissipation/throughput rate ratio for differing

application requirements.

Once a data transfer is complete and D_OUTA and D_OUTB have

returned to three-state, another conversion can be initiated after

CS

the quiet time, t_QUIET, has elapsed by bringing

low again

(assuming the required acquisition time is allowed).

PARTIAL POWER-DOWN MODE

NORMAL MODE

This mode is intended for use in applications where slower

throughput rates are required. Either the ADC is powered down

between each conversion, or a series of conversions may be

performed at a high throughput rate, and the ADC is then

powered down for a relatively long duration between these

bursts of several conversions. When the AD7265 is in partial

power-down, all analog circuitry is powered down except for

the on-chip reference and reference buffer.

This mode is intended for applications that need the fastest

throughput rates because the user does not have to worry about

any power-up times with the AD7265 remaining fully powered

at all times. Figure 34 shows the general diagram of the

operation of the AD7265 in this mode.

CS

1

10

14

SCLK

To enter partial power-down mode, the conversion process

CS

must be interrupted by bringing

second falling edge of SCLK and before the 10^thfalling edge of

CS

high anywhere after the

D

A

B

OUT

LEADING ZEROS + CONVERSION RESULT

SCLK, as shown in Figure 35. Once

window of SCLKs, the part enters partial power-down, the

CS

is brought high in this

Figure 34. Normal Mode Operation

CS

The conversion is initiated on the falling edge of , as

described in the Serial Interface section. To ensure that the part

remains fully powered up at all times,

at least 10 SCLK falling edges have elapsed after the falling edge

conversion that was initiated by the falling edge of

terminated, and D_OUTA and D_OUTB go back into three-state. If

CS

is

CS

must remain low until

is brought high before the second SCLK falling edge, the

part remains in normal mode and does not power down. This

th

CS CS

of . If

is brought high any time after the 10 SCLK falling

CS

avoids accidental power-down due to glitches on the

line.

edge but before the 14^thSCLK falling edge, the part remains

powered up, but the conversion is terminated and D_OUTA and

CS

D

_OUTB go back into three-state. Fourteen serial clock cycles are

1

2

10

14

SCLK

required to complete the conversion and access the conversion

result. The D_OUTline does not return to three-state after 14

D

A

B

THREE-STATE

CS

SCLK cycles have elapsed, but instead does so when

is

is left low for another 2 SCLK cycles

(for example, if only a 16 SCLK burst is available), two trailing

CS

OUT

CS

brought high again. If

Figure 35. Entering Partial Power-Down Mode

zeros are clocked out after the data. If

is left low for a further

14 (or 16) SCLK cycles, the result from the other ADC on board

is also accessed on the same D_OUTline, as shown in Figure 42

(see the Serial Interface section).

Rev. A | Page 19 of 28

AD7265

To exit this mode of operation and power up the AD7265 again,

When the AD7265 is in full power-down, all analog circuitry is

powered down. Full power-down is entered in a similar way as

partial power-down, except the timing sequence shown in

Figure 35 must be executed twice. The conversion process must

CS

a dummy conversion is performed. On the falling edge of

,

the device begins to power up and continues to power up as

th

CS

long as

is held low until after the falling edge of the 10

CS

be interrupted in a similar fashion by bringing high anywhere

SCLK. The device is fully powered up after approximately 1 μs

has elapsed, and valid data results from the next conversion, as

after the second falling edge of SCLK and before the 10^thfalling

edge of SCLK. The device enters partial power-down at this

point. To reach full power-down, the next conversion cycle

must be interrupted in the same way, as shown in Figure 37.

CS

shown in Figure 36. If

is brought high before the second

falling edge of SCLK, the AD7265 again goes into partial

power-down. This avoids accidental power-up due to glitches

CS

Once

is brought high in this window of SCLKs, the part

CS

on the

line. Although the device may begin to power up on

CS

completely powers down.

the falling edge of , it powers down again on the rising edge

CS

of . If the AD7265 is already in partial power-down mode

CS

Note that it is not necessary to complete the 14 SCLKs once

is brought high to enter a power-down mode.

th

CS

and

is brought high between the second and 10 falling

edges of SCLK, the device enters full power-down mode.

To exit full power-down and power up the AD7265, a dummy

conversion is performed, as when powering up from partial

FULL POWER-DOWN MODE

CS

power-down. On the falling edge of , the device begins to

This mode is intended for use in applications where throughput

rates slower than those in the partial power-down mode are

required, as power-up from a full power-down takes

substantially longer than that from partial power-down. This

mode is more suited to applications where a series of

CS

power up and continues to power up, as long as

is held low

until after the falling edge of the 10^thSCLK. The required

power-up time must elapse before a conversion can be initiated,

as shown in Figure 38. See the Power-Up Times section for the

power-up times associated with the AD7265.

conversions performed at a relatively high throughput rate are

followed by a long period of inactivity and thus power-down.

THE PART IS FULLY

POWERED UP; SEE

POWER-UP TIMES

SECTION.

THE PART BEGINS

TO POWER UP.

t_POWER-UP1

CS

1

10

14

1

14

SCLK

D

A

B

OUT

INVALID DATA

VALID DATA

OUT

Figure 36. Exiting Partial Power-Down Mode

THE PART ENTERS

PARTIAL POWER DOWN.

THE PART BEGINS

TO POWER UP.

THE PART ENTERS

FULL POWER DOWN.

CS

1

2

10

14

1

2

10

14

SCLK

D

A

B

THREE-STATE

OUT

INVALID DATA

OUT

Figure 37. Entering Full Power-Down Mode

Rev. A | Page 20 of 28

AD7265

THE PART IS FULLY POWERED UP,

SEE POWER-UP TIMES SECTION.

THE PART BEGINS

TO POWER UP.

t_POWER-UP2

CS

14

10

1

SCLK

D

A

B

OUT

INVALID DATA

VALID DATA

OUT

Figure 38. Exiting Full Power-Down Mode

can be used to make significant power savings. However, the

AD7265 quiescent current is low enough that even without

using the power-down options, there is a noticeable variation in

power consumption with sampling rate. This is true whether a

fixed SCLK value is used or if it is scaled with the sampling rate.

Figure 39 and Figure 40 show plots of power vs. the throughput

rate when operating in normal mode for a fixed maximum

SCLK frequency, and an SCLK frequency that scales with the

sampling rate with V_DD= 3 V and V_DD= 5 V, respectively. In all

cases, the internal reference was used.

POWER-UP TIMES

As described in detail, the AD7265 has two power-down

modes, partial power-down and full power-down. This section

deals with the power-up time required when coming out of

either of these modes. It should be noted that the power-up

times, as explained in this section, apply with the recommended

capacitors in place on the D_CAPA and D_CAPB pins.

To power up from full power-down (whether using an internal

or external reference), approximately 1.5 ms should be allowed

from the falling edge of , shown as t_POWER-UP2in Figure 38.

Powering up from partial power-down requires much less time.

The power-up time from partial power-down is typically 1 μs;

however, if using the internal reference, then the AD7265 must

be in partial power-down for at least 67 μs in order for this

power-up time to apply.

CS

10.0

T

= 25°C

A

9.5

9.0

8.5

8.0

7.5

7.0

6.5

6.0

5.5

5.0

When power supplies are first applied to the AD7265, the ADC

may power up in either of the power-down modes or normal

mode. Because of this, it is best to allow a dummy cycle to

elapse to ensure the part is fully powered up before attempting a

valid conversion. Likewise, if it is intended to keep the part in

the partial power-down mode immediately after the supplies are

VARIABLE SCLK

16MHz SCLK

applied, then two dummy cycles must be initiated. The first

dummy cycle must hold

0

100 200 300 400 500 600 700 800 900 1000

THROUGHPUT (kSPS)

th

CS

low until after the 10 SCLK falling

Figure 39. Power vs. Throughput in Normal Mode with V_DD= 3 V

edge (see Figure 34); in the second cycle,

must be brought

CS

high before the 10^thSCLK edge but after the second SCLK

falling edge (see Figure 35). Alternatively, if it is intended to

place the part in full power-down mode when the supplies are

applied, then three dummy cycles must be initiated. The first

25

T

= 25°C

A

23

21

19

17

15

13

11

9

dummy cycle must hold

low until after the 10^thSCLK falling

CS

VARIABLE SCLK

16MHz SCLK

edge (see Figure 34); the second and third dummy cycles place

the part in full power-down (see Figure 37).

Once supplies are applied to the AD7265, enough time must be

allowed for any external reference to power up and charge the

various reference buffer decoupling capacitors to their final values.

7

POWER vs. THROUGHPUT RATE

5

The power consumption of the AD7265 varies with throughput

rate. When using very slow throughput rates and as fast an

SCLK frequency as possible, the various power-down options

0

100 200 300 400 500 600 700 800 900 1000

THROUGHPUT (kSPS)

Figure 40. Power vs. Throughput in Normal Mode with V_DD= 5 V

Rev. A | Page 21 of 28

AD7265

SERIAL INTERFACE

Figure 41 shows the detailed timing diagram for serial inter-

facing to the AD7265. The serial clock provides the conversion

clock and controls the transfer of information from the AD7265

during conversion.

A minimum of 14 serial clock cycles are required to perform

the conversion process and to access data from one conversion

CS

on either data line of the AD7265.

going low provides the

leading zero to be read in by the microcontroller or DSP. The

remaining data is then clocked out by subsequent SCLK falling

edges, beginning with a second leading zero. Therefore, the first

falling clock edge on the serial clock has the leading zero pro-

vided and also clocks out the second leading zero. The 12-bit

result then follows with the final bit in the data transfer valid on

the 14^thfalling edge, having being clocked out on the previous

(13^th) falling edge. It may also be possible to read in data on

each SCLK rising edge depending on the SCLK frequency or

CS

The

signal initiates the data transfer and conversion process.

CS

The falling edge of

puts the track-and-hold into hold mode,

at which point the analog input is sampled and the bus is taken

out of three-state. The conversion is also initiated at this point

and requires a minimum of 14 SCLKs to complete. Once 13

SCLK falling edges have elapsed, the track-and-hold goes back

into track on the next SCLK rising edge, as shown in Figure 41

at Point B. If a 16-SCLK transfer is used, then two trailing zeros

CS

the supply voltage. The first rising edge of SCLK after the

CS

will appear after the final LSB. On the rising edge of , the

conversion is terminated and D_OUTA and D_OUTB go back into

falling edge would have the second leading zero provided, and

the 13^thrising SCLK edge would have DB0 provided.

CS

three-state. If

is not brought high but is instead held low for

Note that with fast SCLK values, and thus short SCLK periods,

in order to allow adequately for t₂, an SCLK rising edge may

occur before the first SCLK falling edge. This rising edge of

SCLK can be ignored for the purposes of the timing descriptions in

this section. If a falling edge of SCLK is coincident with the

a further 14 (or 16) SCLK cycles on D_OUTA, the data from Con-

version B is output on D_OUTA (followed by 2 trailing zeros).

CS

Likewise, if

is held low for a further 14 (or 16) SCLK cycles

on D_OUTB, the data from Conversion A is output on D_OUTB. This

is illustrated in Figure 42 where the case for D_OUTA is shown. In

CS

falling edge of , then this falling edge of SCLK is not

this case, the D_OUTline in use goes back into three-state on the

acknowledged by the AD7265, and the next falling edge of

nd

CS

32 SCLK falling edge or the rising edge of , whichever

CS

SCLK will be the first registered after the falling edge of

.

occurs first.

CS

t₉

t₂

t₆

B

SCLK

3

4

5

1

2

13

t₅

t_QUIET

t₈

t₇

t₃

t₄

D

A

B

OUT

0

DB11

DB10

DB2

0

DB9

DB8

DB1

DB0

THREE-STATE

THREE-

STATE

2 LEADING ZEROS

Figure 41. Serial Interface Timing Diagram

CS

t₆

t₂

SCLK

3

4

5

1

2

14

15

16

17

32

t₅

t₁₀

t₃

t₄

t₇

DB11

DB10

DB9

DB11

B

0

ZERO

D

A

OUT

THREE-

STATE

THREE-

STATE

2 TRAILING ZEROS

2 LEADING ZEROS

2 LEADING

ZEROS

2 TRAILING ZEROS

Figure 42. Reading Data from Both ADCs on One D_OUTLine with 32 SCLKs

Rev. A | Page 22 of 28

AD7265

MICROPROCESSOR INTERFACING

The serial interface on the AD7265 allows the part to be directly

connected to a range of many different microprocessors. This

section explains how to interface the AD7265 with some of the

more common microcontroller and DSP serial interface

protocols.

The connection diagram is shown in Figure 43. The ADSP-218x

has the TFS0 and RFS0 of the SPORT0 and the RFS1 of

SPORT1 tied together. TFS0 is set as an output, and both RFS0

and RFS1 are set as inputs. The DSP operates in alternate

framing mode, and the SPORT control register is set up as

described. The frame synchronization signal generated on the

AD7265 TO ADSP-218x

CS

TFS is tied to , and, as with all signal processing applications,

The ADSP-218x family of DSPs interface directly to the

AD7265 without any glue logic required. The V_DRIVEpin of the

AD7265 takes the same supply voltage as that of the ADSP-218x.

This allows the ADC to operate at a higher supply voltage than

its serial interface and, therefore, the ADSP-218x, if necessary.

This example shows both D_OUTA and D_OUTB of the AD7265

connected to both serial ports of the ADSP-218x. The SPORT0

and SPORT1 control registers should be set up as shown in

Table 7 and Table 8.

equidistant sampling is necessary. However, in this example, the

timer interrupt is used to control the sampling rate of the ADC

and, under certain conditions, equidistant sampling may not be

achieved.

ADSP-218x¹

AD7265¹

SCLK

SCLK0

SCLK1

TFS0

RFS0

RFS1

DR0

CS

Table 7. SPORT0 Control Register Setup

Setting

Description

D

A

B

OUT

TFSW = RFSW = 1

INVRFS = INVTFS = 1

DTYPE = 00

Alternate framing

Active low frame signal

Right justify data

DR1

OUT

V

DRIVE

SLEN = 1111

16-bit data-word (or may be set to

1101 for 14-bit data-word)

V

DD

ISCLK = 1

TFSR = RFSR = 1

IRFS = 0

Internal serial clock

Frame every word

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 43. Interfacing the AD7265 to the ADSP-218x

ITFS = 1

The timer registers are loaded with a value that provides an

interrupt at the required sample interval. When an interrupt is

received, a value is transmitted with TFS/DT (ADC control

word). The TFS is used to control the RFS, and hence, the

reading of data. The frequency of the serial clock is set in the

SCLKDIV register. When the instruction to transmit with TFS

is given (AX0 = TX0), the state of the SCLK is checked. The

DSP waits until the SCLK has gone high, low, and high again

before transmission starts. If the timer and SCLK values are

chosen such that the instruction to transmit occurs on or near

the rising edge of SCLK, then the data may be transmitted or it

may wait until the next clock edge.

Table 8. SPORT1 Control Register Setup

Setting

Description

TFSW = RFSW = 1

INVRFS = INVTFS = 1

DTYPE = 00

Alternate framing

Active low frame signal

Right justify data

16-bit data-word (or may be set to

1101 for 14-bit data-word)

SLEN = 1111

ISCLK = 0

TFSR = RFSR = 1

IRFS = 0

External serial clock

Frame every word

ITFS = 1

For example, the ADSP-2111 has a master clock frequency of

16 MHz. If the SCLKDIV register is loaded with the value 3,

then an SCLK of 2 MHz is obtained, and eight master clock

periods will elapse for every one SCLK period. If the timer

registers are loaded with the value 803, then 100.5 SCLKs will

occur between interrupts and, subsequently, between transmit

instructions. This situation yields sampling that is not equidistant,

as the transmit instruction is occurring on a SCLK edge. If the

number of SCLKs between interrupts is a whole integer figure

of N, then equidistant sampling will be implemented by the DSP.

To implement the power-down modes, SLEN should be set to

1001 to issue an 8-bit SCLK burst.

Rev. A | Page 23 of 28

AD7265

AD7265 to ADSP-BF53x

AD7265 TO TMS320C541

The ADSP-BF53x family of DSPs interface directly to the

AD7265 without any glue logic required. The availability of

secondary receive registers on the serial ports of the Blackfin®

DSPs means only one serial port is necessary to read from both

The serial interface on the TMS320C541 uses a continuous

serial clock and frame synchronization signals to synchronize

the data transfer operations with peripheral devices like the

CS

AD7265. The

input allows easy interfacing between the

D

_OUTpins simultaneously. Figure 44 shows both D_OUTA and

_OUTB of the AD7265 connected to Serial Port 0 of the

TMS320C541 and the AD7265 without any glue logic required.

The serial ports of the TMS320C541 are set up to operate in

burst mode with internal CLKX0 (TX serial clock on Serial

Port 0) and FSX0 (TX frame sync from Serial Port 0). The serial

port control registers (SPC) must have the following setup.

D

ADSP-BF53x. The SPORT0 Receive Configuration 1 register

and SPORT0 Receive Configuration 2 register should be set up

as outlined in Table 9 and Table 10.

ADSP-BF53x¹

SPORT0

AD7265¹

SERIAL

DEVICE A

(PRIMARY)

Table 11. Serial Port Control Register Setup

SPC

FO

FSM

MCM

TXM

D

A

DR0PRI

RCLK0

RFS0

OUT

SPC0

SPC1

0

1

0

1

0

SCLK

CS

D

V

B

DR0SEC

OUT

The format bit, FO, may be set to 1 to set the word length to

8 bits to implement the power-down modes on the AD7265.

SERIAL

DEVICE B

(SECONDARY)

DRIVE

The connection diagram is shown in Figure 45. For signal

processing applications, it is imperative that the frame

synchronization signal from the TMS320C541 provide

equidistant sampling. The V_DRIVEpin of the AD7265 takes the

same supply voltage as that of the TMS320C541. This allows the

ADC to operate at a higher voltage than its serial interface, and

therefore, the TMS320C541, if necessary.

V

DD

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 44. Interfacing the AD7265 to the ADSP-BF53x

Table 9. The SPORT0 Receive Configuration 1 Register

(SPORT0_RCR1)

AD7265¹

Setting

Description

TMS320C541¹

SCLK

CLKX0

RCKFE = 1

LRFS = 1

RFSR = 1

Sample data with falling edge of RSCLK

Active low frame signal

Frame every word

Internal RFS used

Receive MSB first

Zero fill

Internal receive clock

Receive enabled

16-bit data-word (or may be set to 1101

for 14-bit data-word)

CLKR0

CLKX1

CLKR1

DR0

IRFS = 1

RLSBIT = 0

RDTYPE = 00

IRCLK = 1

RSPEN = 1

D

A

B

OUT

DR1

OUT

CS

FSX0

FSR0

FSR1

V

DRIVE

SLEN = 1111

TFSR = RFSR = 1

V

DD

Table 10. The SPORT0 Receive Configuration 2 Register

(SPORT0_RCR2)

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 45. Interfacing the AD7265 to the TMS320C541

Setting

Description

RXSE = 1

Secondary side enabled

SLEN = 1111

16-bit data-word (or may be set to 1101

for 14-bit data-word)

To implement the power-down modes, SLEN should be set to

1001 to issue an 8-bit SCLK burst. A Blackfin driver for the

AD7265 is available to download at www.analog.com.

Rev. A | Page 24 of 28

AD7265

In the example shown in Figure 46, the serial clock is taken

AD7265 TO DSP563xx

from the ESSI0 so the SCK0 pin must be set as an output,

SCKD = 1, while the SCK1 pin is set as an input, SCKD = 0. The

frame sync signal is taken from SC02 on ESSI0, so SCD2 = 1,

while on ESSI1, SCD2 = 0; therefore, SC12 is configured as an

input. The V_DRIVEpin of the AD7265 takes the same supply

voltage as that of the DSP563xx. This allows the ADC to operate

at a higher voltage than its serial interface and therefore the

DSP563xx, if necessary.

The connection diagram in Figure 46 shows how the AD7265

can be connected to the ESSI (synchronous serial interface) of

the DSP563xx family of DSPs from Motorola. There are two

on-board ESSIs, and each operates in synchronous mode

(Bit SYN = 1 in CRB register) with internally generated word

length frame sync for both TX and RX (Bit FSL1 = 0 and

Bit FSL0 = 0 in CRB).

Normal operation of the ESSI is selected by making MOD = 0

in the CRB. Set the word length to 16 by setting Bit WL1 = 1

and Bit WL0 = 0 in CRA.

DSP563xx¹

AD7265¹

SCLK

SCK0

SCK1

SRD0

SRD1

SC02

SC12

To implement the power-down modes on the AD7265, the

word length can be changed to 8 bits by setting Bit WL1 = 0 and

Bit WL0 = 0 in CRA. The FSP bit in the CRB should be set to 1

so the frame sync is negative. It is imperative for signal

processing applications that the frame synchronization signal

from the DSP563xx provides equidistant sampling.

D

A

B

OUT

CS

V

DRIVE

V

DD

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 46. Interfacing the AD7265 to the DSP563xx

Rev. A | Page 25 of 28

AD7265

APPLICATION HINTS

GROUNDING AND LAYOUT

PCB DESIGN GUIDELINES FOR LFCSP

The lands on the chip scale package (CP-32-3) are rectangular.

The PCB pad for these should be 0.1 mm longer than the

package land length, and 0.05 mm wider than the package land

width, thereby having a portion of the pad exposed. To ensure

that the solder joint size is maximized, the land should be

centered on the pad.

The analog and digital supplies to the AD7265 are independent

and separately pinned out to minimize coupling between the

analog and digital sections of the device. The printed circuit

board (PCB) that houses the AD7265 should be designed so

that the analog and digital sections are separated and confined

to certain areas of the board. This design facilitates the use of

ground planes that can be easily separated.

The bottom of the chip scale package has a thermal pad. The

thermal pad on the PCB should be at least as large as the

exposed pad. On the PCB, there should be a clearance of at least

0.25 mm between the thermal pad and the inner edges of the

pad pattern to ensure that shorting is avoided.

To provide optimum shielding for ground planes, a minimum

etch technique is generally best. All three AGND pins of the

AD7265 should be sunk in the AGND plane. Digital and analog

ground planes should be joined in only one place. If the AD7265

is in a system where multiple devices require an AGND to DGND

connection, the connection should still be made at one point

only, a star ground point that should be established as close as

possible to the ground pins on the AD7265.

To improve thermal performance of the package, use thermal

vias on the PCB incorporating them in the thermal pad at

1.2 mm pitch grid. The via diameter should be between 0.3 mm

and 0.33 mm, and the via barrel should be plated with 1 oz.

copper to plug the via. The user should connect the PCB

thermal pad to AGND.

Avoid running digital lines under the device as this couples

noise onto the die. However, the analog ground plane should be

allowed to run under the AD7265 to avoid noise coupling. The

power supply lines to the AD7265 should use as large a trace as

possible to provide low impedance paths and reduce the effects

of glitches on the power supply line.

EVALUATING THE AD7265 PERFORMANCE

The recommended layout for the AD7265 is outlined in the

evaluation board documentation. The evaluation board package

includes a fully assembled and tested evaluation board, docu-

mentation, and software for controlling the board from the PC

via the evaluation board controller. The evaluation board con-

troller can be used in conjunction with the AD7265 evaluation

board, as well as many other Analog Devices, Inc. evaluation

boards ending in the CB designator, to demonstrate/evaluate

the ac and dc performance of the AD7265.

To avoid radiating noise to other sections of the board, fast

switching signals, such as clocks, should be shielded with digital

ground, and clock signals should never run near the analog

inputs. Avoid crossover of digital and analog signals. To reduce

the effects of feedthrough within the board, traces on opposite

sides of the board should run at right angles to each other. A

microstrip technique is the best method but is not always

possible with a double-sided board. In this technique, the

component side of the board is dedicated to ground planes,

while signals are placed on the solder side.

The software allows the user to perform ac (fast Fourier

transform) and dc (histogram of codes) tests on the AD7265.

The software and documentation are on a CD shipped with the

evaluation board.

Good decoupling is also important. All analog supplies should

be decoupled with 10 μF tantalum capacitors in parallel with

0.1 μF capacitors to GND. To achieve the best results from these

decoupling components, they must be placed as close as

possible to the device, ideally right up against the device. The

0.1 μF capacitors should have low effective series resistance

(ESR) and effective series inductance (ESI), such as the

common ceramic types or surface-mount types. These low ESR

and ESI capacitors provide a low impedance path to ground at

high frequencies to handle transient currents due to internal

logic switching.

Rev. A | Page 26 of 28

AD7265

OUTLINE DIMENSIONS

5.00

BSC SQ

0.60 MAX

PIN 1

INDICATOR

25

24

32

1

PIN 1

INDICATOR

0.50

BSC

TOP

VIEW

3.25

3.10 SQ

2.95

EXPOSED

PAD

(BOTTOM VIEW)

4.75

BSC SQ

0.50

0.40

0.30

17

16

8

9

0.25 MIN

3.50 REF

0.80 MAX

0.65 TYP

12° MAX

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

Figure 47. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad (CP-32-2)

Dimensions shown in millimeters

1.20

0.75

0.60

0.45

MAX

9.00 BSC SQ

25

32

1

24

PIN 1

7.00

BSC SQ

TOP VIEW

(PINS DOWN)

0° MIN

1.05

1.00

0.95

0.20

0.09

7°

8

17

3.5°

0°

0.15

0.05

9

16

SEATING

PLANE

0.08 MAX

COPLANARITY

VIEW A

0.80

0.45

0.37

0.30

BSC

LEAD PITCH

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026ABA

Figure 48. 32-Lead Thin Plastic Quad Flat Package [TQFP]

(SU-32-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model

AD7265BCP

AD7265BCPZ¹

AD7265BCPZ-REEL7¹

AD7265BCPZ-REEL¹

AD7265BSUZ¹

AD7265BSUZ-REEL7¹

AD7265BSUZ-REEL¹

EVAL-AD7265CB²

EVAL-CONTROL BRD2³

Temperature Range

–40ꢁC to +125ꢁC

Package Description

32-Lead LFCSP_VQ

32-Lead TQFP

Evaluation Board

Control Board

Package Option

CP-32-2

SU-32-2

–40ꢁC to +125ꢁC

¹Z = Pb-free part.

²This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL board for evaluation/demonstration purposes.

³This board is a complete unit allowing a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designators. To order a

complete evaluation kit, the particular ADC evaluation board (such as, EVAL-AD7265CB), the EVAL-CONTROL BRD2, and a 12 V transformer must be ordered. See the

relevant evaluation board technical note for more information.

Rev. A | Page 27 of 28

AD7265

NOTES

registered trademarks are the property of their respective owners.

D04674-0-11/06(A)

Rev. A | Page 28 of 28


型号：	AD7265BCPZ-REEL
厂家：	ADI
描述：	Differential/Single-Ended Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC 差分/单端输入，双通道1 MSPS ， 12位， 3通道SAR ADC 转换器模数转换器
文件：	总28页 (文件大小：690K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7265BCPZ-REEL [ADI]

相关型号：

AD7265BCPZ-REEL7

AD7265BSU

AD7265BSUZ

AD7265BSUZ-REEL

AD7265BSUZ-REEL7

AD7266

AD7266ACP

AD7266ASU

AD7266BCP

AD7266BCPZ

AD7266BCPZ-REEL

AD7266BCPZ-REEL7