AD7265_技术文档

Differential Input, Dual 1 MSPS,

12-Bit, 3-Channel SAR ADC

Preliminary Technical Data

AD7265

FUNCTIONAL BLOCK DIAGRAM

FEATURES

Dual 12-bit, 3-channel ADC

AVdd DVdd

D

A

REF SELECT

cap

Fast throughput rate: 1 MSPS

Specified for V_DDof 2.7 V to 5.25 V

Low power: 7 mW max at 1 MSPS with 3 V supplies

16.5 mW max at 1 MSPS with 5 V supplies

Wide input bandwidth

BUF

REF

AD7265

V

A1

12-BIT

OUTPUT

DRIVERS

SUCCESSIVE

APPROXIMATION

ADC

D

A

T/H

A2

OUT

MUX

V

A3

70 dB SNR at 100 kHz input frequency

On-chip reference: 2.5 V

SCLK

V

A4

CS

–40°C to +125°C operation

V

RANGE

A5

CONTROL

LOGIC

DIFF/SE

A0

A1

Flexible power/throughput rate management

Simultaneous conversion/read

No pipeline delays

V

A6

A2

V

B1

V

High speed serial interface SPI®/QSPI™/MICROWIRE™/DSP

compatible

Shutdown mode: 1 µA max

DRIVE

B2

12-BIT

SUCCESSIVE

APPROXIMATION

ADC

OUTPUT

DRIVERS

B3

B4

T/H

D

B

OUT

V

MUX

32-lead LFCSP and TQFP packages

V

B5

B6

BUF

GENERAL DESCRIPTION

The AD7265 is a dual, 12-bit, high speed, low power, successive

approximation ADC that operates from a single 2.7 V to 5.25 V

power supply and features throughput rates up to 1 MSPS. The

device contains two ADCs, each preceded by a 3-channel multi-

plexer, and a low noise, wide bandwidth track-and-hold amplifier

that can handle input frequencies in excess of 10 MHz.

D

B

AGND AGND AGND

DGND

cap

Figure 1

PRODUCT HIGHLIGHTS

1. The AD7265 features two complete ADC functions that allow

simultaneous sampling and conversion of two channels. Each

ADC has 2 analog inputs, 3 fully differential pairs, or 6 single-

ended channels as programmed. The conversion result of both

channels is available simultaneously on separate data lines, or

in succession on one data line if only one serial port is

available.

The conversion process and data acquisition are controlled using

standard control inputs, allowing easy interfacing to microproces-

CS

sors or DSPs. The input signal is sampled on the falling edge of

conversion is also initiated at this point. The conversion time is

;

determined by the SCLK frequency. There are no pipelined delays

associated with the part.

2. High Throughput with Low Power Consumption

The AD7265 offers a 1 MSPS throughput rate with ? mW

maximum power consumption when operating at 3 V.

The AD7265 uses advanced design techniques to achieve very low

power dissipation at high throughput rates. With 5 V supplies and a

1 MSPS throughput rate, the part consumes ? mA maximum. The

part also offers flexible power/throughput rate management when

operating in sleep mode.

3. Flexible Power/Throughput Rate Management

The conversion rate is determined by the serial clock, allowing

power consumption to be reduced as conversion time is re-

duced through an SCLK frequency increase. Power efficiency

can be maximized at lower throughput rates if the part enters

sleep between conversions.

The analog input range for the part can be selected to be a 0 V to

V_REFrange or a 2V_REFrange with either straight binary or twos

complement output coding. The AD7265 has an on-chip 2.5 V

reference that can be overdriven if an external reference is pre-

ferred. This external reference range is 100 mV to 2.5 V. The

AD7265 is available in 32-lead lead frame chip scale (LFCSP) and

thin flat quad (TQFP) lead package.

4. No Pipeline Delay

The part features two standard successive approximation

ADCs with accurate control of the sampling instant via a

input and once off conversion control.

CS

Rev. PrA

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.326.8703

www.analog.com

AD7265

Preliminary Technical Data

TABLE OF CONTENTS

AD7265—Specifications.................................................................. 3

Timing Specifications .................................................................. 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Functional Descriptions.......................... 6

Terminology ...................................................................................... 8

Theory of Operation ...................................................................... 10

Circuit Information.................................................................... 10

Converter Operation.................................................................. 10

Analog Input ............................................................................... 11

Output Coding............................................................................ 11

Transfer Functions ..................................................................... 12

Digital Inputs .............................................................................. 12

V_DRIVE............................................................................................ 12

Modes of Operation....................................................................... 13

Normal Mode.............................................................................. 13

Partial Power-Down Mode ....................................................... 13

Full Power-Down Mode ............................................................ 14

Outline Dimensions....................................................................... 15

Ordering Guide............................................................................... 16

REVISION HISTORY

Revision PrA: Preliminary Version

Rev. PrA | Page 2 of 16

Preliminary Technical Data

AD7265—SPECIFICATIONS¹

AD7265

Table 1. T_A= T_MINto T_MAX, V_DD= 2.7 V to 5.25 V, f_SCLK= 16 MHz, f_S= 1 MSPS, V_DRIVE= 2.7 V to 5.25 V; Reference = 2.5 V 1%,

unless otherwise noted

Parameter

Specification

Unit

Test Conditions/Comments

DYNAMIC PERFORMANCE

Signal-to-Noise + Distortion Ratio (SINAD)²

Total Harmonic Distortion (THD)²

Spurious Free Dynamic Range (SFDR)²

Intermodulation Distortion (IMD)²

Second Order Terms

70

–75

–76

dB min

dB max

f_IN= 100 kHz sine wave

–88

dB typ

Third Order Terms

Channel to Channel Isolation

SAMPLE AND HOLD

Aperture Delay³

Aperture Jitter³

10

50

ns max

ps typ

Aperture Delay Matching³

Full Power Bandwidth

200

20

2.5

ps max

MHz typ

@ 3 dB

@0.1 dB

DC ACCURACY

Resolution

12

1

1.5

0.ꢀ5

Bits

Integral Nonlinearity²

LSB max

0.5 LSB typ; differential configuration

0.5 LSB typ; single-ended configuration

Guaranteed no missed codes to 12 bits

Straight binary output coding

Differential Nonlinearity²

0 V to V_REFInput Range

Offset Error

Offset Error Match

Gain Error

3

0.5

2

LSB max

LSB typ

LSB max

LSB typ

Gain Error Match

0.6

0 V to 2 × V_REFInput Range

Positive Gain Error

Zero Code Error

Zero Code Error Match

Negative Gain Error

ANALOG INPUT

Twos complement output coding

2

3

1

LSB max

LSB typ

LSB max

Input Voltage Ranges

0 V to V_REF

V

CS

RANGE pin low upon falling edge

0 V to 2 x V_REF

CS

RANGE pin high upon falling edge

DC Leakage Current

Input Capactiance

500

1

30

nA max

µA max

pF typ

T_A= –40°C to +85°C

85°C < T_A≤ 125°C

When in track

10

When in hold

REFERENCE INPUT/OUTPUT

Reference Output Voltage⁴

Reference Input Voltage Range

DC Leakage Current

2.4ꢀ/2.51

0.1/2.5

30

V min/V max

µA max

See Typical Performance plots

V_REFpin

160

20

25

10

µA max

pF typ

Ω typ

ppm/°C max

ppm/°C typ

D_CAPA, D_CAPB pins

Input Capactiance

V_REFOutput Impedance⁵

Reference Temperature Coefficient

LOGIC INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current, I_IN

2.8

0.4

1

V min

V max

µA max

pF max

Typically 15 nA, V_IN= 0 V or V_DRIVE

3

Input Capacitance, C_IN

10

Rev. PrA | Page 3 of 16

AD7265

Preliminary Technical Data

Parameter

Specification

Unit

Test Conditions/Comments

LOGIC OUTPUTS

Output High Voltage, V_OH

Output Low Voltage, V_OL

Floating State Leakage Current

Floating State Output Capacitance³

Output Coding

V_DRIVE– 0.2

0.4

1

V min

V max

µA max

pF max

10

Straight (Natural) Binary

Twos Complement

DIFF

SGL/

= 1 with 0 V to V_REFrange selected

DIFF

SGL/

= 0; SGL/

= 1 with 0 V to 2 × V_REFrange

CONVERSION RATE

Conversion Time

Track/Hold Acquisition Time³

Throughput Rate

POWER REQUIREMENTS

V_DD

14

100

TBD

SCLK Cycles

ns max

MSPS max

TBD ns with SCLK = 16 MHz

2.7/5.25

V min/V max

V_DRIVE

6

I_DD

Digital I/Ps = 0 V or V_DRIVE

Normal Mode (Static)

Operational, f_s= 1 MSPS

TBD

3.3

2.3

TBD

mA max

µA max

V_DD= 5 V

V_DD= 3 V

f_s= 200 kSPS

Static

Partial Power-Down Mode

Full Power-Down Mode

Power Dissipation⁶

Normal Mode (Operational)

Partial Power-Down (Static)

Full Power-Down (Static)

16.5

TBD

mW max

V_DD= 5 V

NOTES

¹Temperature ranges as follows: -40°C to +125°C

²See Terminology section.

³Sample tested during initial release to ensure compliance.

⁴Relates to Pins D_CAPA or D_CAPB.

⁵See Reference section for D_CAPA, D_CAPB output impedances.

⁶See Power Versus Throughput Rate section.

TIMING SPECIFICATIONS

Table 2. AV_DD= DV_DD= 2.7 V to 5.25 V, V_DRIVE= 2.7 V to 5.25 V, T_A= T_MAXto T_MIN, unless otherwise noted

Parameter

Limit at T_MIN, T_MAX

Unit

Description

f_SCLK

10

20

14 × t_SCLK

700

35

kHz min

MHz max

ns max

ns min

t_CONVERT

t_SCLK= 1/f_SCLK

f_SCLK= 20 MHz,

t_QUIET

t₂

CS

Minimum time between end of serial read and next falling edge of

10

CS

to SCLK setup time

t₃

t₄

t₅

t₆

t₇

t₈

TBD

ns max

ns min

ns max

CS

Delay from until D_OUTA and D_OUTB are three-state disabled

Data access time after SCLK falling edge.

SCLK low pulse width

TBD

0.4t_SCLK

TBD

SCLK high pulse width

SCLK to data valid hold time

CS

rising edge to D_OUTA, D_OUTB, high impedance

25

t_ꢀ

TBD

ns min

ns max

SCLK falling edge to D_OUTA, D_OUTB, high impedance

Rev. PrA | Page 4 of 16

Preliminary Technical Data

AD7265

ABSOLUTE MAXIMUM RATINGS

Table 3. AD7265 Stress Ratings

Stresses above those listed under Absolute Maximum Ratings

Parameter

Rating

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

V_DDto AGND

DV_DDto DGND

V_DRIVEto DGND

V_DRIVEto AGND

AV_DDto DV_DD

AGND to DGND

Analog Input Voltage to AGND

Digital Input Voltage to DGND

Digital Output Voltage to GND

V_REFto AGND

Input Current to Any Pin Except

Supplies¹

–0.3 V to +7 V

–0.3 V to DV_DD

–0.3 V to AV_DD

–0.3 V to +0.3 V

–0.3 V to AV_DD+0.3 V

–0.3 V to +7 V

–0.3 V to V_DRIVE+0.3 V

–0.3 V to AV_DD+0.3 V

10 mA

Operating Temperature Range

Storage Temperature Range

Junction Temperature

LFCSP Package

–40°C to +125°C

–65°C to +150°C

150°C

θ_JAThermal Impedance

θ_JCThermal Impedance

Lead Temperature, Soldering

Reflow Temperature (10- 30 sec)

ESD

108.2°C/W

32.71°C/W

TBD°C/W

TBD°C

TBD

¹Transient currents of up to 100 mA will not cause SCR latch up.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

Rev. PrA | Page 5 of 16

AD7265

Preliminary Technical Data

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

PIN 1

IDENTIFIER

DGND

1

2

3

4

5

6

7

8

24

23

22

21

20

A1

A2

REF SELECT

AV

DD

SGL/DIFF

D

A

RANGE

CAP

AD7265

TOP VIEW

(Not to Scale)

AGND

D

B

CAP

19 AGND

V

18

17

A1

B1

V

B2

A2

Figure 2. AD7265 Pin Configuration

Table 4. AD7265 Pin Function Descriptions

Pin No. Mnemonic Description

4, 20

D_CAPA,

_CAPB

Decoupling capacitors are connected to these pins to decouple the reference buffer for each respective ADC.. The

on-chip reference can be taken from these pins and applied externally to the rest of a system. The range of the

external reference is dependent on the analog input range selected. See the Reference Configuration Options

section.

D

7–12

18–13

27

V_A1–V_A6

V_B1–V_B6

SCLK

Analog Inputs of ADC A. These may be programmed as six single-ended channels or three true differential analog

input channel pairs. See Table 6.

Analog Inputs of ADC B. These may be programmed as six single-ended channels or three true differential analog

input channel pairs. See Table 6.

Serial Clock. Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7265. This clock

is also used as the clock source for the conversion process.

5, 6, 1ꢀ

AGND

Analog Ground. Ground reference point for all analog circuitry on the AD7265. All analog input signals and any

external reference signal should be referred to this AGND voltage. All three of these AGND pins should connect to

the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential and must not

be more than 0.3 V apart, even on a transient basis.

32

DV_DD

V_DRIVE

DGND

AV_DD

Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the AD7265. The DV_DD

and AV_DDvoltages should ideally be at the same potential and must not be more than 0.3 V apart even on a

transient basis. This supply should be decoupled to DGND.

Logic power supply input. The voltage supplied at this pin determines at what voltage the interface will operate.

This pin should be decoupled to DGND. The voltage at this pin may be different to that at AV_DDand DV_DDbut

should never exceed either by more than 0.3 V.

Digital Ground. This is the ground reference point for all digital circuitry on the AD7265. Both DGND pins should

connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same potential

and must not be more than 0.3 V apart, even on a transient basis.

Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on the AD7265. The

AV_DDand DV_DDvoltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a

transient basis. This supply should be decoupled to AGND.

31

1, 2ꢀ

3

26

CS

Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7265

and frames the serial data transfer.

30, 28

D_OUTA,

Serial Data Outputs. The data output is supplied to this pin as a serial data stream. The bits are clocked out on the

falling edge of the SCLK input and 14 SCLKs are required to access the data. The data appears on both pins

simultaneously from the simultaneous conversions of both ADCs. The data stream consists of one leading zero

D

_OUTB

CS

followed by one identification bit, followed by the 12 bits of conversion data. The data is provided MSB first. If

CS

is held low for 16 SCLK cycles rather than 14, then two trailing zeros will appear after the 12 bits of data. If is

held low for a further 16 SCLK cycles after this on either D_OUTA or D_OUTB, the data from the other ADC follows on

the D_OUTpin. This allows data from a simultaneous conversion on both ADCs to be gathered in serial format on

either D_OUTA or D_OUTB alone using only one serial port. See the Serial Interface section.

Rev. PrA | Page 6 of 16

Preliminary Technical Data

AD7265

Pin No. Mnemonic Description

21

RANGE

Analog Input Range Selection. Logic input. The polarity on this pin will determine what input range the analog

CS

input channels will have. On the falling edge of , the polarity of this pin is checked to determine the analog

input range of the next conversion. If this pin is tied to a logic low, the analog input range is 0 V to VREF. If this pin

CS

is tied to a logic high when

goes low, the analog input range is 2 × V_REF.

25–23

A0–A2

Multiplexer Select. Logic inputs. Thess inputs are used to select the pair of channels to be converted

simultaneously, i.e., Channel 1 of both ADC A and ADC B, Channel 2 of both ADC A and ADC, and so on. The pair of

channels selected may be two single ended channels or two differential pairs. The logic states of these pins are

CS

checked upon the falling edge of , and the multiplexer is set up for the next conversion. See Table 6 for

multiplexer address decoding.

22

2

DIFF

SGL/

Logic Input. This pin selects whether the analog inputs are configured as differential pairs or single ended. A logic

low selects differential operation while a logic high selects single ended operation.

REF SELECT Internal/External reference Selection. Logic Input. If this pin is tied to GND, the on-chip 2.5 V reference is used as

the reference source for both ADC A and ADC B. In addition, Pins D_CAPA and D_CAPB must be tied to decoupling

capacitors. If the REF SELECT pin is tied to a logic high, an external reference can be supplied to the AD7265

through the D_CAPA and/or D_CAPB pins.

Rev. PrA | Page 7 of 16

AD7265

Preliminary Technical Data

TERMINOLOGY

Differential Nonlinearity

Track-and-Hold Acquisition Time

This is the difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

The track-and-hold amplifier returns into track mode after the

end of conversion. Track-and-hold acquisition time is the time

required for the output of the track-and-hold amplifier to reach

its final value, within 1/2 LSB, after the end of conversion.

Integral Nonlinearity

This is the maximum deviation from a straight line passing

through the endpoints of the ADC transfer function. The

endpoints of the transfer function are zero scale, a point 1 LSB

below the first code transition, and full scale, a point 1 LSB

above the last code transition.

Signal to (Noise + Distortion) Ratio

This is the measured ratio of signal to (noise + distortion) at the

output of the A/D converter. The signal is the rms amplitude of

the fundamental. Noise is the sum of all non-fundamental

signals up to half the sampling frequency (f_S/2), excluding dc.

The ratio is dependent on the number of quantization levels in

the digitization process; the more levels, the smaller the

quantization noise. The theoretical signal to (noise + distortion)

ratio for an ideal N-bit converter with a sine wave input is given

by:

Offset Error

This applies to Straight Binary output coding. It is the deviation

of the first code transition (00 . . . 000) to (00 . . . 001) from the

ideal, i.e., AGND + 1 LSB.

Offset Error Match

Signal to (Noise + Distortion) = (6.02N + 1.76) dB

This is the worst case difference in Offset Error between any of

the twelve channels.

Thus for a 12-bit converter, this is 74 dB.

Total Harmonic Distortion

Gain Error

Total harmonic distortion (THD) is the ratio of the rms sum of

harmonics to the fundamental. For the AD7265 it is defined as:

This applies to Straight Binary output coding. It is the deviation

of the last code transition (111 . . . 110) to (111 . . . 111) from the

ideal (i.e., VREF – 1 LSB) after the offset error has been adjusted

out.

2

V₂²+V₃²+V₄²+V₅²+V₆

THD(dB) = 20log

V₁

Gain Error Match

where V₁is the rms amplitude of the fundamental and V₂, V₃,

V₄, V₅and V₆are the rms amplitudes of the second through the

sixth harmonics.

This is the difference in Gain Error between the two channels.

Zero Code Error

Peak Harmonic or Spurious Noise

This applies when using twos complement output coding in

particular with the 2 x V_REFinput range as –V_REFto +V_REFbiased

about the V_REFpoint. It is the deviation of the midscale

transition (all 1s to all 0s) from the ideal V_INvoltage, i.e., V_REF- 1

LSB.

Peak harmonic or spurious noise is defined as the ratio of the

rms value of the next largest component in the ADC output

spectrum (up to fS/2 and excluding dc) to the rms value of the

fundamental. Normally, the value of this specification is

determined by the largest harmonic in the spectrum, but for

ADCs where the harmonics are buried in the noise floor, it will

be a noise peak.

Zero Code Error Match

This refers to the difference in Zero Code Error between the

two channels.

Channel-to-Channel Isolation

Channel-to-channel isolation is a measure of the level of

crosstalk between channels. It is measured by applying a full-

scale (2 x V_REF), 455kHz sine wave signal to all unselected input

channels and determining how much that signal is attenuated in

the selected channel with a 10 kHz signal (0 V to V_REF). The

figure given is the worst-case across all twelve channels for the

AD7265.

Positive Gain Error

This applies when using twos complement output coding in

particular with the 2 x V_REFinput range as –V_REFto +V_REFbiased

about the V_REFpoint. It is the deviation of the last code

transition (011…110) to (011…111) from the ideal (i.e., + V_REF

1 LSB) after the Zero Code Error has been adjusted out.

-

Rev. PrA | Page 8 of 16

Preliminary Technical Data

AD7265

Intermodulation Distortion

As a result, the second and third order terms are specified

separately. The calculation of the intermodulation distortion is

as per the THD specification where it is the ratio of the rms

sum of the individual distortion products to the rms amplitude

of the sum of the fundamentals expressed in dBs.

With inputs consisting of sine waves at two frequencies, fa and

fb, any active device with nonlinearities will create distortion

products at sum and difference frequencies of mfa nfb where

m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are those

for which neither m nor n are equal to zero. For example, the

second order terms include (fa + fb) and (fa – fb), while the

third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa

– 2fb).

PSR (Power Supply Rejection)

Variations in power supply will affect the full-scale transition

but not the converter’s linearity. Power supply rejection is the

maximum change in full-scale transition point due to a change

in power supply voltage from the nominal value. See Typical

Performance Curves.

The AD7265 is tested using the CCIF standard where two input

frequencies near the top end of the input bandwidth are used.

In this case, the second order terms are usually distanced in

frequency from the original sine waves while the third order

terms are usually at a frequency close to the input frequencies.

Rev. PrA | Page ꢀ of 16

AD7265

Preliminary Technical Data

THEORY OF OPERATION

CIRCUIT INFORMATION

CAPACITIVE

DAC

The AD7265 is a fast, micropower, dual 12-bit, single supply,

A/D converter that operates from a 2.7 V to 5.25 V supply.

When operated from either a 5 V or 3V supply, the AD7265 is

capable of throughput rates of 1 MSPS.

COMPARATOR

C

B

A

S

V

IN+

SW1

SW2

CONTROL

LOGIC

SW3

S

A

B

IN–

The AD7265 contains two on-chip differential track-and-hold

amplifiers, two successive approximation A/D converters, and a

serial interface with two separate data output pins, and is

housed in a 32-lead LFCSP package, which offers the user

considerable space-saving advantages over alternative solutions.

The serial clock input accesses data from the part but also

provides the clock source for each successive approximation

ADC. The analog input range for the part can be selected to be a

0 V to V_REFinput or a 2 × V_REFinput with the analog inputs

configured as either single ended or differential. The AD7265

has an on-chip 2.5 V reference that can be overdriven if an

external reference is preferred.

V

REF

CAPACITIVE

DAC

Figure 3. ADC Acquisition Phase

When the ADC starts a conversion (Figure 4), SW3 opens and

SW1 and SW2 move to position B, causing the comparator to

become unbalanced. Both inputs are disconnected once the

conversion begins. The control logic and the charge redistribu-

tion DACs are used to add and subtract fixed amounts of charge

from the sampling capacitor arrays to bring the comparator

back into a balanced condition. When the comparator is

rebalanced, the conversion is complete. The control logic

generates the ADC output code. The output impedances of the

sources driving the V_IN+and V_IN–pins must be matched;

otherwise, the two inputs will have different settling times,

resulting in errors.

The AD7265 also features power-down options to allow power

saving between conversions. The power-down feature is

implemented across the standard serial interface, as described in

the Modes of Operation section.

CONVERTER OPERATION

The AD7265 has two successive approximation analog-to-

digital converters, each based around two capacitive DACs.

Figure 3 and Figure 4 show simplified schematics of one of

these ADCs in acquisition and conversion phase, respectively.

The ADC is comprised of control logic, a SAR, and two

capacitive DACs. In Figure 3 (the acquisition phase), SW3, is

closed, SW1 and SW2 are in position A, the comparator is held

in a balanced condition, and the sampling capacitor arrays

acquire the differential signal on the input.

CAPACITIVE

DAC

COMPARATOR

C

B

A

S

V

IN+

SW1

SW2

CONTROL

LOGIC

SW3

S

A

B

IN–

V

REF

CAPACITIVE

DAC

Figure 4. ADC Conversion Phase

Rev. PrA | Page 10 of 16

Preliminary Technical Data

AD7265

ANALOG INPUT

The channels to be converted on simultaneously are selected via

the multiplexer address inputs A0 to A2. The logic states of

The analog inputs of the AD7265 may be configured as single

ended or true differential via the SGL/

DIFF

logic pin, as shown

CS

these pins are also checked upon the falling edge of

and the

CS

in Figure 5. On the falling edge of , point A, the logic level of

DIFF

channels are chosen for the next conversion. The selected input

channels are decoded as shown in Table 6.

the SGL/

pin is checked to determine the configuration of

the analog input channels for the next conversion. If this pin is

tied to a logic low, the analog input channels to each on-chip

ADC are set up as three true differential pairs. If this pin is at a

The analog input range of the AD7265 can be selected as 0 V to

V_REFor 0 V to 2 × V_REFvia the RANGE pin. This selection is

CS

logic high when

on-chip ADC are set up as six single-ended analog inputs. In

DIFF

goes low, the analog input channels to each

DIFF

made in a similar fashion to that of the SGL/

checking the logic state of the RANGE pin upon the falling edge

CS

pin by

Figure 5 at point A, the SGL/

pin is at a logic high so the

of . The analog input range is set up for the next conversion.

analog inputs are configured as single-ended for the next

conversion, i.e. sampling point B. At point B, the logic level of

CS

If this pin is tied to a logic low upon the falling edge of , the

analog input range for the next conversion is 0 V to V_REF. If this

DIFF

the SGL/

pin has changed to low; there fore, the analog

CS

pin is tied to a logic high upon the falling edge of , the analog

inputs are configured as differential for the next conversion

after this one, even though this current conversion is on single

ended configured inputs.

input range for the next conversion is 0 V to 2 × V_REF

.

OUTPUT CODING

The AD7265 output coding is set to either twos complement or

straight binary depending on which analog input configuration

is selected for a conversion. Table 5 shows which output coding

scheme is used for each possible analog input configuration.

A

B

CS

1

14

1

14

SCLK

Table 5 AD7265 Output Coding

DIFF

Range

Output Coding

SGL/DIFF

SGL/

DIFF

SGL

0 V to V_REF

0 V to 2 × V_REF

0 V to V_REF

Twos Complement

Straight Binary

Figure 5. Selecting Differential or Single Ended Configuration

SGL

PSUEDO DIFF

0 V to 2 × V_REF

0 V to V_REF

0 V to 2 × V_REF

Twos Complement

Straight Binary

Table 6. Analog Input Type and Channel Selection

ADC A

V_IN–

ADC B

V_IN–

DIFF

V_IN+

Comment

A2

0

1

0

1

A1

0

1

0

1

0

A0

0

1

0

1

0

1

0

1

0

1

0

1

SGL/

1

0

V_A1

V_A2

V_A3

V_A4

V_A5

V_A6

V_A1

V_A3

V_A5

AGND

V_B1

V_B2

V_B3

V_B4

V_B5

V_B6

V_B1

V_B3

V_B5

AGND

V_B2

V_B4

V_B6

Single Ended

Fully Differential

Pseudodifferential

Fully Differential

Pseudodifferential

Fully Differential

Pseudodifferential

AGND

V_A2

V_A4

V_A6

V_B6

Rev. PrA | Page 11 of 16

AD7265

Preliminary Technical Data

DIGITAL INPUTS

TRANSFER FUNCTIONS

The digital inputs applied to the AD7265 are not limited by the

maximum ratings that limit the analog inputs. Instead, the

digital inputs applied can go to 7 V and are not restricted by the

V_DD+ 0.3 V limit as on the analog inputs. See the Absolute

Maximum Ratings. Another advantage of SCLK, RANGE,

The designed code transitions occur at successive integer LSB

values (i.e., 1 LSB, 2 LSB, and so on). The LSB size is V_REF/4096.

The ideal transfer characteristic for the AD7265 when straight

binary coding is output is shown in Figure 6, and the ideal

transfer characteristic for the AD7265 when twos complement

coding is output is shown in Figure 7.

CS

A0–A2, and

not being restricted by the V_DD+ 0.3 V limit is

that power supply sequencing issues are avoided. If one of these

digital inputs is applied before V_DD, there is no risk of latch-up,

as there would be on the analog inputs if a signal greater than

0.3 V were applied prior to V_DD.

111...111

111...110

V_DRIVE

The AD7265 also has the V_DRIVEfeature, which controls the

voltage at which the serial interface operates. V_DRIVEallows the

ADC to easily interface to both 3 V and 5 V processors. For

example, if the AD7265 was operated with a V_DDof 5 V, the

V_DRIVEpin could be powered from a 3 V supply, allowing a large

dynamic range with low voltage digital processors. For example,

the AD7265 could be used with the 2 × V_REFinput range, with a

V_DDof 5 V while still being able to interface to 3 V digital parts.

111...000

1LSB = V

REF

/4096

011...111

000...010

000...001

000...000

1LSB

V

– 1LSB

REF

ANALOG INPUT

0V

Figure 6. Straight Binary Transfer Characteristic

1LSB = 2

×

V

/4096

REF

011...111

011...110

000...001

000...000

111...111

100...010

100...001

100...000

–V

+ 1LSB

V

– 1LSB

+V

– 1 LSB

REF

ANALOG INPUT

Figure 7. Twos Complement Transfer Characteristic with V_REFV_REFInput

Range

Rev. PrA | Page 12 of 16

Preliminary Technical Data

AD7265

MODES OF OPERATION

The mode of operation of the AD7265 is selected by controlling

accessed on the same DOUT line, as shown in Figure TBD (see

the Serial Interface section). The identification bit provided

prior to each conversion result identifies which on-board ADC

the following result is from. Once 32 SCLK cycles have elapsed,

the DOUT line returns to three-state on the 32^ndSCLK falling

CS

the (logic) state of the

three possible modes of operation: normal mode, partial power-

CS

signal during a conversion. There are

down mode, and full power-down mode. The point at which

is pulled high after the conversion has been initiated determines

which power-down mode, if any, the device enters. Similarly, if

CS

edge. If

to three-state at that point. Thus,

cycles until it is brought high again sometime prior to the next

CS

is brought high prior to this, the DOUT line returns

CS

may idle low after 32 SCLK

CS

already in a power-down mode,

can control whether the

device returns to normal operation or remains in power-down.

These modes of operation are designed to provide flexible

power management options. These options can be chosen to

optimize the power dissipation/throughput rate ratio for

differing application requirements.

conversion (effectively idling

low), if so desired, since the

bus still returns to three-state upon completion of the dual

result read.

Once a data transfer is complete and D_OUTA and D_OUTB have

returned to three-state, another conversion can be initiated after

NORMAL MODE

CS

the quiet time, t_QUIET, has elapsed by bringing

low again.

This mode is intended for fastest throughput rate performance

since the user does not have to worry about any power-up times

with the AD7265 remaining fully powered all the time. Figure 8

shows the general diagram of the operation of the AD7265 in

this mode.

PARTIAL POWER-DOWN MODE

This mode is intended for use in applications where slower

throughput rates are required. Either the ADC is powered down

between each conversion, or a series of conversions may be

performed at a high throughput rate and the ADC is then

powered down for a relatively long duration between these

bursts of several conversions. When the AD7265 is in partial

power-down, all analog circuitry is powered down except for

the on-chip reference and reference buffer.

CS

1

10

14

SCLK

D

A

B

OUT

To enter partial power-down, the conversion process must be

LEADING ZERO, I.D. BIT + CONVERSION RESULT

OUT

CS

interrupted by bringing

falling edge of SCLK and before the 10^thfalling edge of SCLK, as

CS

high anywhere after the second

Figure 8. Normal Mode Operation

shown in Figure 9. Once

window of SCLKs, the part enters partial power-down, the

CS

has been brought high in this

CS

The conversion is initiated on the falling edge of , as

described in the Serial Interface section. To ensure that the part

remains fully powered up at all times,

at least 10 SCLK falling edges have elapsed after the falling edge

conversion that was initiated by the falling edge of

terminated, and D_OUTA and D_OUTB go back into three-state. If

CS

is

CS

must remain low until

is brought high before the second SCLK falling edge, the

part remains in normal mode and does not power down. This

th

CS CS

of . If

is brought high any time after the 10 SCLK falling

CS

avoids accidental power-down due to glitches on the

line.

edge but before the 14^thSCLK falling edge, the part remains

powered up but the conversion is terminated and D_OUTA and

D_OUTB go back into three-state. Fourteen serial clock cycles are

required to complete the conversion and access the conversion

result. The DOUT line does not return to three-state after 14

CS

1

2

10

14

CS

SCLK cycles have elapsed, but instead does so when

is

is left low for another 2 SCLK cycles

(e.g. if only a 16 SCLK burst is available), two trailing zeros are

CS

SCLK

CS

brought high again. If

D

A

B

TRI-STATE

OUT

D

OUT

clocked out after the data. If

is left low for a further 16 SCLK

cycles again, the result from the other ADC on board is also

Figure 9. Entering Partial Power-Down Mode

Rev. PrA | Page 13 of 16

AD7265

Preliminary Technical Data

AD7265 is in full power-down, all analog circuitry is powered

down. Full power-down is entered in a similar way as partial

power-down, except the timing sequence shown in Figure 9

must be executed twice. The conversion process must be

To exit this mode of operation and power up the AD7265 again,

CS

a dummy conversion is performed. On the falling edge of

,

the device begins to power up, and continues to power up as

th

CS

long as

is held low until after the falling edge of the 10

CS

interrupted in a similar fashion by bringing

high anywhere

SCLK. The device is fully powered up after approximately 1 µs

has elapsed, and valid data results from the next conversion, as

after the second falling edge of SCLK and before the 10^thfalling

edge of SCLK. The device enters partial power-down at this

point. To reach full power-down, the next conversion cycle must

be interrupted in the same way, as shown in Figure TBD. Once

CS

shown in Figure 10. If

is brought high before the second

falling edge of SCLK, the AD7265 again goes into partial power-

down. This avoids accidental power-up due to glitches on the

CS

has been brought high in this window of SCLKs, the part

CS

line. Although the device may begin to power up on the

CS

powers down completely.

falling edge of , it powers down again on the rising edge of

CS

. If the AD7265 is already in partial power-down mode and

is brought high between the second and 10 falling edges of

CS

Note that it is not necessary to complete the 14 SCLKs once

has been brought high to enter a power-down mode.

th

SCLK, the device enters full power-down mode.

To exit full power-down and power the AD7265 up again, a

FULL POWER-DOWN MODE

dummy conversion is performed, as when powering up from

CS

partial power-down. On the falling edge of , the device

This mode is intended for use in applications where throughput

rates slower than those in the partial power-down mode are

required, as power-up from a full power-down takes substan-

tially longer than that from partial power-down. This mode is

more suited to applications where a series of conversions

performed at a relatively high throughput rate are followed by a

long period of inactivity and thus power-down. When the

CS

begins to power up and continues to power up as long as

is

held low until after the falling edge of the 10^thSCLK. The

power-up time required must elapse before a conversion can be

initiated, as shown in Figure TBD. See the Power-Up Times

section for the power-up times associated with the AD7265.

THE PART BEGINS

TO POWER-UP

THE PART IS FULLY POWERED UP,

SEE POWER-UP TIMES SECTION

T

POWER-UP

CS

1

10

14

1

14

SCLK

A

D

A

B

OUT

INVALID DATA

VALID DATA

OUT

Figure 10. Exiting Partial Power-Down Mode

Rev. PrA | Page 14 of 16

Preliminary Technical Data

OUTLINE DIMENSIONS

AD7265

5.00

0.60 MAX

BSC SQ

0.60 MAX

PIN 1

INDICATOR

25

24

32

1

PIN 1

INDICATOR

0.50

BSC

3.25

4.75

TOP

BOTTOM

VIEW

BSC SQ

3.10 SQ

2.95

VIEW

0.50

0.40

0.30

17

16

8

9

0.25 MIN

3.50 REF

0.80 MAX

12° MAX

0.65 TYP

0.05 MAX

0.02 NOM

1.00

0.85

0.80

0.30

0.23

0.18

COPLANARITY

0.08

0.20 REF

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

Figure 11. 32-Lead Frame Chip Scale Package [LFCSP

(CP-32)

Dimensions shown in millimeters

1.20

MAX

9.00 SQ

0.75

0.60

0.45

24

17

16

25

TOP VIEW

7.00

SQ

(PINS DOWN)

32

9

1

8

0.15

0.05

0.80

0.45

0.37

0.30

BSC

1.05

1.00

0.95

7°

0°

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-026ABA

Figure 12. 32-Lead Thin Flat Quad Package [TQFP]

(SU-32)

Dimensions shown in millimeters

Rev. PrA | Page 15 of 16

AD7265

Preliminary Technical Data

ORDERING GUIDE

AD7265 Products

AD7265ACP

Temperature Package

–40°C to +125°C

Package Description

Lead Frame Chip Scale Package

Thin Quad Flat Package

Evaluation Board

Package Outline

CP-32

SU-32

AD7265BCP

AD7265ASU

AD7265BSU

EVAL-AD7265CB¹

EVAL-CONTROL BRD2²

Controller Board

¹This can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONTROL Board for evaluation/demonstration purposes.

²This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators. To order a complete

evaluation kit, the particular ADC evaluation board, e.g., EVAL-AD7265CB, the EVAL-CONTROL BRD2, and a 12V transformer must be ordered. See relevant Evaluation

Board Technical note for more information.

©

registered trademarks are the property of their respective owners.

PR04674–0–1/04(PrA)

Rev. PrA | Page 16 of 16


型号：	AD7265
厂家：	ADI
描述：	Differential Input, Dual 1 MSPS, 12-Bit, 3-Channel SAR ADC 差分输入，双通道1 MSPS ， 12位， 3通道SAR ADC
文件：	总16页 (文件大小：706K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD7265 [ADI]

相关型号：

AD7265ACP

AD7265ASU

AD7265BCP

AD7265BCP

AD7265BCPZ

AD7265BCPZ

AD7265BCPZ-REEL

AD7265BCPZ-REEL7

AD7265BSU

AD7265BSUZ

AD7265BSUZ-REEL

AD7265BSUZ-REEL7