AD73411_技术文档

Low-Power

Analog Front End with DSP Microcomputer

a

AD73411

FEATURES

FUNCTIONAL BLOCK DIAGRAM

AFE PERFORMANCE

16-Bit A/D Converter

16-Bit D/A Converter

POWER-DOWN

CONTROL

FULL MEMORY

MODE

Programmable Input/Output Sample Rates

76 dB ADC SNR

77 dB DAC SNR

64 kS/s Maximum Sample Rate

–90 dB Crosstalk

Low Group Delay (25 ␮s Typ per ADC Channel,

50 ␮s Typ per DAC Channel)

Programmable Input/Output Gain

On-Chip Reference

DATA

MEMORY

PROGRAMMABLE

ADDRESS

EXTERNAL

ADDRESS

BUS

16K PM

(OPTIONAL (OPTIONAL

8K) 8K)

16K DM

PROGRAM

I/O

GENERATORS

SEQUENCER

AND

FLAGS

DAG 1 DAG 2

EXTERNAL

DATA

BUS

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

BYTE DMA

CONTROLLER

PROGRAM MEMORY DATA

DATA MEMORY DATA

OR

EXTERNAL

DATA

BUS

ARITHMETIC UNITS

ALU MAC SHIFTER

SERIAL PORTS

TIMER

INTERNAL

DMA

PORT

SPORT 0 SPORT 1

DSP PERFORMANCE

19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS

Sustained Performance

AD73411-80

80K Bytes of On-Chip RAM, Conﬁgured as 16K Words

Program Memory RAM and 16K Words

Data Memory RAM

ADSP-2100 BASE

ARCHITECTURE

HOST MODE

SERIAL PORT

SPORT 2

REF

ADC

DAC

AD73411-40

ANALOG FRONT END

SECTION

40K Bytes of On-Chip RAM, Conﬁgured as 8K Words

Program Memory RAM and 8K Words

Data Memory RAM

The sampling rate of the AFE is programmable with four sepa-

rate settings offering 64, 32, 16, and 8 kHz sampling rates (from

a master clock of 16.384 MHz) while the serial port (SPORT2)

allows easy expansion of the number of I/O channels by cascad-

ing extra AFEs external to the AD73411.

GENERAL DESCRIPTION

The AD73411 is a single device incorporating a single analog front

end (AFE) and a microcomputer optimized for digital signal

processing (DSP) and other high-speed numeric processing

applications.

The AD73411’s DSP engine combines the ADSP-2100 family

base architecture (three computational units, data address gen-

erators, and a program sequencer) with two serial ports, a 16-bit

internal DMA port, a byte DMA port, a programmable timer,

Flag I/O, extensive interrupt capabilities, and on-chip program

and data memory.

The AD73411’s analog front end (AFE) section is suitable for

general-purpose applications including speech and telephony.

The AFE section features a 16-bit A/D converter and a 16-bit

D/A converter. Each converter provides 76 dB signal-to-noise

ratio over a voiceband signal bandwidth.

The AD73411 is particularly suitable for a variety of applications

in the speech and telephony area, including low bit rate, high-

quality compression, speech enhancement, recognition, and

synthesis. The low group delay characteristic of the AFE makes

it suitable for single or multichannel active control applications.

The A/D and D/A conversion channels feature programmable

input/output gains with ranges of 38 dB and 21 dB respectively.

An on-chip reference voltage is included to allow single supply

operation.

The AD73411-80 integrates 80K bytes of on-chip memory

conﬁgured as 16K words (24-bit) of program RAM, and 16K

words (16-bit) of data RAM. The AD73411-40 integrates

40K bytes of on-chip memory conﬁgured as 8K words (24-

bit) of program RAM, and 8K words (16-bit) of data RAM.

Power-down circuitry is also provided to meet the low power

needs of battery-operated portable equipment. The AD73411

is available in a 119-ball PBGA package.

REV. 0

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

(AVDD = DVDD = 3.0 V to 3.6 V; DGND = AGND = 0 V, f_MCLK= 16.384 MHz,

f_SAMP= 64 kHz; T_A= T_MINto T_MAX, unless otherwise noted.)

AD73411–SPECIFICATIONS¹

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

AFE SECTION

REFERENCE

REFCAP

Absolute Voltage, V_REFCAP

REFCAP TC

REFOUT

Typical Output Impedance

1.08

1.2

50

1.32

V

ppm/°C

0.1 µF Capacitor Required from

REFCAP to AGND2

145

1.2

Ω

V

Absolute Voltage, V_REFOUT

Unloaded

ADC SPECIFICATIONS

Maximum Input Range at VIN^{2, 3}

1.578

–2.85

1.0954

–6.02

V p-p

dBm

V p-p

dBm

Measured Differentially

Max Input = (1.578/1.2) × V_REFCAP

Measured Differentially

Nominal Reference Level at VIN

(0 dBm0)

Absolute Gain

PGA = 0 dB

PGA = 38 dB

Gain Tracking Error

Signal to (Noise + Distortion)

PGA = 0 dB

–2.2

–0.6

–1.0

0.1

+1.0

dB

1.0 kHz, 0 dBm0

1.0 kHz, +3 dBm0 to –50 dBm0

Refer to Figure ?

300 Hz to 3400 Hz;

71

70

76

74

72

56

60

59

dB

0 Hz to f_SAMP/2

300 Hz to 3400 Hz; f_SAMP= 64 kHz

0 Hz to f_SAMP/2; f_SAMP= 64 kHz

300 Hz to 3400 Hz;

PGA = 38 dB

0 Hz to f_SAMP/2

Total Harmonic Distortion

PGA = 0 dB

PGA = 38 dB

Intermodulation Distortion

Idle Channel Noise

Crosstalk

–85

–82

–76

–100

–75

dB

dBm0

dB

300 Hz to 3400 Hz

PGA = 0 dB

ADC Input Signal Level: 1.0 kHz, 0 dBm0

DAC Input at Idle

DC Offset

Power Supply Rejection

–20

+2

–84

+25

mV

dB

PGA = 0 dB

Input Signal Level at AVDD and DVDD

Pins 1.0 kHz, 100 mV p-p Sine Wave

f_SAMP= 64 kHz

Group Delay^{4, 5}

25

45

µs

kΩ

Input Resistance at PGA^{2, 4, 6}

DMCLK = 16.384 MHz

DAC SPECIFICATIONS

Maximum Voltage Output Swing²

Single-Ended

1.578

–2.85

3.156

3.17

V p-p

dBm

V p-p

dBm

PGA = 6 dB

Max Output = (1.578/1.2) × V_REFCAP

PGA = 6 dB

Differential

Max Output = 2 × ((1.578/1.2) × V_REFCAP

Nominal Voltage Output Swing (0 dBm0)

Single-Ended

1.0954

–6.02

2.1909

0

1.2

–0.7

0.1

V p-p

dBm

V p-p

dBm

V

dB

PGA = 6 dB

Differential

Output Bias Voltage⁴

Absolute Gain

Gain Tracking Error

Signal to (Noise + Distortion)

PGA = 0 dB

1.08

–1.8

1.32

+0.4

REFOUT Unloaded

1.0 kHz, 0 dBm0; Unloaded

1.0 kHz, +3 dBm0 to –50 dBm0

70

77

76

77

dB

300 Hz to 3400 Hz

300 Hz to 3400 Hz; f_SAMP= 64 kHz

300 Hz to 3400 Hz

300 Hz to 3400 Hz; f_SAMP= 64 kHz

PGA = 6 dB

Total Harmonic Distortion at 0 dBm0

PGA = 0 dB

PGA = 6 dB

Intermodulation Distortion

Idle Channel Noise

Crosstalk

–80

–76

–82

–100

–70

dB

dBm0

dB

PGA = 0 dB

ADC Input Signal Level: AGND; DAC

Output Signal Level: 1.0 kHz, 0 dBm0

–2–

REV. 0

AD73411

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DAC SPECIFICATIONS (Continued)

Power Supply Rejection

–81

dB

Input Signal Level at AVDD and DVDD

Pins: 1.0 kHz, 100 mV p-p Sine Wave

f_SAMP= 64 kHz; Interpolator Bypassed

f_SAMP= 64 kHz

Group Delay^{4, 5}

25

50

+5

µs

mV

Output DC Offset^{2, 7}

–30

+50

PGA = 6 dB

LOGIC INPUTS

V_INH, Input High Voltage

V_INL, Input Low Voltage

I_IH, Input Current

DVDD – 0.8

0

–10

DVDD

0.8

+10

V

µA

LOGIC OUTPUT

V_OH, Output High Voltage

V_OL, Output Low Voltage

Three-State Leakage Current

DVDD – 0.4

0

–10

DVDD

0.4

+10

V

µA

|IOUT| ≤ 100 µA

POWER SUPPLIES

AVDD

3.0

3.6

V

DVDD

9

I_DD

See Table I

NOTES

¹Operating temperature range is as follows: –20°C to +85°C. Therefore, T_MIN= –20°C and T_MAX= +85°C.

²Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted).

³At input to sigma-delta modulator of ADC.

⁴Guaranteed by design.

⁵Overall group delay will be affected by the sample rate and the external digital ﬁltering.

⁶The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (3.3 × 10¹¹)/DMCLK.

⁷Between VOUTP and VOUTN.

⁸At VOUT output.

⁹Test Conditions: no load on digital inputs, analog inputs ac-coupled to ground, no load on analog outputs.

Speciﬁcations subject to change without notice.

–3–

REV. 0

(AVDD = DVDD = VDD = 3.0 V to 3.6 V; DGND = AGND = 0 V, f_MCLK= 16.384 MHz,

f_SAMP= 64 kHz; T_A= T_MINto T_MAX, unless otherwise noted.)

AD73411–SPECIFICATIONS

Parameter

Test Conditions

Min

Typ

Max

Unit

DSP SECTION

V_IH

V_IL

Hi-Level Input Voltage^{1, 2}

Hi-Level CLKIN Voltage

Lo-Level Input Voltage^{1, 3}

Hi-Level Output Voltage^{1, 4, 5}

@ VDD = max

@ VDD = min

2.0

2.2

V

0.8

V_OH

I

_OH= –0.5 mA

2.4

V

@ VDD = min

I_OH= –100 µA⁶

@ VDD = min

VDD – 0.3

V

V_OL

I_IH

Lo-Level Output Voltage^{1, 4, 5}

Hi-Level Input Current³

I

_OL= 2 mA

@ VDD = max

_IN= VDD max

0.4

10

V

µA

I_IL

Lo-Level Input Current³

Three-State Leakage Current⁷

Supply Current (Idle)⁹

@ VDD = max

V_IN= 0 V

I_OZH

I_OZL

I_DD

@ VDD = max

V

_IN= VDD max⁸

@ VDD = max

V

_IN= 0 V⁸

@ VDD = 3.3

t_CK= 19 ns¹⁰

12

11

10

mA

t

_CK= 25 ns¹⁰

_CK= 30 ns¹⁰

I_DD

Supply Current (Dynamic)¹¹

@ VDD = 3.3

_AMB= 25°C

_CK= 19 ns¹⁰

t_CK= 25 ns¹⁰

_CK= 30 ns¹⁰

T

t

45

43

36

mA

t

C_I

Input Pin Capacitance^{3, 6, 12}

@ V_IN= 2.5 V

f_IN= 1.0 MHz

T

_AMB= 25°C

8

pF

C_O

Output Pin Capacitance^{6, 7, 12, 13}

@ V_IN= 2.5 V

f_IN= 1.0 MHz

T_AMB= 25°C

NOTES

¹Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.

²Input only pins: RESET, BR, DR0, DR1, PWD.

³Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.

⁴Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.

⁵Although speciﬁed for TTL outputs, all AD73411 outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.

⁶Guaranteed but not tested.

⁷Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.

⁸0 V on BR.

⁹Idle refers to AD73411 state of operation during execution of IDLE instruction. Deasserted pins are driven to either VDD or GND.

10

11

V

I

= 0 V and 3 V. For typical ﬁgures for supply currents, refer to Power Dissipation section.

measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2

IN

DD

and Type 6, and 20% are idle instructions.

¹²Applies to PBGA package type.

¹³Output pin capacitance is the capacitive load for any three-stated output pin.

Speciﬁcations subject to change without notice.

–4–

REV. 0

AD73411

POWER CONSUMPTION

Parameter

Typ

Max

SE

MCLK On

Test Conditions

AFE SECTION

ADC Only On

7

11

0.65

2.7

8

1

0

Yes

No

REFOUT Disabled

ADC and DAC On

REFCAP Only On

REFCAP and

12.5

1.00

3.8

REFOUT Only On

All AFE Sections Off

0.6

5 µA

0.75

30 µA

0

Yes

No

MCLK Active Levels Equal to 0 V and DVDD

Digital Inputs Static and Equal to 0 V or DVDD

DSP SECTION

Idle Mode

6.4

43

Dynamic

NOTES

The above values are in mA and are typical values unless otherwise noted.

Speciﬁcations subject to change without notice.

TIMING CHARACTERISTICS–AFE SECTION

Parameter

Limit

Unit

Description

Clock Signals

See Figure 1

t₁

t₂

t₃

61

24.4

ns min

16.384 MHz AMCLK Period

MCLK Width High

MCLK Width Low

Serial Port

See Figures ? and ?

t₄

t₅

t₆

t₇

t₈

t₉

t₁₀

t₁₁

t₁₂

t₁₃

t₁

ns min

ns max

ns min

ns max

SCLK Period (SCLK = AMCLK)

SCLK Width High

SCLK Width Low

SDI/SDIFS Setup Before SCLK Low

SDI/SDIFS Hold After SCLK Low

SDOFS Delay from SCLK High

SDOFS Hold After SCLK High

SDO Hold After SCLK High

SDO Delay from SCLK High

SCLK Delay from MCLK

0.4 × t₁

20

0

10

30

Speciﬁcations subject to change without notice.

–5–

REV. 0

AD73411

Reflow Soldering

ABSOLUTE MAXIMUM RATINGS*

(T_A= +25°C unless otherwise noted)

Maximum Temperature . . . . . . . . . . . . . . . . . . . . . . . 225°C

Time at Maximum Temperature . . . . . . . . . . . . . . . . . 15 sec

Maximum Temperature Ramp Rate . . . . . . . . . . . . 1.3°C/sec

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this speciﬁcation is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

AVDD, DVDD to GND . . . . . . . . . . . . . . . . –0.3 V to +4.6 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V

Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –20°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –40°C to +125°C

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150°C

PBGA, θ_JAThermal Impedance . . . . . . . . . . . . . . . . . 25°C/W

ORDERING GUIDE

Temperature

Range

Package

Description

Package

Option

Model

AD73411BB-80

AD73411BB-40

–20°C to +85°C

119-Ball Plastic Ball Grid Array

B-119

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD73411 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

PBGA BALL CONFIGURATION

2

3

VDD (INT)

WR

5

6

7

1

4

A

B

C

D

E

F

DMS

CLKIN

A11/IAD10

A12/IAD11

A13/IAD12

GND

A7/IAD6

A8/IAD7

A9/IAD8

A10/IAD9

A4/IAD3

A5/IAD4

GND

IRQE/PF4

IRQL0/PF5

IRQL1/PF6

IRQ2/PF7

PMS

IOMS

CMS

XTAL

RD

VDD (EXT)

CLKOUT

BMS

A6/IAD5

DT0

DR0

TFS0

SCLK0

RFS0

DT1/F0

DR1/FI

RESET

ECLK

A3/IAD2

PWDACK

GND

A2/IAD1

BGH

A1/IAD0

A0

MODE A/PF0 MODE B/PF1

VDD (EXT) MODE C/PF2

G

H

J

TFS1/IRQ1

SCLK1

EMS

RFS1/IRQ0

ERESET

EE

PWD

PF3

FL0

FL1

D21

FL2

D20

D23

D22

K

L

ELOUT

BG

ELIN

EINT

D5/IAL

D4/IS

D19

D18

D17

D16

D3/IACK

D2/IAD15

D1/IAD14

D0/IAD13

SDOFS

D8

D9

D12

D15

EBG

D7/IWR

D6/IRD

DGND

SDI

VDD (EXT)

D11

D14

M

N

P

R

T

BR

VDD (INT)

DVDD

SDIFS

VINN

GND

ARESET

SE

D10

D13

EBR

SCLK2

REFCAP

NC

AMCLK

REFOUT

NC

SDO

NC

VINP

NC

AGND

U

AVDD

NC

VOUTP

VOUTN

NC

TOP VIEW

NOTES:

VDD (INT) – DSP CORE SUPPLY

VDD (EXT) – DSP I/O DRIVER SUPPLY

BOTH VDD (INT) AND VDD (EXT) SHOULD BE POWERED FROM THE SAME SUPPLY.

–6–

REV. 0

AD73411

PBGA BALL FUNCTION DESCRIPTIONS

BGA

Mnemonic

Location

Function

VINP

T1

T3

R7

R6

This pin allows direct access to the positive input of the sigma-delta modulator.

This pin allows direct access to the negative input of the sigma-delta modulator.

Buffered Reference Output, which has a nominal value of 1.2 V.

VINN

REFOUT

REFCAP

A Bypass Capacitor to AGND of 0.1 µF is required for the on-chip reference. The capacitor should be

ﬁxed to this pin.

DGND

DVDD

P4

P3

P5

AFE Digital Ground/Substrate Connection.

AFE Digital Power Supply Connection.

ARESET

Active Low Reset Signal. This input resets the entire analog front end, resetting the control registers and

clearing the digital circuitry.

SCLK2

P6

Output Serial Clock whose rate determines the serial transfer rate to/from the codec. It is used to clock data

or control information to and from the serial port (SPORT2). The frequency of SCLK is equal to the

frequency of the master clock (AMCLK) divided by an integer number—this integer number being the product

of the external master clock rate divider and the serial clock rate divider.

AMCLK

P7

AFE Master Clock Input. AMCLK is driven from an external clock signal. If it is required to run the DSP

and AFE sections from a common clock crystal, AMCLK should be connected to the XTAL pin of the

DSP section.

SDO

R1

R2

Serial Data Output of the Codec. Both data and control information may be output on this pin and is clocked on

the positive edge of SCLK. SDO is in three-state when no information is being transmitted and when SE is low.

SDOFS

Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and is active one SCLK

period before the ﬁrst bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK.

SDOFS is in three-state when SE is low.

SDIFS

R3

Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and is valid one SCLK

period before the ﬁrst bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK and

is ignored when SE is low.

SDI

SE

R4

R5

Serial Data Input of the Codec. Both data and control information may be input on this pin and are clocked

on the negative edge of SCLK. SDI is ignored when SE is low.

SPORT2 Enable. Asynchronous input enable pin for SPORT2. When SE is set low by the DSP, the output

pins of SPORT2 are three-stated and the input pins are ignored. SCLK2 is also disabled internally in order

to decrease power dissipation. When SE is brought high, the control and data registers of SPORT2 are at

their original values (before SE was brought low), however the timing counters and other internal regis-

ters are at their reset values.

AGND

AVDD

VOUTP

VOUTN

RESET

BR

U1

U2

U5

U6

H3

N1

L1

F5

AFE Analog Ground/Substrate Connection.

AFE Analog Power Supply Connection.

Analog Output from the Positive Terminal of the Output.

Analog Output from the Negative Terminal of the Output.

(Input) Processor Reset Input.

(Input) Bus Request Input.

BG

(Output) Bus Grant Output.

BGH

DMS

PMS

(Output) Bus Grant Hung Output.

A2

B2

C2

D3

D2

C3

B3

(Output) Data Memory Select Output.

(Output) Program Memory Select Output.

(Output) Memory Select Output.

IOMS

BMS

(Output) Byte Memory Select Output.

(Output) Combined Memory Select Output.

(Output) Memory Read Enable Output.

(Output) Memory Write Enable Output.

(Input) Edge- or Level-Sensitive Interrupt Request¹.

CMS

RD

WR

IRQ2/

PF7

IRQL1/

PF6

D1

C1

(Input/Output) Programmable I/O Pin.

(Input) Level-Sensitive Interrupt Requests¹.

(Input/Output) Programmable I/O Pin.

–7–

REV. 0

AD73411

PBGA BALL FUNCTION DESCRIPTIONS (Continued)

BGA

Location

Mnemonic

Function

IRQL0/

PF5

IRQE/

PF4

PF3

(Input) Level-Sensitive Interrupt Requests¹.

B1

(Input/Output) Programmable I/O Pin.

(Input) Edge-Sensitive Interrupt Requests¹.

A1

H4

(Input/Output) Programmable I/O Pin.

(Input/Output) Programmable I/O Pin During Normal Operation.

(Input) Mode Select Input—Checked Only During RESET.

(Input/Output) Programmable I/O Pin During Normal Operation.

(Input) Mode Select Input—Checked Only During RESET.

(Input/Output) Programmable I/O Pin During Normal Operation.

(Input) Mode Select Input—Checked Only During RESET.

(Input/Output) Programmable I/O Pin During Normal Operation.

(Inputs) Clock or Quartz Crystal Input. The CLKIN input cannot be halted or changed during operation

nor operated below 10 MHz during normal operation.

(Output) Processor Clock Output.

Mode C/

PF2

Mode B/

PF1

Mode A/

PF0

CLKIN

XTAL

CLKOUT

SPORT0

TFS0

RFS0

DT0

G7

F7

F6

A4

B4

D4

E2

E3

E1

F1

F2

(Input/Output) SPORT0 Transmit Frame Sync.

(Input/Output) SPORT0 Receive Frame Sync.

(Output) SPORT0 Transmit Data.

(Input) SPORT0 Receive Data.

(Input/Output) SPORT0 Serial Clock.

DR0

SCLK0

SPORT1

TFS1/

IRQ1

RFS1

IRQ0

(Input/Output) SPORT1 Transmit Frame Sync.

(Input) Edge or Level Sensitive Interrupt.

(Input/Output) SPORT1 Receive Frame Sync.

(Input) Edge or Level Sensitive Interrupt.

(Output) SPORT1 Transmit Data.

(Output) Flag Out².

G1

G2

F3

DT1/

FO

DR1/

FI

SCLK1

FL0

FL1

FL2

VDD(INT)

(Input) SPORT1 Receive Data.

G3

H1

H5

H6

H7

A3

N3

C4

G6

M5

C7

D5

G4

N5

(Input) Flag In².

(Input/Output) SPORT1 Serial Clock.

(Output) Flag 0.

(Output) Flag 1.

(Output) Flag 2.

(Input) DSP Core Supply.

VDD(EXT)

GND

(Input) DSP I/O Interface Supply.

DSP Ground.

EZ-ICE Port

ERESET

EMS

H2

J1

J2

EE

ECLK

ELOUT

ELIN

EINT

EBR

J3

K1

K2

K3

P1

M1

EBG

A

ddress Bus

A0–E7; A1/IAD0–E6; A2/IAD1–E5; A3/IAD2–E4; A4/IAD3–A7; A5/IAD4–B7; A6/IAD5–D7; A7/IAD6–A6;

A8/IAD7–B6; A9/IAD8–C6; A10/IAD9–D6; A11/IAD10–A5; A12/IAD11–B5; A13/IAD12–C5

D0/IAD13–P2; D1/IAD14–N2; D2/IAD15–M2; D3/IACK–L2; D4/IS–M3; D5/IAL–L3; D6/IRD–N4; D7/IWR–M4;

D8–L4; D9–L5; D10–N6; D11–M6; D12–L6; D13–N7; D14–M7; D15–L7; D16–K7; D17–K6; D18–K5;

D19–K4; D20–J7; D21–J6; D22–J5; D23–J4

Data Bus

NOTES

¹Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt

vector address when the pin is asserted, either by external devices, or set as a programmable flag.

²SPORT conﬁguration determined by the DSP System Control Register. Software conﬁgurable.

–8–

REV. 0

AD73411

ARCHITECTURE OVERVIEW

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches (from data memory and

program memory). Each DAG maintains and updates four

address pointers. Whenever the pointer is used to access data

(indirect addressing), it is post-modiﬁed by the value of one of

four possible modify registers. A length value may be associated

with each pointer to implement automatic modulo addressing

for circular buffers.

The two address buses (PMA and DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the

two data buses (PMD and DMD) share a single external data

bus. Byte memory space and I/O memory space also share the

external buses.

The AD73411 instruction set provides flexible data moves and

multifunction (one or two data moves with a computation)

instructions. Every instruction can be executed in a single pro-

cessor cycle. The AD73411 assembly language uses an algebraic

syntax for ease of coding and readability. A comprehensive set

of development tools supports program development.

POWER-DOWN

CONTROL

FULL MEMORY

MODE

DATA

MEMORY

PROGRAMMABLE

ADDRESS

EXTERNAL

ADDRESS

BUS

16K PM

(OPTIONAL (OPTIONAL

8K) 8K)

16K DM

PROGRAM

SEQUENCER

I/O

GENERATORS

AND

FLAGS

DAG 1 DAG 2

EXTERNAL

DATA

BUS

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

An interface to low-cost byte-wide memory is provided by the

Byte DMA port (BDMA port). The BDMA port is bidirectional

and can directly address up to four megabytes of external RAM

or ROM for off-chip storage of program overlays or data tables.

BYTE DMA

CONTROLLER

PROGRAM MEMORY DATA

DATA MEMORY DATA

OR

EXTERNAL

DATA

BUS

ARITHMETIC UNITS

ALU MAC SHIFTER

SERIAL PORTS

TIMER

The AD73411 can respond to eleven interrupts. There can be

up to six external interrupts (one edge-sensitive, two level-sensitive,

and three conﬁgurable), and seven internal interrupts generated

by the timer, the serial ports (SPORTs), the Byte DMA port

and the power-down circuitry. There is also a master RESET

signal. The two serial ports provide a complete synchronous

serial interface with optional companding in hardware and a

wide variety of framed or frameless data transmit and receive

modes of operation.

INTERNAL

DMA

PORT

SPORT 0 SPORT 1

ADSP-2100 BASE

ARCHITECTURE

HOST MODE

SERIAL PORT

SPORT 2

REF

ADC

DAC

ANALOG FRONT END

SECTION

Each port can generate an internal programmable serial clock or

accept an external serial clock.

Figure 1. Functional Block Diagram

Figure 1 is an overall block diagram of the AD73411. The pro-

cessor section contains three independent computational units:

the ALU, the multiplier/accumulator (MAC) and the shifter. The

computational units directly process 16-bit data and have provi-

sions to support multiprecision computations. The ALU performs

a standard set of arithmetic and logic operations; division primi-

tives are also supported. The MAC performs single-cycle multiply,

multiply/add and multiply/subtract operations with 40 bits of

accumulation. The shifter performs logical and arithmetic shifts,

normalization, denormalization, and derive exponent operations.

The AD73411 provides up to 13 general-purpose flag pins. The

data input and output pins on SPORT1 can be alternatively

conﬁgured as an input flag and an output flag. In addition, eight

flags are programmable as inputs or outputs and three flags are

always outputs.

A programmable interval timer generates periodic interrupts. A

16-bit count register (TCOUNT) is decremented every n pro-

cessor cycle, where n is a scaling value stored in an 8-bit register

(TSCALE). When the value of the count register reaches zero,

an interrupt is generated and the count register is reloaded from

a 16-bit period register (TPERIOD).

The internal result (R) bus connects the computational units so

that the output of any unit may be the input of any unit on the

next cycle.

Analog Front End

The AFE section is conﬁgured as a separate block that is normally

connected to either SPORT0 or SPORT1 of the DSP section.

As it is not hardwired to either SPORT, users have total flexibil-

ity in how they wish to allocate system resources to support the

AFE. It is also possible to further expand the number of analog

I/O channels connected to the SPORT by cascading other single

or dual channel AFEs (AD73311 or AD73322) external to the

AD73411.

A powerful program sequencer and two dedicated data address

generators ensure efﬁcient delivery of operands to these com-

putational units. The sequencer supports conditional jumps,

subroutine calls and returns in a single cycle. With internal loop

counters and loop stacks, the AD73411 executes looped code

with zero overhead; no explicit jump instructions are required

to maintain loops.

–9–

REV. 0

AD73411

AVDD1

AVDD2

DVDD

SDI

ANALOG

LOOPBACK/

SINGLE-ENDED

ENABLE

VINP

VINN

ANALOG

SIGMA-DELTA

MODULATOR

0/38dB

PGA

DECIMATOR

SDIFS

SCLK

SDO

SERIAL

I/O

PORT

SDOFS

VOUTP

SWITCHED-

CONTINUOUS

TIME

LOW-PASS FILTER

DIGITAL

SIGMA-DELTA

MODULATOR

1-BIT

DAC

SE

+6/–15dB

PGA

CAPACITOR

INTERPOLATOR

LOW-PASS FILTER

VOUTN

MCLK

RESET

REFCAP

REFERENCE

AD73411

REFOUT

AGND2

AGND1

DGND

Figure 2. Functional Block Diagram of Analog Front End Section

The AFE is conﬁgured as a single I/O channel (similar to that of

the discrete AD73311L; refer to the AD73311L data sheet for

more details) having a 16-bit sigma-delta-based ADC and DAC.

Both ADC and DAC share a common reference whose nominal

value is 1.2 V. Figure 2 shows a block diagram of the AFE sec-

tion of the AD73411. It shows an ADC and DAC as well as a

common reference. Communication to both channels is handled

by the SPORT2 block which interfaces to either SPORT0 or

SPORT1 of the DSP section.

or from the DAC output via the Analog Loop-Back (ALB)

arrangement. Differential inputs can be inverted and it is also

possible to use the device in single-ended mode, which allows

the option of using the VINP, VINN pins as two separate

single-ended inputs, either of which can be selected under soft-

ware control.

Programmable Gain Ampliﬁer

The encoder section’s analog front end comprises a switched

capacitor PGA that also forms part of the sigma-delta modulator.

The SC sampling frequency is DMCLK/8. The PGA, whose

programmable gain settings are shown in Table I, may be

used to increase the signal level applied to the ADC from low

output sources such as microphones, and can be used to avoid

placing external ampliﬁers in the circuit. The input signal level

to the sigma-delta modulator should not exceed the maximum

input voltage permitted.

The I/O channel features fully differential inputs and outputs.

The input section allows direct connection to the internal Pro-

grammable Gain Ampliﬁer at the input of the sigma-delta

ADC section. The input section also features programmable differ-

ential channel inversion and conﬁguration of the differential

input as two separate single-ended inputs. The ADC features a

second order sigma-delta modulator which samples at MCLK/8.

Its bitstream output is ﬁltered and decimated by a Sinc-cubed

decimator to provide a sample rate selectable from 64 kHz,

32 kHz, 16 kHz or 8 kHz (based on an MCLK of 16.384 MHz).

The PGA gain is set by bits IGS0, IGS1 and IGS2 (CRD:0–2)

in Control Register D.

The DAC channel features a Sinc-cubed interpolator which

increases the sample rate from the selected rate to the digital

sigma-delta modulator rate of MCLK/8. The digital sigma-delta

modulator’s output bitstream is fed to a single-bit DAC whose

output is reconstructed/ﬁltered by two stages of low-pass ﬁltering

(switched capacitor and continuous time) before being applied

to the differential output driver.

Table I. PGA Settings for the Encoder Channel

IGS2

IGS1

IGS0

Gain (dB)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

6

12

18

20

26

32

38

FUNCTIONAL DESCRIPTION

Encoder Channel

The encoder channel consists of an input conﬁguration block, a

switched capacitor PGA and a sigma-delta analog-to-digital

converter (ADC). An on-board digital ﬁlter, which forms part

of the sigma-delta ADC, also performs critical system-level

ﬁltering. Due to the high level of oversampling, the input anti-

alias requirements are reduced such that a simple single pole

RC stage is sufﬁcient to give adequate attenuation in the band

of interest.

ADC

The ADC consists of an analog sigma-delta modulator and a

digital antialiasing decimation ﬁlter. The sigma-delta modu-

lator noise-shapes the signal and produces 1-bit samples at a

DMCLK/8 rate. This bitstream, representing the analog input

signal, is input to the antialiasing decimation ﬁlter. The decima-

tion ﬁlter reduces the sample rate and increases the resolution.

Input Conﬁguration Block

The input conﬁguration block consists of a multiplexing arrange-

ment that allows selection of various input conﬁgurations. This

includes ADC input selection from either the VINP, VINN pins

–10–

REV. 0

AD73411

Analog Sigma-Delta Modulator

multiple of DMCLK/256, which is the decimation ﬁlter update

rate. The ﬁnal detail in Figure 4d shows the application of a

ﬁnal antialias ﬁlter in the DSP engine. This has the advantage of

being implemented according to the user’s requirements and

available MIPS. The ﬁltering in Figures 4a through 4c is imple-

mented in the AD73411.

The AD73411 input channel employs a sigma-delta conver-

sion technique, which provides a high resolution 16-bit output

with system ﬁltering being implemented on-chip.

Sigma-delta converters employ a technique known as over-

sampling, where the sampling rate is many times the highest

frequency of interest. In the case of the AD73411, the initial

sampling rate of the sigma-delta modulator is DMCLK/8. The

main effect of oversampling is that the quantization noise is

spread over a very wide bandwidth, up to f_S/2 = DMCLK/16

(Figure 3a). This means that the noise in the band of interest is

much reduced. Another complementary feature of sigma-delta

converters is the use of a technique called noise-shaping. This

technique has the effect of pushing the noise from the band of

interest to an out-of-band position (Figure 3b). The combina-

tion of these techniques, followed by the application of a digital

ﬁlter, sufﬁciently reduces the noise in band to ensure good

dynamic performance from the part (Figure 3c).

F

= 4kHz

F

= DMCLK/8

B

SINIT

a. Analog Antialias Filter Transfer Function

SIGNAL TRANSFER FUNCTION

NOISE TRANSFER FUNCTION

F

= 4kHz

F

= DMCLK/8

B

SINIT

BAND

OF

INTEREST

f /2

S

DMCLK/16

b. Analog Sigma-Delta Modulator Transfer Function

a.

F

= 4kHz

F

= DMCLK/256

NOISE-SHAPING

B

SINTER

c. Digital Decimator Transfer Function

BAND

OF

INTEREST

f /2

S

DMCLK/16

b.

DIGITAL FILTER

F

= 4kHz

F

= 8kHz

F

= DMCLK/256

B

SFINAL

SINTER

d. Final Filter LPF (HPF) Transfer Function

BAND

OF

INTEREST

f /2

S

DMCLK/16

Figure 4. AD73411 ADC Frequency Responses

c.

Decimation Filter

The digital ﬁlter used in the AD73411 carries out two impor-

tant functions. Firstly, it removes the out-of-band quantization

noise, which is shaped by the analog modulator and secondly, it

decimates the high-frequency bitstream to a lower rate 15-bit word.

Figure 3. Sigma-Delta Noise Reduction

Figure 4 shows the various stages of ﬁltering that are employed

in a typical AD73411 application. In Figure 4a we see the

transfer function of the external analog antialias ﬁlter. Even

though it is a single RC pole, its cutoff frequency is sufﬁciently

far away from the initial sampling frequency (DMCLK/8) that it

takes care of any signals that could be aliased by the sampling

frequency. This also shows the major difference between the

initial oversampling rate and the bandwidth of interest. In Figure

4b, the signal and noise-shaping responses of the sigma-delta

modulator are shown. The signal response provides further

rejection of any high frequency signals while the noise-shaping

will push the inherent quantization noise to an out-of-band

position. The detail of Figure 4c shows the response of the

digital decimation ﬁlter (Sinc-cubed response) with nulls every

The antialiasing decimation ﬁlter is a sinc-cubed digital ﬁlter that

reduces the sampling rate from DMCLK/8 at the modulator to

an output rate at the SPORT of DMCLK/M (where M depends

on the sample rate setting—M = 256 @ 64 kHz; M = 512 @

32 kHz, M = 1024 @ 16 kHz, M = 2048 @ 8 kHz), and increases

the resolution from a single bit to 15 bits. Its Z transform is given

as: [(1–Z^–N)/(1–Z^–1)]³where N is determined by the sampling rate

(N = 32 @ 64 kHz, N = 64 @ 32 kHz, N = 128 @ 16 kHz, N =

256 @ 8 kHz). This ensures a minimal group delay of 25 µs at the

64 kHz sampling rate.

–11–

REV. 0

AD73411

The output of the interpolation ﬁlter is fed to the DAC’s digital

sigma-delta modulator, which converts the 16-bit data to 1-bit

samples at a rate of DMCLK/8. The modulator noise-shapes

the signal so that errors inherent to the process are minimized

in the passband of the converter. The bitstream output of the

sigma-delta modulator is fed to the single bit DAC where it is

converted to an analog voltage.

ADC Coding

The ADC coding scheme is in twos complement format (see

Figure 5). The output words are formed by the decimation

ﬁlter, which grows the word length from the single-bit output of

the sigma-delta modulator to a 15-bit word, which is the 16-bit

transfer being used as a flag bit to indicate either control or data

in the frame.

Analog Smoothing Filter and PGA

V

INN

V

+ (V

؋

0.32875)

The output of the single-bit DAC is sampled at DMCLK/8,

therefore it is necessary to ﬁlter the output to reconstruct the

low frequency signal. The decoder’s analog smoothing ﬁlter

consists of a continuous-time ﬁlter preceded by a third-order

switched-capacitor ﬁlter. The continuous-time ﬁlter forms part

of the output programmable gain ampliﬁer (PGA). The PGA

can be used to adjust the output signal level from –15 dB to

+6 dB in 3 dB steps, as shown in Table II. The PGA gain is

set by bits OGS0, OGS1 and OGS2 (CRD:4-6) in Control

Register D.

REF

ANALOG

INPUT

V

REF

V

– (V

؋

0.32875)

V

REF

INP

10...00

00...00

01...11

ADC CODE DIFFERENTIAL

Table II. PGA Settings for the Decoder Channel

V

+ (V

؋

0.6575)

REF

V

INN

OGS2

OGS1

OGS0

Gain (dB)

ANALOG

INPUT

V

REF

0

1

0

1

0

1

0

1

0

1

0

1

0

1

6

3

0

–3

–6

–9

–12

–15

V

– (V

؋

0.6575)

REF

V

INP

10...00

00...00

01...11

ADC CODE SINGLE-ENDED

Figure 5. ADC Transfer Function

Decoder Channel

The decoder channel consists of a digital interpolator, digital

sigma-delta modulator, a single bit digital-to-analog converter

(DAC), an analog smoothing ﬁlter and a programmable gain

ampliﬁer with differential output.

Differential Output Ampliﬁers

The decoder has a differential analog output pair (VOUTP and

VOUTN). The output channel can be muted by setting the

MUTE bit (CRD:7) in Control Register D. The output signal is

dc-biased to the codec’s on-chip voltage reference.

DAC Coding

Voltage Reference

The DAC coding scheme is in twos complement format with

0x7FFF being full-scale positive and 0x8000 being full-scale

negative.

The AD73411 reference, REFCAP, is a bandgap reference

that provides a low noise, temperature-compensated reference

to the DAC and ADC. A buffered version of the reference is

also made available on the REFOUT pin and can be used to

bias other external analog circuitry. The reference has a default

nominal value of 1.2 V.

Interpolation Filter

The anti-imaging interpolation ﬁlter is a sinc-cubed digital ﬁlter

which upsamples the 16-bit input words from the SPORT

input rate of DMCLK/M (where M depends on the sample rate

setting (M = 256 @ 64 kHz; M = 512 @ 32 kHz, M = 1024 @

16 kHz, M = 2048 @ 8 kHz), to a rate of DMCLK/8 while

ﬁltering to attenuate images produced by the interpolation pro-

cess. Its Z transform is given as: [(1–Z^–N)/(1–Z^–1)]³where N is

determined by the sampling rate (N = 32 @ 64 kHz, N = 64 @

32 kHz, N = 128 @ 16 kHz, N = 256 @ 8 kHz). The DAC

receives 16-bit samples from the host DSP processor at a rate of

DMCLK/M. If the host processor fails to write a new value to

the serial port, the existing (previous) data is read again. The

data stream is ﬁltered by the anti-imaging interpolation ﬁlter,

but there is an option to bypass the interpolator for the mini-

mum group delay conﬁguration by setting the IBYP bit (CRE:5) of

Control Register E. The interpolation ﬁlter has the same charac-

teristics as the ADC’s antialiasing decimation ﬁlter.

The reference output (REFOUT) can be enabled for biasing

external circuitry by setting the RU bit (CRC:6) of CRC.

AFE Serial Port (SPORT2)

The AFE section communicates with the DSP section via its

bidirectional synchronous serial port (SPORT2), which interfaces

to either SPORT0 or SPORT1 of the DSP section. SPORT2 is

used to transmit and receive digital data and control information.

This allows other single or dual codec devices to be cascaded

together (up to a limit of eight codec units).

In both transmit and receive modes, data is transferred at the

serial clock (SCLK2) rate with the MSB being transferred first.

Communications between the AFE section and the DSP section

must always be initiated by the AFE section (AFE is in master

mode—DSP SPORT is in slave mode). This ensures that there

is no collision between input data and output samples.

–12–

REV. 0

AD73411

SPORT2 Overview

master clock divider. When working at the lower SCLK rate of

DMCLK/8, which is intended for interfacing with slower DSPs,

the SPORT will support a maximum of two devices in cascade

with the sample rate of DMCLK/256.

SPORT2 is a flexible, full-duplex, synchronous serial port

whose protocol has been designed to allow extra AFE devices

(AD733xx series), up to a maximum of eight I/O channels, to be

connected in cascade to a DSP SPORT (0 or 1). It has a very

flexible architecture that can be configured by programming two

of the internal control registers. SPORT2 has three distinct

modes of operation: Control Mode, Data Mode and Mixed

Control/Data Mode.

SPORT2 Register Maps

There are two register banks for the AD73411: the control

register bank and the data register bank. The control register

bank consists of six read/write registers, each eight bits wide.

Table VII shows the control register map for the AD73411. The

ﬁrst two control registers, CRA and CRB, are reserved for con-

trolling the SPORT. They hold settings for parameters such as

bit rate, internal master clock rate, and device count (used when

more than one AFE is connected in cascade from a single

SPORT). The other three registers; CRC, CRD, and CRE are

used to hold control settings for the ADC, DAC, Reference,

and Power Control sections of the device. Control registers

are written to on the negative edge of SCLK. The data register

bank consists of two 16-bit registers that are the DAC and

ADC registers.

In Control Mode (CRA:0 = 0), the device’s internal conﬁgura-

tion can be programmed by writing to the ﬁve internal control

registers. In this mode, control information can be written to or

read from the codec. In Data Mode (CRA:0 = 1), information

that is sent to the device is used to update the decoder section

(DAC), while the encoder section (ADC) data is read from the

device. In this mode, only DAC and ADC data is written to or

read from the device. Mixed mode (CRA:0 = 1 and CRA:1 = 1)

allows the user to choose whether the information being sent to

the device contains either control information or DAC data.

This is achieved by using the MSB of the 16-bit frame as a flag

bit. Mixed mode reduces the resolution to 15 bits, with the MSB

being used to indicate whether the information in the 16-bit frame

is control information or DAC/ADC data.

Master Clock Divider

The AD73411 features a programmable master clock divider

that allows the user to reduce an externally available master

clock, at pin MCLK, by one of the ratios 1, 2, 3, 4, or 5, to

produce an internal master clock signal (DMCLK) that is used

to calculate the sampling and serial clock rates. The master

clock divider is programmable by setting CRB:4–6. Table III

shows the division ratio corresponding to the various bit settings.

The default divider ratio is divide-by-one.

The SPORT features a single 16-bit serial register that is used for

both input and output data transfers. As the input and output

data must share the same register some precautions must be

observed. The primary precaution is that no information be

written to the SPORT without reference to an output sample

event, which is when the serial register will be overwritten with

the latest ADC sample word. Once the SPORT starts to output

the latest ADC word, it is safe for the DSP to write new control

or data words to the codec. In certain conﬁgurations, data can be

written to the device to coincide with the output sample being

shifted out of the serial register—see section on interfacing devices.

The serial clock rate (CRB:2–3) deﬁnes how many 16-bit words

can be written to a device before the next output sample event

will happen.

Table III. DMCLK (Internal) Rate Divider Settings

MCD2

MCD1

MCD0

DMCLK Rate

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MCLK

MCLK/2

MCLK/3

MCLK/4

MCLK/5

MCLK

The SPORT block diagram, shown in Figure 6, details the six

control registers (A–F), external MCLK to internal DMCLK

divider, and serial clock divider. The divider rates are controlled

by the setting of Control Register B. The AD73411 features a

master clock divider that allows users the flexibility of dividing

externally available high-frequency DSP or CPU clocks to gen-

erate a lower frequency master clock internally in the codec which

may be more suitable for either serial transfer or sampling rate

requirements. The master clock divider has ﬁve divider options

(÷1 default condition, ÷2, ÷3, ÷4, ÷5) that are set by loading

the master clock divider ﬁeld in Register B with the appropri-

ate code. Once the internal device master clock (DMCLK)

has been set using the master clock divider, the sample rate

and serial clock settings are derived from DMCLK.

MCLK

Serial Clock Rate Divider

The AD73411 features a programmable serial clock divider that

allows users to match the serial clock (SCLK) rate of the data to

that of the DSP engine or host processor. The maximum SCLK

rate available is DMCLK and the other available rates are:

DMCLK/2, DMCLK/4, and DMCLK/8. The slowest rate

(DMCLK/8) is the default SCLK rate. The serial clock divider

is programmable by setting bits CRB:2–3. Table IV shows the

serial clock rate corresponding to the various bit settings.

Table IV. SCLK Rate Divider Settings

The SPORT can work at four different serial clock (SCLK) rates:

chosen from DMCLK, DMCLK/2, DMCLK/4, or DMCLK/8,

where DMCLK is the internal or device master clock resulting

from the external or pin master clock being divided by the

SCD1

SCD0

SCLK Rate

0

1

0

1

0

1

DMCLK/8

DMCLK/4

DMCLK/2

DMCLK

–13–

REV. 0

AD73411

MCLK

(EXTERNAL)

DMCLK

(INTERNAL)

MCLK

DIVIDER

SCLK

SE

SCLK

SERIAL PORT

(SPORT)

DIVIDER

RESET

SDIFS

SDI

SDOFS

SDO

SERIAL REGISTER

2

8

3

8

CONTROL

REGISTER F

CONTROL

REGISTER A

CONTROL

REGISTER B

CONTROL

REGISTER C

CONTROL

REGISTER D

CONTROL

REGISTER E

Figure 6. SPORT Block Diagram

Sample Rate Divider

OPERATION

The AD73411 features a programmable sample rate divider that

allows users flexibility in matching the codec’s ADC and DAC

sample rates to the needs of the DSP software. The maximum

sample rate available is DMCLK/256, which offers the lowest

conversion group delay, while the other available rates are:

DMCLK/512, DMCLK/1024, and DMCLK/2048. The slowest

rate (DMCLK/2048) is the default sample rate. The sample

rate divider is programmable by setting bits CRB:0–1. Table V

shows the sample rate corresponding to the various bit settings.

Resetting the AFE Section of the AD73411

The RESET pin resets all the control registers. All registers are

reset to zero, indicating that the default SCLK rate (DMCLK/8)

and sample rate (DMCLK/2048) are at a minimum to ensure

that slow speed DSP engines can communicate effectively. As well

as resetting the control registers using the RESET pin, the device

can be reset using the RESET bit (CRA:7) in Control Register

A. Both hardware and software resets require four DMCLK cycles.

On reset, DATA/PGM (CRA:0) is set to 0 (default condition)

thus enabling Program Mode. The reset conditions ensure that

the device must be programmed to the correct settings after

power-up or reset. Following a reset, the SDOFS will be asserted

2048 DMCLK cycles after RESET going high. The data that

is output following RESET and during Program Mode is random

and contains no valid information until either Data or Mixed

Mode is set.

Table V. Sample Rate Divider Settings

DIR1

DIR0

SCLK Rate

0

1

0

1

0

1

DMCLK/2048

DMCLK/1024

DMCLK/512

DMCLK/256

Power Management

The individual functional blocks of the AFE can be enabled

separately by programming the power control register CRC. It

allows certain sections to be powered down if not required,

which adds to the device’s flexibility in that the user need not

incur the penalty of having to provide power for a certain

section if it is not necessary to their design. The power control

register provides individual control settings for the major func-

tional blocks and also a global override that allows all sections to

be powered up by setting the bit. Using this method the user

could, for example, individually enable a certain section, such

as the reference (CRC:5), and disable all others. The global

power-up (CRC:0) can be used to enable all sections but if

power-down is required using the global control, the reference

will still be enabled, in this case, because its individual bit is set.

Refer to Table XI for details of the settings of CRC.

DAC Advance Register

The loading of the DAC is internally synchronized with the

unloading of the ADC data in each sampling interval. The

default DAC load event happens one SCLK cycle before the

SDOFS flag is raised by the ADC data being ready. However,

this DAC load position can be advanced before this time by

modifying the contents of the DAC Advance ﬁeld in Control

Register E (CRE:0–4). The ﬁeld is ﬁve bits wide, allowing 31

increments of weight 1/(DMCLK/8); see Table VI. In certain

circumstances this can reduce the group delay when the ADC

and DAC are used to process data in series.

Note: The DAC advance register should be changed before the

DAC section is powered up.

Table VI. DAC Timing Control

DA4

DA3

DA2

DA1

DA0

Time Advance*

0

—

0

—

0

—

0

1

—

0

1

0

—

0 ns

488.2 ns

976.5 ns

—

1

0

1

14.64 µs

15.13 µs

*DMCLK = 16.384 MHz.

–14–

REV. 0

AD73411

Table VII. Control Register Map

Address (Binary)

Name

Description

Type

Width

Reset Setting (Hex)

000

001

010

011

100

101

110 to 111

CRA

CRB

CRC

CRD

CRE

CRF

Control Register A

Control Register B

Control Register C

Control Register D

Control Register E

Control Register F

Reserved

R/W

8

0x00

Table VIII. Control Word Description

10

Register Address

15

14

13

12

11

9

8

7

6

5

4

3

2

1

0

C/D

R/W

Device Address

Register Data

Control

Frame

Description

Bit 15

Control/Data

When set high, it signiﬁes a control word in Program or Mixed Program/Data Modes. When

set low, it signiﬁes a data word in Mixed Program/Data Mode or an invalid control word in

Program Mode.

Bit 14

Read/Write

When set low, it tells the device that the data ﬁeld is to be written to the register selected by

the register ﬁeld setting provided the address ﬁeld is zero. When set high, it tells the device

that the selected register is to be written to the data ﬁeld in the input serial register and that

the new control word is to be output from the device via the serial output.

Bits 13–11

Device Address

This 3-bit ﬁeld holds the address information. Only when this ﬁeld is zero is a device selected.

If the address is not zero, it is decremented and the control word is passed out of the device

via the serial output.

Bits 10–8

Bits 7–0

Register Address

Register Data

This 3-bit ﬁeld is used to select one of the ﬁve control registers on the AD73411.

This 8-bit ﬁeld holds the data that is to be written to or read from the selected register provided

the address ﬁeld is zero.

Table IX. Control Register A Description

CONTROL REGISTER A

7

6

5

4

3

2

1

0

RESET

DC2

DC1

DC0

SLB

DLB

MM

DATA/PGM

Bit

Name

Description

0

1

2

3

4

5

6

7

DATA/PGM Operating Mode (0 = Program; 1 = Data Mode)

MM

DLB

SLB

DC0

DC1

DC2

RESET

Mixed Mode (0 = Off; 1 = Enabled)

Digital Loop-Back Mode (0 = Off; 1 = Enabled)

SPORT Loop-Back Mode (0 = Off; 1 = Enabled)

Device Count (Bit 0)

Device Count (Bit 1)

Device Count (Bit 2)

Software Reset (0 = Off; 1 = Initiates Reset)

–15–

REV. 0

AD73411

Table X. Control Register B Description

CONTROL REGISTER B

7

6

5

4

3

2

1

0

CEE

MCD2

MCD1

MCD0

SCD1

SCD0

DIR1

DIR0

Bit

Name

Description

0

1

2

3

4

5

6

7

DIR0

DIR1

Decimation/Interpolation Rate (Bit 0)

Decimation/Interpolation Rate (Bit 1)

Serial Clock Divider (Bit 0)

Serial Clock Divider (Bit 1)

Master Clock Divider (Bit 0)

Master Clock Divider (Bit 1)

Master Clock Divider (Bit 2)

Control Echo Enable (0 = Off; 1 = Enabled)

SCD0

SCD1

MCD0

MCD1

MCD2

CEE

Table XI. Control Register C Description

CONTROL REGISTER C

7

6

5

4

3

2

1

0

RES

RU

PUREF PUDAC PUADC

RES

PU

Bit

Name

Description

0

1

2

3

4

5

6

PU

Power-Up Device (0 = Power Down; 1 = Power-On)

Must Be Programmed to Zero (0)

ADC Power (0 = Power Down; 1 = Power On)

DAC Power (0 = Power Down; 1 = Power On)

REF Power (0 = Power Down; 1 = Power On)

REFOUT Use (0 = Disable REFOUT; 1 = Enable

REFOUT)

Reserved

PUADC

PUDAC

PUREF

RU

7

Reserved

Must Be Programmed to Zero (0)

Table XII. Control Register D Description

CONTROL REGISTER D

7

6

5

4

3

2

1

0

MUTE OGS2 OGS1 OGS0 RMOD IGS2

IGS1

IGS0

Bit

Name

Description

0

1

2

3

4

5

6

7

IGS0

IGS1

IGS2

RMOD

OGS0

OGS1

OGS2

MUTE

Input Gain Select (Bit 0)

Input Gain Select (Bit 1)

Input Gain Select (Bit 2)

Reset ADC Modulator (0 = Off; 1 = Reset Enabled)

Output Gain Select (Bit 0)

Output Gain Select (Bit 1)

Output Gain Select (Bit 2)

Output Mute (0 = Mute Off; 1 = Mute Enabled)

–16–

REV. 0

AD73411

Table XIII. Control Register E Description

CONTROL REGISTER E

7

6

5

4

3

2

1

0

RES

IBYP

DA4

DA3

DA2

DA1

DA0

Bit

Name

Description

0

1

2

3

4

5

DA0

DA1

DA2

DA3

DA4

IBYP

DAC Advance Setting (Bit 0)

DAC Advance Setting (Bit 1)

DAC Advance Setting (Bit 2)

DAC Advance Setting (Bit 3)

DAC Advance Setting (Bit 4)

Interpolator Bypass (0 = Bypass Disabled;

1 = Bypass Enabled)

6

7

Reserved

Must Be Programmed to Zero (0)

Table XIV. Control Register F Description

CONTROL REGISTER F

7

6

5

4

3

2

1

0

ALB

INV

SEEN

RES

Bit

Name

Description

0

1

2

3

4

5

6

7

Reserved

SEEN

Must Be Programmed to Zero (0)

Single-Ended Enable (0 = Disabled; 1 = Enabled)

Input Invert (0 = Disabled; 1 = Enabled)

Analog Loopback of Output to Input (0 = Disabled; 1 = Enabled)

INV

ALB

–17–

REV. 0

AD73411

AFE Operating Modes

received at the SDIFS pin. When that number equals the device

count stored in the device count ﬁeld of CRA, the device knows

that the present data frame being received is its own DAC update

data. When the device is in normal Data Mode (i.e., mixed

mode disabled), it must receive a hardware reset to reprogram

any of the control register settings. In a single codec conﬁgura-

tion, each 16-bit data frame sent from the DSP to the device is

interpreted as DAC data. The default device count is 1, therefore

each input frame sync will cause the 16-bit data frame to be

loaded to the DAC register.

Five operating modes are available on the AFE. Two of these—

Digital Loop-Back and Sport Loop-Back—are provided as

diagnostic modes with the other three, Program, Data and

Mixed Program/Data, being available for general-purpose use.

The device conﬁguration—register settings—can be changed

only in Program, and Mixed Program/Data Modes. In all modes,

transfers of information to or from the device occur in 16-bit

packets, therefore the DSP engine’s SPORT will be programmed

for 16-bit transfers.

Program (Control) Mode

Mixed Program/Data Mode

In Program Mode, CRA:0 = 0, the user writes to the control

registers to set up the device for desired operation—SPORT

operation, cascade length, power management, input/output

gain, etc. In this mode, the 16-bit information packet sent to the

device by the DSP engine is interpreted as a control word whose

format is shown in Table VIII. In this mode, the user must address

the device to be programmed using the address ﬁeld of the control

word. This ﬁeld is read by the device and if it is zero (000 bin),

the device recognizes the word as being addressed to it. If the

address ﬁeld is not zero, it is then decremented and the control

word is passed out of the device—either to the next device in a

cascade or back to the DSP engine. This 3-bit address format

allows the user to uniquely address any one of up to eight devices

in a cascade; please note that this addressing scheme is valid only

in sending control information to the device—a different format

is used to send DAC data to the device(s). In a single codec

conﬁguration, all control word addresses must be zero, other-

wise they will not be recognized; in a multicodec conﬁguration

all addresses from zero to N-1 (where N = number of devices in

cascade) are valid.

This mode allows the user to send control words to the device

along with the DAC data. This permits adaptive control of the

device whereby control of the input/output gains can be affected

by interleaving control words along with the normal flow of

DAC data. The standard data frame remains 16 bits, but now

the MSB is used as a flag bit to indicate whether the remaining

15 bits of the frame represent DAC data or control information.

In the case of DAC data, the 15 bits are loaded with MSB justi-

ﬁcation and LSB set to 0 to the DAC register. Mixed Mode is

enabled by setting the MM bit (CRA:1) to 1 and the DATA/PGM

bit (CRA:0) to 1. In the case where control setting changes will

be required during normal operation, this mode allows the

ability to load both control and data information with the slight

inconvenience of formatting the data. Note that the output

samples from the ADC will also have the MSB set to zero to

indicate it is a data word.

Digital Loop-Back

This mode can be used for diagnostic purposes and allows the

user to feed the ADC samples from the ADC register directly to

the DAC register. This forms a loop-back of the analog input to

the analog output by reconstructing the encoded signal using

the decoder channel. The serial interface will continue to work,

which allows the user to control gain settings, etc. Only when

DLB is enabled with Mixed Mode operation can the user disable

the DLB, otherwise the device must be reset.

Following reset, when the SE pin is enabled, the codec responds

by raising the SDOFS pin to indicate that an output sample

event has occurred. Control words can be written to the device to

coincide with the data being sent out of the SPORT, as shown in

Figure 7, or they can lag the output words by a time interval

that should not exceed the sample interval. After reset, output

frame sync pulses will occur at a slower default sample rate, which

is DMCLK/2048, until Control Register B is programmed, after

which the SDOFS pulses will occur at a rate set by the DIR0–1 bits

of CRB. This is to allow slow controller devices to establish

communication with the AFE. During Program Mode, the

data output by the device is random and should not be inter-

preted as ADC data.

Sport Loop-Back

This mode allows the user to verify the DSP interfacing and

connection by writing words to the SPORT of the device and

have them returned back unchanged at the next sample interval.

The frame sync and data word that are sent to the device are

returned via the output port. Again, SLB mode can only be

disabled when used in conjunction with mixed mode, otherwise

the device must be reset.

Data Mode

Analog Loop-Back

Once the device has been conﬁgured by programming the cor-

rect settings to the various control registers, the device may exit

Program Mode and enter Data Mode. This is done by program-

ming the DATA/PGM (CRA:0) bit to a 1 and MM (CRA:1) to

0. Once the device is in Data Mode, the 16-bit input data frame

is now interpreted as DAC data rather than a control frame. This

data is therefore loaded directly to the DAC register. In Data

Mode, as the entire input data frame contains DAC data, the

device relies on counting the number of input frame syncs

In Analog Loop-Back mode, the differential DAC output is

connected, via a loop-back switch, to the ADC input (see Figure

9). This mode allows the ADC channel to check functionality of

the DAC channel as the reconstructed output signal can be

monitored using the ADC as a sampler. Analog Loop-Back is

enabled by setting the ALB bit (CRF:7).

–18–

REV. 0

AD73411

SE

SCLK

SDOFS

SDO

SAMPLE WORD (DEVICE 1)

SDIFS

SDI

DATA (CONTROL) WORD (DEVICE 1)

Figure 7. Interface Signal Timing for Single Device Operation

SE

SCLK

SDOFS(2)

SDO(2)

SAMPLE WORD (DEVICE 2)

SAMPLE WORD (DEVICE 1)

SDOFS(1)

SDIFS(2)

SDO(1)

SDI(2)

DATA (CONTROL) WORD (DEVICE 2)

SAMPLE WORD (DEVICE 1)

SDIFS(1)

SDI(1)

DATA (CONTROL) WORD (DEVICE 2)

DATA (CONTROL) WORD (DEVICE 1)

Figure 8. Interface Signal Timing for Cascade of Two Devices

–19–

REV. 0

AD73411

ANALOG

LOOP-BACK

SELECT

SDIFS

SDI

TFS

DT

SINGLE-ENDED

ENABLE

INVERT

DSP

SECTION

SCLK

AFE

SECTION

VINP

VINN

0/38dB

PGA

DR

SDO

RFS

SDOFS

V

REF

VOUTP

VOUTN

CONTINUOUS

TIME

LOW-PASS

FILTER

+6/–15dB

Figure 10. Indirectly Coupled or Nonframe Sync Loop-

Back Conﬁguration

PGA

REFOUT

REFCAP

Cascade Operation

AD73411

REFERENCE

The AD73411 has been designed to support up to eight codecs in

a cascade connected to a single serial port. The SPORT interface

protocol has been designed so that device addressing is built

into the packet of information sent to the device. This allows the

cascade to be formed with no extra hardware overhead for

control signals or addressing. A cascade can be formed in

either of the two modes previously discussed.

Figure 9. Analog Loop-Back Connectivity

AFE Interfacing

The AFE section SPORT (SPORT2) can be interfaced to either

SPORT0 or SPORT1 of the DSP section. Both serial input and

output data use an accompanying frame synchronization signal

which is active high one clock cycle before the start of the 16-bit

word or during the last bit of the previous word if transmission

is continuous. The serial clock (SCLK) is an output from the

codec and is used to define the serial transfer rate to the DSP’s

Tx and Rx ports. Two primary configurations can be used: the

first is shown in Figure 10 where the DSP’s Tx data, Tx Frame

Sync, Rx data and Rx Frame Sync are connected to the codec’s

SDI, SDIFS, SDO and SDOFS respectively. This configuration,

referred to as indirectly coupled or nonframe sync loop-back,

has the effect of decoupling the transmission of input data from

the receipt of output data. The delay between receipt of codec

output data and transmission of input data for the codec is

determined by the DSP’s software latency. When programming

the DSP serial port for this configuration, it is necessary to set

the Rx Frame Sync as an input and the Tx Frame Sync as an

output generated by the DSP. This configuration is most useful

when operating in mixed mode, as the DSP has the ability to

decide how many words (either DAC or control) can be sent to

the codecs. This means that full control can be implemented

over the device configuration as well as updating the DAC in a

given sample interval. The second configuration (shown in

Figure 11) has the DSP’s Tx data and Rx data connected to the

codec’s SDI and SDO, respectively while the DSP’s Tx and Rx

frame syncs are connected to the codec’s SDIFS and SDOFS.

In this configuration, referred to as directly coupled or frame

sync loop-back, the frame sync signals are connected together

and the input data to the codec is forced to be synchronous with

the output data from the codec. The DSP must be programmed

so that both the Tx Frame Sync and Rx Frame Sync are inputs

as the codec SDOFS will be input to both. This configuration

guarantees that input and output events occur simultaneously

and is the simplest configuration for operation in normal Data

Mode. Note that when programming the DSP in this configuration

it is advisable to preload the Tx register with the first control

word to be sent before the codec is taken out of reset. This

ensures that this word will be transmitted to coincide with the

first output word from the device(s).

There may be some restrictions in cascade operation due to the

number of devices conﬁgured in the cascade and the serial clock

rate chosen. Table XV details the requirements for SCLK rate

for cascade lengths from 1 to 8 devices. This assumes a directly

coupled frame sync arrangement as shown in Figure 11.

Table XV. Cascade Options

Number of Devices in Cascade

SCLK

1

2

3

4

5

6

7

8

DMCLK

ꢀ

X

ꢀ

X

ꢀ

X

ꢀ

X

ꢀ

X

ꢀ

X

DMCLK/2

DMCLK/4

DMCLK/8

SDIFS

TFS

DT

SDI

SCLK

AFE

SECTION

DSP

SECTION

DR

SDO

RFS

SDOFS

Figure 11. Directly Coupled or Frame Sync Loop-

Back Conﬁguration

When using the indirectly coupled frame sync conﬁguration in

cascaded operation it is necessary to be aware of the restrictions

in sending data to all devices in the cascade. Effectively, the

time allowed is given by the sampling interval (256/DMCLK)

which is 15.625 µs for a sample rate of 64 kHz. In this interval, the

DSP must transfer N × 16 bits of information where N is the

number of devices in the cascade. Each bit will take 1/SCLK

and, allowing for any latency between the receipt of the Rx

interrupt and the transmission of the Tx data, the relationship

for successful operation is given by:

256/DMCLK > ((N × 16/SCLK) + T_{INTERRUPT LATENCY}

)

The interrupt latency will include the time between the ADC

sampling event and the Rx interrupt being generated in the

DSP—this should be 16 SCLK cycles.

–20–

REV. 0

AD73411

In Cascade Mode, each device must know the number of devices

in the cascade because the Data and Mixed modes use a method

of counting input frame sync pulses to decide when they should

update the DAC register from the serial input register. Control

Register A contains a 3-bit ﬁeld (DC0–2) that is programmed

by the DSP during the programming phase. The default condi-

tion is that the ﬁeld contains 000b, which is equivalent to a

single device in cascade (see Table XVI). For cascade operation,

however this ﬁeld must contain a binary value that is one less

than the number of devices in the cascade.

accumulation. The shifter performs logical and arithmetic shifts,

normalization, denormalization and derive exponent operations.

The shifter can be used to efﬁciently implement numeric

format control including multiword and block floating-point

representations.

The internal result (R) bus connects the computational units so

that the output of any unit may be the input of any unit on the

next cycle.

A powerful program sequencer and two dedicated data address

generators ensure efﬁcient delivery of operands to these com-

putational units. The sequencer supports conditional jumps,

subroutine calls and returns in a single cycle. With internal loop

counters and loop stacks, the AD73411 executes looped code

with zero overhead; no explicit jump instructions are required to

maintain loops.

Table XVI. Device Count Settings

DC2

DC1

DC0

Cascade Length

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

3

4

5

6

7

8

Two data address generators (DAGs) provide addresses for

simultaneous dual operand fetches (from data memory and

program memory). Each DAG maintains and updates four

address pointers. Whenever the pointer is used to access data

(indirect addressing), it is post-modiﬁed by the value of one of

four possible modify registers. A length value may be associated

with each pointer to implement automatic modulo addressing

for circular buffers.

FUNCTIONAL DESCRIPTION—DSP

The AD73411 instruction set provides flexible data moves and

multifunction (one or two data moves with a computation)

instructions. Every instruction can be executed in a single pro-

cessor cycle. The AD73411 assembly language uses an algebraic

syntax for ease of coding and readability. A comprehensive set

of development tools supports program development.

Efﬁcient data transfer is achieved with the use of ﬁve internal

buses:

• Program Memory Address (PMA) Bus

• Program Memory Data (PMD) Bus

• Data Memory Address (DMA) Bus

• Data Memory Data (DMD) Bus

• Result (R) Bus

POWER-DOWN

CONTROL

FULL MEMORY

MODE

The two address buses (PMA and DMA) share a single external

address bus, allowing memory to be expanded off-chip, and the

two data buses (PMD and DMD) share a single external data

bus. Byte memory space and I/O memory space also share the

external buses.

DATA

MEMORY

PROGRAMMABLE

ADDRESS

EXTERNAL

ADDRESS

BUS

16K PM

(OPTIONAL (OPTIONAL

8K) 8K)

16K DM

PROGRAM

SEQUENCER

I/O

GENERATORS

AND

FLAGS

DAG 1 DAG 2

EXTERNAL

DATA

PROGRAM MEMORY ADDRESS

DATA MEMORY ADDRESS

BUS

BYTE DMA

CONTROLLER

Program memory can store both instructions and data, permitting

the AD73411 to fetch two operands in a single cycle, one from

program memory and one from data memory. The AD73411

can fetch an operand from program memory and the next in-

struction in the same cycle.

PROGRAM MEMORY DATA

DATA MEMORY DATA

OR

EXTERNAL

DATA

BUS

ARITHMETIC UNITS

ALU MAC SHIFTER

SERIAL PORTS

TIMER

INTERNAL

DMA

PORT

SPORT 0 SPORT 1

ADSP-2100 BASE

ARCHITECTURE

In lieu of the address and data bus for external memory connec-

tion, the AD73411 may be conﬁgured for 16-bit Internal DMA

port (IDMA port) connection to external systems. The IDMA

port is made up of 16 data/address pins and ﬁve control pins.

The IDMA port provides transparent, direct access to the DSPs

on-chip program and data RAM.

HOST MODE

SERIAL PORT

SPORT 2

REF

ADC1

DAC1

ANALOG FRONT END

SECTION

An interface to low-cost byte-wide memory is provided by the

Byte DMA port (BDMA port). The BDMA port is bidirectional

and can directly address up to four megabytes of external RAM

or ROM for off-chip storage of program overlays or data tables.

Figure 12. Functional Block Diagram

Figure 12 is an overall block diagram of the AD73411. The

processor contains three independent computational units: the

ALU, the multiplier/accumulator (MAC) and the shifter. The

computational units process 16-bit data directly and have provi-

sions to support multiprecision computations. The ALU performs

a standard set of arithmetic and logic operations; division primi-

tives are also supported. The MAC performs single-cycle multiply,

multiply/add and multiply/subtract operations with 40 bits of

The byte memory and I/O memory space interface supports slow

memories and I/O memory-mapped peripherals with program-

mable wait state generation. External devices can gain control of

external buses with bus request/grant signals (BR, BGH, and

BG). One execution mode (Go Mode) allows the AD73411 to

continue running from on-chip memory. Normal execution

mode requires the processor to halt while buses are granted.

–21–

REV. 0

AD73411

The AD73411 can respond to eleven interrupts. There can be

up to six external interrupts (one edge-sensitive, two level-

sensitive and three conﬁgurable) and seven internal interrupts

generated by the timer, the serial ports (SPORTs), the Byte DMA

port and the power-down circuitry. There is also a master RESET

signal. The two serial ports provide a complete synchronous

serial interface with optional companding in hardware and a

wide variety of framed or frameless data transmit and receive

modes of operation.

DSP SECTION PIN DESCRIPTIONS

The AD73411 is available in a 119-ball PBGA package. In order

to maintain maximum functionality and reduce package size and

pin count, some serial port, programmable flag, interrupt, and

external bus pins have dual, multiplexed functionality. The exter-

nal bus pins are conﬁgured during RESET only, while serial port

pins are software conﬁgurable during program execution. Flag

and interrupt functionality is retained concurrently on multi-

plexed pins. In cases where pin functionality is reconﬁgurable,

the default state is shown in plain text; alternate functionality is

shown in italics. See Pin Function Descriptions section.

Each port can generate an internal programmable serial clock or

accept an external serial clock.

Memory Interface Pins

The AD73411 provides up to 13 general-purpose flag pins. The

data input and output pins on SPORT1 can be alternatively

conﬁgured as an input flag and an output flag. In addition, eight

flags are programmable as inputs or outputs and three flags are

always outputs.

The AD73411 processor can be used in one of two modes, Full

Memory Mode, which allows BDMA operation with full exter-

nal overlay memory and I/O capability, or Host Mode, which

allows IDMA operation with limited external addressing capa-

bilities. The operating mode is determined by the state of the

Mode C pin during RESET and cannot be changed while the

processor is running. See Full Memory Mode Pins and Host

Mode Pins charts for descriptions.

A programmable interval timer generates periodic interrupts. A

16-bit count register (TCOUNT) is decremented every n pro-

cessor cycle, where n is a scaling value stored in an 8-bit register

(TSCALE). When the value of the count register reaches zero,

an interrupt is generated and the count register is reloaded from

a 16-bit period register (TPERIOD).

Full Memory Mode Pins (Mode C = 0)

# of

Input/

Name(s) Pins Output Function

Serial Ports

The DSP section incorporates two complete synchronous serial

ports (SPORT0 and SPORT1) for serial communications and

multiprocessor communication.

A13:0

D23:0

14

24

O

Address Output Pins for Program,

Data, Byte, and I/O Spaces

Data I/O Pins for Program, Data,

Byte, and I/O Spaces (8 MSBs are

also used as Byte Memory

addresses)

I/O

Following is a brief list of the capabilities of the SPORTs. For

additional information on Serial Ports, refer to the ADSP-2100

Family User’s Manual, Third Edition.

•

SPORTs are bidirectional and have a separate, double-

buffered transmit and receive section.

Host Mode Pins (Mode C = 1)

Pin # of Input/

Name(s) Pins Output Function

SPORTs can use an external serial clock or generate their

own serial clock internally.

IAD15:0 16

I/O

O

IDMA Port Address/Data Bus

Address Pin for External I/O,

Program, Data, or Byte Access

SPORTs have independent framing for the receive and trans-

mit sections. Sections run in a frameless mode or with frame

synchronization signals internally or externally generated.

Frame sync signals are active high or inverted, with either of

two pulsewidths and timings.

A0

1

D23:8

16

I/O

Data I/O Pins for Program, Data

Byte and I/O Spaces

IWR

IRD

IAL

IS

1

I

IDMA Write Enable

IDMA Read Enable

IDMA Address Latch Pin

IDMA Select

•

SPORTs support serial data word lengths from 3 to 16 bits

and provide optional A-law and µ-law companding according

to CCITT recommendation G.711.

•

SPORT receive and transmit sections can generate unique

interrupts on completing a data word transfer.

IACK

O

IDMA Port Acknowledge

SPORTs can receive and transmit an entire circular buffer of

data with only one overhead cycle per data word. An inter-

rupt is generated after a data buffer transfer.

NOTE

In Host Mode, external peripheral addresses can be decoded using the A0,

CMS, PMS, DMS, and IOMS signals.

•

SPORT0 has a multichannel interface to selectively receive

and transmit a 24- or 32-word, time-division multiplexed,

serial bitstream.

SPORT1 can be conﬁgured to have two external interrupts

(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The

internally generated serial clock may still be used in this

conﬁguration.

–22–

REV. 0

AD73411

NOTES

Terminating Unused Pin

The following chart shows the recommendations for terminating

unused pins.

*Hi-Z = High Impedance.

1. If the CLKOUT pin is not used, turn it OFF.

2. If the Interrupt/Programmable Flag pins are not used, there are two options:

Option 1: When these pins are conﬁgured as INPUTS at reset and function

as interrupts and input flag pins, pull the pins High (inactive).

Option 2: Program the unused pins as OUTPUTS, set them to 1, and let

them float.

3. All bidirectional pins have three-stated outputs. When the pins is conﬁgured

as an output, the output is Hi-Z (high impedance) when inactive.

4. CLKIN, RESET, and PF3:0 are not included in the table because these pins

must be used.

Pin Terminations

I/O

Hi-Z*

Caused

By

3-State Reset

Unused

Conﬁguration

Name

(Z)

State

XTAL

CLKOUT

A13:1 or

IAD12:0

A0

D23:8

D7 or

IWR

I

O

I

O

Float

High (Inactive)

Float

High (Inactive)

Float

Low (Inactive)

Float

High (Inactive)

Float

O (Z)

I/O (Z)

O (Z)

I/O (Z)

I

Hi-Z

I

BR, EBR

IS

BR, EBR

Interrupts

The interrupt controller allows the processor to respond to the

eleven possible interrupts and RESET with minimum overhead.

The AD73411 provides four dedicated external interrupt

input pins, IRQ2, IRQL0, IRQL1, and IRQE. In addition,

SPORT1 may be reconﬁgured for IRQ0, IRQ1, FLAG_IN,

and FLAG_OUT, for a total of six external interrupts. The

AD73411 also supports internal interrupts from the timer, the

byte DMA port, the two serial ports, software, and the power-

down control circuit. The interrupt levels are internally prioritized

and individually maskable (except power-down and reset). The

IRQ2, IRQ0, and IRQ1 input pins can be programmed to be

either level- or edge-sensitive. IRQL0 and IRQL1 are level-

sensitive and IRQE is edge-sensitive. The priorities and vector

addresses of all interrupts are shown in Table XVII.

D6 or

IRD

I/O (Z)

I

Hi-Z

I

BR, EBR

D5 or

IAL

D4 or

IS

I/O (Z)

I

I/O (Z)

I

Hi-Z

I

Hi-Z

I

BR, EBR

D3 or

IACK

D2:0 or

IAD15:13

PMS

DMS

BMS

IOMS

CMS

RD

I/O (Z)

Hi-Z

I/O (Z)

O (Z)

I

Hi-Z

O

BR, EBR

IS

BR, EBR

Float

High (Inactive)

Float

Table XVII. Interrupt Priority and Interrupt Vector Addresses

Interrupt Vector

Address (Hex)

Source of Interrupt

WR

BR

RESET (or Power-Up with PUCR = 1) 0000 (Highest Priority)

Power-Down (Nonmaskable)

IRQ2

IRQL1

IRQL0

SPORT0 Transmit

SPORT0 Receive

IRQE

BDMA Interrupt

SPORT1 Transmit or IRQ1

SPORT1 Receive or IRQ0

Timer

I

002C

0004

0008

000C

0010

0014

0018

001C

BG

BGH

O (Z)

O

EE

Float

IRQ2/PF7 I/O (Z)

IRQL1/PF6 I/O (Z)

IRQL0/PF5 I/O (Z)

IRQE/PF4 I/O (Z)

I

Input = High (Inactive)

or Program as Output,

Set to 1, Let Float

Input = High (Inactive)

or Program as Output,

Set to 1, Let Float

Input = High (Inactive)

or Program as Output,

Set to 1, Let Float

Input = High (Inactive)

or Program as Output,

Set to 1, Let Float

Input = High or Low,

Output = Float

High or Low

Float

I

0020

0024

0028 (Lowest Priority)

Interrupt routines can either be nested, with higher priority

interrupts taking precedence, or processed sequentially. Interrupts

can be masked or unmasked with the IMASK register. Individual

interrupt requests are logically ANDed with the bits in IMASK;

the highest priority unmasked interrupt is then selected. The

power-down interrupt is nonmaskable.

SCLK0

I/O

RFS0

DR0

TFS0

DT0

I/O

I

I/O

O

I

O

I

SCLK1

I/O

Input = High or Low,

Output = Float

High or Low

Float

The AD73411 masks all interrupts for one instruction cycle

following the execution of an instruction that modiﬁes the

IMASK register. This does not affect serial port autobuffering

or DMA transfers.

RFS1/IRQ0 I/O

DR1/FI

TFS1/IRQ1 I/O

I

O

I

DT1/FO

EE

O

I

The interrupt control register, ICNTL, controls interrupt nest-

ing and deﬁnes the IRQ0, IRQ1, and IRQ2 external interrupts

to be either edge- or level-sensitive. The IRQE pin is an external

edge-sensitive interrupt and can be forced and cleared. The

IRQL0 and IRQL1 pins are external level-sensitive interrupts.

EBR

I

EBG

ERESET

EMS

EINT

ECLK

ELIN

ELOUT

O

I

O

I

O

I

O

I

The IFC register is a write-only register used to force and clear

interrupts. On-chip stacks preserve the processor status and are

automatically maintained during interrupt handling. The stacks

O

–23–

REV. 0

AD73411

are twelve levels deep to allow interrupt, loop, and subroutine

nesting. The following instructions allow global enable or dis-

able servicing of the interrupts (including power-down), regardless

of the state of IMASK. Disabling the interrupts does not affect

serial port autobuffering or DMA.

clock rate, is speciﬁed by a selectable divisor given in the IDLE

instruction. The format of the instruction is

IDLE (n);

where n = 16, 32, 64, or 128. This instruction keeps the processor

fully functional, but operating at the slower clock rate. While it

is in this state, the processor’s other internal clock signals, such

as SCLK, CLKOUT, and Timer Clock, are reduced by the same

ratio. The default form of the instruction, when no clock divisor

is given, is the standard IDLE instruction.

ENA INTS;

DIS INTS;

When the processor is reset, interrupt servicing is enabled.

LOW-POWER OPERATION

When the IDLE (n) instruction is used, it effectively slows down

the processor’s internal clock and thus its response time to

incoming interrupts. The one-cycle response time of the standard

idle state is increased by n, the clock divisor. When an enabled

interrupt is received, the AD73411 will remain in the idle state

for up to a maximum of n processor cycles (n = 16, 32, 64, or 128)

before resuming normal operation.

The AD73411 has three low-power modes that signiﬁcantly

reduce the power dissipation when the device operates under

standby conditions. These modes are:

• Power-Down

• Idle

• Slow Idle

The CLKOUT pin may also be disabled to reduce external

power dissipation.

When the IDLE (n) instruction is used in systems that have an

externally generated serial clock (SCLK), the serial clock rate

may be faster than the processor’s reduced internal clock rate.

Under these conditions, interrupts must not be generated at a

rate faster than can be serviced, due to the additional time the

processor takes to come out of the idle state (a maximum of n

processor cycles).

Power-Down

The AD73411 processor has a low-power feature that lets the

processor enter a very low-power dormant state through hard-

ware or software control. Here is a brief list of power-down

features. Refer to the ADSP-2100 Family User’s Manual, Third

Edition, “System Interface” chapter, for detailed information

about the power-down feature.

SYSTEM INTERFACE

Figure 13 shows a typical basic system conﬁguration with the

AD73411, two serial devices, a byte-wide EPROM, and

optional external program and data overlay memories (mode

selectable). Programmable wait state generation allows the proces-

sor to connect easily to slow peripheral devices. The AD73411 also

provides four external interrupts and two serial ports or six

external interrupts and one serial port. Host Memory Mode allows

access to the full external data bus, but limits addressing to a

single address bit (A0). Additional system peripherals can be

added in this mode through the use of external hardware to

generate and latch address signals.

•

Quick recovery from power-down. The processor begins

executing instructions in as few as 400 CLKIN cycles.

•

Support for an externally generated TTL or CMOS proces-

sor clock. The external clock can continue running during

power-down without affecting the 400 CLKIN cycle recovery.

•

Support for crystal operation includes disabling the oscillator

to save power (the processor automatically waits 4096 CLKIN

cycles for the crystal oscillator to start and stabilize), and

letting the oscillator run to allow 400 CLKIN cycle startup.

Power-down is initiated by either the power-down pin (PWD)

or the software power-down force bit. Interrupt support

allows an unlimited number of instructions to be executed

before optionally powering down. The power-down interrupt

also can be used as a nonmaskable, edge-sensitive interrupt.

Clock Signals

The AD73411 can be clocked by either a crystal or a TTL-

compatible clock signal.

The CLKIN input cannot be halted, changed during opera-

tion, or operated below the speciﬁed frequency during normal

operation. The only exception is while the processor is in the

power-down state. For detailed information on this power-down

feature, refer to Chapter 9, ADSP-2100 Family User’s Manual,

Third Edition.

•

Context clear/save control allows the processor to continue

where it left off or start with a clean context when leaving the

power-down state.

•

The RESET pin also can be used to terminate power-down.

Power-down acknowledge pin indicates when the processor

has entered power-down.

If an external clock is used, it should be a TTL-compatible signal

running at half the instruction rate. The signal is connected to

the processor’s CLKIN input. When an external clock is used,

the XTAL input must be left unconnected.

Idle

When the AD73411 is in the Idle Mode, the processor waits

indeﬁnitely in a low power state until an interrupt occurs. When

an unmasked interrupt occurs, it is serviced; execution then

continues with the instruction following the IDLE instruction.

In Idle Mode IDMA, BDMA, and Autobuffer Cycle steals still

occur.

The AD73411 uses an input clock with a frequency equal to half

the instruction rate; a 26.00 MHz input clock yields a 19 ns

processor cycle (which is equivalent to 52 MHz). Normally,

instructions are executed in a single processor cycle. All device

timing is relative to the internal instruction clock rate, which is

indicated by the CLKOUT signal when enabled.

Slow Idle

The IDLE instruction on the AD73411 slows the processor’s

internal clock signal, further reducing power consumption. The

reduced clock frequency, a programmable fraction of the normal

–24–

REV. 0

AD73411

A clock output (CLKOUT) signal is generated by the processor

at the processor’s cycle rate. This can be enabled and disabled

by the CLK0DIS bit in the SPORT0 Autobuffer Control Register.

FULL MEMORY MODE

AD73411

14

24

A

13–0

1/2x CLOCK

OR

ADDR13–0

CLKIN

D

23–16

A0–A21

XTAL

CRYSTAL

BYTE

Reset

D

15–8

MEMORY

FL0–2

DATA23–0

PF3

DATA

The RESET signal initiates a master reset of the DSP section of

the AD73411. The RESET signal must be asserted during the

power-up sequence to assure proper initialization. RESET during

initial power-up must be held long enough to allow the internal

clock to stabilize. If RESET is activated any time after power-up,

the clock continues to run and does not require stabilization time.

BMS

CS

IRQ2/PF7

A

IRQE/PF4

10–0

ADDR

IRQL0/PF5

IRQL1/PF6

WR

RD

I/O SPACE

(PERIPHERALS)

D

23–8

MODE C/PF2

MODE B/PF1

MODE A/PF0

DATA

CS

2048

LOCATIONS

IOMS

A

D

13–0

SPORT1

SCLK1

OVERLAY

MEMORY

ADDR

DATA

The power-up sequence is deﬁned as the total time required for

the crystal oscillator circuit to stabilize after a valid V_DDis applied

to the processor, and for the internal phase-locked loop (PLL)

to lock onto the speciﬁc crystal frequency. A minimum of 2000

CLKIN cycles ensures that the PLL has locked, but does not

include the crystal oscillator start-up time. During this power-up

sequence the RESET signal should be held low. On any subse-

quent resets, the RESET signal must meet the minimum pulsewidth

AFE*

SECTION

OR

SERIAL

DEVICE

23–0

RFS1 OR IRQ0

TFS1 OR IRQ1

DT1 OR FO

DR1 OR FI

TWO 8K

PMS

DMS

CMS

PM SEGMENTS

TWO 8K

DM SEGMENTS

SPORT0

BR

BG

BGH

SCLK0

RFS0

TFS0

DT0

AFE*

SECTION

OR

SERIAL

DEVICE

DR0

PWD

PWDACK

speciﬁcation, t_RSP

.

HOST MEMORY MODE

AD73411

The RESET input contains some hysteresis; however, if an

RC circuit is used to generate the RESET signal, an external

Schmitt trigger is recommended.

1

1/2x CLOCK

OR

CRYSTAL

CLKIN

A0

16

XTAL

DATA23–8

FL0–2

PF3

The master reset sets all internal stack pointers to the empty stack

condition, masks all interrupts, and clears the MSTAT register.

When RESET is released, if there is no pending bus request and

the chip is conﬁgured for booting, the boot-loading sequence is

performed. Once boot loading completes, the ﬁrst instruction is

fetched from on-chip program memory location 0x0000.

BMS

IRQ2/PF7

IRQE/PF4

IRQL0/PF5

IRQL1/PF6

MODE C/PF2

MODE B/PF1

MODE A/PF0

WR

RD

SPORT1

SCLK1

RFS1 OR IRQ0

TFS1 OR IRQ1

DT1 OR FO

DR1 OR FI

IOMS

MODES OF OPERATION

Table XVII summarizes the AD73411 memory modes.

AFE*

SECTION

OR

SERIAL

DEVICE

PMS

DMS

CMS

Setting Memory Mode

Memory Mode selection for the AD73411 is made during

chip reset through the use of the Mode C pin. This pin is multi-

plexed with the DSP’s PF2 pin, so care must be taken in how

the mode selection is made. The two methods for selecting the

value of Mode C are active and passive.

SPORT0

BR

BG

BGH

SCLK0

RFS0

TFS0

DT0

AFE*

SECTION

OR

SERIAL

DEVICE

DR0

PWD

PWDACK

IDMA PORT

Passive Conﬁguration involves the use a pull-up or pull-down

resistor connected to the Mode C pin. To minimize power

consumption, or if the PF2 pin is to be used as an output in the

DSP application, a weak pull-up or pull-down, on the order

of 100 kΩ, can be used. This value should be sufﬁcient to pull the

pin to the desired level and still allow the pin to operate as

a programmable flag output without undue strain on the

processor’s output driver. For minimum power consumption

during power-down, reconﬁgure PF2 to be an input, as the

pull-up or pull-down will hold the pin in a known state and will

not switch.

IRD/D6

IWR/D7

IS/D4

IAL/D5

IACK/D3

SYSTEM

INTERFACE

OR

*AFE SECTION CAN BE

CONNECTED TO EITHER

SPORT0 OR SPORT1

␮CONTROLLER

16

IAD15-0

Figure 13. Basic System Conﬁguration

CLKIN

XTAL

CLKOUT

DSP

Active Conﬁguration involves the use of a three-statable

external driver connected to the Mode C pin. A driver’s output

enable should be connected to the DSP’s RESET signal such

that it only drives the PF2 pin when RESET is active (low).

When RESET is deasserted, the driver should three-state, thus

allowing full use of the PF2 pin as either an input or output. To

minimize power consumption during power-down, conﬁgure the

programmable flag as an output when connected to a three-stated

buffer. This ensures that the pin will be held at a constant level

and not oscillate should the three-state driver’s level hover around

the logic switching point.

Figure 14. External Crystal Connections

Because the AD73411 includes an on-chip oscillator circuit, an

external crystal may be used. The crystal should be connected

across the CLKIN and XTAL pins, with two capacitors connected

as shown in Figure 14. Capacitor values are dependent on crystal

type and should be speciﬁed by the crystal manufacturer. A

parallel-resonant, fundamental frequency, microprocessor-grade

crystal should be used.

–25–

REV. 0

AD73411

Table XVIII. Modes of Operations¹

MODE C²MODE B³MODE A⁴Booting Method

0

1

0

1

0

1

BDMA feature is used to load the ﬁrst 32 program memory words from the byte memory

space. Program execution is held off until all 32 words have been loaded. Chip is conﬁgured

in Full Memory Mode.⁵

No automatic boot operations occur. Program execution starts at external memory location

0. Chip is conﬁgured in Full Memory Mode. BDMA can still be used, but the processor does

not automatically use or wait for these operations.

BDMA feature is used to load the ﬁrst 32 program memory words from the byte memory

space. Program execution is held off until all 32 words have been loaded. Chip is conﬁg-

ured in Host Mode.⁶

IDMA feature is used to load any internal memory as desired. Program execution is held off

until internal program memory location 0 is written to. Chip is conﬁgured in Host Mode.⁵

1

NOTES

¹All mode pins are recognized while RESET is active (low).

²When Mode C = 0, Full Memory enabled. When Mode C = 1, Host Memory Mode enabled.

³When Mode B = 0, Autobooting enabled. When Mode B = 1, no Autobooting.

⁴When Mode A = 0, BDMA enabled. When Mode A = 1, IDMA enabled.

⁵Considered as standard operating settings. Using these conﬁgurations allows for easier design and better memory management.

⁶Requires additional hardware.

1

PM (MODE B = 0)

MEMORY ARCHITECTURE

PM (MODE B = 1)

The AD73411 provides a variety of memory and peripheral

interface options. The key functional groups are Program

Memory, Data Memory, Byte Memory, and I/O. Refer to the

following ﬁgures and tables for PM and DM memory allocations

in the AD73411.

ALWAYS

ACCESSIBLE

RESERVED

AT ADDRESS

0x0000 – 0x1FFF

0x2000–

INTERNAL

MEMORY

0x3FFF

INTERNAL

MEMORY

ACCESSIBLE

WHEN

PMOVLAY = 0

0x2000–

0x3FFF

ACCESSIBLE

WHEN

PMOVLAY = 0

0x0000–

0x1FFF

2

ACCESSIBLE

WHEN

PMOVLAY = 0

0x2000–

0x3FFF

2

ACCESSIBLE

WHEN

PMOVLAY = 1

PROGRAM MEMORY

0x2000–

EXTERNAL

MEMORY

RESERVED

2

Program Memory (Full Memory Mode) is a 24-bit-wide

space for storing both instruction op codes and data. The

AD73411-80 has 16K words of Program Memory RAM on chip

(the AD73411-40 has 8K words of Program Memory RAM on

chip), and the capability of accessing up to two 8K external

memory overlay spaces using the external data bus.

0x3FFF

EXTERNAL

MEMORY

ACCESSIBLE

WHEN

PMOVLAY = 2

1

WHEN MODE B = 1, PMOVLAY MUST BE

SET TO 0

SEE TABLE XIX FOR PMOVLAY BITS

2

PROGRAM MEMORY

MODE B = 0

PROGRAM MEMORY

MODE B = 1

ADDRESS

0x3FFF

ADDRESS

0x3FFF

Program Memory (Host Mode) allows access to all internal

memory. External overlay access is limited by a single external

address line (A0). External program execution is not available in

host mode due to a restricted data bus that is only 16 bits wide.

8K INTERNAL

PMOVLAY = 0

OR

8K EXTERNAL

PMOVLAY = 1 OR 2

8K INTERNAL

PMOVLAY = 0

0x2000

0x1FFF

0x2000

0x1FFF

8K EXTERNAL

Table XIX. PMOVLAY Bits

8K INTERNAL

0x0000

PMOVLAY Memory A13

A12:0

0

1

Internal

External

Overlay 1

Not Applicable Not Applicable

Figure 15. Program Memory Map

DATA MEMORY

0

1

13 LSBs of Address

Between 0x2000

and 0x3FFF

13 LSBs of Address

Between 0x2000

and 0x3FFF

Data Memory (Full Memory Mode) is a 16-bit-wide space

used for the storage of data variables and for memory-mapped

control registers. The AD73411-80 has 16K words on Data

Memory RAM on-chip (the AD73411-40 has 8K words on Data

Memory RAM on-chip), consisting of 16,352 user-accessible

locations in the case of the AD73411-80 (8,160 user-accessible

locations in the case of the AD73411-40) and 32 memory-

mapped registers. Support also exists for up to two 8K external

memory overlay spaces through the external data bus. All inter-

nal accesses complete in one cycle. Accesses to external memory

are timed using the wait states speciﬁed by the DWAIT register.

2

External

Overlay 2

–26–

REV. 0

AD73411

DATA MEMORY

ADDRESS

DATA MEMORY

The CMS pin functions like the other memory select signals,

with the same timing and bus request logic. A 1 in the enable bit

causes the assertion of the CMS signal at the same time as the

selected memory select signal. All enable bits default to 1 at reset,

except the BMS bit.

0x3FFF

32 MEMORY

MAPPED

REGISTERS

ALWAYS

ACCESSIBLE

AT ADDRESS

0x2000 – 0x3FFF

0

x

3FE0

0

x

3FDF

INTERNAL

8160

WORDS

0

x

0000–

INTERNAL

MEMORY

0

x1FFF

0

x

2000

0

x1FFF

ACCESSIBLE WHEN

DMOVLAY = 0

0

x

0000–

0

x

1FFF

8K INTERNAL

DMOVLAY = 0

OR

EXTERNAL 8K

DMOVLAY = 1, 2

Boot Memory Select (BMS) Disable

0

x

0000–

The AD73411 also lets you boot the processor from one exter-

nal memory space while using a different external memory space

for BDMA transfers during normal operation. You can use the

CMS to select the ﬁrst external memory space for BDMA trans-

fers and BMS to select the second external memory space for

booting. The BMS signal can be disabled by setting Bit 3 of the

System Control Register to 1. The System Control Register is

illustrated in Figure 17.

ACCESSIBLE WHEN

DMOVLAY = 1

0

x

1FFF

0x0000

EXTERNAL

MEMORY

ACCESSIBLE WHEN

DMOVLAY = 2

Figure 16. Data Memory Map

Data Memory (Host Mode) allows access to all internal memory.

External overlay access is limited by a single external address

line (A0). The DMOVLAY bits are deﬁned in Table XX.

SYSTEM CONTROL REGISTER

15 14 13 12 11 10

9

8

7

6

5

4

3

0

2

1

0

1

Table XX. DMOVLAY Bits

DM (0x3FFF)

0

1

0

DMOVLAY Memory A13

A12:0

SPORT0 ENABLE

1 = ENABLED

PWAIT

PROGRAM MEMORY

WAIT STATES

0

1

Internal

External

Overlay 1

Not Applicable Not Applicable

0 = DISABLED

SPORT1 ENABLE

1 = ENABLED

0 = DISABLED

0

1

13 LSBs of Address

Between 0x2000

and 0x3FFF

13 LSBs of Address

Between 0x2000

and 0x3FFF

BMS ENABLE

0 = ENABLED

1 = DISABLED

SPORT1 CONFIGURE

1 = SERIAL PORT

0 = FI, FO, IRQ0,

2

External

IRQ1, SCLK

Overlay 2

Figure 17. System Control Register

Byte Memory

The byte memory space is a bidirectional, 8-bit-wide, external

memory space used to store programs and data. Byte memory is

accessed using the BDMA feature. The BDMA Control Regis-

ter is shown in Figure 18. The byte memory space consists of

256 pages, each of which is 16K × 8.

I/O Space (Full Memory Mode)

The AD73411 supports an additional external memory space

called I/O space. This space is designed to support simple connec-

tions to peripherals (such as data converters and external registers)

or to bus interface ASIC data registers. I/O space supports 2048

locations of 16-bit-wide data. The lower 11-bits of the external

address bus are used; the upper three bits are undeﬁned. Two

instructions were added to the core ADSP-2100 Family Instruc-

tion Set to read from and write to I/O memory space. The I/O

space also has four dedicated 3-bit wait state registers, IOWAIT0-

3, that specify up to seven wait states to be automatically generated

for each of four regions. The wait states act on address ranges as

shown in Table XXI.

The byte memory space on the AD73411 supports read and

write operations as well as four different data formats. The byte

memory uses data bits 15:8 for data. The byte memory uses

data bits 23:16 and address bits 13:0 to create a 22-bit address.

This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be

used without glue logic. All byte memory accesses are timed by

the BMWAIT register.

Byte Memory DMA (BDMA, Full Memory Mode)

Table XXI. Wait States

The Byte memory DMA controller allows loading and storing of

program instructions and data using the byte memory space.

The BDMA circuit is able to access the byte memory space

while the processor is operating normally, and steals only one

DSP cycle per 8-, 16-, or 24-bit word transferred.

Address Range Wait State Register

0x000–0x1FF

0x200–0x3FF

0x400–0x5FF

0x600–0x7FF

IOWAIT0

IOWAIT1

IOWAIT2

IOWAIT3

BDMA CONTROL

15 14 13 12 11 10

9

8

7

6

5

4

0

3

1

2

0

1

0

DM (0x3FE3)

0

Composite Memory Select (CMS)

BTYPE

BDIR

BMPAGE

The AD73411 has a programmable memory select signal that is

useful for generating memory select signals for memories mapped

to more than one space. The CMS signal is generated to have

the same timing as each of the individual memory select signals

(PMS, DMS, BMS, IOMS) but can combine their functionality.

0 = LOAD FROM BM

1 = STORE TO BM

BCR

0 = RUN DURING BDMA

1 = HALT DURING BDMA

Each bit in the CMSSEL register, when set, causes the CMS

signal to be asserted when the selected memory select is asserted.

For example, to use a 32K word memory to act as both program

and data memory, set the PMS and DMS bits in the CMSSEL

register and use the CMS pin to drive the chip select of the

memory; use either DMS or PMS as the additional address bit.

Figure 18. BDMA Control Register

The BDMA circuit supports four different data formats that are

selected by the BTYPE register ﬁeld. The appropriate number

of 8-bit accesses are done from the byte memory space to build

the word size selected. Table XXII shows the data formats sup-

ported by the BDMA circuit.

–27–

REV. 0

AD73411

Table XXII. Data Formats

4. Host uses IS and IRD (or IWR) to read (or write) DSP inter-

nal memory (PM or DM).

Internal

Memory Space

5. Host checks IACK line to see if the DSP has completed the

BTYPE

Word Size

Alignment

previous IDMA operation.

00

01

10

11

Program Memory

Data Memory

24

16

8

Full Word

MSBs

6. Host ends IDMA transfer.

The IDMA port has a 16-bit multiplexed address and data bus

and supports 24-bit program memory. The IDMA port is

completely asynchronous and can be written to while the

AD73411 is operating at full speed.

8

LSBs

Unused bits in the 8-bit data memory formats are ﬁlled with 0s.

The BIAD register ﬁeld is used to specify the starting address

for the on-chip memory involved with the transfer. The 14-bit

BEAD register speciﬁes the starting address for the external

byte memory space. The 8-bit BMPAGE register speciﬁes the

starting page for the external byte memory space. The BDIR

register ﬁeld selects the direction of the transfer. Finally the

14-bit BWCOUNT register speciﬁes the number of DSP words

to transfer and initiates the BDMA circuit transfers.

The DSP memory address is latched and then automatically

incremented after each IDMA transaction. An external device

can therefore access a block of sequentially addressed memory

by specifying only the starting address of the block. This in-

creases throughput as the address does not have to be sent for

each memory access.

IDMA Port access occurs in two phases. The first is the IDMA

Address Latch cycle. When the acknowledge is asserted, a

14-bit address and 1-bit destination type can be driven onto the

bus by an external device. The address specifies an on-chip

memory location; the destination type specifies whether it is a

DM or PM access. The falling edge of the address latch signal

latches this value into the IDMAA register.

BDMA accesses can cross page boundaries during sequential

addressing. A BDMA interrupt is generated on the completion

of the number of transfers speciﬁed by the BWCOUNT register.

The BWCOUNT register is updated after each transfer so it can

be used to check the status of the transfers. When it reaches

zero, the transfers have ﬁnished and a BDMA interrupt is gener-

ated. The BMPAGE and BEAD registers must not be accessed

by the DSP during BDMA operations.

Once the address is stored, data can either be read from or

written to the AD73411’s on-chip memory. Asserting the

select line (IS) and the appropriate read or write line (IRD and

IWR respectively) signals the AD73411 that a particular trans-

action is required. In either case, there is a one-processor-cycle

delay for synchronization. The memory access consumes one

additional processor cycle.

The source or destination of a BDMA transfer will always be

on-chip program or data memory.

When the BWCOUNT register is written with a nonzero value,

the BDMA circuit starts executing byte memory accesses with

wait states set by BMWAIT. These accesses continue until the

count reaches zero. When enough accesses have occurred to

create a destination word, it is transferred to or from on-chip

memory. The transfer takes one DSP cycle. DSP accesses to exter-

nal memory have priority over BDMA byte memory accesses.

Once an access has occurred, the latched address is automati-

cally incremented and another access can occur.

Through the IDMAA register, the DSP can also specify the

starting address and data format for DMA operation. Asserting

the IDMA port select (IS) and address latch enable (IAL) di-

rects the AD73411 to write the address onto the IAD0–14 bus

into the IDMA Control Register. The IDMAA register, shown

below, is memory mapped at address DM (0x3FE0). Note that

the latched address (IDMAA) cannot be read back by the

host. See Figure 19 for more information on IDMA and DMA

memory maps.

The BDMA Context Reset bit (BCR) controls whether or not

the processor is held off while the BDMA accesses are occur-

ring. Setting the BCR bit to 0 allows the processor to continue

operations. Setting the BCR bit to 1 causes the processor to

stop execution while the BDMA accesses are occurring, to clear

the context of the processor and start execution at address 0

when the BDMA accesses have completed.

IDMA CONTROL (U = UNDEFINED AT RESET)

The BDMA overlay bits specify the OVLAY memory blocks to

be accessed for internal memory.

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

DM(0x3FE0)

U

Internal Memory DMA Port (IDMA Port; Host Memory

Mode)

IDMAA ADDRESS

IDMAD

The IDMA Port provides an efficient means of communication

between a host system and the AD73411. The port is used to

access the on-chip program memory and data memory of the

DSP with only one DSP cycle per word overhead. The IDMA

port cannot be used, however, to write to the DSP’s memory-

mapped control registers. A typical IDMA transfer process is

described as follows:

DESTINATION MEMORY TYPE:

0 = PM

1 = DM

Figure 19. IDMA Control/OVLAY Registers

Bootstrap Loading (Booting)

The AD73411 has two mechanisms to allow automatic loading

of the internal program memory after reset. The method for

booting after reset is controlled by the Mode A, B and C con-

ﬁguration bits.

1. Host starts IDMA transfer.

2. Host checks IACK control line to see if the DSP is busy.

When the mode pins specify BDMA booting, the AD73411

initiates a BDMA boot sequence when reset is released.

3. Host uses IS and IAL control lines to latch the DMA starting

address (IDMAA) into the DSP’s IDMA control registers.

IAD[15] must be set = 0.

–28–

REV. 0

AD73411

When BDMA booting is speciﬁed, the BDMA interface is set up

during reset to the following defaults: the BDIR, BMPAGE,

BIAD and BEAD registers are set to 0, the BTYPE register is

set to 0 to specify program memory 24-bit words, and the

BWCOUNT register is set to 32. This causes 32 words of on-

chip program memory to be loaded from byte memory. These

32 words are used to set up the BDMA to load in the remaining

program code. The BCR bit is also set to 1, which causes pro-

gram execution to be held off until all 32 words are loaded into

on-chip program memory. Execution then begins at address 0.

Flag I/O Pins

The AD73411 has eight general-purpose programmable input/

output flag pins. They are controlled by two memory-mapped

registers. The PFTYPE register determines the direction, 1 =

output and 0 = input. The PFDATA register is used to read and

write the values on the pins. Data being read from a pin conﬁg-

ured as an input is synchronized to the AD73411’s clock. Bits

that are programmed as outputs will read the value being out-

put. The PF pins default to input during reset.

In addition to the programmable flags, the AD73411 has ﬁve

ﬁxed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1, and

FL2. FL0–FL2 are dedicated output flags; FLAG_IN and

FLAG_OUT are available as an alternate conﬁguration of

SPORT1.

The ADSP-2100 Family Development Software (Revision 5.02

and later) fully supports the BDMA booting feature and can

generate byte memory-space-compatible boot code.

The IDLE instruction can also be used to allow the processor to

hold off execution while booting continues through the BDMA

interface. For BDMA accesses while in Host Mode, the ad-

dresses to boot memory must be constructed externally to the

AD73411. A0 is the only memory address bit provided by the

processor.

Note: Pins PF0, PF1, PF2, and PF3 are also used for device

conﬁguration during reset.

INSTRUCTION SET DESCRIPTION

The AD73411 assembly language instruction set has an algebraic

syntax that was designed for ease of coding and readability. The

assembly language, which takes full advantage of the processor’s

unique architecture, offers the following beneﬁts:

IDMA Port Booting

The AD73411 can also boot programs through its Internal DMA

port. If Mode C = 1, Mode B = 0 and Mode A = 1, the AD73411

boots from the IDMA port. IDMA feature can load as much on-

chip memory as desired. Program execution is held off until

on-chip program memory location 0 is written to.

•

The algebraic syntax eliminates the need to remember cryp-

tic assembler mnemonics. For example, a typical arithmetic

add instruction, such as AR = AX0 + AY0, resembles a

simple equation.

Bus Request and Bus Grant (Full Memory Mode)

•

Every instruction assembles into a single, 24-bit word that

can execute in a single instruction cycle.

The AD73411 can relinquish control of the data and address buses

to an external device. When the external device requires access

to memory, it asserts the bus request (BR) signal. If the AD73411

is not performing an external memory access, it responds to

the active BR input in the following processor cycle by:

The syntax is a superset ADSP-2100 Family assembly language

and is completely source-and object-code-compatible with other

family members. Programs may need to be relocated to utilize

on-chip memory and conform to the AD73411’s interrupt

vector and reset vector map.

•

Three-stating the data and address buses and the PMS,

DMS, BMS, CMS, IOMS, RD, WR output drivers

•

Asserting the bus grant (BG) signal

Halting program execution

•

Sixteen condition codes are available. For conditional jump,

call, return, or arithmetic instructions, the condition can be

checked and the operation executed in the same instruction

cycle.

If Go Mode is enabled, the AD73411 will not halt program

execution until it encounters an instruction that requires an

external memory access.

Multifunction instructions allow parallel execution of an

arithmetic instruction with up to two fetches or one write to

processor memory space during a single instruction cycle.

If the AD73411 is performing an external memory access when

the external device asserts the BR signal, it will not three-state

the memory interfaces or assert the BG signal until the processor

cycle after the access completes. The instruction does not need

to be completed when the bus is granted. If a single instruction

requires two external memory accesses, the bus will be granted

between the two accesses.

DESIGNING AN EZ-ICE^®-COMPATIBLE SYSTEM

The AD73411 has on-chip emulation support and an ICE-Port,

a special set of pins that interface to the EZ-ICE. These features

allow in-circuit emulation without replacing the target system

processor by using only a 14-pin connection from the target

system to the EZ-ICE. Target systems must have a 14-pin con-

nector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.

See the ADSP-2100 Family EZ-Tools^™data sheet for complete

information on ICE products.

When the BR signal is released, the processor releases the BG

signal, reenables the output drivers and continues program

execution from the point at which it stopped.

The bus request feature operates at all times, including when

the processor is booting and when RESET is active.

Issuing the chip reset command during emulation causes the

DSP to perform a full chip reset, including a reset of its memory

mode. Therefore, it is vital that the mode pins are set correctly

prior to issuing a chip reset command from the emulator user

interface. If you are using a passive method of maintaining

mode information (as discussed in Setting Memory Modes), it

does not matter that the mode information is latched by an

emulator reset. However, if using the RESET pin as a method

The BGH pin is asserted when the AD73411 is ready to execute

an instruction, but is stopped because the external bus is already

granted to another device. The other device can release the bus

by deasserting bus request. Once the bus is released, the AD73411

deasserts BG and BGH and executes the external memory access.

EZ-ICE^®registered trademark of Analog Devices.

EZ-Tools^™registered trademark of Analog Devices.

–29–

REV. 0

AD73411

of setting the value of the mode pins, the effects of an emulator

reset must be taken into consideration.

ing should be 0.1 × 0.1 inches. The pin strip header must have

at least 0.15 inch clearance on all sides to accept the EZ-ICE

probe plug.

One method of ensuring that the values located on the mode

pins are those desired, is to construct a circuit like the one shown

in Figure 20. This circuit forces the value located on the Mode

A pin to logic high; regardless if it is latched via the RESET or

ERESET pin.

Pin strip headers are available from vendors such as 3M,

McKenzie, and Samtec.

1

3

5

2

4

BG

GND

EBG

EBR

ERESET

RESET

BR

6

AD73411

EINT

ELIN

1k⍀

MODE A/PFO

7

؋

8

KEY (NO PIN)

ELOUT

PROGRAMMABLE

I/O

10

12

14

9

ECLK

Figure 20. Mode A Pin/EZ-ICE Circuit

11

13

EMS

EE

The ICE-Port interface consists of the following AD73411 pins:

RESET

ERESET

EBR

EMS

ELIN

EBG

EINT

ELOUT

ERESET

ECLK

EE

TOP VIEW

Figure 21. Target Board Connector for EZ-ICE

Target Memory Interface

For your target system to be compatible with the EZ-ICE

emulator, it must comply with the memory interface guidelines

listed below.

These AD73411 pins must be connected only to the EZ-ICE

connector in the target system. These pins have no function

except during emulation, and do not require pull-up or pull-

down resistors. The traces for these signals between the AD73411

and the connector must be kept as short as possible, no longer

than three inches.

PM, DM, BM, IOM and CM

Design your Program Memory (PM), Data Memory (DM),

Byte Memory (BM), I/O Memory (IOM) and Composite

Memory (CM) external interfaces to comply with worst-case

device timing requirements and switching characteristics as speci-

ﬁed in the DSP’s data sheet. The performance of the EZ-ICE

may approach published worst case speciﬁcation for some memory

access timing requirements and switching characteristics.

The following pins are also used by the EZ-ICE:

BR

BG

RESET GND

The EZ-ICE uses the EE (emulator enable) signal to take control

of the AD73411 in the target system. This causes the processor

to use its ERESET, EBR, and EBG pins instead of the RESET,

BR, and BG pins. The BG output is three-stated. These signals do

not need to be jumper-isolated in your system.

Note: If your target does not meet the worst-case chip speciﬁca-

tion for memory access parameters, you may not be able to

emulate your circuitry at the desired CLKIN frequency. Depend-

ing on the severity of the speciﬁcation violation, you may have

trouble manufacturing your system as DSP components statisti-

cally vary in switching characteristic and timing requirements

within published limits.

The EZ-ICE connects to your target system via a ribbon cable

and a 14-pin female plug. The ribbon cable is 10 inches in length

with one end ﬁxed to the EZ-ICE. The female plug is plugged

onto the 14-pin connector (a pin strip header) on the target board.

Target Board Connector for EZ-ICE Probe

The EZ-ICE connector (a standard pin strip header) is shown

in Figure 21. You must add this connector to your target board

design if you intend to use the EZ-ICE. Be sure to allow enough

room in your system to ﬁt the EZ-ICE probe onto the 14-pin

connector.

Restriction: All memory strobe signals on the AD73411 (RD,

WR, PMS, DMS, BMS, CMS, and IOMS) used in your target

system must have 10 kΩ pull-up resistors connected when the

EZ-ICE is being used. The pull-up resistors are necessary because

there are no internal pull-ups to guarantee their state during

prolonged three-state conditions resulting from typical EZ-ICE

debugging sessions. These resistors may be removed at your

option when the EZ-ICE is not being used.

The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-

tion—you must remove Pin 7 from the header. The pins must

be 0.025 inch square and at least 0.20 inch in length. Pin spac-

–30–

REV. 0

AD73411

Target System Interface Signals

of the SE and ARESET signals is synchronized at each device in

the cascade. A simple D-type flip-flop is sufﬁcient to sync each

signal to the master clock AMCLK, as in Figure 23.

When the EZ-ICE board is installed, the performance on some

system signals changes. Design your system to be compatible

with the following system interface signal changes introduced by

the EZ-ICE board:

SE SIGNAL

SYNCHRONIZED

TO AMCLK

DSP

CONTROL

TO SE

D

Q

1/2

74HC74

•

EZ-ICE emulation introduces an 8 ns propagation delay be-

tween your target circuitry and the DSP on the RESET signal.

EZ-ICE emulation introduces an 8 ns propagation delay

between your target circuitry and the DSP on the BR signal.

EZ-ICE emulation ignores RESET and BR when single-

stepping.

EZ-ICE emulation ignores RESET and BR when in Emula-

tor Space (DSP halted).

EZ-ICE emulation ignores the state of target BR in certain

modes. As a result, the target system may take control of the

DSP’s external memory bus only if bus grant (BG) is asserted

by the EZ-ICE board’s DSP.

CLK

AMCLK

ARESET SIGNAL

SYNCHRONIZED

TO AMCLK

DSP

CONTROL

TO ARESET

D

Q

1/2

74HC74

CLK

AMCLK

Figure 23. SE and ARESET Sync Circuit for Cascaded

Operation

Connection of a cascade of devices to a DSP, as shown in Figure

24, is no more complicated than connecting a single device.

Instead of connecting the SDO and SDOFS to the DSP’s Rx

port, these are now daisy-chained to the SDI and SDIFS of the

next device in the cascade. The SDO and SDOFS of the ﬁnal

device in the cascade are connected to the DSP section’s Rx port

to complete the cascade. SE and ARESET on all devices are fed

from the signals that were synchronized with the AMCLK using

the circuit as described above. The SCLK from only one device

need be connected to the DSP section’s SCLK input(s) as all

devices will be running at the same SCLK frequency and phase.

ANALOG FRONT END (AFE) INTERFACING

The AFE section of the AD73411 features a voiceband input/

output channel, each with 16-bit linear resolution. Connectivity

to the AFE section from the DSP is uncommitted, thus allowing

the user the flexibility of connecting in the mode or conﬁguration

of their choice. This section will detail several conﬁgurations—

with no extra AFE channels conﬁgured and with two extra AFE

channels conﬁgured (using an external AD73322 dual AFE).

DSP SPORT to AFE Interfacing

AD73411

TFS

SDIFS

The SCLK, SDO, SDOFS, SDI and SDIFS pins of SPORT2

must be connected to the Serial Clock, Receive Data, Receive

Data Frame Sync, Transmit Data, and Transmit Data Frame

Sync pins respectively of either SPORT0 or SPORT1. The SE

pin may be controlled from a parallel output pin or flag pin such

as FL0–2 or, where SPORT2 power-down is not required, it

can be permanently strapped high using a suitable pull-up

resistor. The ARESET pin may be connected to the system

hardware reset structure or it may also be controlled using a

dedicated control line. In the event of tying it to the global system

reset, it is advisable to operate the device in mixed mode, which

allows a software reset, otherwise there is no convenient way of

resetting the AFE section.

AMCLK

SE

DT

SDI

SCLK

SDO

AFE

SCLK

DSP

SECTION

DR

ARESET

RFS

SDOFS

DEVICE 1

FL0

FL1

SDIFS

SDI

AMCLK

SE

ADDITIONAL

AD73322

CODEC

SCLK

SDO

D1

D2

Q1

Q2

ARESET

74HC74

SDOFS

DEVICE 2

SDIFS

SDI

TFS

DT

Figure 24. Connection of an AD73322 Cascaded to

AD73411

SCLK

DR

SDO

SDOFS

DSP

SECTION

AFE

SECTION

Interfacing to the AFE’s Analog Inputs and Outputs

The AFE section of the AD73411 offers a flexible interface for

microphone pickups, line level signals, or PSTN line interfaces.

This section will detail some of the conﬁgurations that can be

used with the input and output sections.

RFS

FL0

FL1

ARESET

SE

Figure 22. AD73411 AFE to DSP Connection

Cascade Operation

Where it is required to conﬁgure extra analog I/O channels to

the existing two channels on the AD73411, it is possible to

cascade up to seven more channels (using single channel AD73311

or dual channel AD73322 AFEs) by using the scheme described

in Figure 24. It is necessary, however, to ensure that the timing

The AD73411 features both differential inputs and outputs to

provide optimal performance and avoid common-mode noise. It is

also possible to interface either inputs or outputs in single-ended

mode. This section details the choice of input and output conﬁgu-

rations and also gives some tips toward successful conﬁguration of

the analog interface sections.

–31–

REV. 0

AD73411

ANTIALIAS

FILTER

VINP

VINN

100⍀

0.047␮F

VINP

VINN

0/38dB

PGA

0/38dB

PGA

V

REF

100⍀

V

REF

VOUTP

VOUTN

REFOUT

CONTINUOUS

TIME

LOW-PASS

FILTER

+6/–15dB

PGA

VOUTP

VOUTN

CONTINUOUS

TIME

LOW-PASS

FILTER

OPTIONAL

BUFFER

+6/–15dB

PGA

AD73411

REFERENCE

REFCAP

0.1␮F

REFOUT

AD73411

REFERENCE

REFCAP

Figure 26. Analog Input (DC-Coupled) Using External

Ampliﬁers

0.1␮F

Figure 25. Analog Input (DC-Coupled)

Analog Inputs

The analog input (encoder) section of the AD73411 can be inter-

faced to external circuitry in either ac-coupled or dc-coupled modes.

The AD73411’s ADC inputs are biased about the internal refer-

ence level (REFCAP level), therefore, it may be necessary to bias

external signals to this level using the buffered REFOUT level

as the reference. This is applicable in either dc- or ac-coupled

conﬁgurations. In the case of dc coupling, the signal (biased

to REFOUT) may be applied directly to the inputs as shown in

Figure 25, or it may be conditioned in an external op amp where

it can also be biased to the reference level using the buffered

REFOUT signal as shown in Figure 26.

It is also possible to drive the ADC in either differential or

single-ended modes. If the single-ended mode is chosen it is

possible, using software control, to multiplex between two single-

ended inputs connected to the positive and negative input pins.

The primary concerns in interfacing to the ADC are to provide

adequate antialias ﬁltering and to ensure that the signal source

will drive the switched-capacitor input of the ADC correctly.

The sigma-delta design of the ADC and its oversampling char-

acteristics simplify the antialias requirements, but it must be

remembered that the single-pole RC ﬁlter is primarily intended

to eliminate aliasing of frequencies above the Nyquist frequency of

the sigma-delta modulator’s sampling rate (typically 2.048 MHz).

It may still require a more speciﬁc digital ﬁlter implementa-

tion in the DSP to provide the ﬁnal signal frequency response

characteristics. It is recommended that for optimum performance

the capacitors used for the antialiasing ﬁlter be of high quality

dielectric (NPO). The second issue mentioned above is interfacing

the signal source to the ADC’s switched capacitor input load.

The SC input presents a complex dynamic load to a signal

source, therefore, it is important to understand that the slew

rate characteristic is an important consideration when choosing

external buffers for use with the AD73411.

In the case of ac-coupling, a capacitor is used to couple the

signal to the input of the ADC. The ADC input must be biased

to the internal reference (REFCAP) level, which is done by

connecting the input to the REFOUT pin through a 10 kΩ

resistor as shown in Figure 27.

0.1␮F

100⍀

10k⍀

100⍀

VINP

0.047␮F

VINN

0/38dB

PGA

0.1␮F

10k⍀

0.047␮F

V

REF

VOUTP

CONTINUOUS

TIME

LOW-PASS

FILTER

+6/–15dB

PGA

VOUTN

REFOUT

REFERENCE

AD73411

The AD73411’s on-chip 38 dB preampliﬁer can be enabled

when there is not enough gain in the input circuit; the preampli-

ﬁer is conﬁgured by bits IGS0–2 of CRD. The total gain must be

conﬁgured to ensure that a full-scale input signal produces a signal

level at the input to the sigma-delta modulator of the ADC that

does not exceed the maximum input range.

REFCAP

0.1␮F

Figure 27. Analog Input (AC-Coupled) Differential

If the ADC is being connected in single-ended mode, the

AD73411 should be programmed for single-ended mode using

the SEEN and INV bits of CRF, and the inputs connected as

shown in Figure 28. When operated in single-ended input mode,

the AD73411 can multiplex one of the two inputs to the ADC

input, as shown in Figures 28 and 29.

The dc biasing of the analog input signal is accomplished with

an on-chip voltage reference. If the input signal is not biased at

the internal reference level (via REFOUT), it must be ac-coupled

with external coupling capacitors. C_INshould be 0.1 µF or larger.

The dc biasing of the input can then be accomplished using

resistors to REFOUT as in Figures 27 through 29.

–32–

REV. 0

AD73411

Analog Output

0.1␮F

10k⍀

100⍀

VINP

VINN

The AD73411’s differential analog output (VOUT) is produced

by an on-chip differential ampliﬁer. The differential output can

be ac-coupled or dc-coupled directly to a load that can be a

headset or the input of an external ampliﬁer. It is possible to

connect the outputs in either a differential or a single-ended

conﬁguration, but please note that the effective maximum output

voltage swing (peak-to-peak) is halved in the case of single-ended

connection. Figure 31 shows a simple circuit providing a differ-

ential output with ac coupling. The capacitors in this circuit

(C_OUT) are optional; if used, their value can be chosen as follows:

0.047

␮F

0/38dB

PGA

V

REF

VOUTP

CONTINUOUS

TIME

LOW-PASS

FILTER

+6/–15dB

PGA

VOUTN

REFOUT

REFERENCE

AD73411

REFCAP

0.1␮F

Figure 28. Analog Input (AC-Coupled) Single-Ended

1

C_OUT

=

2 π f_CR_LOAD

VINP

0/38dB

PGA

where f_C= desired cutoff frequency.

0.1␮F

10k⍀

VINN

100⍀

0.047

␮F

V

REF

VINP

VINN

VOUTP

VOUTN

CONTINUOUS

TIME

LOW-PASS

FILTER

+6/–15dB

PGA

C

OUT

VOUTP

REFOUT

CONTINUOUS

TIME

LOW-PASS

FILTER

AD73411

REFERENCE

+6/–15dB

PGA

R

LOAD

REFCAP

VOUTN

0.1␮F

C

OUT

REFOUT

REFCAP

AD73411

REFERENCE

Figure 29. Analog Input (AC-Coupled) Single-Ended

(Alternate Input)

C

REFCAP

Interfacing to an Electret Microphone

Figure 31. Example Circuit for Differential Output

Figure 30 details an interface for an electret microphone which

may be used in some voice applications. Electret microphones

typically feature a FET ampliﬁer whose output is accessed on

the same lead that supplies power to the microphone; therefore,

this output signal must be capacitively coupled to remove the

power supply (dc) component. In this circuit the AD73411

input channel is being used in single-ended mode where the

inverting ampliﬁer provides suitable gain to scale the input

signal relative to the ADC’s full-scale input range. The buffered

internal reference level at REFOUT is used via an external

buffer to provide power to the electret microphone. This pro-

vides a quiet, stable supply for the microphone. If this is not a

concern, the microphone can be powered from the system

power supply.

Figure 32 shows an example circuit for providing a single-ended

output with ac coupling. The capacitor of this circuit (C_OUT) is

not optional if dc current drain is to be avoided.

VINP

VINN

C

OUT

VOUTP

CONTINUOUS

TIME

LOW-PASS

FILTER

+6/–15dB

PGA

R

LOAD

VOUTN

REFOUT

REFCAP

AD73411

REFERENCE

C

REFCAP

5V

R

A

Figure 32. Example Circuit for Single-Ended Output

C1

R2

10␮F

R

B

R1

VINP

VINN

C2

0/38dB

PGA

ELECTRET

MICROPHONE

V

REF

VOUTP

CONTINUOUS

TIME

LOW-PASS

FILTER

+6/–15dB

PGA

VOUTN

REFOUT

REFERENCE

REFCAP

C

REFCAP

Figure 30. Electret Microphone Interface Circuit

–33–

REV. 0

AD73411

Differential-to-Single-Ended Output

In some applications it may be desirable to convert the full

differential output of the decoder channel to a single-ended

signal. The circuit of Figure 33 shows a scheme for doing this.

AFE DIGITAL

AFE ANALOG

DSP

7

6

5

4

3

2

1

VINP

VINN

R

F

VOUTP

CONTINUOUS

R

TIME

LOW-PASS

FILTER

I

+6/–15dB

PGA

R

LOAD

VOUTN

A B C D

E F G H J K L M N P R T U

R

F

REFOUT

REFCAP

AD73411

REFERENCE

DIGITAL

GROUND PLANE

ANALOG

GROUND PLANE

C

REFCAP

Figure 34. Ground Plane Layout

Figure 33. Example Circuit for Differential-to-Single-

Ended Output Conversion

Avoid running digital lines under the AFE section of the device

for they will couple noise onto the die. The analog ground plane

should be allowed to run under the AD73411’s AFE section to

avoid noise coupling (see Figure 34). The power supply lines to

the AD73411 should use as large a trace as possible to provide

low impedance paths and reduce the effects of glitches on the

power supply lines. Fast switching signals such as clocks should

be shielded with digital ground to avoid radiating noise to other

sections of the board, and clock signals should never be run near

Grounding and Layout

As the analog inputs to the AD73411’s AFE section are differ-

ential, most of the voltages in the analog modulator are common-

mode voltages. The excellent common-mode rejection of the

part will remove common-mode noise on these inputs. The

analog and digital supplies of the AD73411 are independent and

separately pinned out to minimize coupling between analog and

digital sections of the device. The digital ﬁlters on the encoder

section will provide rejection of broadband noise on the power

supplies, except at integer multiples of the modulator sampling

frequency. The digital ﬁlters also remove noise from the analog

inputs provided the noise source does not saturate the analog

modulator. However, because the resolution of the AD73411’s

ADC is high, and the noise levels from the AD73411 are so low,

care must be taken with regard to grounding and layout.

the analog inputs. Traces on opposite sides of the board should

run at right angles to each other. This will reduce the effects of

feedthrough through the board. A microstrip technique is by far

the best but is not always possible with a double-sided board. In

this technique, the component side of the board is dedicated to

ground planes while signals are placed on the other side.

Good decoupling is important when using high-speed devices.

On the AD73411 both the reference (REFCAP) and supplies

need to be decoupled. It is recommended that the decoupling

capacitors used on both REFCAP and the supplies, be placed as

close as possible to their respective ball connections to ensure

high performance from the device. All analog and digital sup-

plies should be decoupled to AGND and DGND respectively,

with 0.1 µF ceramic capacitors in parallel with 10 µF tantalum

capacitors. The AFE’s digital section supply (DVDD) should be

connected to the digital supply that feeds the DSP’s VDD(Ext)

connections while the AFE’s digital ground DGND should be

returned to the digital ground plane.

The printed circuit board that houses the AD73411 should be

designed so the analog and digital sections are separated and

conﬁned to certain sections of the board. The AD73411 ball-

out conﬁguration offers a major advantage in that its analog

interfaces are conﬁned to the last three rows of the package.

This facilitates the use of ground planes that can be easily sepa-

rated, as shown in Figure 34. A minimum etch technique is

generally best for ground planes as it gives the best shielding.

Digital and analog ground planes should be joined in only one

place. If this connection is close to the device, it is recommended

to use a ferrite bead inductor.

–34–

REV. 0

AD73411

TABLE OF CONTENTS

Topic

Page

Topic

Page

FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1

GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1

SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

POWER CONSUMPTION . . . . . . . . . . . . . . . . . . . . . . . . . 5

TIMING CHARACTERISTICS—AFE SECTION . . . . . . . 5

ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PBGA BALL CONFIGURATIONS . . . . . . . . . . . . . . . . . . . 6

PBGA BALL FUNCTION DESCRIPTIONS . . . . . . . . . . . 7

ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . . 9

Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . 10

Encoder Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Input Configuration Block . . . . . . . . . . . . . . . . . . . . . . . . 10

Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . 10

ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Analog Sigma-Delta Modulator . . . . . . . . . . . . . . . . . . . . 11

Decimation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

ADC Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Decoder Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

DAC Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Interpolation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Analog Smoothing Filter and PGA . . . . . . . . . . . . . . . . . 12

Differential Output Amplifiers . . . . . . . . . . . . . . . . . . . . . 12

Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

AFE Serial Port (SPORT2) . . . . . . . . . . . . . . . . . . . . . . . 12

SPORT2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

SPORT2 Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Master Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Serial Clock Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . 13

Sample Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

DAC Advance Register . . . . . . . . . . . . . . . . . . . . . . . . . . 14

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Resetting the AFE Section of the AD73411 . . . . . . . . . . . 14

Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

AFE Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Program (Control) Mode . . . . . . . . . . . . . . . . . . . . . . . . . 18

Data Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Mixed Program/Data Mode . . . . . . . . . . . . . . . . . . . . . . . 18

Digital Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Sport Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Analog Loop-Back . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

AFE Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Cascade Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

FUNCTIONAL DESCRIPTION—DSP . . . . . . . . . . . . . . 21

Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

DSP SECTION PIN DESCRIPTIONS . . . . . . . . . . . . . . . 22

Memory Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Terminating Unused Pin . . . . . . . . . . . . . . . . . . . . . . . . . 23

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

LOW-POWER OPERATION . . . . . . . . . . . . . . . . . . . . . . . 24

Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Slow Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . 25

Setting Memory Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

MEMORY ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . 26

PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Program Memory (Full Memory Mode) . . . . . . . . . . . . . 26

Program Memory (Host Mode) . . . . . . . . . . . . . . . . . . . . 26

DATA MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Data Memory (Full Memory Mode) . . . . . . . . . . . . . . . . 26

I/O Space (Full Memory Mode) . . . . . . . . . . . . . . . . . . . . 27

Composite Memory Select (CMS) . . . . . . . . . . . . . . . . . . 27

Boot Memory Select (BMS) Disable . . . . . . . . . . . . . . . . 27

Byte Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Byte Memory DMA (BDMA, Full Memory Mode) . . . . . 27

Internal Memory DMA Port (IDMA Port; Host Memory

Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Bootstrap Loading (Booting) . . . . . . . . . . . . . . . . . . . . . . 29

IDMA Port Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Bus Request and Bus Grant (Full Memory Mode) . . . . . . 29

Flag I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

INSTRUCTION SET DESCRIPTION . . . . . . . . . . . . . . . 29

DESIGNING AN EZ-ICE^®-COMPATIBLE SYSTEM . . . 29

Target Board Connector for EZ-ICE Probe . . . . . . . . . . . 30

Target Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . 30

PM, DM, BM, IOM, and CM . . . . . . . . . . . . . . . . . . . . . 30

Target Systems Interface Signals . . . . . . . . . . . . . . . . . . . 30

ANALOG FRONT END (AFE) INTERFACING . . . . . . . 31

DSP SPORT to AFE Interfacing . . . . . . . . . . . . . . . . . . . 31

Cascade Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Interfacing to the AFE’s Analog Inputs and Outputs . . . . 31

Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Interfacing to an Electret Microphone . . . . . . . . . . . . . . . 33

Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Differential-to-Single-Ended Output . . . . . . . . . . . . . . . . 34

Grounding and Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 36

–35–

REV. 0

AD73411

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

119-Ball Plastic Ball Grid Array (PBGA)

B-119

0.300 (7.62) BSC

0.559 (14.20)

BOTTOM

0.543 (13.80)

7

6 5 4 3 2 1

VIEW

A

B

C

D

E

F

A1

G

H

J

K

L

0.050

(1.27)

BSC

0.800

(20.32)

BSC

0.874 (22.20)

0.858 (21.80)

TOP VIEW

M

N

P

R

T

0.033

(0.84)

REF

U

0.050 (1.27)

BSC

0.126 (3.19)

REF

0.037 (0.95)

0.033 (0.85)

DETAIL A

0.028 (0.70)

0.020 (0.50)

0.089 (2.27)

0.073 (1.85)

0.022 (0.56)

REF

0.035 (0.90)

0.024 (0.60)

BALL DIAMETER

SEATING

PLANE

–36–

REV. 0


型号：	AD73411
厂家：	ADI
描述：	Low-Power Analog Front End with DSP Microcomputer DSP与单片机的低功耗模拟前端
文件：	总36页 (文件大小：351K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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