AD73460 [ADI]
Six-Input Channel Analog Front End; 六路输入通道模拟前端
| 型号： | AD73460 |
| 厂家： | 
ADI |
| 描述： | Six-Input Channel Analog Front End |
| 文件： | 总32页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Six-Input Channel
Analog Front End
a
AD73460
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AFE PERFORMANCE
Six 16-Bit A/D Converters
Programmable Input Sample Rate
Simultaneous Sampling
72 dB SNR
64 kS/s Maximum Sample Rate
–80 dB Crosstalk
Low Group Delay (25 s Typ per ADC Channel)
Programmable Input Gain
Single Supply Operation
On-Chip Reference
POWER-DOWN
CONTROL
AD73460
DATA
MEMORY
PROGRAMMABLE
ADDRESS
16K PM
(OPTIONAL (OPTIONAL
8K) 8K)
16K DM
PROGRAM
SEQUENCER
I/O
GENERATORS
AND
FLAGS
FULL MEMORY
MODE
DAG 1 DAG 2
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
EXTERNAL
DATA
BUS
PROGRAM MEMORY DATA
DATA MEMORY DATA
BYTE DMA
CONTROLLER
ARITHMETIC UNITS
ALU MAC SHIFTER
SERIAL PORTS
DSP PERFORMANCE
19 ns Instruction Cycle Time @ 3.3 V, 52 MIPS
Sustained Performance
TIMER
SPORT 0 SPORT 1
ADSP-2100 BASE
ARCHITECTURE
Single-Cycle Instruction Execution
Single-Cycle Context Switch
SERIAL PORT
SPORT 2
REF
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 400 Cycle Recovery from
Power-Down Condition
ANALOG FRONT END
SECTION
Low Power Dissipation in Idle Mode
GENERAL DESCRIPTION
The AD73460’s DSP engine combines the ADSP-2100 family
base architecture (three computational units, data address gen-
erators, and a program sequencer) with two serial ports, a 16-bit
internal DMA port, a byte DMA port, a programmable timer,
Flag I/O, extensive interrupt capabilities, and on-chip program
and data memory.
The AD73460 is a six-input channel analog front-end processor
for general-purpose applications including industrial power meter-
ing or multichannel analog inputs. It features six 16-bit A/D
conversion channels, each of which provides 72 dB signal-to-noise
ratio over a dc-to-2 kHz signal bandwidth. Each channel also
features a programmable input gain amplifier (PGA) with gain
settings in eight stages from 0 dB to 38 dB.
The AD73460-80 integrates 80K bytes of on-chip memory
configured as 16K words (24-bit) of program RAM and 16K
(16-bit) of data RAM. The AD73460-40 integrates 40K bytes
of on-chip memory configured as 8K words (24-bit) of program
RAM and 8K (16-bit) of data RAM. Power-down circuitry is
also provided to meet the low power needs of battery-operated
portable equipment. The AD73460 is available in a 119-ball
PBGA package.
The AD73460 is particularly suitable for industrial power metering
as each channel samples synchronously, ensuring that there is
no (phase) delay between the conversions. The AD73460 also
features low group delay conversions on all channels.
An on-chip reference voltage of 1.25 V is included. The sampling
rate of the device is programmable with separate settings
offering 64 kHz, 32 kHz, 16 kHz, and 8 kHz sampling rates (from
a master clock of 16.384 MHz), while the serial port (SPORT2)
allows easy expansion of the number of input channels by cas-
cading an extra AFE external to the AD73460.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2001
AD73460
TABLE OF CONTENTS
Topic
Page
Topic
Page
FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . 1
GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . 1
SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . 5
ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . 6
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
PBGA BALL CONFIGURATION . . . . . . . . . . . . . . . . . . . . 7
PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 8
ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . 10
ANALOG FRONT END . . . . . . . . . . . . . . . . . . . . . . . . . . 10
FUNCTIONAL DESCRIPTION–AFE . . . . . . . . . . . . . . . 11
Encoder Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Signal Conditioner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Programmable Gain Amplifier . . . . . . . . . . . . . . . . . . . . . 11
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Analog Sigma-Delta Modulator . . . . . . . . . . . . . . . . . . . . 12
Decimation Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
ADC Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
AFE Serial Port (SPORT2) . . . . . . . . . . . . . . . . . . . . . . . 13
SPORT2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SPORT Register Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Master Clock Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Serial Clock Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . 14
Decimation Rate Divider . . . . . . . . . . . . . . . . . . . . . . . . . 14
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Resetting the AFE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Channel Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
INTERFACING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Cascade Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
FUNCTIONAL DESCRIPTION—DSP . . . . . . . . . . . . . . 20
Serial Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
DSP SECTION PIN DESCRIPTIONS . . . . . . . . . . . . . . . 21
Memory Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Terminating Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . 22
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
LOW POWER OPERATION . . . . . . . . . . . . . . . . . . . . . . . 23
Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Slow Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
SYSTEM INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MODES OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . 25
Setting Memory Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Passive Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Active Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
MEMORY ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . 25
PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Program Memory (Full Memory Mode) . . . . . . . . . . . . . 26
Program Memory (Host Mode) . . . . . . . . . . . . . . . . . . . . 26
DATA MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Data Memory (Full Memory Mode) . . . . . . . . . . . . . . . . 26
I/O Space (Full Memory Mode) . . . . . . . . . . . . . . . . . . . . 26
Composite Memory Select (CMS) . . . . . . . . . . . . . . . . . . 26
Boot Memory Select (BMS) Disable . . . . . . . . . . . . . . . . 27
Byte Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Byte Memory DMA (BDMA, Full Memory Mode) . . . . . 27
Internal Memory DMA Port (IDMA Port;
Host Memory Mode) . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Bootstrap Loading (Booting) . . . . . . . . . . . . . . . . . . . . . . 28
IDMA Port Booting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Bus Request and Bus Grant (Full Memory Mode) . . . . . . 28
Flag I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
INSTRUCTION SET DESCRIPTION . . . . . . . . . . . . . . . 29
DESIGNING AN EZ-ICE-COMPATIBLE
SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Target Board Connector for EZ-ICE Probe . . . . . . . . . . . 30
Target Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . 30
PM, DM, BM, IOM, and CM . . . . . . . . . . . . . . . . . . . . . 30
Target System Interface Signals . . . . . . . . . . . . . . . . . . . . 30
ANALOG FRONT END (AFE) INTERFACING . . . . . . . 30
DSP SPORT TO AFE INTERFACING . . . . . . . . . . . . . . 30
CASCADE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . 31
Interfacing to the AFE’s Analog Inputs . . . . . . . . . . . . . . 31
Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 32
–2–
REV. 0
AD73460
(AVDD = 3.0 V to 3.6 V; DVDD = 3.0 V to 3.6 V; DGND = AGND = 0 V, fMCLK = 16.384 MHz, fSCLK = 8.192 MHz,
SPECIFICATIONS fS = 8 kHz; TA = TMIN to TMAX, unless otherwise noted.)
AD73460B
Typ
Parameter
Min
Max
Unit
Test Conditions/Comments1
REFERENCE
REFCAP
Absolute Voltage, VREFCAP
REFCAP TC
1.125
1.25
50
1.375
V
ppm/°C
0.1 µF Capacitor Required from REFCAP
to AGND2
REFOUT
Typical Output Impedance
Absolute Voltage, VREFOUT
Minimum Load Resistance
Maximum Load Capacitance
130
1.25
Ω
1.125
1
1.375
100
V
Unloaded
kΩ
pF
ADC SPECIFICATIONS
Maximum Input Range at VIN2, 3
1.644
–2.85
1.1413
–6.02
V p-p
dBm
V p-p
dBm
Measured Differentially
Measured Differentially
Nominal Reference Level at VIN
(0 dBm0)
Absolute Gain
PGA = 0 dB
–1.2
+0.6
dB
1.0 kHz
Signal to (Noise + Distortion)
PGA = 0 dB
PGA = 0 dB
71
72
dB
dB
0 Hz to 4 kHz; fS = 8 kHz; fIN = 60 Hz
0 Hz to 2 kHz; fS = 8 kHz; fIN = 60 Hz
70
Total Harmonic Distortion
PGA = 0 dB
Intermodulation Distortion
Idle Channel Noise
Crosstalk ADC-to-ADC
–77
–76
–70
–83
–72
dB
dB
dB
dB
PGA = 0 dB
PGA = 0 dB
ADC1 Input at Idle
ADC2 to ADC6 Input Signal: 1.0 kHz
ADC1 Input at Idle
–95
dB
ADC2 to ADC6 Input Signal: 60 Hz
PGA = 0 dB
DC Offset
Power Supply Rejection
–30
+10
–55
+45
mV
dB
Input Signal Level at AVDD and DVDD
Pins 1.0 kHz, 100 mV p-p Sine Wave
64 kHz Output Sample Rate
32 kHz Output Sample Rate
16 kHz Output Sample Rate
8 kHz Output Sample Rate
DMCLK = 16.384 MHz
fIN = 1 kHz
Group Delay4, 5
25
50
95
190
25
0.15
0.01
µs
µs
µs
µs
Input Resistance at VIN2, 4
Phase Mismatch
kΩ6
Degrees
Degrees
fIN = 60 Hz
FREQUENCY RESPONSE
(ADC)7 Typical Output
Frequency (Normalized to fS)
0
0
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
0.03125
0.0625
0.125
0.1875
0.25
0.3125
0.375
0.4375
> 0.5
–0.1
–0.25
–0.6
–1.4
–2.8
–4.5
–7.0
–9.5
< –12.5
–3–
REV. 0
(AVDD = 3.0 V to 3.6 V; DVDD = 3.0 V to 3.6 V; DGND = AGND = 0 V,
AD73460–SPECIFICATIONS fMCLK = 16.384 MHz, fSAMP = 64 kHz; TA = TMIN to TMAX, unless otherwise noted.)
AD73460B
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LOGIC INPUTS
V
INH, Input High Voltage
VDD – 0.8
0
VDD
0.8
10
V
V
µA
pF
VINL, Input Low Voltage
IIH, Input Current
CIN, Input Capacitance
10
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
Three-State Leakage Current
VDD – 0.4
0
–10
VDD
0.4
+10
V
V
µA
|IOUT| ≤ 100 µA
|IOUT| ≤ 100 µA
POWER SUPPLIES
AVDD1, AVDD2
DVDD
3.0
3.0
3.6
3.6
V
V
8
IDD
See Table I
NOTES
1Operating temperature range is as follows: –20°C to +85°C. Therefore, TMIN = –20°C and TMAX = +85°C.
2Test conditions: Input PGA set for 0 dB gain (unless otherwise noted).
3At input to sigma-delta modulator of ADC.
4Guaranteed by design.
5Overall group delay will be affected by the sample rate and the external digital filtering.
6The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (4 × 1011)/DMCLK.
7Frequency response of ADC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB preamplifier
bypassed and input gain of 0 dB.
8Test Conditions: no load on digital inputs, analog inputs ac coupled to ground.
Specifications subject to change without notice.
Table I. AFE Section Current Summary (AVDD = DVDD = 3.3 V)
Total
Current
(Max)
MCLK
ON
Conditions
SE
Comments
REFCAP Only On
REFCAP and
1.0
0
No
REFOUT Disabled
REFOUT Only On
All Sections On
All Sections Off
All Sections Off
4.5
26.5
1.5
0
1
0
0
No
Yes
Yes
No
REFOUT Enabled
MCLK Active Levels Equal to 0 V and DVDD
Digital Inputs Static and Equal to 0 V or DVDD
0.1
The above values are in mA. MCLK = 16.384 MHz; SCLK = 16.384 MHz.
–4–
REV. 0
AD73460
(AVDD = 3.0 V to 3.6 V; DVDD = 3.0 V to 3.6 V; DGND = AGND = 0 V, fMCLK = 16.384 MHz, fSAMP = 64 kHz;
SPECIFICATIONS TA = TMIN to TMAX, unless otherwise noted.)
Parameter
Test Conditions
Min
Typ
Max
Unit
DSP SECTION
VIH Hi-Level Input Voltage1, 2
VIH Hi-Level CLKIN Voltage
VIL Lo-Level Input Voltage1, 3
VOH Hi-Level Output Voltage1, 4, 5
@ VDD = max
@ VDD = max
@ VDD = min
2.0
2.2
V
V
V
V
V
V
µA
µA
µA
µA
0.8
@ VDD = min, IOH = –0.5 mA
@ VDD = min, IOH = –100 µA6
@ VDD = min, IOL = 2 mA
@ VDD = max, VIN = VDD max
@ VDD = max, VIN = 0 V
@ VDD = max, VIN = VDD max8
@ VDD = max, VIN = 0 V8
@ VDD = 3.3 V
2.4
VDD–0.3
VOL Lo-Level Output Voltage1, 4, 5
0.4
10
10
10
10
IIH
IIL
Hi-Level Input Current3
Lo-Level Input Current3
IOZH Three-State Leakage Current7
IOZL Three-State Leakage Current7
IDD Supply Current (Idle)9
t
CK = 19 ns10
tCK = 25 ns10
CK = 30 ns10
14
12
10
mA
mA
mA
t
IDD Supply Current (Dynamic)11
@ VDD = 3.3 V, TAMB = 25°C
tCK = 19 ns10
54
43
37
mA
mA
mA
pF
t
t
CK = 25 ns10
CK = 30 ns10
CI
CO Output Pin Capacitance6, 7, 12, 13
Input Pin Capacitance3, 6, 12
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
@ VIN = 2.5 V, fIN = 1.0 MHz, TAMB = 25°C
8
8
pF
NOTES
1Bidirectional pins: D0–D23, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A1–A13, PF0–PF7.
2Input only pins: RESET, BR, DR0, DR1, PWD.
3Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD.
4Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2–0, BGH.
5Although specified for TTL outputs, all AD73460 outputs are CMOS-compatible and will drive to VDD and GND, assuming no dc loads.
6Guaranteed but not tested.
7Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF0–PF7.
80 V on BR.
9Idle refers to AD73460 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND.
10
11
V
I
= 0 V and 3 V. For typical figures for supply currents, refer to Power Dissipation section.
measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2
IN
DD
and Type 6, and 20% are idle instructions.
12Applies to PBGA package type.
13Output pin capacitance is the capacitive load for any three-stated output pin.
Specifications subject to change without notice.
–5–
REV. 0
AD73460
(AVDD = 3 V to 3.6 V; DVDD = 3 V to 3.6 V; AGND = DGND = 0 V;
TA = TMlN to TMAX, unless otherwise noted.)
TIMING CHARACTERISTICS–AFE SECTION1
Limit at
Parameter
TA = –20؇C to +85؇C
Unit
Description
Clock Signals
t1
t2
t3
See Figure 1
AMCLK Period
AMCLK Width High
AMCLK Width Low
61
24.4
24.4
ns min
ns min
ns min
Serial Port
See Figures 3 and 4
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t1
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns max
ns max
SCLK Period (SCLK = AMCLK)
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from AMCLK
0.4 × t1
0.4 × t1
20
0
10
10
10
10
30
NOTES
1For details of the DSP section timing, please refer to the ADSP-2185L data sheet and the ADSP-2100 Family User’s Manual, Third Edition.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150°C
PBGA, θJA Thermal Impedance . . . . . . . . . . . . . . . . . 25°C/W
Reflow Soldering
Maximum Temperature . . . . . . . . . . . . . . . . . . . . . . 225°C
Time at Maximum Temperature . . . . . . . . . . . . . . . 15 sec
AVDD, DVDD to GND . . . . . . . . . . . . . . . –0.3 V to +4.6 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Digital I/O Voltage to DGND . . . . . –0.3 V to DVDD + 0.3 V
Analog I/O Voltage to AGND . . . . . –0.3 V to AVDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –20°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –20°C to +125°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Options
Model
AD73460BB-80
AD73460BB-40
–20°C to +85°C
–20°C to +85°C
119-Ball Plastic Grid Array
119-Ball Plastic Grid Array
B-119
B-119
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD73460 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
–6–
REV. 0
AD73460
PBGA BALL CONFIGURATIONS
PBGA
Number
Ball
Name
PBGA
Number
Ball
Name
PBGA
Number
Ball
Name
PBGA
Number
Ball
Name
A1
A2
A3
A4
A5
A6
A7
B1
B2
B3
B4
B5
B6
B7
C1
C2
C3
C4
C5
C6
C7
D1
D2
D3
D4
D5
D6
D7
E1
E2
IRQE/PF4
DMS
E3
E4
E5
E6
E7
F1
F2
F3
F4
F5
F6
F7
G1
G2
G3
G4
G5
G6
G7
H1
H2
H3
H4
H5
H6
H7
J1
RFS0
J5
J6
J7
D22
D21
D20
ELOUT
ELIN
EINT
D19
D18
D17
D16
BG
D3/IACK
D5/IAL
D8
D9
D12
D15
EBG
D2/IAD15
D4/IS
D7/IWR
VDD(EXT) T7
D11
D14
BR
D1/IAD14
VDD(INT)
D6/IRD
GND
N7
P1
P2
P3
P4
P5
P6
P7
R1
R2
R3
R4
R5
R6
R7
T1
T2
T3
T4
T5
T6
D13
EBR
A3/IAD2
A2/IAD1
A1/IAD0
A0
DR0
SCLK0
DT1
PWDACK
BGH
Mode A/PF0
Mode B/PF1
TFS1
RFS1
DR1
GND
PWD
VDD(EXT)
Mode C/PF2
SCLK1
ERESET
RESET
PF3
VDD(INT)
CLKIN
A11/IAD10
A7/IAD6
A4/IAD3
IRQL0/PF5
PMS
WR
XTAL
A12/IAD11
A8/IAD7
A5/IAD4
IRQL1/PF6
IOMS
D0/IAD13
DVDD
DGND
ARESET
SCLK2
MCLK
SDO
SDOFS
SDIFS
SDI
K1
K2
K3
K4
K5
K6
K7
L1
L2
L3
L4
L5
L6
L7
M1
M2
M3
M4
M5
M6
M7
N1
N2
N3
N4
N5
N6
SE
REFCAP
REFOUT
VINN2
VINP2
VINN1
VINP1
VINN3
VINP3
VINN4
AGND
AVDD
VINP6
VINN6
VINP5
VINN5
VINP4
RD
VDD(EXT)
A13/IAD12
A9/IAD8
GND
IRQ2/PF7
CMS
BMS
CLKOUT
GND
U1
U2
U3
U4
U5
U6
U7
FL0
FL1
FL2
EMS
EE
ECLK
D23
A10/IAD9
A6/IAD5
DT0
J2
J3
J4
TFS0
D10
PBGA BALL CONFIGURATION
1
2
3
4
5
6
7
A
B
C
D
E
F
A
B
C
D
E
F
G
H
J
G
H
J
K
L
K
L
M
N
P
R
T
M
N
P
R
T
U
U
1
2
3
4
5
6
7
REV. 0
–7–
AD73460
PIN FUNCTION DESCRIPTIONS1
Mnemonic
VINP1
VINN1
VINP2
VINN2
VINP3
VINN3
VINP4
VINN4
VINP5
VINN5
VINP6
VINN6
REFOUT
REFCAP
Function
Analog Input to the Positive Terminal of Input Channel 1.
Analog Input to the Negative Terminal of Input Channel 1.
Analog Input to the Positive Terminal of Input Channel 2.
Analog Input to the Negative Terminal of Input Channel 2.
Analog Input to the Positive Terminal of Input Channel 3.
Analog Input to the Negative Terminal of Input Channel 3.
Analog Input to the Positive Terminal of Input Channel 4.
Analog Input to the Negative Terminal of Input Channel 4.
Analog Input to the Positive Terminal of Input Channel 5.
Analog Input to the Negative Terminal of Input Channel 5.
Analog Input to the Positive Terminal of Input Channel 6.
Analog Input to the Negative Terminal of Input Channel 6.
Buffered Reference Output, which has a nominal value of 1.25 V.
A Bypass Capacitor to AGND2 of 0.1 µF is required for the on-chip reference. The capacitor should be fixed
to this pin. This pin can be overdriven by an external reference if required.
AVDD
AGND
DGND
DVDD
ARESET
Analog Power Supply Connection
Analog Ground/Substrate Connection
Digital Ground/Substrate Connection
Digital Power Supply Connection
Active Low Reset Signal. This input resets the analog front end of the AD73460, resetting the control registers and
clearing the digital circuitry.
SCLK2
Output Serial Clock whose rate determines the serial transfer rate to/from the AFE. It is used to clock data or
control information to and from the serial port (SPORT2). The frequency of SCLK is equal to the frequency
of the master clock (MCLK) divided by an integer number—this integer number being the product of the
external master clock rate divider and the serial clock rate divider.
MCLK
SDO
Master Clock Input of the analog front end. MCLK is driven from an external clock signal.
Serial Data Output of the AD73460. Both data and control information may be output on this pin and are clocked
on the positive edge of SCLK2. SDO is in three-state when no information is being transmitted and when SE is low.
SDOFS
SDIFS
Framing Signal Output for SDO Serial Transfers. The frame sync is one bit wide and it is active one SCLK period
before the first bit (MSB) of each output word. SDOFS is referenced to the positive edge of SCLK2. SDOFS is in
three-state when SE is low.
Framing Signal Input for SDI Serial Transfers. The frame sync is one bit wide and it is valid one SCLK period before
the first bit (MSB) of each input word. SDIFS is sampled on the negative edge of SCLK2 and is ignored when SE
is low.
SDI
SE
Serial Data Input of the AD73460. Both data and control information may be input on this pin and are clocked on
the negative edge of SCLK2. SDI is ignored when SE is low.
SPORT Enable. Asynchronous input enable pin for the SPORT. When SE is set low by the DSP, the output pins
of the SPORT are three-stated and the input pins are ignored. SCLK2 is also disabled internally in order to
decrease power dissipation. When SE is brought high, the control and data registers of the SPORT are
at their original values (before SE was brought low); however, the timing counters and other internal registers are
at their reset values.
RESET
BR
(Input) Processor Reset Input
(Input) Bus Request Input
BG
(Output) Bus Grant Output
BGH
DMS
PMS
IOMS
BMS
CMS
RD
(Output) Bus Grant Hung Output
(Output) Data Memory Select Output
(Output) Program Memory Select Output
(Output) Memory Select Output
(Output) Byte Memory Select Output
(Output) Combined Memory Select Output
(Output) Memory Read Enable Output
–8–
REV. 0
AD73460
PIN FUNCTION DESCRIPTIONS1 (continued)
Mnemonic
Function
WR
(Output) Memory Write Enable Output
IRQ2/
PF7
IRQL0/
PF6
IRQL1/
PF5
IRQE/
PF4
(Input) Edge- or Level-Sensitive Interrupt
(Input/Output) Request.2 Programmable I/O Pin
(Input) Level-Sensitive Interrupt Requests2
(Input/Output) Programmable I/O Pin
(Input) Level-Sensitive Interrupt Requests2
(Input/Output) Programmable I/O Pin
(Input) Edge-Sensitive Interrupt Requests2
(Input/Output) Programmable I/O Pin
Mode D/
PF3
Mode C/
PF2
Mode B/
PF1
Mode A/
PF0
CLKIN,
XTAL
CLKOUT
SPORT0
SPORT1
IRQ1:0
FI
(Input) Mode Select Input—Checked Only During RESET
(Input/Output) Programmable I/O Pin During Normal Operation
(Input) Mode Select Input—Checked Only During RESET
(Input/Output) Programmable I/O Pin During Normal Operation
(Input) Mode Select Input—Checked Only During RESET
(Input/Output) Programmable I/O Pin During Normal Operation
(Input) Mode Select Input—Checked Only During RESET
(Input/Output) Programmable I/O Pin During Normal Operation
(Inputs) Clock or Quartz Crystal Input
(Output) Processor Clock Output
(Inputs/Outputs) Serial Port I/O Pins
(Inputs/Outputs) Serial Port I/O Pins
(Inputs) Edge- or Level-Sensitive Interrupts,
(Input) Flag In3
FO
(Output) Flag Out3
PWD
(Input) Power-Down Control Input
(Output) Power-Down Control Output
(Outputs) Output Flags
PWDACK
FL0, FL1,
FL2
A13 to A0
D23 to D0
VDD and
GND
(Output) Address Output Pins for Program, Data, Byte, and I/O Space
(Input/Output) Data I/O Pins for Program, Data, Byte, and I/O Space
Power and Ground
EZ-ICE Port
ERESET
EMS
(Inputs/Outputs) For Emulation Use
EE
ECLK
ELOUT
ELIN
EINT
EBR
EBG
NOTES
1Refer to the ADSP-2185L data sheet for a detailed description of the DSP pins.
2Interrupt/Flag Pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt
vector address when the pin is asserted, either by external devices, or set as a programmable flag.
3SPORT configuration determined by the DSP System Control Register. Software configurable.
REV. 0
–9–
AD73460
ARCHITECTURE OVERVIEW
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
The AD73460 instruction set provides flexible data moves and
multifunction (one or two data moves with a computation) instruc-
tions. Every instructions can be executed in a single processor
cycle. The AD73460 assembly language uses an algebraic syntax
for ease of coding and readability. A comprehensive set of devel-
opment tools supports program development.
POWER-DOWN
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
CONTROL
AD73460
DATA
MEMORY
PROGRAMMABLE
ADDRESS
16K PM
(OPTIONAL (OPTIONAL
8K) 8K)
16K DM
PROGRAM
SEQUENCER
I/O
GENERATORS
AND
FLAGS
FULL MEMORY
MODE
DAG 1 DAG 2
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
An interface to low-cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
EXTERNAL
DATA
BUS
PROGRAM MEMORY DATA
DATA MEMORY DATA
BYTE DMA
CONTROLLER
ARITHMETIC UNITS
ALU MAC SHIFTER
SERIAL PORTS
TIMER
The AD73460 can respond to eleven interrupts. There can be
up to six external interrupts (one edge-sensitive, two level-sensitive
and three configurable) and seven internal interrupts generated
by the timer, the serial ports (SPORTs), the Byte DMA port
and the power-down circuitry. There is also a master RESET
signal. The two serial ports provide a complete synchronous
serial interface with optional companding in hardware and a
wide variety of framed or frameless data transmit and receive
modes of operation.
SPORT 0 SPORT 1
ADSP-2100 BASE
ARCHITECTURE
SERIAL PORT
SPORT 2
REF
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ANALOG FRONT END
ANALOG FRONT END
SECTION
The analog front end (AFE) of the AD73460 is configured as a
separate block that is normally connected to either SPORT0 or
SPORT1 of the DSP section. As it is not hardwired to either
SPORT users have total flexibility in how they wish to allocate
system resources to support the AFE. It is also possible to
further expand the number of analog input channels connected
to the SPORT by cascading an AD73360 device external to
the AD73460.
Figure 1. Functional Block Diagram
Figure 1 is an overall block diagram of the AD73460. The pro-
cessor section contains three independent computational units:
the ALU, the multiplier/accumulator (MAC) and the shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU performs
a standard set of arithmetic and logic operations; division primi-
tives are also supported. The MAC performs single-cycle multiply,
multiply/add and multiply/subtract operations with 40 bits of
accumulation. The shifter performs logical and arithmetic shifts,
normalization, denormalization, and derive exponent operations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
The AFE is configured as six input channels. It comprises six
independent encoder channels each featuring signal condition-
ing, programmable gain amplifier, sigma-delta A/D convertor
and decimator sections. Each of these sections is described in
further detail below. All channels share a common internal
reference whose nominal value is 1.25 V. Figure 2 shows a block
diagram of the AFE section of the AD73460. It shows six input
channels along with a common reference. Communication to all
channels is handled by the SPORT2 block which interfaces to
either SPORT0 or SPORT1 of the DSP section.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. The sequencer supports conditional jumps,
sub routine calls and returns in a single cycle. With internal
loop counters and loop stacks, the AD73460 executes looped
code with zero overhead; no explicit jump instructions are
required to maintain loops.
–10–
REV. 0
AD73460
AD73460
VINP1
VINN1
ANALOG
⌺-⌬
SIGNAL
0/38dB
PGA
DECIMATOR
DECIMATOR
DECIMATOR
SDI
CONDITIONING
MODULATOR
SDIFS
SCLK2
VINP2
VINN2
ANALOG
⌺-⌬
MODULATOR
SIGNAL
CONDITIONING
0/38dB
PGA
VINP3
VINN3
ANALOG
⌺-⌬
MODULATOR
SIGNAL
CONDITIONING
0/38dB
PGA
ARESET
AMCLK
SE
REFCAP
REFOUT
REFERENCE
SERIAL
I/O
PORT
AFE SECTION
VINP4
VINN4
ANALOG
⌺-⌬
SIGNAL
0/38dB
PGA
DECIMATOR
DECIMATOR
DECIMATOR
CONDITIONING
MODULATOR
VINP5
VINN5
ANALOG
⌺-⌬
MODULATOR
SIGNAL
CONDITIONING
0/38dB
PGA
SDO
SDOFS
VINP6
VINN6
ANALOG
⌺-⌬
MODULATOR
SIGNAL
CONDITIONING
0/38dB
PGA
Figure 2. Functional Block Diagram of Analog Front End
FUNCTIONAL DESCRIPTION—AFE
Table II. PGA Settings for the Encoder Channel
Encoder Channel
IxGS2
IxGS1
IxGS0
Gain (dB)
Each encoder channel consists of a signal conditioner, a switched
capacitor PGA, and a sigma-delta analog-to-digital converter
(ADC). An on-board digital filter, which forms part of the
sigma-delta ADC, also performs critical system-level filtering.
Due to the high level of oversampling, the input antialias require-
ments are reduced such that a simple single pole RC stage is
sufficient to give adequate attenuation in the band of interest.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
6
12
18
20
26
32
38
Signal Conditioner
Each analog channel has an independent signal conditioning
block. This allows the analog input to be configured by the user
depending on whether differential or single-ended mode is used.
ADC
Each channel has its own ADC consisting of an analog sigma-
delta modulator and a digital antialiasing decimation filter. The
sigma-delta modulator noise-shapes the signal and produces
1-bit samples at a DMCLK/8 rate. This bitstream, representing
the analog input signal, is input to the antialiasing decimation
filter. The decimation filter reduces the sample rate and increases
the resolution.
Programmable Gain Amplifier
Each encoder section’s analog front end comprises a Switched
Capacitor PGA that also forms part of the sigma-delta modulator.
The SC sampling frequency is DMCLK/8. The PGA, whose
programmable gain settings are shown in Table II, may be used
to increase the signal level applied to the ADC from low output
sources such as microphones, and can be used to avoid placing
external amplifiers in the circuit. The input signal level to the
sigma-delta modulator should not exceed the maximum input
voltage permitted.
The PGA gain is set by bits IGS0, IGS1, and IGS2 in control
Registers D, E, and F.
REV. 0
–11–
AD73460
Analog Sigma-Delta Modulator
(Sinc-cubed response) with nulls every multiple of DMCLK/256,
which is the decimation filter update rate. The final detail in
Figure 4d shows the application of a final antialias filter in the
DSP engine. This has the advantage of being implemented accord-
ing to the user’s requirements and available MIPS. The filtering
in Figures 4a through 4c is implemented in the AD73460.
The AD73460 input channels employ a sigma-delta conversion
technique, which provides a high resolution 16-bit output with
system filtering being implemented on-chip.
Sigma-delta converters employ a technique known as over-
sampling, where the sampling rate is many times the highest
frequency of interest. In the case of the AD73460, the initial
sampling rate of the sigma-delta modulator is DMCLK/8. The
main effect of oversampling is that the quantization noise is
spread over a very wide bandwidth, up to fS/2 = DMCLK/16
(Figure 3a). This means that the noise in the band of interest is
much reduced. Another complementary feature of sigma-delta
converters is the use of a technique called noise-shaping. This
technique has the effect of pushing the noise from the band of
interest to an out-of-band position (Figure 3b). The combina-
tion of these techniques, followed by the application of a digital
filter, reduces the noise in band sufficiently to ensure good
dynamic performance from the part (Figure 3c).
fSINIT = DMCLK/8
fB = 4kHz
a. Analog Antialias Filter Transfer Function
SIGNAL TRANSFER FUNCTION
NOISE TRANSFER FUNCTION
fSINIT = DMCLK/8
fB = 4kHz
BAND
f
/2
S
OF
DMCLK/16
INTEREST
b. Analog Sigma-Delta Modulator Transfer Function
a.
b.
NOISE-SHAPING
BAND
OF
INTEREST
f
/2
S
DMCLK/16
fSINTER = DMCLK/256
fB = 4kHz
c. Digital Decimator Transfer Function
DIGITAL FILTER
BAND
OF
INTEREST
f
/2
S
DMCLK/16
c.
fSFINAL = 8kHz
fSINTER = DMCLK/256
fB = 4kHz
Figure 3. Sigma-Delta Noise Reduction
d. Final Filter LPF (HPF) Transfer Function
Figure 4 shows the various stages of filtering that are employed
in a typical AD73460 application. In Figure 4a we see the trans-
fer function of the external analog antialias filter. Even though it
is a single RC pole, its cutoff frequency is sufficiently far away
from the initial sampling frequency (DMCLK/8) that it takes
care of any signals that could be aliased by the sampling frequency.
This also shows the major difference between the initial over-
sampling rate and the bandwidth of interest. In Figure 4b, the
signal and noise-shaping responses of the sigma-delta modulator
are shown. The signal response provides further rejection of any
high frequency signals while the noise-shaping will push the inher-
ent quantization noise to an out-of-band position. The detail of
Figure 4c shows the response of the digital decimation filter
Figure 4. DC Frequency Responses
Decimation Filter
The digital filter used in the AD73460 carries out two important
functions. Firstly, it removes the out-of-band quantization noise,
which is shaped by the analog modulator and secondly, it deci-
mates the high frequency bitstream to a lower rate 15-bit word.
The antialiasing decimation filter is a sinc-cubed digital filter
that reduces the sampling rate from DMCLK/8 to DMCLK/256,
and increases the resolution from a single bit to 15 bits. Its Z
transform is given as: [(1–Z–32)/(1–Z–1)]3. This ensures a mini-
mal group delay of 25 µs.
–12–
REV. 0
AD73460
ADC Coding
0.5
0.0
The ADC coding scheme is in two’s complement format (see
Figure 5). The output words are formed by the decimation
filter, which grows the word length from the single-bit output of
the sigma-delta modulator to a 15-bit word, which is the final
output of the ADC block. In 16-bit Data Mode this value is left
shifted with the LSB being set to 0. For input values equal to or
greater than positive full scale however, the output word is set at
0x7FFF, which has the LSB set to 1. In mixed Control/Data
Mode, the resolution is fixed at 15 bits, with the MSB of the
16-bit transfer being used as a flag bit to indicate either control
or data in the frame.
–0.5
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
V
V
+ (V
؋
0.32875) REF
INN
REF
1.00
1.10
1.20
1.30
1.40
1.50
REFCAP – V
ANALOG
INPUT
V
REF
Figure 6. REFCAP Voltage vs. Current
additional external AFE can be cascaded to the internal AFE
(up to a limit of seven) to provide additional input channels
if required.
V
INP
V
– (V
REF
؋
0.32875) REF
10...00
00...00
01...11
In both transmit and receive modes, data is transferred at the
serial clock (SCLK2) rate with the MSB being transferred first.
Communication between the AFE section and DSP section
must always be initiated by the AFE section (AFE is in master
mode, DSP is in slave mode). This ensures that there is no
collision between input data and output samples.
ADC CODE DIFFERENTIAL
V
+ (V
؋
0.6575) REF
REF
V
INN
ANALOG
INPUT
SPORT2 Overview
V
SPORT2 is a flexible, full-duplex, synchronous serial port
whose protocol has been designed to allow an additional AFE to
be connected in cascade to the DSP section. It has a very
flexible architecture that can be configured by programming two
of the internal control registers in each AFE block. SPORT2 has
three distinct modes of operation: Control Mode, Data Mode,
and Mixed Control/Data Mode.
INP
V
– (V
؋
0.6575) REF
REF
10...00
00...00
ADC CODE SINGLE-ENDED
01...11
Figure 5. ADC Transfer Function
Voltage Reference
The AD73460 contains an internal bandgap reference that
provides a low noise, temperature-compensated reference to the
ADCs. The reference has a nominal value of 1.25 V and is avail-
able on the REFCAP pin. A buffered version of the reference is
available on the REFOUT pin and can be used to bias external
analog circuitry if required. The reference output (REFOUT) can
be enabled by setting the RU bit (CRC:6) in Control Register
C. It is possible to overdrive the internal reference by connecting
an external reference to the REFCAP pin. This may be required
when a different value of reference or better temperature coeffi-
cient is required. The current sink and source capabilities of the
REFCAP pin must be taken into consideration when overdriv-
ing the reference. When a lower value of external reference is
required it must have sufficient current sink capability to over-
ride the current source capabilities of the REFCAP pin. When a
higher value of external reference is required it can usually be
connected directly to the REFCAP pin as the pin can typically
only sink 0.25 mA before its value changes. Figure 6 shows a
plot of REFCAP Voltage versus Current. Note that the negative
values indicate that the external reference is sinking current to
provide the required reference voltage.
NOTE: As each AFE has its own SPORT section, the register
settings in each must be programmed. The registers that control
SPORT and sample rate operation (CRA and CRB) must be
programmed with the same values to ensure correct operation.
In Control Mode (CRA:0 = 0), the device’s internal configura-
tion can be programmed by writing to the eight internal control
registers. In this mode, control information can be written to or
read from the AFE. In Data Mode (CRA:0 = 1), any information
that is sent to the AFE is ignored, while the encoder section
(ADC) data is read from the device. In this mode, only ADC
data is read from the device. Mixed mode (CRA:0 = 1 and
CRA:1 = 1) allows the user to send control information and
receive either control information or ADC data. This is achieved
by using the MSB of the 16-bit frame as a flag bit. Mixed mode
reduces the resolution to 15 bits with the MSB being used to
indicate whether the information in the 16-bit frame is control
information or ADC data.
SPORT2 features a single 16-bit serial register that is used for
both input and output data transfers. As the input and output
data must share the same register, some precautions must be
observed. The primary precaution is that no information must
be written to SPORT2 without reference to an output sample
event, which is when the serial register will be overwritten with
the latest ADC sample word. Once SPORT2 starts to output
the latest ADC word, it is safe for the DSP to write new control
AFE Serial Port (SPORT2)
The AFE section communicates with DSP via the bidirectional
synchronous serial port (SPORT2) which interfaces to either
SPORT0 or SPORT1 of the DSP section. SPORT2 is used to
transmit and receive digital data and control information. An
REV. 0
–13–
AD73460
words to the AFE. In certain configurations, data can be written
to the device to coincide with the output sample being shifted
out of the serial register—see section on interfacing devices. The
serial clock rate (CRB:2–3) defines how many 16-bit words
can be written to a device before the next output sample event
will happen.
Master Clock Divider
The AFE features a programmable master clock divider that
allows the user to reduce an externally available master clock, at
pin AMCLK, by one of the ratios 1, 2, 3, 4, or 5 to produce an
internal master clock signal (DMCLK) that is used to calculate
the sampling and serial clock rates. The master clock divider is
programmable by setting CRB:4–6. Table III shows the division
ratio corresponding to the various bit settings. The default divider
ratio is divide-by-one.
The SPORT2 block diagram, shown in Figure 7, details the
blocks associated with AFE including the eight control registers
(A–H), external AMCLK to internal DMCLK divider and serial
clock divider. The divider rates are controlled by the setting of
Control Register B. The AFE features a master clock divider
that allows users the flexibility of dividing externally available
high frequency DSP clocks to generate a lower frequency master
clock internally in the AFE, which may be more suitable for
either serial transfer or sampling rate requirements. The master
clock divider has five divider options (÷1 default condition, ÷2,
÷3, ÷4, ÷5) that are set by loading the master clock divider field
in Register B with the appropriate code (see Table VIII). Once
the internal device master clock (DMCLK) has been set using
the master clock divider, the sample rate and serial clock set-
tings are derived from DMCLK.
Table III. DMCLK (Internal) Rate Divider Settings
MCD2
MCD1
MCD0
DMCLK Rate
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AMCLK
AMCLK/2
AMCLK/3
AMCLK/4
AMCLK/5
AMCLK
AMCLK
AMCLK
Serial Clock Rate Divider
AMCLK
(EXTERNAL)
The AFE features a programmable serial clock divider that allows
users to match the serial clock (SCLK2) rate of the data to that
of the DSP. The maximum SCLK2 rate available is DMCLK
and the other available rates are: DMCLK/2, DMCLK/4 and
DMCLK/8. The slowest rate (DMCLK/8) is the default SCLK2
rate. The serial clock divider is programmable by setting bits
CRB:2–3. Table IV shows the serial clock rate corresponding to
the various bit settings.
DMCLK
(INTERNAL)
MCLK
DIVIDER
SCLK
SCLK2
SE
ARESET
SDIFS
SDI
DIVIDER
SERIAL PORT
(SPORT)
SDOFS
SDO
SERIAL REGISTER
2
3
Table IV. SCLK Rate Divider Settings
8
8
8
8
8
CONTROL
REGISTER
C
CONTROL
REGISTER
E
CONTROL
REGISTER
B
CONTROL
REGISTER
D
CONTROL
REGISTER
A
SCD1
SCD0
SCLK2 Rate
0
0
1
1
0
1
0
1
DMCLK/8
DMCLK/4
DMCLK/2
DMCLK
CONTROL
REGISTER
G
CONTROL
REGISTER
H
CONTROL
REGISTER
F
8
Figure 7. SPORT Block Diagram
Decimation Rate Divider
SPORT2 can work at four different serial clock (SCLK) rates:
chosen from DMCLK, DMCLK/2, DMCLK/4, or DMCLK/8,
where DMCLK is the internal or device master clock resulting
from the external or pin master clock being divided by the mas-
ter clock divider. Care should be taken when selecting Master
Clock, Serial Clock, and Sample Rate divider settings to ensure
that there is sufficient time to read all the data from the AFE
before the next sample interval.
The AFE features a programmable decimation rate divider that
allows users flexibility in matching the AFE’s ADC sample rates
to the needs of the DSP software. The maximum sample rate
available is DMCLK/256 and the other available rates are:
DMCLK/512, DMCLK/1024 and DMCLK/2048. The slowest
rate (DMCLK/2048) is the default sample rate. The sample rate
divider is programmable by setting bits CRB:0–1. Table V shows
the sample rate corresponding to the various bit settings.
SPORT Register Maps
There are eight control registers for the AFE, each eight bits
wide. Table VI shows the control register map for the AFE.
The first two control registers, CRA and CRB, are reserved for
controlling SPORT2. They hold settings for parameters such as
bit rate, internal master clock rate, and device count. If multiple
AFEs are cascaded, registers CRA and CRB on both devices
must be programmed with the same setting to ensure correct
operation. The other six registers, CRC through CRH, are used
to hold control settings for the Reference, Power Control, ADC
channel, and PGA sections of the device. It is not necessary that
the contents of CRC through CRH on each AFE are similar.
Control registers are written to on the negative edge of SCLK2.
Table V. Decimation Rate Divider Settings
DR1
DR0
Sample Rate
0
0
1
1
0
1
0
1
DMCLK/2048
DMCLK/1024
DMCLK/512
DMCLK/256
–14–
REV. 0
AD73460
Table VI. Control Register Map
Address (Binary)
Name
Description
Type
Width
Reset Setting (Hex)
000
001
010
011
100
101
110
111
CRA
CRB
CRC
CRD
CRE
CRF
CRG
CRH
Control Register A
Control Register B
Control Register C
Control Register D
Control Register E
Control Register F
Control Register G
Control Register H
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
8
8
8
8
8
8
8
8
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Table VII. Control Word Description
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R/W
DEVICE ADDRESS
REGISTER ADDRESS
REGISTER DATA
C/D
Control
Frame
Description
Bit 15
CONTROL/DATA
When set high, it signifies a control word in Program or Mixed Program/Data Modes. When
set low, it signifies an invalid control word in Program Mode.
Bit 14
READ/WRITE
When set low, it tells the device that the data field is to be written to the register selected by
the register field setting provided the address field is zero. When set high, it tells the device
that the selected register is to be written to the data field in the serial register and that
the new control word is to be output from the device via the serial output.
Bits 13–11 DEVICE ADDRESS
This 3-bit field holds the address information. Only when this field is zero is a device se-
lected. If the address is not zero, it is decremented and the control word is passed out of the
device via the serial output.
Bits 10–8
Bits 7–0
REGISTER ADDRESS This 3-bit field is used to select one of the eight control registers on the AD73460.
REGISTER DATA
This 8-bit field holds the data that is to be written to or read from the selected register pro-
vided the address field is zero.
Table VIII. Control Register A Description
CONTROL REGISTER A
7
6
5
4
3
2
1
0
RESET DC2
DC1
DC0
SLB
RES
MM
DATA/PGM
Bit
Name
Description
0
1
2
3
4
5
6
7
DATA/PGM
MM
Reserved
SLB
DC0
DC1
DC2
RESET
Operating Mode (0 = Program; 1 = Data Mode)
Mixed Mode (0 = OFF; 1 = Enabled)
Must Be Programmed to Zero (0)
SPORT Loop-Back Mode (0 = OFF; 1 = Enabled)
Device Count (Bit 0)
Device Count (Bit 1)
Device Count (Bit 2)
Software Reset (0 = OFF; 1 = Initiates Reset)
REV. 0
–15–
AD73460
Table IX. Control Register B Description
CONTROL REGISTER B
7
6
5
4
3
2
1
0
CEE
MCD2 MCD1 MCD0 SCD1
SCD0
DR1
DR0
Bit
Name
Description
0
1
2
3
4
5
6
7
DR0
DR1
Decimation Rate (Bit 0)
Decimation Rate (Bit 1)
Serial Clock Divider (Bit 0)
Serial Clock Divider (Bit 1)
Master Clock Divider (Bit 0)
Master Clock Divider (Bit 1)
Master Clock Divider (Bit 2)
SCD0
SCD1
MCD0
MCD1
MCD2
CEE
Control Echo Enable (0 = OFF; 1 = Enabled)
Table X. Control Register C Description
CONTROL REGISTER C
7
6
5
4
3
2
1
0
RES
RU
PUREF
RES
RES
RES
RES
GPU
Bit
Name
Description
0
1
2
3
4
5
6
7
GPU
Global Power-Up Device (0 = Power Down; 1 = Power Up)
Must Be Programmed to Zero (0)
Must Be Programmed to Zero (0)
Must Be Programmed to Zero (0)
Must Be Programmed to Zero (0)
REF Power (0 = Power Down; 1 = Power Up)
REFOUT Use (0 = Disable REFOUT; 1 = Enable REFOUT)
Must Be Programmed to Zero (0)
Reserved
Reserved
Reserved
Reserved
PUREF
RU
Reserved
Table XI. Control Register D Description
CONTROL REGISTER D
7
6
5
4
3
2
1
0
PUI2
I2GS2 I2GS1 I2GS0
PUI1
I1GS2 I1GS1 I1GS0
Bit
Name
Description
0
1
2
3
4
5
6
7
I1GS0
I1GS1
I1GS2
PUI1
I2GS0
I2GS1
I2GS2
PUI2
ADC1: Input Gain Select (Bit 0)
ADC1: Input Gain Select (Bit 1)
ADC1: Input Gain Select (Bit 2)
Power Control (ADC1): 1 = ON, 0 = OFF
ADC2: Input Gain Select (Bit 0)
ADC2: Input Gain Select (Bit 1)
ADC2: Input Gain Select (Bit 2)
Power Control (ADC2): 1 = ON, 0 = OFF
–16–
REV. 0
AD73460
Table XII. Control Register E Description
CONTROL REGISTER E
7
6
5
4
3
2
1
0
PUI4
I4GS2 I4GS1 I4GS0
PUI3
I3GS2 I3GS1 I3GS0
Bit
Name
Description
0
1
2
3
4
5
6
7
I3GS0
I3GS1
I3GS2
PUI3
I4GS0
I4GS1
I4GS2
PUI4
ADC3: Input Gain Select (Bit 0)
ADC3: Input Gain Select (Bit 1)
ADC3: Input Gain Select (Bit 2)
Power Control (ADC3): 1 = ON, 0 = OFF
ADC4: Input Gain Select (Bit 0)
ADC4: Input Gain Select (Bit 1)
ADC4: Input Gain Select (Bit 2)
Power Control (ADC4): 1 = ON, 0 = OFF
Table XIII. Control Register F Description
CONTROL REGISTER F
7
6
5
4
3
2
1
0
PUI6
I6GS2 I6GS1 I6GS0
PUI5
I5GS2 I5GS1 I5GS0
Bit
Name
Description
0
1
2
3
4
5
6
7
I5GS0
I5GS1
I5GS2
PUI5
I6GS0
I6GS1
I6GS2
PUI6
ADC5: Input Gain Select (Bit 0)
ADC5: Input Gain Select (Bit 1)
ADC5: Input Gain Select (Bit 2)
Power Control (ADC5): 1 = ON, 0 = OFF
ADC6: Input Gain Select (Bit 0)
ADC6: Input Gain Select (Bit 1)
ADC6: Input Gain Select (Bit 2)
Power Control (ADC6): 1 = ON, 0 = OFF
Table XIV. Control Register G Description
CONTROL REGISTER G
7
6
5
4
3
2
1
0
SEEN RMOD
CH6
CH5
CH4
CH3
CH2
CH1
Bit
Name
Description
0
1
2
3
4
5
6
7
CH1
CH2
CH3
CH4
CH5
CH6
RMOD
SEEN
Channel 1 Select
Channel 2 Select
Channel 3 Select
Channel 4 Select
Channel 5 Select
Channel 6 Select
Reset Analog Modulator
Enable Single-Ended Input Mode
REV. 0
–17–
AD73460
Table XV. Control Register H Description
CONTROL REGISTER H
7
6
5
4
3
2
1
0
INV
TME
CH6
CH5
CH4
CH3
CH2
CH1
Bit
Name
Description
0
1
2
3
4
5
6
7
CH1
CH2
CH3
CH4
CH5
CH6
TME
INV
Channel 1 Select
Channel 2 Select
Channel 3 Select
Channel 4 Select
Channel 5 Select
Channel 6 Select
Test Mode Enable
Enable Invert Channel Mode
OPERATION
Resetting the AFE
Operating Modes
Three operating modes are available on the AFE. They are
Control (Program) Mode, Data Mode, and Mixed Control/
Data Mode. The device configuration—register settings—can be
changed only in Program and Mixed Program/Data Modes. In
all modes, transfers of information to or from the device occur
in 16-bit packets, therefore the DSP engine’s SPORT will be
programmed for 16-bit transfers.
The ARESET pin resets all the control registers. All the AFE
registers are reset to zero, indicating that the default SCLK2
rate (DMCLK/8) and sample rate (DMCLK/2048) are at a mini-
mum. As well as resetting the control registers of the AFE using
the ARESET pin, the device can be reset using the RESET bit
(CRA:7) in Control Register A. Both hardware and software
resets require four DMCLK cycles. On reset, DATA/PGM
(CRA:0) is set to 0 (default condition) thus enabling Control
Mode. The reset conditions ensure that the device must be
programmed to the correct settings after power-up or reset.
Following a reset, the SDOFS will be asserted approximately
2070 master (AMCLK) cycles after ARESET goes high. The
data that is output following the reset and during Control Mode
is random and contains no valid information until either data or
mixed mode is set.
Control Mode
In Control Mode, CRA:0 = 0, the user writes to the control
registers to set up the device for desired operation—SPORT2
operation, cascade length, power management, input/output gain,
etc. In this mode, the 16-bit information packet sent to the device
by the DSP is interpreted as a control word whose format is shown
in Table VII. In this mode, the user m=ust address the device to
be programmed using the address field of the control word. This
field is read by the device and if it is zero (000 bin), the device
recognizes the word as being addressed to it. If the address field is
not zero, it is then decremented and the control word is passed
out of the device—either to the next device in a cascade or back to
the DSP. This 3-bit address format allows the user to uniquely
address any device in a cascade. If the AFE is used in a standalone
configuration connected to the DSP, the device address corre-
sponds to 0.
Power Management
The individual functional blocks of the AFE can be enabled
separately by programming the power control register CRC.
(The Power Management functions of the DSP section are
separate and will be referred to later.) It allows certain sections
to be powered down if not required, which adds to the device’s
flexibility in that the user need not incur the penalty of having to
provide power for a certain section if it is not necessary to their
design. The power control registers provide individual control
settings for the major functional blocks on each analog front end
unit and also a global override that allows all sections to be
powered up/down by setting/clearing the bit. Using this method
the user could, for example, individually enable a certain section,
such as the reference (CRC:5), and disable all others. The glo-
bal power-up (CRC:0) can be used to enable all sections, but if
power-down is required using the global control, the reference
will still be enabled; in this case, because its individual bit is set.
Refer to Table X for details of the settings of CRC. CRD–CRF
can be used to control the power status of individual channels
allowing multiple channels to be powered down if required.
Following reset, when the SE pin is enabled, the AFE responds
by raising the SDOFS pin to indicate that an output sample
event has occurred. Control words can be written to the device
to coincide with the data being sent out of SPORT2, as shown in
Figure 9 (Directly Coupled), or they can lag the output words
by a time interval that should not exceed the sample interval
(Indirectly Coupled). Refer to the Digital Interface section for
more information. After reset, output frame sync pulses will
occur at a slower default sample rate, which is DMCLK/2048,
until Control Register B is programmed, after which the SDOFS
will be pulsed at the selected rate. While the AFE is in Control
Mode, the data output by the device is random and should not
be interpreted as ADC data.
–18–
REV. 0
AD73460
Data Mode
the input data to the AFE is forced to be synchronous with the
output data from the AFE. The DSP must be programmed so
that both the Tx and Rx frame syncs are inputs as the AFE’s
SDOFS will be input to both. This configuration guarantees that
input and output events occur simultaneously and is the simplest
configuration for operation in normal Data Mode. Note that when
programming the AFE in this configuration it is advisable to
preload the transmit register with the first control word to be sent
before the AFE is taken out of reset. This ensures that this word
will be transmitted to coincide with the first output word from the
device(s).
Once the device has been configured by programming the cor-
rect settings to the various control registers, the device may exit
Program Mode and enter Data Mode. This is done by program-
ming the DATA/PGM (CRA:0) bit to 1 and MM (CRA:1) to 0.
Once the device is in Data Mode, the input data is ignored.
When the device is in normal Data Mode (i.e., mixed mode
disabled), it must receive a hardware reset to reprogram any of
the control register settings.
Mixed Program/Data Mode
This mode allows the user to send control words to the device
while receiving ADC words. This permits adaptive control of
the device whereby control of the input gains can be affected by
reprogramming the control registers. The standard data frame
remains 16 bits, but now the MSB is used as a flag bit to indi-
cate that the remaining 15 bits of the frame represent control
information. Mixed mode is enabled by setting the MM bit
(CRA:1) to 1 and the DATA/PGM bit (CRA:0) to 1. In the case
where control setting changes will be required during normal
operation, this mode allows the ability to load control informa-
tion with the slight inconvenience of formatting the data. Note
that the output samples from the ADC will also have the MSB
set to zero to indicate it is a data word.
SDIFS
TFS(0/1)
SDI
DT(0/1)
DSP
SECTION
AFE
SECTION
SCLK
SCLK(0/1)
DR(0/1)
SDO
RFS(0/1)
SOFS
Figure 8. Indirectly Coupled or Nonframe Sync Loop-Back
Configuration
Channel Selection
The ADC channels of the AD73460 can be powered up or down
individually by programming the PUIx bit of registers CRD to
CRF. If the AD73460 is being used in Mixed Data/Control Mode,
individual channels may be powered up or down as the program
requires. In Data Mode, the number of channels selected while the
AD73460 was in Program Mode is fixed and cannot be altered
without resetting and reprogramming the AD73460. In all cases
ADC Channel 1 must be powered up as the frame sync pulse
generated by this channel defines the start of a new sample interval.
SDIFS
SDI
TFS(0/1)
DT(0/1)
AFE
SECTION
DSP
SECTION
SCLK(0/1)
SCLK
DR(0/1)
SDO
RFS(0/1)
SDOFS
INTERFACING
Figure 9. Directly Coupled or Frame Sync Loop-Back
Configuration
The AFE section SPORT (SPORT2) can be interfaced to either
SPORT0 or SPORT1 of the DSP section. Both serial input and
output data use an accompanying frame synchronization signal
that is active high one clock cycle before the start of the 16-bit
word or during the last bit of the previous word if transmission
is continuous. The serial clock (SCLK) is an output from the
AFE and is used to define the serial transfer rate to the DSP’s
Tx and Rx ports. Two primary configurations can be used: the
first is shown in Figure 8 where the DSP’s Tx data, Tx frame
sync, Rx data and Rx frame sync are connected to the AD73460’s
SDI, SDIFS, SDO, and SDOFS, respectively. This configuration,
referred to as indirectly coupled or nonframe sync loop-back,
has the effect of decoupling the transmission of input data from
the receipt of output data. When programming the DSP serial
port for this configuration, it is necessary to set the Rx frame
sync as an input to the DSP and the Tx frame sync as an output
generated by the DSP. This configuration is most useful when
operating in mixed mode, as the DSP has the ability to decide
how many words can be sent to the AFE(s). This means that full
control can be implemented over the device configuration in a
given sample interval. The second configuration (shown in Figure
9) has the DSP’s Tx data and Rx data connected to the AFE’s SDI
and SDO, respectively, while the DSP’s Tx and Rx frame syncs
are connected to the AD73460’s SDIFS and SDOFS. In this
configuration, referred to as directly coupled or frame sync
loop-back, the frame sync signals are connected together and
Cascade Operation
The AD73460 has been designed to support cascading of an
external AFE from either SPORT0 or SPORT1. The SPORT2
interface protocol has been designed so that device addressing is
built into the packet of information sent to the device. This allows
the cascade to be formed with no extra hardware overhead for
control signals or addressing. A cascade can be formed in either
of the two modes previously discussed.
There may be some restrictions in cascade operation due to the
number of devices configured in the cascade and the serial clock
rate chosen. The formula below gives an indication of whether
the combination of sample rate, serial clock, and number of
devices can be successfully cascaded. This assumes a directly
coupled frame sync arrangement as shown in Figure 9 and does
not take any interrupt latency into account.
1
fS
6 × [((Device Count − 1) × 16) + 17]
≥
SCLK
When using the indirectly coupled frame sync configuration in
cascaded operation it is necessary to be aware of the restrictions
in sending control word data to all devices in the cascade. The
user should ensure that there is sufficient time for all the control
words to be sent between reading the last ADC sample and the
start of the next sample period.
REV. 0
–19–
AD73460
FUNCTIONAL DESCRIPTION—DSP
In Cascade Mode, both devices must know the number of devices
in the cascade to be able to output data at the correct time.
Control Register A contains a 3-bit field (DC0–2) that is pro-
grammed by the DSP during the programming phase. The
default condition is that the field contains 000b, which is equiva-
lent to a single device in cascade (see Table XVI). However, for
cascade operation this field must contain a binary value that is
one less than the number of devices in the cascade. With a cascade,
each device takes a turn to send an ADC result to the DSP. For
example, in a cascade of two devices the data will be output as
Device 2-Channel 1, Device 1-Channel 1, Device 2-Channel 2,
Device 1-Channel 2 etc. When the first device in the cascade
has transmitted its channel data there is an additional SCLK
period during which the last device asserts its SDOFS as it
begins its transmission of the next channel. This will not cause
a problem for most DSPs as they count clock edges after a
frame sync and hence the extra bit will be ignored.
The AD73460 instruction set provides flexible data moves and
multifunction (one or two data moves with a computation) instruc-
tions. Every instruction can be executed in a single processor cycle.
The AD73460 assembly language uses an algebraic syntax for ease
of coding and readability. A comprehensive set of development
tools supports program development.
Figure 10 is an overall block diagram of the AD73460. The
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC), and the shifter. The
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. The ALU performs
a standard set of arithmetic and logic operations; division primi-
tives are also supported. The MAC performs single-cycle
multiply, multiply/add, and multiply/subtract operations with 40
bits of accumulation. The shifter performs logical and arithmetic
shifts, normalization, denormalization, and derive exponent
operations.
When two devices are connected in cascade there are also
restrictions concerning which ADC channels can be powered
up. In all cases the cascaded devices must all have the same
channels powered up (i.e., for a cascade requiring Channels 1
and 2 on Device 1 and Channel 5 on Device 2, Channels 1, 2,
and 5 must be powered up on both devices to ensure correct
operation).
The shifter can be used to efficiently implement numeric
format control including multiword and block floating-point
representations.
The internal result (R) bus connects the computational units so
that the output of any unit may be the input of any unit on the
next cycle.
Table XVI. Device Count Settings
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these com-
putational units. The sequencer supports conditional jumps,
subroutine calls and returns in a single cycle. With internal loop
counters and loop stacks, the AD73460 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.
DC2
DC1
DC0
Cascade Length
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
3
4
5
6
7
8
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access data
POWER-DOWN
CONTROL
AD73460
DATA
MEMORY
16K PM 16K DM
(OPTIONAL (OPTIONAL
PROGRAMMABLE
ADDRESS
PROGRAM
SEQUENCER
I/O
GENERATORS
AND
FLAGS
FULL MEMORY
8K) 8K)
DAG 1 DAG 2
MODE
EXTERNAL
ADDRESS
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
EXTERNAL
DATA
PROGRAM MEMORY DATA
DATA MEMORY DATA
BUS
BYTE DMA
CONTROLLER
ARITHMETIC UNITS
ALU MAC SHIFTER
SERIAL PORTS
TIMER
SPORT 0 SPORT 1
ADSP-2100 BASE
ARCHITECTURE
SERIAL PORT
SPORT 2
REF
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ANALOG FRONT END
SECTION
Figure 10. Functional Block Diagram
–20–
REV. 0
AD73460
(indirect addressing), it is post-modified by the value of one of
four possible modify registers. A length value may be associated
with each pointer to implement automatic modulo addressing
for circular buffers.
(TSCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (TPERIOD).
Serial Ports
Efficient data transfer is achieved with the use of five internal
buses:
The AD73460 incorporates two complete synchronous serial
ports (SPORT0 and SPORT1) for serial communications and
multiprocessor communication.
•
•
•
•
•
Program Memory Address (PMA) Bus
Program Memory Data (PMD) Bus
Data Memory Address (DMA) Bus
Data Memory Data (DMD) Bus
Result (R) Bus
Here is a brief list of the capabilities of the AD73460 SPORTs.
For additional information on Serial Ports, refer to the ADSP-
2100 Family User’s Manual, Third Edition.
•
•
•
SPORTs are bidirectional and have a separate, double-
buffered transmit and receive section.
The two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
SPORTs can use an external serial clock or generate their
own serial clock internally.
SPORTs have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulsewidths and timings.
Program memory can store both instructions and data, permit-
ting the AD73460 to fetch two operands in a single cycle, one
from program memory and one from data memory. The AD73460
can fetch an operand from program memory and the next
instruction in the same cycle.
•
SPORTs support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCITT recommendation G.711.
In lieu of the address and data bus for external memory connec-
tion, the AD73460 may be configured for 16-bit Internal DMA
port (IDMA port) connection to external systems. The IDMA
port is made up of 16 data/address pins and five control pins.
The IDMA port provides transparent, direct access to the DSPs
on-chip program and data RAM.
•
•
SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
SPORTs can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An inter-
rupt is generated after a data buffer transfer.
An interface to low-cost byte-wide memory is provided by the
Byte DMA port (BDMA port). The BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
•
•
SPORT0 has a multichannel interface to selectively receive
and transmit a 24- or 32-word, time-division multiplexed,
serial bitstream.
The byte memory and I/O memory space interface supports slow
memories and I/O memory-mapped peripherals with program-
mable wait state generation. External devices can gain control of
external buses with bus request/grant signals (BR, BGH, and
BG). One execution mode (Go Mode) allows the AD73460 to
continue running from on-chip memory. Normal execution
mode requires the processor to halt while buses are granted.
SPORT1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. The
internally generated serial clock may still be used in this
configuration.
DSP SECTION PIN DESCRIPTIONS
The AD73460 is available in a 119-ball PBGA package. In order
to maintain maximum functionality and reduce package size and
pin count, some serial port, programmable flag, interrupt, and
external bus pins have dual, multiplexed functionality. The
external bus pins are configured during RESET only, while
serial port pins are software configurable during program execu-
tion. Flag and interrupt functionality is retained concurrently on
multiplexed pins. In cases where pin functionality is reconfigurable,
the default state is shown in plain text; alternate functionality is
shown in italics. See Pin Function Descriptions.
The AD73460 can respond to eleven interrupts. There can be
up to six external interrupts (one edge-sensitive, two level-
sensitive and three configurable) and seven internal interrupts
generated by the timer, the serial ports (SPORTs), the Byte
DMA port and the power-down circuitry. There is also a master
RESET signal. The two serial ports provide a complete synchro-
nous serial interface with optional companding in hardware and
a wide variety of framed or frameless data transmit and receive
modes of operation.
Memory Interface Pins
Each port can generate an internal programmable serial clock or
accept an external serial clock.
The AD73460 processor can be used in one of two modes, Full
Memory Mode, which allows BDMA operation with full exter-
nal overlay memory and I/O capability, or Host Mode, which
allows IDMA operation with limited external addressing capa-
bilities. The operating mode is determined by the state of the
Mode C pin during RESET and cannot be changed while the
processor is running. See tables for Full Memory Mode Pins
and Host Mode Pins for descriptions.
The AD73460 provides up to 13 general-purpose flag pins. The
data input and output pins on SPORT1 can be alternatively
configured as an input flag and an output flag. In addition, there
are eight flags that are programmable as inputs or outputs and
three flags that are always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (TCOUNT) is decremented every n pro-
cessor cycle, where n is a scaling value stored in an 8-bit register
REV. 0
–21–
AD73460
Full Memory Mode Pins (Mode C = 0)
Pin Terminations (continued)
I/O
Pin
# of Input/
Hi-Z*
Caused
By
Pin
Three-
Reset
Unused
Configuration
Name(s) Pins Output Function
Name
State (Z) State
A13:0
D23:0
14
24
O
Address Output Pins for Program,
Data, Byte and I/O Spaces
Data I/O Pins for Program, Data,
Byte and I/O Spaces (8 MSBs are
also used as Byte Memory addresses)
WR
BR
O (Z)
I
O
I
BR, EBR Float
High (Inactive)
Float
I/O
BG
BGH
IRQ2/PF7
O (Z)
O
I/O (Z)
O
O
I
EE
Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High (Inactive)
or Program as Output,
Set to 1, Let Float
Input = High or Low,
Output = Float
High or Low
High or Low
High or Low
Float
Input = High or Low,
Output = Float
High or Low
High or Low
High or Low
Host Mode Pins (Mode C = 1)
IRQL1/PF6 I/O (Z)
IRQL0/PF5 I/O (Z)
I
I
I
I
Pin
# of Input/
Name(s) Pins Output Function
IAD15:0 16
I/O
O
IDMA Port Address/Data Bus
Address Pin for External I/O, Pro-
gram, Data or Byte access
A0
1
IRQE/PF4
I/O (Z)
I/O
D23:8
16
I/O
Data I/O Pins for Program, Data
Byte and I/O spaces
SCLK0
IWR
IRD
IAL
IS
1
1
1
1
1
I
I
I
I
IDMA Write Enable
IDMA Read Enable
IDMA Address Latch Pin
IDMA Select
IDMA Port Acknowledge Configur-
able in Mode D; Open Source
RFS0
DR0
I/O
I
I
I
O
O
I
TFS0
DT0
I/O
O
IACK
O
SCLK1
I/O
NOTE
RFS1/IRQ0 I/O
DR1/FL1
TFS1/IRQ1 I/O
I
I
O
O
I
In Host Mode, external peripheral addresses can be decoded using the A0, CMS,
PMS, DMS, and IOMS signals
I
Terminating Unused Pin
The following table shows the recommendations for terminating
unused pins.
DT1/FO
EE
O
I
Float
EBR
I
I
EBG
ERESET
EMS
EINT
ECLK
ELIN
ELOUT
O
I
O
I
I
I
O
I
O
I
I
I
Pin Terminations
I/O
Hi-Z*
Caused
By
Pin
Three-
Reset
Unused
Configuration
Name
State (Z) State
XTAL
CLKOUT
A13:1 or
IAD12:0
A0
D23:8
D7 or
IWR
I
O
I
O
Float
Float
O
O
NOTES
*Hi-Z = High Impedance.
1. If the CLKOUT pin is not used, turn it OFF.
O (Z)
I/O (Z)
O (Z)
I/O (Z)
I/O (Z)
I
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
I
Hi-Z
I
Hi-Z
BR, EBR Float
IS Float
BR, EBR Float
BR, EBR Float
BR, EBR Float
2. If the Interrupt/Programmable Flag pins are not used, there are two options:
Option 1: When these pins are configured as INPUTS at reset and function as
interrupts and input flag pins, pull the pins High (inactive).
Option 2: Program the unused pins as OUTPUTS, set them to 1, and let
them float.
3. All bidirectional pins have three-stated outputs. When the pins is configured
as an output, the output is Hi-Z (high impedance) when inactive.
4. CLKIN, RESET, and PF3:0 are not included in the table because these pins
must be used.
High (Inactive)
D6 or
IRD
I/O (Z)
I
BR, EBR Float
BR, EBR High (Inactive)
Float
Low (Inactive)
BR, EBR Float
High (Inactive)
BR, EBR Float
Float
D5 or
I/O (Z)
IAL
D4 or
IS
I
I
I/O (Z)
I
Hi-Z
I
Hi-Z
D3 or
IACK
D2:0 or
IAD15:13
PMS
DMS
BMS
IOMS
CMS
I/O (Z)
I/O (Z)
I/O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
O (Z)
Hi-Z
Hi-Z
O
O
O
O
O
O
BR, EBR Float
IS
Float
BR, EBR Float
BR, EBR Float
BR, EBR Float
BR, EBR Float
BR, EBR Float
BR, EBR Float
RD
–22–
REV. 0
AD73460
Interrupts
LOW POWER OPERATION
The interrupt controller allows the processor to respond to the
eleven possible interrupts and RESET with minimum overhead.
The AD73460 provides four dedicated external interrupt
input pins, IRQ2, IRQL0, IRQL1, and IRQE. In addition,
SPORT1 may be reconfigured for IRQ0, IRQ1, FLAG_IN,
and FLAG_OUT, for a total of six external interrupts. The
AD73460 also supports internal interrupts from the timer, the
byte DMA port, the two serial ports, software and the power-down
control circuit. The interrupt levels are internally prioritized
and individually maskable (except power down and reset). The
IRQ2, IRQ0, and IRQ1 input pins can be programmed to be
either level- or edge-sensitive. IRQL0 and IRQL1 are level-
sensitive and IRQE is edge-sensitive. The priorities and vector
addresses of all interrupts are shown in Table XVII.
The AD73460 has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. These modes are:
•
•
•
Power-Down
Idle
Slow Idle
The CLKOUT pin may also be disabled to reduce external
power dissipation.
Power-Down
The AD73460 processor has a low power feature that lets the
processor enter a very low power dormant state through hard-
ware or software control. Following is a brief list of power-down
features. Refer to the ADSP-2100 Family User’s Manual, Third
Edition, “System Interface” chapter, for detailed information
about the power-down feature.
Table XVII. Interrupt Priority and Interrupt Vector Addresses
Interrupt Vector
•
Quick recovery from power-down. The processor begins
executing instructions in as few as 400 CLKIN cycles.
Source of Interrupt
Address (Hex)
•
Support for an externally generated TTL or CMOS processor
clock. The external clock can continue running during power-
down without affecting the 400 CLKIN cycle recovery.
RESET (or Power-Up with PUCR = 1) 0000 (Highest Priority)
Power-Down (Nonmaskable)
IRQ2
002C
0004
•
•
Support for crystal operation includes disabling the oscillator
to save power (the processor automatically waits 4096 CLKIN
cycles for the crystal oscillator to start and stabilize), and
letting the oscillator run to allow 400 CLKIN cycle start up.
IRQL1
0008
IRQL0
000C
SPORT0 Transmit
SPORT0 Receive
IRQE
0010
0014
0018
Power-down is initiated by either the power-down pin (PWD)
or the software power-down force bit. Interrupt support allows
an unlimited number of instructions to be executed before
optionally powering down. The power-down interrupt can
also be used as a nonmaskable, edge-sensitive interrupt.
BDMA Interrupt
SPORT1 Transmit or IRQ1
SPORT1 Receive or IRQ0
Timer
001C
0020
0024
0028 (Lowest Priority)
•
Context clear/save control allows the processor to continue
where it left off or start with a clean context when leaving the
power-down state.
Interrupt routines can either be nested with higher priority
interrupts taking precedence or processed sequentially. Inter-
rupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. The power-down interrupt is nonmaskable.
•
•
The RESET pin can also be used to terminate power-down.
Power-down acknowledge pin indicates when the processor
has entered power-down.
The AD73460 masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. This does not affect serial port autobuffering
or DMA transfers.
Idle
When the AD73460 is in the Idle Mode, the processor waits
indefinitely in a low power state until an interrupt occurs. When
an unmasked interrupt occurs, it is serviced; execution then con-
tinues with the instruction following the IDLE instruction. In
Idle Mode IDMA, BDMA, and autobuffer cycle steals still occur.
The interrupt control register, ICNTL, controls interrupt nest-
ing and defines the IRQ0, IRQ1, and IRQ2 external interrupts
to be either edge- or level-sensitive. The IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. The
IRQL0 and IRQL1 pins are external level-sensitive interrupts.
Slow Idle
The IDLE instruction on the AD73460 slows the processor’s
internal clock signal, further reducing power consumption. The
reduced clock frequency, a programmable fraction of the normal
clock rate, is specified by a selectable divisor given in the IDLE
instruction. The format of the instruction is
The IFC register is a write-only register used to force and clear
interrupts. On-chip stacks preserve the processor status and are
automatically maintained during interrupt handling. The stacks
are twelve levels deep to allow interrupt, loop and subroutine
nesting. The following instructions allow global enable or disable
servicing of the interrupts (including power-down), regardless of
the state of IMASK. Disabling the interrupts does not affect
serial port autobuffering or DMA.
IDLE (n);
where n = 16, 32, 64, or 128. This instruction keeps the proces-
sor fully functional, but operating at the slower clock rate. While
it is in this state, the processor’s other internal clock signals,
such as SCLK, CLKOUT, and timer clock, are reduced by the
same ratio. The default form of the instruction, when no clock
divisor is given, is the standard IDLE instruction.
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
REV. 0
–23–
AD73460
When the IDLE (n) instruction is used, it effectively slows
down the processor’s internal clock and thus its response time to
incoming interrupts. The one-cycle response time of the stan-
dard idle state is increased by n, the clock divisor. When an
enabled interrupt is received, the AD73460 will remain in the
idle state for up to a maximum of n processor cycles (n = 16,
32, 64, or 128) before resuming normal operation.
FULL MEMORY MODE
AD73460
14
24
A
13–0
1/2x CLOCK
OR
CLKIN
XTAL
ADDR13–0
D
A0-A21
23–16
CRYSTAL
BYTE
D
15–8
MEMORY
FL0–2
PF3
DATA
DATA23–0
CS
BMS
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
A
10–0
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
rate faster than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
ADDR
WR
RD
I/O SPACE
(PERIPHERALS)
D
23–8
MODE C/PF2
MODE B/PF1
MODE A/PF0
DATA
2048
LOCATIONS
IOMS
CS
A
13–0
SPORT1
SCLK1
ADDR OVERLAY
MEMORY
DATA
D
AFE*
SECTION
OR
SERIAL
DEVICE
23–0
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
TWO 8K
PMS
DMS
CMS
PM SEGMENTS
TWO 8K
DM SEGMENTS
SYSTEM INTERFACE
SPORT0
BR
BG
BGH
SCLK0
RFS0
TFS0
DT0
AFE*
SECTION
OR
Figure 11 shows a typical basic system configuration with the
AD73460, two serial devices, a byte-wide EPROM, and
optional external program and data overlay memories (mode
selectable). Programmable wait state generation allows the pro-
cessor to easily connect to slow peripheral devices. The AD73460
also provides four external interrupts and two serial ports or six
external interrupts and one serial port. Host Memory Mode
allows access to the full external data bus, but limits addressing
to a single address bit (A0) Additional system peripherals can be
added in this mode through the use of external hardware to
generate and latch address signals.
SERIAL
DEVICE
DR0
PWD
PWDACK
HOST MEMORY MODE
AD73460
1
1/2x CLOCK
OR
CRYSTAL
CLKIN
A0
16
XTAL
DATA23–8
FL0–2
PF3
BMS
IRQ2/PF7
IRQE/PF4
IRQL0/PF5
IRQL1/PF6
Clock Signals
MODE C/PF2
MODE B/PF1
MODE A/PF0
WR
RD
The AD73460 can be clocked by either a crystal or a TTL-
compatible clock signal.
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
IOMS
The CLKIN input cannot be halted, changed during operation,
or operated below the specified frequency during normal operation.
The only exception is while the processor is in the power-
down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual, Third Edition, for detailed
information on this power-down feature.
AFE*
SECTION
OR
PMS
DMS
CMS
SERIAL
DEVICE
SPORT0
BR
BG
BGH
SCLK0
RFS0
TFS0
DT0
AFE*
SECTION
OR
SERIAL
DEVICE
If an external clock is used, it should be a TTL-compatible
signal running at half the instruction rate. The signal is con-
nected to the processor’s CLKIN input. When an external clock
is used, the XTAL input must be left unconnected.
DR0
PWD
PWDACK
IDMA PORT
IRD/D6
IWR/D7
IS/D4
IAL/D5
IACK/D3
SYSTEM
INTERFACE
OR
*AFE SECTION CAN BE
CONNECTED TO EITHER
SPORT0 OR SPORT1
The AD73460 uses an input clock with a frequency equal to
half the instruction rate; a 26.00 MHz input clock yields a 19 ns
processor cycle (which is equivalent to 52 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
CONTROLLER
16
IAD15–0
Figure 11. Basic System Configuration
Because the AD73460 includes an on-chip oscillator circuit, an
external crystal may be used. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors connected
as shown in Figure 12. Capacitor values are dependent on crystal
type and should be specified by the crystal manufacturer. A
parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used.
XTAL
CLKIN
CLKOUT
Figure 12. External Crystal Connections
A clock output (CLKOUT) signal is generated by the processor
at the processor’s cycle rate. This can be enabled and disabled
by the CLK0DIS bit in the SPORT0 Autobuffer Control Register.
–24–
REV. 0
AD73460
Table XVIII. Modes of Operation1
MODE C2 MODE B3 MODE A4 Booting Method
0
0
1
0
0
0
0
0
1
BDMA feature is used to load the first 32 program memory words from the byte
memory space. Program execution is held off until all 32 words have been loaded.
Chip is configured in Full Memory Mode.5
No automatic boot operations occur. Program execution starts at external memory
location 0. Chip is configured in Full Memory Mode. BDMA can still be used, but
the processor does not automatically use or wait for these operations.
BDMA feature is used to load the first 32 program memory words from the byte
memory space. Program execution is held off until all 32 words have been loaded.
Chip is configured in Host Mode. (REQUIRES ADDITIONAL HARDWARE.)
IDMA feature is used to load any internal memory as desired. Program execution is
held off until internal program memory location 0 is written to. Chip is configured in
Host Mode.5
0
1
1
NOTES
1All mode pins are recognized while RESET is active (low).
2When Mode C = 0, Full Memory enabled. When Mode C = 1, Host Memory Mode enabled.
3When Mode B = 0, Auto Booting enabled. When Mode B = 1, no Auto Booting.
4When Mode A = 0, BDMA enabled. When Mode A = 1, IDMA enabled.
5Considered as standard operating settings. Using these configurations allows for easier design and better memory management.
RESET
Passive Configuration involves the use a pull-up or pull-down
resistor connected to the Mode C pin. To minimize power con-
sumption, or if the PF2 pin is to be used as an output in the
DSP application, a weak pull-up or pull-down, on the order of
100 kΩ, can be used. This value should be sufficient to pull the
pin to the desired level and still allow the pin to operate as a pro-
grammable flag output without undue strain on the processor’s
output driver. For minimum power consumption during power-
down, reconfigure PF2 to be an input, as the pull-up or pull-down
will hold the pin in a known state, and will not switch.
The RESET signal initiates a master reset of the AD73460. The
RESET signal must be asserted during the power-up sequence
to assure proper initialization. RESET during initial power-up
must be held long enough to allow the internal clock to stabi-
lize. If RESET is activated any time after power-up, the clock
continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is applied
to the processor, and for the internal phase-locked loop (PLL)
to lock onto the specific crystal frequency. A minimum of 2000
CLKIN cycles ensures that the PLL has locked, but does not
include the crystal oscillator start-up time. During this power-up
sequence the RESET signal should be held low. On any sub-
sequent resets, the RESET signal must meet the minimum
Active Configuration involves the use of a three-statable
external driver connected to the Mode C pin. A driver’s out-
put enable should be connected to the DSP’s RESET signal
such that it only drives the PF2 pin when RESET is active
(low). When RESET is deasserted, the driver should three-
state, thus allowing full use of the PF2 pin as either an input or
output. To minimize power consumption during power-down,
configure the programmable flag as an output when connected
to a three-stated buffer. This ensures that the pin will be held at
a constant level and not oscillate should the three-state driver’s
level hover around the logic switching point.
pulsewidth specification, tRSP
.
The RESET input contains some hysteresis; however, if an RC
circuit is used to generate the RESET signal, an external Schmidt
trigger is recommended.
The master reset sets all internal stack pointers to the empty stack
condition, masks all interrupts and clears the MSTAT register.
When RESET is released, if there is no pending bus request
and the chip is configured for booting, the boot-loading sequence
is performed. The first instruction is fetched from on-chip
program memory location 0x0000 once boot loading completes.
MEMORY ARCHITECTURE
The AD73460 provides a variety of memory and peripheral
interface options. The key functional groups are Program Memory,
Data Memory, Byte Memory, and I/O. Refer to the following
figures and tables for PM and DM memory allocations in the
AD73460.
MODES OF OPERATION
Table XVIII summarizes the AD73460 memory modes.
Setting Memory Mode
PROGRAM MEMORY
Memory Mode selection for the AD73460 is made during chip
reset through the use of the Mode C pin. This pin is multi-
plexed with the DSP’s PF2 pin, so care must be taken in how
the mode selection is made. The two methods for selecting the
value of Mode C are active and passive.
Program Memory (Full Memory Mode) is a 24-bit-wide
space for storing both instruction opcodes and data. The
AD73460-80 has 16K words of Program Memory RAM on chip
(the AD73460-40 has 8K words of Program Memory RAM on
chip), and the capability of accessing up to two 8K external memory
overlay spaces using the external data bus.
REV. 0
–25–
AD73460
DATA MEMORY
ADDRESS
0x3FFF
DATA MEMORY
Program Memory (Host Mode) allows access to all internal
memory. External overlay access is limited by a single exter-
nal address line (A0). External program execution is not
available in host mode due to a restricted data bus that is
only 16 bits wide.
32 MEMORY
MAPPED
REGISTERS
ALWAYS
ACCESSIBLE
AT ADDRESS
0x2000 – 0x3FFF
0x3FE0
0x3FDF
INTERNAL
8160
WORDS
INTERNAL
MEMORY
0x0000–
0x1FFF
0x2000
0x1FFF
ACCESSIBLE WHEN
DMOVLAY = 0
0x0000–
0x1FFF
8K INTERNAL
DMOVLAY = 0
OR
Table XIX. PMOVLAY Bits
ACCESSIBLE WHEN
DMOVLAY = 1
0x0000–
0x1FFF
EXTERNAL 8K
DMOVLAY = 1, 2
PMOVLAY Memory A13
A12:0
EXTERNAL
MEMORY
ACCESSIBLE WHEN
DMOVLAY = 2
0x0000
0
1
Internal
Not Applicable Not Applicable
External
Overlay 1
0
1
13 LSBs of Address
Between 0x2000
and 0x3FFF
13 LSBs of Address
Between 0x2000
and 0x3FFF
Figure 14. Data Memory Map
Data Memory (Host Mode) allows access to all internal memory.
External overlay access is limited by a single external address
line (A0). The DMOVLAY bits are defined in Table XX.
2
External
Overlay 2
Table XX. DMOVLAY Bits
DMOVLAY Memory A13
A12:0
1
PM (MODE B = 0)
PM (MODE B = 1)
0
1
Internal
External
Overlay 1
Not Applicable Not Applicable
ALWAYS
ACCESSIBLE
AT ADDRESS
0x0000 – 0x1FFF
RESERVED
0
1
13 LSBs of Address
Between 0x2000
and 0x3FFF
13 LSBs of Address
Between 0x2000
and 0x3FFF
0x2000–
INTERNAL
MEMORY
0x3FFF
INTERNAL
MEMORY
ACCESSIBLE WHEN
PMOVLAY = 0
0x2000–
3
0x3FFF
0x0000–
0x1FFF
ACCESSIBLE WHEN
PMOVLAY = 0
2
2
External
Overlay 2
3
0x2000–
ACCESSIBLE WHEN
PMOVLAY = 0
2
0x3FFF
ACCESSIBLE WHEN
PMOVLAY = 1
0x2000–
EXTERNAL
RESERVED
2
0x3FFF
MEMORY
EXTERNAL
MEMORY
ACCESSIBLE WHEN
PMOVLAY = 2
I/O Space (Full Memory Mode)
The AD73460 supports an additional external memory space
called I/O space. This space is designed to support simple con-
nections to peripherals (such as data converters and external
registers) or to bus interface ASIC data registers. I/O space
supports 2048 locations of 16-bit wide data. The lower eleven
bits of the external address bus are used; the upper three bits are
undefined. Two instructions were added to the core ADSP-2100
Family instruction set to read from and write to I/O memory
space. The I/O space also has four dedicated 3-bit wait state
registers, IOWAIT0-3, that specify up to seven wait states to be
automatically generated for each of four regions. The wait states
act on address ranges as shown in Table XXI.
PROGRAM MEMORY
MODE B = 0
PROGRAM MEMORY
MODE B = 1
ADDRESS
ADDRESS
0x3FFF
0x3FFF
8K INTERNAL
PMOVLAY = 0
3
8K INTERNAL
3
OR
PMOVLAY = 0
8K EXTERNAL
PMOVLAY = 1 OR 2
0x2000
0x1FFF
0x2000
0x1FFF
8K EXTERNAL
8K INTERNAL
0x0000
0x0000
NOTES:
1
WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0
SEE TABLE III FOR PMOVLAY BITS
NOT ACCESSIBLE ON AD73422-40
2
3
Table XXI. Wait States
Address Range
Wait State Register
Figure 13. Program Memory Map
0x000–0x1FF
0x200–0x3FF
0x400–0x5FF
0x600–0x7FF
IOWAIT0
IOWAIT1
IOWAIT2
IOWAIT3
DATA MEMORY
Data Memory (Full Memory Mode) is a 16-bit-wide space
used for the storage of data variables and for memory-mapped
control registers. The AD73460-80 has 16K words on Data
Memory RAM on chip (the AD73460-40 has 8K words on Data
Memory RAM on chip), consisting of 16,352 user-accessible
locations in the case of the AD73460-80 (8,160 user-accessible
locations in the case of the AD73460-40) and 32 memory-
mapped registers. Support also exists for up to two 8K external
memory overlay spaces through the external data bus. All inter-
nal accesses complete in one cycle. Accesses to external memory
are timed using the wait states specified by the DWAIT register.
Composite Memory Select (CMS)
The AD73460 has a programmable memory select signal that is
useful for generating memory select signals for memories mapped
to more than one space. The CMS signal is generated to have the
same timing as each of the individual memory select signals (PMS,
DMS, BMS, IOMS) but can combine their functionality.
Each bit in the CMSSEL register, when set, causes the CMS
signal to be asserted when the selected memory select is asserted.
For example, to use a 32K word memory to act as both program
and data memory, set the PMS and DMS bits in the CMSSEL
register and use the CMS pin to drive the chip select of the
memory; use either DMS or PMS as the additional address bit.
–26–
REV. 0
AD73460
The CMS pin functions like the other memory select signals,
with the same timing and bus request logic. A 1 in the enable bit
causes the assertion of the CMS signal at the same time as the
selected memory select signal. All enable bits default to 1 at
reset, except the BMS bit.
Table XXII. Data Formats
Internal
Memory Space
BTYPE
Word Size
Alignment
00
01
10
11
Program Memory
Data Memory
Data Memory
Data Memory
24
16
8
Full Word
Full Word
MSBs
Boot Memory Select (BMS) Disable
The AD73460 also lets you boot the processor from one exter-
nal memory space while using a different external memory space
for BDMA transfers during normal operation. You can use the
CMS to select the first external memory space for BDMA trans-
fers and BMS to select the second external memory space for
booting. The BMS signal can be disabled by setting Bit 3 of the
System Control Register to 1. The System Control Register is
illustrated in Figure 15.
8
LSBs
Unused bits in the 8-bit data memory formats are filled with 0s.
The BIAD register field is used to specify the starting address
for the on-chip memory involved with the transfer. The 14-bit
BEAD register specifies the starting address for the external byte
memory space. The 8-bit BMPAGE register specifies the start-
ing page for the external byte memory space. The BDIR register
field selects the direction of the transfer. Finally the 14-bit
BWCOUNT register specifies the number of DSP words to
transfer and initiates the BDMA circuit transfers.
SYSTEM CONTROL REGISTER
15 14 13 12 11 10
9
8
7
6
5
4
3
0
2
1
1
1
0
1
DM (0x3FFF)
0
0
0
0
0
1
0
0
0
0
0
0
SPORT0 ENABLE
1 = ENABLED
PWAIT
PROGRAM MEMORY
WAIT STATES
BDMA accesses can cross page boundaries during sequential
addressing. A BDMA interrupt is generated on the completion
of the number of transfers specified by the BWCOUNT register.
0 = DISABLED
SPORT1 ENABLE
1 = ENABLED
0 = DISABLED
BMS ENABLE
0 = ENABLED
1 = DISABLED
The BWCOUNT register is updated after each transfer so it can
be used to check the status of the transfers. When it reaches
zero, the transfers have finished and a BDMA interrupt is gener-
ated. The BMPAGE and BEAD registers must not be accessed
by the DSP during BDMA operations.
SPORT1 CONFIGURE
1 = SERIAL PORT
0 = FI, FO, IRQ0,
IRQ1, SCLK
Figure 15. System Control Register
Byte Memory
The byte memory space is a bidirectional, 8-bit-wide, external
memory space used to store programs and data. Byte memory is
accessed using the BDMA feature. The BDMA Control Regis-
ter is shown in Figure 16. The byte memory space consists of
256 pages, each of which is 16K × 8.
The source or destination of a BDMA transfer will always be
on-chip program or data memory.
When the BWCOUNT register is written with a nonzero value,
the BDMA circuit starts executing byte memory accesses with
wait states set by BMWAIT. These accesses continue until the
count reaches zero. When enough accesses have occurred to create
a destination word, it is transferred to or from on-chip memory.
The transfer takes one DSP cycle. DSP accesses to external
memory have priority over BDMA byte memory accesses.
The byte memory space on the AD73460 supports read and
write operations as well as four different data formats. The byte
memory uses data bits 15:8 for data. The byte memory uses
data bits 23:16 and address bits 13:0 to create a 22-bit address.
This allows up to a 4 meg × 8 (32-megabit) ROM or RAM to be
used without glue logic. All byte memory accesses are timed by
the BMWAIT register.
The BDMA Context Reset bit (BCR) controls whether or not
the processor is held off while the BDMA accesses are occur-
ring. Setting the BCR bit to 0 allows the processor to continue
operations. Setting the BCR bit to 1 causes the processor to
stop execution while the BDMA accesses are occurring, to clear
the context of the processor and start execution at address 0
when the BDMA accesses have completed.
Byte Memory DMA (BDMA, Full Memory Mode)
The Byte memory DMA controller allows loading and storing of
program instructions and data using the byte memory space.
The BDMA circuit is able to access the byte memory space
while the processor is operating normally, and steals only one
DSP cycle per 8-, 16-, or 24-bit word transferred.
The BDMA overlay bits specify the OVLAY memory blocks to
be accessed for internal memory.
Internal Memory DMA Port (IDMA Port; Host Memory
Mode)
BDMA CONTROL
15 14 13 12 11 10
9
8
7
6
5
0
4
0
3
1
2
0
1
0
0
0
The IDMA Port provides an efficient means of communication
between a host system and the AD73460. The port is used to
access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot be used, however, to write to the DSP’s memory-
mapped control registers. A typical IDMA transfer process is
described as follows:
DM (0x3FE3)
0
0
0
0
0
0
0
0
0
0
BTYPE
BDIR
BMPAGE
0 = LOAD FROM BM
1 = STORE TO BM
BCR
0 = RUN DURING BDMA
1 = HALT DURING BDMA
Figure 16. BDMA Control Register
1. Host starts IDMA transfer.
The BDMA circuit supports four different data formats that are
selected by the BTYPE register field. The appropriate number
of 8-bit accesses are done from the byte memory space to build
the word size selected. Table XXII shows the data formats sup-
ported by the BDMA circuit.
2. Host checks IACK control line to see if the DSP is busy.
REV. 0
–27–
AD73460
3. Host uses IS and IAL control lines to latch either the DMA
starting address (IDMAA) or the PM/DM OVLAY selection
into the DSP’s IDMA control registers.
Bootstrap Loading (Booting)
The AD73460 has two mechanisms to allow automatic loading
of the internal program memory after reset. The method for
booting after reset is controlled by the Mode A, B and C con-
figuration bits.
IAD[15] must be set to 0.
4. Host uses IS and IRD (or IWR) to read (or write) DSP inter-
When the mode pins specify BDMA booting, the AD73460
initiates a BDMA boot sequence when reset is released.
nal memory (PM or DM).
5. Host checks IACK line to see if the DSP has completed the
The BDMA interface is set up during reset to the following
defaults when BDMA booting is specified: the BDIR, BMPAGE,
BIAD, and BEAD registers are set to 0, the BTYPE register is
set to 0 to specify program memory 24-bit words, and the
BWCOUNT register is set to 32. This causes 32 words of on-
chip program memory to be loaded from byte memory. These
32 words are used to set up the BDMA to load in the remaining
program code. The BCR bit is also set to 1, which causes pro-
gram execution to be held off until all 32 words are loaded into
on-chip program memory. Execution then begins at address 0.
previous IDMA operation.
6. Host ends IDMA transfer.
The IDMA port has a 16-bit multiplexed address and data bus
and supports 24-bit program memory. The IDMA port is
completely asynchronous and can be written to while the
AD73460 is operating at full speed.
The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device
can therefore access a block of sequentially addressed memory
by specifying only the starting address of the block. This increases
throughput as the address does not have to be sent for each
memory access.
The ADSP-2100 Family Development Software (Revision 5.02
and later) fully supports the BDMA booting feature and can
generate byte memory space compatible boot code.
The IDLE instruction can also be used to allow the processor to
hold off execution while booting continues through the BDMA
interface. For BDMA accesses while in Host Mode, the addresses
to boot memory must be constructed externally to the AD73460.
The only memory address bit provided by the processor is A0.
IDMA Port access occurs in two phases. The first is the IDMA
Address Latch cycle. When the acknowledge is asserted, a
14-bit address and 1-bit destination type can be driven onto the
bus by an external device. The address specifies an on-chip
memory location; the destination type specifies whether it is a
DM or PM access. The falling edge of the address latch signal
latches this value into the IDMAA register.
IDMA Port Booting
The AD73460 can also boot programs through its Internal
DMA port. If Mode C = 1, Mode B = 0 and Mode A = 1, the
AD73460 boots from the IDMA port. IDMA feature can load
as much on-chip memory as desired. Program execution is held
off until on-chip program memory location 0 is written to.
Once the address is stored, data can either be read from or
written to the AD73460’s on-chip memory. Asserting the select
line (IS) and the appropriate read or write line (IRD and IWR
respectively) signals the AD73460 that a particular transaction
is required. In either case, there is a one-processor-cycle delay
for synchronization. The memory access consumes one addi-
tional processor cycle.
Bus Request and Bus Grant (Full Memory Mode)
The AD73460 can relinquish control of the data and address
buses to an external device. When the external device requires
access to memory, it asserts the bus request (BR) signal. If the
AD73460 is not performing an external memory access, it
responds to the active BR input in the following processor
cycle by:
Once an access has occurred, the latched address is automati-
cally incremented and another access can occur.
Through the IDMAA register, the DSP can also specify the
starting address and data format for DMA operation. Asserting
the IDMA port select (IS) and address latch enable (IAL) directs
the AD73460 to write the address onto the IAD0–14 bus into
the IDMA Control Register. If IAD[15] is set to 0, IDMA
latches the address. The IDMAA register, shown below, is
memory mapped at address DM (0x3FE0). Note that the
latched address (IDMAA) cannot be read back by the host. The
IDMA OVLAY register is memory mapped at address DM
(0x3FE7). See Figure 17 for more information on IDMA and
DMA memory maps.
•
three-stating the data and address buses and the PMS, DMS,
BMS, CMS, IOMS, RD, WR output drivers,
•
•
asserting the bus grant (BG) signal, and
halting program execution.
If Go Mode is enabled, the AD73460 will not halt program
execution until it encounters an instruction that requires an
external memory access.
If the AD73460 is performing an external memory access when
the external device asserts the BR signal, it will not three-state
the memory interfaces nor assert the BG signal until the proces-
sor cycle after the access completes. The instruction does not
need to be completed when the bus is granted. If a single
instruction requires two external memory accesses, the bus will
be granted between the two accesses.
IDMA CONTROL (U = UNDEFINED AT RESET)
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
DM(0x3FE0)
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
IDMAA ADDRESS
IDMAD
DESTINATION MEMORY TYPE:
0 = PM
1 = DM
When the BR signal is released, the processor releases the BG
signal, reenables the output drivers and continues program
execution from the point at which it stopped.
Figure 17. IDMA Control/OVLAY Registers
–28–
REV. 0
AD73460
The bus request feature operates at all times, including when
the processor is booting and when RESET is active.
Issuing the chip reset command during emulation causes the
DSP to perform a full chip reset, including a reset of its memory
mode. Therefore, it is vital that the mode pins are set correctly
PRIOR to issuing a chip reset command from the emulator user
interface. If you are using a passive method of maintaining mode
information (as discussed in Setting Memory Modes) then it
does not matter that the mode information is latched by an
emulator reset. However, if you are using the RESET pin as a
method of setting the value of the mode pins, then you have to
take into consideration the effects of an emulator reset.
The BGH pin is asserted when the AD73460 is ready to execute
an instruction, but is stopped because the external bus is already
granted to another device. The other device can release the bus
by deasserting bus request. Once the bus is released, the AD73460
deasserts BG and BGH and executes the external memory access.
Flag I/O Pins
The AD73460 has eight general-purpose programmable input/
output flag pins. They are controlled by two memory-mapped
registers. The PFTYPE register determines the direction, 1 =
output and 0 = input. The PFDATA register is used to read and
write the values on the pins. Data being read from a pin config-
ured as an input is synchronized to the AD73460’s clock. Bits that
are programmed as outputs will read the value being output.
The PF pins default to input during reset.
One method of ensuring that the values located on the mode
pins are those desired is to construct a circuit like the one shown
in Figure 18. This circuit forces the value located on the Mode
A pin to logic high; regardless if it latched via the RESET or
ERESET pin.
In addition to the programmable flags, the AD73460 has five
fixed-mode flags, FLAG_IN, FLAG_OUT, FL0, FL1, and FL2.
FL0–FL2 are dedicated output flags. FLAG_IN and FLAG_OUT
are available as an alternate configuration of SPORT1.
ERESET
RESET
AD73460
Note: Pins PF0, PF1, PF2, and PF3 are also used for device
configuration during reset.
1kꢀ
MODE A /PFO
INSTRUCTION SET DESCRIPTION
PROGRAMMABLE I/O
The AD73460 assembly language instruction set has an algebraic
syntax that was designed for ease of coding and readability. The
assembly language, which takes full advantage of the processor’s
unique architecture, offers the following benefits:
Figure 18. Mode A Pin/EZ-ICE Circuit
The ICE-Port interface consists of the following AD73460 pins:
EBR
EMS
ELIN
EBG
EINT
ELOUT
ERESET
ECLK
EE
•
The algebraic syntax eliminates the need to remember cryp-
tic assembler mnemonics. For example, a typical arithmetic
add instruction, such as AR = AX0 + AY0, resembles a
simple equation.
These AD73460 pins must be connected only to the EZ-ICE
connector in the target system. These pins have no function
except during emulation, and do not require pull-up or pull-down
resistors. The traces for these signals between the AD73460 and
the connector must be kept as short as possible, no longer than
three inches.
•
•
Every instruction assembles into a single, 24-bit word that
can execute in a single instruction cycle.
The syntax is a superset ADSP-2100 Family assembly lan-
guage and is completely source and object code compatible
with other family members. Programs may need to be relo-
cated to utilize on-chip memory and conform to the AD73460’s
interrupt vector and reset vector map.
The following pins are also used by the EZ-ICE:
BR
RESET
BG
GND
•
•
Sixteen condition codes are available. For conditional jump,
call, return, or arithmetic instructions, the condition can
be checked and the operation executed in the same instruc-
tion cycle.
The EZ-ICE uses the EE (emulator enable) signal to take
control of the AD73460 in the target system. This causes the
processor to use its ERESET, EBR, and EBG pins instead of
the RESET, BR, and BG pins. The BG output is three-stated.
These signals do not need to be jumper-isolated in your system.
The EZ-ICE connects to your target system via a ribbon cable
and a 14-pin female plug. The ribbon cable is 10 inches in length
with one end fixed to the EZ-ICE. The female plug is plugged
onto the 14-pin connector (a pin strip header) on the target board.
Multifunction instructions allow parallel execution of an
arithmetic instruction with up to two fetches or one write to
processor memory space during a single instruction cycle.
DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM
The AD73460 has on-chip emulation support and an ICE-Port,
a special set of pins that interface to the EZ-ICE. These features
allow in-circuit emulation without replacing the target system
processor by using only a 14-pin connection from the target
system to the EZ-ICE. Target systems must have a 14-pin con-
nector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug.
See the ADSP-2100 Family EZ-Tools data sheet for complete
information on ICE products.
REV. 0
–29–
AD73460
Target System Interface Signals
Target Board Connector for EZ-ICE Probe
When the EZ-ICE board is installed, the performance on some
system signals changes. Design your system to be compatible
with the following system interface signal changes introduced by
the EZ-ICE board:
The EZ-ICE connector (a standard pin strip header) is shown in
Figure 19. You must add this connector to your target board
design if you intend to use the EZ-ICE. Be sure to allow
enough room in your system to fit the EZ-ICE probe onto the
14-pin connector.
•
EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the RESET
signal.
1
3
5
2
4
BG
GND
EBG
EBR
•
•
•
•
EZ-ICE emulation introduces an 8 ns propagation delay
between your target circuitry and the DSP on the BR signal.
BR
EZ-ICE emulation ignores RESET and BR when single-
stepping.
6
EINT
ELIN
7
؋
8
EZ-ICE emulation ignores RESET and BR when in Emulator
Space (DSP halted).
KEY (NO PIN)
ELOUT
EE
10
12
14
9
EZ-ICE emulation ignores the state of target BR in certain
modes. As a result, the target system may take control of the
DSP’s external memory bus only if bus grant (BG) is asserted
by the EZ-ICE board’s DSP.
ECLK
11
13
EMS
RESET
ERESET
ANALOG FRONT END (AFE) INTERFACING
TOP VIEW
The AFE section of the AD73460 features six input channels
each with 16-bit linear resolution. Connectivity to the AFE
section from the DSP is uncommitted thus allowing the user the
flexibility of connecting in the mode or configuration of their
choice. This section will detail several configurations—with no
extra AFE channels configured and with an extra AFE section
configured (using an external AD73360 AFE).
Figure 19. Target Board Connector for EZ-ICE
The 14-pin, 2-row pin strip header is keyed at the Pin 7 loca-
tion—you must remove Pin 7 from the header. The pins must
be 0.025 inch square and at least 0.20 inch in length. Pin spac-
ing should be 0.1 × 0.1 inches. The pin strip header must have
at least 0.15-inch clearance on all sides to accept the EZ-ICE
probe plug.
DSP SPORT TO AFE INTERFACING
Pin strip headers are available from vendors such as 3M,
McKenzie, and Samtec.
The SCLK, SDO, SDOFS, SDI, and SDIFS must be connected
to the SCLK, DR, RFS, DT, and TFS pins of the DSP respec-
tively. The SE pin may be controlled from a parallel output pin
or flag pin such as FL0–2 or, where SPORT power-down is not
required, it can be permanently strapped high using a suitable
pull-up resistor. For consistent performance the SE pin should
be synchronized to the rising edge of the AMCLK using a cir-
cuit similar to that of Figure 23. The ARESET pin may be
connected to the system hardware reset structure or it may also
be controlled using a dedicated control line. In the event of
tying it to the global system reset, it is necessary to operate the
device in mixed mode, which allows a software reset, otherwise
there is no convenient way of resetting the device.
Target Memory Interface
For your target system to be compatible with the EZ-ICE
emulator, it must comply with the memory interface guide-
lines listed below.
PM, DM, BM, IOM, and CM
Design your Program Memory (PM), Data Memory (DM),
Byte Memory (BM), I/O Memory (IOM), and Composite
Memory (CM) external interfaces to comply with worst-case
device timing requirements and switching characteristics as
specified in the DSP’s data sheet. The performance of the
EZ-ICE may approach published worst-case specification for
some memory access timing requirements and switching
characteristics.
TFS
DT
SDIFS
SDI
Note: If your target does not meet the worst-case chip specifica-
tion for memory access parameters, you may not be able to
emulate your circuitry at the desired CLKIN frequency.
Depending on the severity of the specification violation, you
may have trouble manufacturing your system as DSP compo-
nents statistically vary in switching characteristic and timing
requirements within published limits.
SCLK
SCLK
AFE
SECTION
DSP
SECTION
DR
SDO
RFS
SDOFS
ARESET
FL0
FL1
Restriction: All memory strobe signals on the AD73460 (RD,
WR, PMS, DMS, BMS, CMS, and IOMS) used in your target
system must have 10 kΩ pull-up resistors connected when the
EZ-ICE is being used. The pull-up resistors are necessary
because there are no internal pull-ups to guarantee their state
during prolonged three-state conditions resulting from typical
EZ-ICE debugging sessions. These resistors may be removed at
your option when the EZ-ICE is not being used.
SE
Figure 20. DSP to AD73460 AFE Connection
–30–
REV. 0
AD73460
CASCADE OPERATION
AD73460
Where it is required to configure an extra analog input channels
to the existing six channels on the AD73460 it is possible to
cascade six more channels (using external AD73360 AFEs) by
using the scheme described in Figure 22. It is necessary how-
ever to ensure that the timing of the SE and ARESET signals is
synchronized at each device in the cascade. A simple D-type
flip-flop is sufficient to synchronize each signal to the master
clock AMCLK as shown in Figure 21.
SDIFS
SDI
TFS
DT
AMCLK
SE
AFE
DSP
SCLK
DR
SCLK
SDO
SECTION
DEVICE 1
ARESET
RFS
SDOFS
FL0
FL1
SDIFS
SDI
SE SIGNAL SYNCHRONIZED
TO AMCLK
MCLK
SE
DSP CONTROL
TO SE
D
Q
1/2
ADDITIONAL
AD73360
AFE
74HC74
SCLK
SDO
AMCLK
CLK
RESET
DEVICE 2
SDOFS
ARESET SIGNAL SYNCHRONIZED
TO AMCLK
DSP CONTROL
TO ARESET
Q0
Q1
D0
D1
D
Q
74HC74
1/2
74HC74
CLK
CLK
AMCLK
Figure 22. Connection of an AD73360 Cascaded to the
AD73460
Figure 21. SE and ARESET Sync Circuit for Cascaded
Operation
Interfacing to the AFE’s Analog Inputs
There may be some restrictions in cascade operation due to the
number of devices configured in the cascade and the serial clock
rate chosen. The formula below gives an indication of whether
the combination of sample rate, and serial clock can be success-
fully cascaded. This assumes a directly coupled frame sync
arrangement as shown in Figure 20 and does not take any interrupt
latency into account.
The AD73460 features six signal conditioning inputs. Each
signal conditioning block allows the AD73460 to be used with
either a single-ended or differential signal. The applied signal
can also be inverted internally by the AD73460 if required. The
analog input signal to the AD73460 can be dc-coupled, pro-
vided that the dc bias level of the input signal is the same as the
internal reference level (REFOUT). Figure 23 shows the recom-
mended differential input circuit for the AD73460. The circuit
of Figure 23 implements first-order low-pass filters with a 3 dB
point at 34 kHz; these are the only filters that must be imple-
mented external to the AD73460 to prevent aliasing of the
sampled signal. Since the ADC uses a highly oversampled
approach that transfers the bulk of the antialiasing filtering into
the digital domain, the off-chip antialiasing filter need only be of
a low order. It is recommended that for optimum performance
the capacitors used for the antialiasing filter be of high quality
dielectric (NPO).
1
fS
6 × [((Device Count − 1) × 16) + 17]
≥
SCLK
When using the indirectly coupled frame sync configuration in
cascaded operation it is necessary to be aware of the restrictions
in sending control word data to all devices in the cascade. The
user should ensure that there is sufficient time for all the control
words to be sent between reading the last ADC sample and the
start of the next sample period.
Connection of a cascade, as shown in Figure 22, is no more
complicated than connecting a single device. Instead of connect-
ing the SDO and SDOFS to the DSP’s Rx port, these are now
daisy-chained to the SDI and SDIFS of the next device in the
cascade. The SDO and SDOFS of the final device in the cascade
are connected to the DSP’s Rx port to complete the cascade. SE
and ARESET on all devices are fed from the signals that were
synchronized with the AMCLK using the circuit of Figure 21.
The SCLK from only one device need be connected to the DSP’s
SCLK input(s) as both devices will be running at the same SCLK
frequency and phase.
100⍀
VINPx
100⍀
0.047F
VIN
VINNx
0.047F
TO INPUT BIAS
CIRCUITRY
REFOUT
VOLTAGE
REFERENCE
REFCAP
0.1F
Figure 23. Example Circuit for Differential Input
(DC Coupling)
REV. 0
–31–
AD73460
Figure 24 details the dc-coupled input circuits for single-ended
operation respectively.
Digital Interface
As there are a number of variations of sample rate and clock
speeds that can be used with the AD73460 in a particular appli-
cation, it is important to select the best combination to achieve
the desired performance. High-speed serial clocks will read the
data from the AD73460 in a shorter time, giving more time for
processing at the expense of injecting some digital noise into the
circuit. Digital noise can also be reduced by connecting resistors
(typ <50 Ω) in series with the digital input and output lines.
The noise can be minimized by good grounding and layout.
Typically the best performance is achieved by selecting the
slowest sample rate and SCLK frequency for the required appli-
cation as this will produce the least amount of digital noise.
100⍀
VINPx
VINNx
VIN
0.047F
REFOUT
VOLTAGE
REFERENCE
REFCAP
0.1F
Figure 24. Example Circuit for Single-Ended Input
(DC Coupling)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
119-Ball Plastic Ball Grid Array (PBGA)
(B-119)
0.300 (7.62) BSC
0.559 (14.20)
BOTTOM
0.543 (13.80)
7
6 5 4 3 2 1
VIEW
A
B
C
D
E
F
A1
G
H
J
K
L
0.050
(1.27)
BSC
0.800
(20.32)
BSC
0.866 (22.00)
0.858 (21.80)
TOP VIEW
M
N
P
R
T
0.033
(0.84)
REF
U
0.050 (1.27)
BSC
0.126 (3.19)
REF
0.037 (0.95)
0.033 (0.85)
DETAIL A
DETAIL A
0.028 (0.70)
0.020 (0.50)
0.089 (2.27)
0.073 (1.85)
0.022 (0.56)
REF
0.035 (0.90)
0.024 (0.60)
BALL DIAMETER
SEATING
PLANE
–32–
REV. 0
相关型号：
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