AD7366-5_15 [ADI]
True Bipolar Input, 12-/14-Bit, 2-Channel, Simultaneous Sampling SAR ADCs;
| 型号： | AD7366-5_15 |
| 厂家： | 
ADI |
| 描述： | True Bipolar Input, 12-/14-Bit, 2-Channel, Simultaneous Sampling SAR ADCs |
| 文件： | 总29页 (文件大小：651K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
True Bipolar Input, 12-/14-Bit,
2-Channel, Simultaneous Sampling SAR ADCs
AD7366-5/AD7367-5
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
D
A
AV
DV
CC
Dual 12-bit/14-bit, 2-channel ADCs
True bipolar analog inputs
Programmable input ranges
10 V, 5 V, 0 V to +10 V
DD
CAP
CC
BUF
REF
AD7366-5/AD7367-5
12 V with +3 V external reference
Throughput rate: 500 kSPS
Simultaneous conversion with read in less than 2 μs
High analog input impedance
Low current consumption
5.1 mA typical in normal mode
320 nA typical in shutdown mode
AD7366-5
72 dB SNR at 50 kHz input frequency
12-bit no missing codes
AD7367-5
76 dB SNR at 50 kHz input frequency
14-bit no missing codes
Accurate on-chip reference: 2.5 V 0.2%
–40°C to +85°C operation
V
V
A1
12-/14-BIT
SUCCESSIVE
APPROXIMATION
ADC
OUTPUT
DRIVERS
MUX
T/H
D
A
OUT
A2
SCLK
CNVST
CS
BUSY
ADDR
RANGE0
RANGE1
REFSEL
CONTROL
LOGIC
V
V
B1
V
DRIVE
MUX
T/H
12-/14-BIT
SUCCESSIVE
APPROXIMATION
ADC
OUTPUT
DRIVERS
D
B
OUT
B2
BUF
High speed serial interface
SPI-/QSPI-/MICROWIRE-/DSP-compatible
iCMOS process technology
Available in a 24-lead TSSOP
AGND AGND
V
D
B
DGND
SS
CAP
Figure 1.
GENERAL DESCRIPTION
The devices have an on-chip 2.5 V reference that can be disabled to
allow the use of an external reference. If a 3 V reference is applied
to the DCAPA andDCAPB pins, the AD7366-5/AD7367-5 can
accept a true bipolar 12 V analog input. Minimum 12 V VDD
and VSS supplies are required for the 12 V input range.
The AD7366-5/AD7367-51 are dual, 12-/14-bit, low power,
successive approximation analog-to-digital converters (ADCs)
that feature throughput rates up to 500 kSPS. Each device contains
two ADCs, which are both preceded by a 2-channel multiplexer,
and a low noise, wide bandwidth, track-and-hold amplifier.
PRODUCT HIGHLIGHTS
The AD7366-5/AD7367-5 are fabricated on the Analog
Devices, Inc., industrial CMOS process (iCMOS®)2, which is
a technology platform combining the advantages of low and
high voltage CMOS. The process allows the parts to accept
high voltage bipolar signals in addition to reducing power
consumption and package size. The AD7366-5/AD7367-5 can
accept true bipolar analog input signals in the 10 V range,
5 V range, and 0 V to +10 V range.
1. True bipolar analog input signals can be accepted, as well
as 10 V, 5 V, 12 V (with external reference), and 0 V to
+10 V unipolar signals.
2. Two complete ADC functions allow simultaneous
sampling and conversion of two channels.
3. A 500 kSPS serial interface is SPI-/QSPI™-/MICROWIRE™-/
DSP-compatible.
Table 1. Related Products
Device
Resolution
Throughput Rate
1 MSPS
No. of Channels
Dual, 2-channel
Dual, 2-channel
Dual, 2-channel
Dual, 2-channel
AD7366
AD7366-5
AD7367
AD7367-5
12-Bit
1 Protected by U.S. Patent No. 6,731,232.
2 For analog systems designers within industrial/instrumentation equipment
OEMs who need high performance ICs at higher voltage levels, iCMOS is a
technology platform that enables the development of analog ICs capable of
+30 V and operating at 15 V supplies while allowing dramatic reductions in
power consumption and package size, and increased ac and dc performance.
12-Bit
500 kSPS
14-Bit
1 MSPS
14-Bit
500 kSPS
Rev. B
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: 781.461.3113 ©2007-2011 Analog Devices, Inc. All rights reserved.
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AD7366-5/AD7367-5
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Connection Diagram ................................................... 18
Driver Amplifier Choice ........................................................... 19
Reference ..................................................................................... 19
Modes of Operation ....................................................................... 20
Normal Mode.............................................................................. 20
Shutdown Mode ......................................................................... 21
Power-Up Times......................................................................... 21
Serial Interface ................................................................................ 22
Microprocessor Interfacing........................................................... 24
AD7366-5/AD7367-5 to ADSP-218x ...................................... 24
AD7366-5/AD7367-5 to ADSP-BF53x ................................... 25
AD7366-5/AD7367-5 to TMS320VC5506 ............................. 25
AD7366-5/AD7367-5 to DSP563xx......................................... 26
Application Hints ........................................................................... 27
Layout and Grounding .............................................................. 27
Evaluating the AD7366-5/AD7367-5...................................... 27
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AD7366-5 Specifications............................................................. 3
AD7367-5 Specifications............................................................. 5
Timing Specifications .................................................................. 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 11
Terminology .................................................................................... 14
Theory of Operation ...................................................................... 16
Circuit Information.................................................................... 16
Converter Operation.................................................................. 16
Analog Inputs.............................................................................. 17
Transfer Function....................................................................... 17
REVISION HISTORY
7/11—Rev. A to Rev. B
Changes to Serial Interface Section.............................................. 22
Changes to Figure 27...................................................................... 23
8/09—Rev. 0 to Rev. A
Changes to Table 2............................................................................ 4
Changes to Table 3............................................................................ 6
7/07—Revision 0: Initial Version
Rev. B | Page 2 of 28
AD7366-5/AD7367-5
SPECIFICATIONS
AD7366-5 SPECIFICATIONS
AVCC = DVCC = 4.75 V to 5.25 V; VDD = 5 V to 16.5 V; VSS = −16.5 V to −5 V; VDRIVE = 2.7 V to 5.25 V; fSAMPLE = 500 kSPS; fSCLK = 20 MHz;
REF = 2.5 V internal/external; TA = −40°C to +85°C, unless otherwise noted.
V
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)1
Signal-to-Noise (+ Distortion) Ratio (SINAD)1
Total Harmonic Distortion (THD)1
Spurious-Free Dynamic Range (SFDR)1
Intermodulation Distortion (IMD)1
Second-Order Terms
fIN = 50 kHz sine wave
70
70
72
71
−85
−87
dB
dB
dB
dB
−78
−78
fa = 49 kHz, fb = 51 kHz
−88
−88
−90
dB
dB
dB
Third-Order Terms
Channel-to-Channel Isolation1
SAMPLE AND HOLD
Aperture Delay2
Aperture Jitter2
10
ns
ps
40
Aperture Delay Matching2
Full Power Bandwidth
100
35
8
ps
MHz
MHz
@ 3 dB, 10 V range
@ 0.1 dB, 10 V range
DC ACCURACY
Resolution
12
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Integral Nonlinearity (INL)1
Differential Nonlinearity (DNL)1
Positive Full-Scale Error1
0.5
0.25
1
1
0.5
7
Guaranteed no missed codes to 12 bits
5 V and 10 V analog input range
0 V to 10 V analog input range
1
6
Positive Full-Scale Error Match1
Zero Code Error1
1.5
0.1
0.5
1
1.5
0.1
1
1
1.5
0.1
Matching from ADC A to ADC B
Channel-to-channel matching for ADC A and ADC B
5 V and 10 V analog input range
0 V to 10 V analog input range
3
6
Zero Code Error Match1
Negative Full-Scale Error1
Negative Full-Scale Error Match1
ANALOG INPUT
Matching from ADC A to ADC B
Channel-to-channel matching for ADC A and ADC B
5 V and 10 V analog input range
0 V to 10 V analog input range
Matching from ADC A to ADC B
Channel-to-channel matching for ADC A and ADC B
7
6
Input Voltage Ranges
10
V
(Programmed via RANGE Pins)
5
V
0 to 10
1
V
DC Leakage Current
Input Capacitance
0.01
μA
pF
pF
kΩ
MΩ
kΩ
MΩ
9
When in track, 10 V range
When in track, 5 V or 0 V to +10 V range
For 10 V @ 500 kSPS
For 10 V @ 100 kSPS
For 5 V/0 V to +10 V @ 500 kSPS
For 5 V/0 V to +10 V @ 100 kSPS
13
Input Impedance
500
2.5
250
1.2
Rev. B | Page 3 of 28
AD7366-5/AD7367-5
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REFERENCE INPUT/OUTPUT
Reference Output Voltage3
Long-Term Stability
Output Voltage Hysteresis1
Reference Input Voltage Range
DC Leakage Current
2.494
2.5
150
50
2.506
V
0.2ꢀ maꢁimum @ 25°C
For 1000 hours
ppm
ppm
V
μA
pF
pF
Ω
ppm/°C
μV rms
2.5
3.0
1
0.01
Eꢁternal reference applied to Pin DCAPA/Pin DCAP
5 V and 10 V analog input range
0 V to 10 V analog input range
B
Input Capacitance
25
17
7
6
20
DCAPA, DCAPB Output Impedance
Reference Temperature Coefficient
VREF Noise
25
Bandwidth = 3 kHz
VIN = 0 V or VDRIVE
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
0.7 × VDRIVE
V
V
μA
pF
+0.8
1
0.01
2
Input Capacitance, CIN
6
8
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating State Leakage Current
Floating State Output Capacitance2
VDRIVE − 0.2
V
V
μA
pF
0.4
1
0.01
CONVERSION RATE
Conversion Time
1.25
140
500
ꢂs
ns
kSPS
Track/Hold Acquisition Time2
Full-scale step input
For 2.7 V ≤ VDRIVE ≤ 5.25 V, fSCLK = 20 MHz
Digital inputs = 0 V or VDRIVE
See Table 7
See Table 7
See Table 7
Throughput Rate
POWER REQUIREMENTS
VCC
VDD
VSS
4.75
5
−16.5
2.7
5.25
16.5
−5
V
V
V
V
VDRIVE
5.25
Normal Mode (Static)
IDD
ISS
ICC
370
40
1.5
550
60
2.25
μA
μA
mA
VDD = 16.5 V
VSS = −16.5 V
VCC = 5.5 V
Normal Mode (Operational)
fS = 500 kSPS
IDD
ISS
ICC
1
0.7
3.4
1.2
0.82
4
mA
mA
mA
VDD = 16.5 V
VSS = −16.5 V
VCC = 5.25 V, internal reference enabled
Shutdown Mode
IDD
ISS
ICC
0.01
0.01
0.3
1
1
3
μA
μA
μA
VDD = 16.5 V
VSS = −16.5 V
VCC = 5.25 V
Power Dissipation
Normal Mode (Operational)
46
54.5
mW
VDD = +16.5 V, VSS = −16.5 V, VCC = +5.25 V,
fS = 500 kSPS
15
20
1.9
mW
mW
μW
10 V input range, fS = 100 kSPS
5 V and 0 V to +10 V input range, fS = 100 kSPS
VDD = +16.5 V, VSS = −16.5 V, VCC = +5.25 V
Shutdown Mode
48.75
1 See the Terminology section.
2 Sample tested during initial release to ensure compliance.
3 Refers to Pin DCAPA or Pin DCAPB specified for 25oC.
Rev. B | Page 4 of 28
AD7366-5/AD7367-5
AD7367-5 SPECIFICATIONS
AVCC = DVCC = 4.75 V to 5.25 V; VDD = 5 V to 16.5 V; VSS = −16.5 V to −5 V; VDRIVE = 2.7 V to 5.25 V; fSAMPLE = 500 kSPS; fSCLK = 20 MHz;
REF = 2.5 V internal/external; TA = −40°C to +85°C, unless otherwise noted.
V
Table 3.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)1
Signal-to-Noise (+ Distortion) Ratio (SINAD)1
Total Harmonic Distortion (THD)1
Spurious-Free Dynamic Range (SFDR)1
Intermodulation Distortion (IMD)1
Second-Order Terms
fIN = 50 kHz sine wave
74
73
76
75
−84
−87
dB
dB
dB
dB
−78
−79
fa = 49 kHz, fb = 51 kHz
−91
−89
−90
dB
dB
dB
Third-Order Terms
Channel-to-Channel Isolation1
SAMPLE AND HOLD
Aperture Delay2
Aperture Jitter2
10
ns
ps
40
Aperture Delay Matching2
Full Power Bandwidth
100
35
8
ps
MHz
MHz
@ 3 dB, 10 V range
@ 0.1 dB, 10 V range
DC ACCURACY
Resolution
14
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
Integral Nonlinearity (INL)1
Differential Nonlinearity (DNL)1
Positive Full-Scale Error1
2
0.5
4
5
3
0.2
1
5
3
0.2
4
5
3
0.2
3.5
0.90
25
25
Guaranteed no missed codes to 14 bits
5 V and 10 V analog input range
0 V to 10 V analog input range
Positive Full-Scale Error Match1
Zero Code Error1
Matching from ADC A to ADC B
Channel-to-channel matching for ADC A and ADC B
5 V and 10 V analog input range
0 V to 10 V analog input range
10
25
Zero Code Error Match1
Negative Full-Scale Error1
Negative Full-Scale Error Match1
ANALOG INPUT
Matching from ADC A to ADC B
Channel-to-channel matching for ADC A and ADC B
5 V and 10 V analog input range
0 V to 10 V analog input range
Matching from ADC A to ADC B
Channel-to-channel matching for ADC A and ADC B
25
25
Input Voltage Ranges
10
V
(Programmed via RANGE Pins)
5
V
0 to 10
1
V
See Table 7
DC Leakage Current
Input Capacitance
0.01
μA
pF
pF
kΩ
MΩ
kΩ
MΩ
9
When in track, 10 V range
When in track, 5 V or 0 V to +10 V range
For 10 V @ 500 kSPS
For 10 V @ 100 kSPS
For 5 V/0 V to +10 V @ 500 kSPS
For 5 V/0 V to +10 V @ 100 kSPS
13
Input Impedance
500
2.5
250
1.2
Rev. B | Page 5 of 28
AD7366-5/AD7367-5
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REFERENCE INPUT/OUTPUT
Reference Output Voltage3
Long-Term Stability
Output Voltage Hysteresis1
Reference Input Voltage Range
DC Leakage Current
2.494
2.5
150
50
2.506
V
0.2ꢀ maꢁimum @ 25°C
For 1000 hours
ppm
ppm
V
μA
pF
pF
Ω
ppm/°C
μV rms
2.5
3.0
1
0.01
Eꢁternal reference applied to DCAPA/Pin DCAP
5 V and 10 V analog input range
0 V to 10 V analog input range
B
Input Capacitance
25
17
7
6
20
DCAPA, DCAPB Output Impedance
Reference Temperature Coefficient
VREF Noise
25
Bandwidth = 3 kHz
VIN = 0 V or VDRIVE
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
0.7 × VDRIVE
V
V
μA
pF
0.8
1
0.01
2
Input Capacitance, CIN
6
8
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating State Leakage Current
Floating State Output Capacitance2
VDRIVE − 0.2
V
V
μA
pF
0.4
1
0.01
CONVERSION RATE
Conversion Time
1.25
140
500
ns
ns
kSPS
Track/Hold Acquisition Time2
Full-scale step input
For 2.7 V ≤ VDRIVE ≤ 5.25 V, fSCLK = 20 MHz
Digital inputs = 0 V or VDRIVE
See Table 7
See Table 7
See Table 7
Throughput Rate
POWER REQUIREMENTS
VCC
VDD
VSS
4.75
5
−16.5
2.7
5.25
16.5
−5
V
V
V
V
VDRIVE
5.25
Normal Mode (Static)
IDD
ISS
ICC
370
40
1.5
550
60
2.25
μA
μA
mA
VDD = 16.5 V
VSS = −16.5 V
VCC = 5.5 V
Normal Mode (Operational)
fS = 500 kSPS
IDD
ISS
ICC
1
0.7
3.4
1.2
0.82
4
mA
mA
mA
VDD = 16.5 V
VSS = −16.5 V
VCC = 5.25 V, internal reference enabled
Shutdown Mode
IDD
ISS
ICC
0.01
0.01
0.3
1
1
3
μA
μA
μA
VDD = 16.5 V
VSS = −16.5 V
VCC = 5.25 V
Power Dissipation
Normal Mode (Operational)
46
15
20
1.9
54.5
mW
mW
mW
μW
VDD = +16.5 V, VSS = −16.5 V, VCC = +5.25 V
10 V input range, fS = 100 kSPS
5 V and 0 V to +10 V input range, fS = 100 kSPS
VDD = +16.5 V, VSS = −16.5 V, VCC = +5.25 V
Shutdown Mode
48.75
1 See the Terminology section.
2 Sample tested during initial release to ensure compliance.
3 Refers to Pin DCAPA or Pin DCAPB.
Rev. B | Page 6 of 28
AD7366-5/AD7367-5
TIMING SPECIFICATIONS
AVCC = DVCC = 4.75 V to 5.25 V; VDD = 5 V to 16.5 V; VSS = −16.5 V to −5 V; VDRIVE = 2.7 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted.1
Table 4.
Parameter 2.7 V ≤ VDRIVE ≤ 5.25 V Unit
Test Conditions/Comments
tCONVERT
Conversion time, internal clock. CONVST falling edge to BUSY falling edge.
For the AD7367-5.
For the AD7366-5.
1.25
1.25
10
20
50
μs maꢁ
μs maꢁ
kHz min
MHz maꢁ
ns min
fSCLK
Frequency of serial read clock.
tQUIET
Minimum quiet time required between the end of serial read and the start of the neꢁt
conversion.
t1
t2
t3
t4
10
ns min
ns min
ns min
ns maꢁ
ns maꢁ
ns min
ns min
ns min
ns maꢁ
μs maꢁ
Minimum CONVST low pulse.
40
CONVST falling edge to BUSY rising edge.
BUSY falling edge to MSB valid once CS is low for t4 prior to BUSY going low.
Delay from CS falling edge until Pin 1 (DOUTA) and Pin 23 (DOUTB) are three-state disabled.
Data access time after SCLK falling edge.
SCLK to data valid hold time.
SCLK low pulse width.
SCLK high pulse width.
CS rising edge to DOUTA, DOUTB, high impedance.
0
10
2
t5
t6
t7
t8
20
7
0.3 × tSCLK
0.3 × tSCLK
10
t9
tPOWER-UP
70
Power up time from shutdown mode; time required between CONVST rising edge and
CONVST falling edge.
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10ꢀ to 90ꢀ of VDRIVE) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance. With a load capacitance greater than this value, a digital buffer or latch must be used. See the
Terminology section and Figure 25.
2 The time required for the output to cross is 0.4 V or 2.4 V.
Rev. B | Page 7 of 28
AD7366-5/AD7367-5
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to AGND, DGND
VSS to AGND, DGND
VDRIVE to DGND
−0.3 V to +16.5 V
−16.5 V to +0.3 V
−0.3 V to DVCC
VDD to AVCC
AVCC to AGND, DGND
DVCC to AVCC
(VCC − 0.3 V) to +16.5 V
−0.3 V to +7 V
−0.3 V to +0.3 V
−0.3 V to +7 V
DVCC to DGND
ESD CAUTION
VDRIVE to AGND
−0.3 V to DVCC
AGND to DGND
−0.3 V to +0.3 V
VSS − 0.3 V to VDD + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to AVCC + 0.3 V
10 mA
−40°C to +85°C
−65°C to +150°C
150°C
Analog Input Voltage to AGND
Digital Input Voltage to DGND
Digital Output Voltage to GND
DCAPB, DCAPB Input to AGND
Input Current to Any Pin Eꢁcept Supplies1
Operating Temperature Range
Storage Temperature Range
Junction Temperature
TSSOP Package
θJA Thermal Impedance
θJC Thermal Impedance
Pb-free Temperature, Soldering
Reflow
128°C/W
42°C/W
260(+0)°C
1.5 kV
ESD
1 Transient currents of up to 100 mA do not cause latch-up.
Rev. B | Page 8 of 28
AD7366-5/AD7367-5
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
D
V
A
1
2
24 DGND
OUT
23
D
B
DRIVE
OUT
DV
CC
3
22 BUSY
21 CNVST
20 SCLK
19 CS
AD7366-5/
AD7367-5
4
RANGE1
RANGE0
ADDR
5
TOP VIEW
6
(Not to Scale)
AGND
7
18 REFSEL
AV
CC
17
16
15
14
13
AGND
8
D
A
D B
CAP
9
CAP
V
10
11
12
V
SS
DD
V
V
V
A1
A2
B1
B2
V
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Description
1, 23
DOUTA, DOUT
B
Serial Data Outputs. The data output is supplied to each pin as a serial data stream. The bits are clocked out on
the falling edge of the SCLK input and 12 SCLK cycles are required to access the data from the AD7366-5 while
14 SCLK cycle are required for the AD7367-5. The data simultaneously appears on both pins from the simultaneous
conversions of both ADCs. The data stream consists of the 12 bits of conversion data for the AD7366-5 and 14 bits
for the AD7367-5 and is provided MSB first. If CS is held low for a further 12 SCLK cycles for the AD7366-5 or 14 SCLK
cycles for the AD7367-5, on either DOUTA or DOUTB, the data from the other ADC follows on that DOUT pin. This
allows data from a simultaneous conversion on both ADCs to be gathered in serial format on either DOUTA or
D
OUTB using only one serial port. See the Serial Interface section for more information.
2
3
VDRIVE
DVCC
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
This pin should be decoupled to DGND. The voltage range on this pin is 2.7 V to 5.25 V and may be different than
the voltage at AVCC and DVCC, but should never eꢁceed either by more than 0.3 V.
Digital Supply Voltage, 4.75 V to 5.25 V. The DVCC and AVCC voltages should ideally be at the same potential.
For best performance, it is recommended that the DVCC and AVCC pins be shorted together, to ensure that the
voltage difference between them never eꢁceeds 0.3 V, even on a transient basis. This supply should be decoupled
to DGND. Place 10 μF and 100 nF decoupling capacitors on the DVCC pin.
4, 5
6
RANGE1,
RANGE0
ADDR
Analog Input Range Selection, Logic Inputs. The polarity on these pins determines the input range of the analog
input channels. See the Analog Inputs section and Table 8 for details.
Multipleꢁer Select, Logic Input. This input is used to select the pair of channels to be simultaneously converted,
either Channel 1 of both ADC A and ADC B, or Channel 2 of both ADC A and ADC B. The logic state on this pin is
latched on the rising edge of BUSY to set up the multipleꢁer for the neꢁt conversion.
7, 17
8
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7366-5/AD7367-5. All analog input
signals and any eꢁternal reference signal should be referred to this AGND voltage. Both AGND pins should
connect to the AGND plane of a system. The AGND and DGND voltages ideally should be at the same potential
and must not be more than 0.3 V apart, even on a transient basis.
Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC cores. The AVCC and DVCC voltages
should ideally be at the same potential. For best performance, it is recommended that the DVCC and AVCC pins be
shorted together to ensure that the voltage difference between them never eꢁceeds 0.3 V even on a transient
basis. This supply should be decoupled to AGND. Place 10 μF and 100 nF decoupling capacitors on the AVCC pin.
AVCC
9, 16
10
DCAPA, DCAP
B
Decoupling Capacitor Pins. Decoupling capacitors are connected to these pins to decouple the reference buffer
for each respective ADC. For best performance, it is recommended to use a 680 nF decoupling capacitor on these
pins. Provided the output is buffered, the on-chip reference can be taken from these pins and applied eꢁternally
to the rest of a system.
Negative Power Supply Voltage. This is the negative supply voltage for the high voltage analog input structure
of the AD7366-5/AD7367-5. The supply must be less than or equal to −5 V (see Table 7 for further details).
Place 10 μF and 100 nF decoupling capacitors on the VSS pin.
VSS
11, 12
13, 14
15
VA1, VA2
VB2, VB1
VDD
Analog Inputs of ADC A. These are both single-ended analog inputs. The analog input range on these channels is
determined by the RANGE0 and RANGE1 pins.
Analog Inputs of ADC B. These are both single-ended analog inputs. The analog input range on these channels is
determined by the RANGE0 and RANGE1 pins.
Positive Power Supply Voltage. This is the positive supply voltage for the high voltage analog input structure
of the AD7366-5/AD7367-5. The supply must be greater than or equal to 5 V (see Table 7 for further details).
Place 10 μF and 100 nF decoupling capacitors on the VDD pin.
Rev. B | Page 9 of 28
AD7366-5/AD7367-5
Pin No. Mnemonic
Description
18
REFSEL
Internal/Eꢁternal Reference Selection, Logic Input. If this pin is tied to logic high, the on-chip 2.5 V reference is
used as the reference source for both ADC A and ADC B. In addition, Pin DCAPA and Pin DCAPB must be tied to
decoupling capacitors. If the REFSEL pin is tied to GND, an eꢁternal reference can be supplied to the AD7366-5/
AD7367-5 through the DCAPA and/or DCAPB pins.
19
CS
Chip Select, Active Low Logic Input. This input frames the serial data transfer. When CS is logic low, the output bus
is enabled, and the conversion result is output on DOUTA and DOUTB.
20
21
SCLK
CNVST
Serial Clock, Logic Input. A serial clock input provides the SCLK for accessing the data from the AD7366-5/AD7367-5.
Conversion Start, Logic Input. This pin is edge triggered. On the falling edge of this input, the track/hold goes into
hold mode and the conversion is initiated. If CNVST is low at the end of a conversion, the part goes into power-
down mode. In this case, the rising edge of CNVST instructs the part to power up again.
22
24
BUSY
DGND
Busy Output. BUSY transitions high when a conversion starts and remains high until the conversion completes.
Digital Ground. This is the ground reference point for all digital circuitry on the AD7366-5/AD7367-5. The DGND
pin should connect to the DGND plane of a system. The DGND and AGND voltages should ideally be at the same
potential and must not be more than 0.3 V apart, even on a transient basis.
Rev. B | Page 10 of 28
AD7366-5/AD7367-5
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
1.0
0.8
0.6
0.4
0.2
0
–76
–78
0V TO +10V RANGE
±10V RANGE
±5V RANGE
–80
–82
–0.2
–0.4
AV
V
= 5V, DV = 5V
CC
CC
DD
AV
V
= 5V, DV = 5V
CC
= 15V, V = –15V
SS
CC
–0.6
–0.8
–1.0
–84
–86
= 15V, V = –15V
SS
V
= 3V
DD
DRIVE
V
= 3V
DRIVE
fS = 500kSPS
fS = 500kSPS
T
= 25°C
A
INTERNAL REFERENCE
INTERNAL REFERENCE
0
2000 4000 6000 8000 10000 12000 14000 16000
CODE
10
100
1000
ANALOG INPUT FREQUENCY (kHz)
Figure 3. AD7367-5 Typical DNL
Figure 6. THD vs. Analog Input Frequency
2.0
1.5
AV
DD
= 5V, DV = 5V
–66
–71
–76
–81
–86
CC
CC
V
V
= 15V, V = –15V
SS
= 3V
fSD=RIV5E00kSPS
INTERNAL REFERENCE
±5V RANGE
R
= 2000Ω
IN
1.0
0.5
R
= 1300Ω
IN
R
= 3000Ω
IN
0
R
= 470Ω
IN
R
= 5100Ω
IN
–0.5
–1.0
–1.5
–2.0
AV
DD
= 5V, DV = 5V
CC
CC
V
= 15V, V = –15V
SS
V
= 3V
R
= 240Ω
IN
DRIVE
R
= 56Ω
fS = 500kSPS
IN
T
= 25°C
A
R
= 3900Ω
INTERNAL REFERENCE
IN
0
2000 4000 6000 8000 10000 12000 14000 16000
CODE
10
100
1000
ANALOG INPUT FREQUENCY (kHz)
Figure 4. AD7367-5 Typical INL
Figure 7. THD vs. Analog Input Frequency for Various Source Impedances
0
–20
AV
DD
= 5V, DV = 5V
CC
CC
77
V
= 15V, V = –15V
SS
V
= 3V
DRIVE
fS = 500kSPS, fIN = 50kHz
INTERNAL REFERENCE
SNR = 76dB, SINAD = 75dB
±10V RANGE
–40
75
–60
0V TO +10V RANGE
73
71
69
67
–80
–100
–120
–140
–160
AV
DD
= 5V, DV = 5V
CC
CC
V
V
= 15V, V = –15V
SS
= 3V
fSD=RIV5E00kSPS
INTERNAL REFERENCE
±5V RANGE
10
100
1000
0
50
100
150
200
250
ANALOG INPUT FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 5. AD7367-5 FFT
Figure 8. SINAD vs. Analog Input Frequency
Rev. B | Page 11 of 28
AD7366-5/AD7367-5
–70
–75
–80
–70
–80
V
, ADC A
CC
100mV p-p SINE WAVE ON AV
CC
NO DECOUPLING CAPACITOR
V
= 15V, V = –15V
DD
SS
V
, ADC B
CC
V
= 3V
DRIVE
±5V RANGE
–85
fS = 500kSPS
–90
V
ADC B
DD,
0V TO +10V RANGE
±10V RANGE
–90
–95
–100
–110
–120
V , ADC B
SS
V
, ADC A
DD
–100
–105
–110
AV
DD
= 5V, DV = 5V
CC
CC
V
= 15V, V = –15V
SS
V
= 3V
DRIVE
V
, ADC A
800
SS
fS = 500kSPS
INTERNAL REFERENCE
0
100
200
300
400
500
600
0
200
400
600
1000
1200
FREQUENCY OF INPUT NOISE (kHz)
SUPPLY RIPPLE FREQUENCY (kHz)
Figure 9. Channel-to-Channel Isolation
Figure 11. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
110000
100000
90000
80000
70000
60000
50000
40000
30000
20000
10000
0
106091 CODES
AV
V
= 5V, DV = 5V
CC
CC
DD
31 CODES
344 CODES
40
30
20
10
0
= 15V, V = –15V
SS
V
= 0V TO +10V
V
= 3V
IN
fSD=RIV5E00kSPS
INTERNAL REFERENCE
V
= +5V
IN
V
= +10V
IN
–10
–20
V
= –10V
IN
V
= –5V
250
IN
8191
8192
8193
CODE
8194
8195
8196
100
150
200
300
350
400
450
500
THROUGHPUT RATE (kSPS)
Figure 10. Histogram of Codes for 200k Samples
Figure 12. Analog Input Current vs. Throughput Rate
Rev. B | Page 12 of 28
AD7366-5/AD7367-5
2.5050
2.5045
2.5040
2.5035
2.5030
2.5025
2.5020
2.5015
2.5010
2.5005
2.5000
45
40
35
30
25
20
15
AV
V
= 5V, DV = 5V
CC
CC
DD
= 15V, V = –15V
SS
V
= 3V
fSD=RIV5E00kSPS
INTERNAL REFERENCE
±5V RANGE
0V TO +10V RANGE
±10V RANGE
AV
V
DRIVE
= 5V, DV = 5V
CC
CC
DD
= 15V, V = –15V
SS
V
= 3V,
0
10
20
30
40
50
60
70
80
90
100
150
200
250
300
350
400
450
500
CURRENT (µA)
SAMPLING FREQUENCY (kSPS)
Figure 13. VREF vs. Reference Output Current Drive
Figure 15. Power vs. Sampling Frequency in Normal Mode
0.300
0.250
0.200
0.150
0.100
0.50
0
D
SOURCE CURRENT
OUT
D
OUT
SINK CURRENT
AV
DD
= 5V, DV = 5V
CC
CC
V
= 15V, V = 15V
SS
V
= 3V, fS = 500kSPS
DRIVE
INTERNAL REFERENCE
0
500
1000
1500
2000
2500
CURRENT (µA)
Figure 14. DOUT Source Current vs. (VCC − VOUT ) and
DOUT Sink Current vs. VOUT
Rev. B | Page 13 of 28
AD7366-5/AD7367-5
TERMINOLOGY
Differential Nonlinearity (DNL)
Total Harmonic Distortion (THD)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7366-5/AD7367-5, it is defined as:
2
2
2
2
2
V2 + V3 + V4 + V5 + V6
Integral Nonlinearity (INL)
THD(dB) = 20 log
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale, a single (1)
LSB point below the first code transition and full scale, a point
1 LSB above the last code transition.
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Zero Code Error
Peak Harmonic or Spurious Noise
This is the deviation of the midscale transition (all 1s to all 0s)
from the ideal VIN voltage, that is, AGND – ½ LSB for bipolar
ranges and 2 × VREF − 1 LSB for the unipolar range.
Peak harmonic, or spurious noise, is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2, excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum. However, for
ADCs where the harmonics are buried in the noise floor, it is
a noise peak.
Positive Full-Scale Error
This is the deviation of the last code transition (011…110) to
(011…111) from the ideal (that is, 4 × VREF − 1 LSB or 2 × VREF
– 1 LSB) after the zero code error has been adjusted out.
Channel-to-Channel Isolation
Negative Full-Scale Error
Channel-to-channel isolation is a measure of the level of cross-
talk between any two channels when operating in any of the
input ranges. It is measured by applying a full-scale, 150 kHz
sine wave signal to all unselected input channels and determin-
ing how much that signal is attenuated in the selected channel
with a 50 kHz signal. The figure given is the typical across all
four channels for the AD7366-5/AD7367-5 (see the Figure 9 for
more information).
This is the deviation of the first code transition (10…000) to
(10…001) from the ideal (that is, −4 × VREF + 1 LSB, −2 × VREF
1 LSB, or AGND + 1 LSB) after the zero code error has been
adjusted out.
+
Zero Code Error Match
This is the difference in zero code error across all 12 channels.
Positive Full-Scale Error Match
This is the difference in positive full-scale error across all channels.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with nonlinearities creates distortion
products at the sum, and different frequencies of mfa nfb
where m, n = 0, 1, 2, 3, and so on. Intermodulation distortion
terms are those for which neither m nor n is equal to zero.
For example, the second-order terms include (fa + fb) and
(fa − fb), while the third-order terms include (2fa + fb),
(2fa − fb), (fa + 2fb), and (fa − 2fb).
Negative Full-Scale Error Match
This is the difference in negative full-scale error across all channels.
Track-and-Hold Acquisition Time
The track-and-hold amplifier returns to track mode at the end
of a conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ½ LSB, after the end of conversion.
The AD7366-5/AD7367-5 is tested using the CCIF standard
where two input frequencies near the top end of the input
bandwidth are used. In this case, the second-order terms are
usually distanced in frequency from the original sine waves,
while the third-order terms are usually at a frequency close to
the input frequencies. As a result, the second- and third-order
terms are specified separately. The calculation of the intermodula-
tion distortion is as per the THD specification, where it is the ratio
of the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in decibels.
Signal-to-Noise (+ Distortion) Ratio (SINAD)
This ratio is the measured ratio of signal-to-noise (+ distortion)
at the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitiza-
tion process: the more levels, the smaller the quantization noise.
The theoretical signal-to-noise (+ distortion) ratio for an ideal
N-bit converter with a sine wave input is given by:
Signal-to-Noise (+ Distortion) = (6.02N + 1.76) dB
Thus, for a 12-bit converter, this is 74 dB.
Rev. B | Page 14 of 28
AD7366-5/AD7367-5
Power Supply Rejection Ration (PSRR)
It is expressed in ppm using the following equation:
Variations in power supply affect the full-scale transition but
not the converter’s linearity. PSRR is the maximum change in
the full-scale transition point due to a change in power supply
voltage from the nominal value (see Figure 11).
V
REF (25°C)−VREF (T _ HYS)
V
HYS (ppm) =
× 106
V
REF (25°C)
where:
V
REF(25°C) is VREF at 25°C.
Thermal Hysteresis
VREF(T_HYS) is the maximum change of VREF at T_HYS+
or T_HYS−.
Thermal hysteresis is defined as the absolute maximum change
of reference output voltage after the device is cycled through
temperature from either
T_HYS+ = +25°C to TMAX to +25°C
or
T_HYS− = +25°C to TMIN to +25°C
Rev. B | Page 15 of 28
AD7366-5/AD7367-5
THEORY OF OPERATION
If the internal reference is the preferred option, the user must
tie the REFSEL pin logic high. Alternatively, if REFSEL is tied to
GND, an external reference can be supplied to both ADCs
through the DCAPA and DCAPB pins.
CIRCUIT INFORMATION
The AD7366-5/AD7367-5 are fast, dual, 2-channel, 12-/14-bit,
bipolar input, simultaneous sampling, serial ADCs. The
AD7366-5/AD7367-5 can accept bipolar input ranges of 10 V
and 5 V. They can also accept a 0 V to 10 V unipolar input
range. The AD7366-5/AD7367-5 require VDD and VSS dual
supplies for the high voltage analog input structure. These
supplies must be greater than or equal to the analog input range
(see Table 7 for the minimum requirements on these supplies
for each analog input range). The AD7366-5/AD7367-5 require
a low voltage 4.75 V to 5.25 V VCC supply to power the ADC core.
The analog inputs are configured as two single-ended inputs for
each ADC. The various different input voltage ranges can be
selected by programming the RANGE bits as shown in Table 8.
CONVERTER OPERATION
The AD7366-5/AD7367-5 have two successive approximation
ADCs, each based around two capacitive DACs. Figure 16 and
Figure 17 show simplified schematics of an ADC in acquisition
and conversion phases, respectively. The ADC is comprised of
control logic, a SAR, and a capacitive DAC. In Figure 16 (the
acquisition phase), SW2 is closed, SW1 is in Position A, the
comparator is held in a balanced condition, and the sampling
capacitor arrays acquire the signal on the input.
Table 7. Reference and Supply Requirements for Each
Analog Input Range
Selected
Analog Input
Range (V)
Full-Scale
Input
Range (V)
Reference
Voltage (V)
Minimum
AVCC (V) VDD/VSS (V)
10
+2.5
+3.0
+2.5
+3.0
+2.5
+3.0
10
+5
+5
+5
+5
+5
+5
10
12
12
5
5
5
CAPACITIVE
DAC
6
6
0 to +10
0 to +10
0 to +12
+10/AGND
+12/AGND
A
V
IN
CONTROL
LOGIC
SW1
B
SW2
Each AD7366-5/AD7367-5 contains two on-chip, track-and-hold
amplifiers, two successive approximation ADCs, and a serial
interface with two separate data output pins. The device is housed
in a 24-lead TSSOP, offering the user considerable space-saving
advantages over alternative solutions.
COMPARATOR
AGND
Figure 16. ADC Acquisition Phase
When the ADC starts a conversion (see Figure 17), SW2 opens,
and SW1 moves to Position B, causing the comparator to
become unbalanced. The control logic and the charge redis-
tribution DAC is used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is
balanced again, the conversion is complete. The control logic
generates the ADC output code.
CNVST
The AD7366-5/AD7367-5 require a
CNVST
signal to start a
conversion. On the falling edge of
, both track-and-
holds are placed into hold mode, and the conversions are
initiated. The BUSY signal goes high to indicate that the
conversions are taking place. The clock source for each
successive approximation ADC is provided by an internal
oscillator. The BUSY signal goes low to indicate the end of
conversion. On the falling edge of BUSY, the track-and-hold
returns to track mode. Once the conversion is finished, the
serial clock input accesses data from the part.
CAPACITIVE
DAC
A
V
IN
CONTROL
LOGIC
SW1
The AD7366-5/AD7367-5 have an on-chip 2.5 V reference that
can be disabled when an external reference is preferred. If the
internal reference is to be used elsewhere in a system, the output
from DCAPA and DCAPB must first be buffered. On power-up, the
REFSEL pin must be tied to a high or low logic state to select
either the internal or external reference option.
B
SW2
COMPARATOR
AGND
Figure 17. ADC Conversion Phase
Rev. B | Page 16 of 28
AD7366-5/AD7367-5
TRANSFER FUNCTION
ANALOG INPUTS
The output coding of the AD7366-5/AD7367-5 is twos comple-
ment. The designed code transitions occur at successive integer
LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size is
dependent on the analog input range selected (see Table 10).
The ideal transfer characteristic is shown in Figure 19.
Each ADC in the AD7366-5/AD7367-5 has two single-ended
analog inputs. Figure 18 shows the equivalent circuit of the
analog input structure of the AD7366-5/AD7367-5. The two
diodes provide ESD protection. Care must be taken to ensure
that the analog input signals never exceed the supply rails by
more than 300 mV. Otherwise, these diodes become forward-
biased and start conducting current into the substrate. The
diodes can conduct up to 10 mA without causing irreversible
damage to the part. The resistors are lumped components made
up of the on resistance of the switches. The value of these resistors
is typically 170 Ω. Capacitor C1 can primarily be attributed to
pin capacitance while Capacitor C2 is the sampling capacitor of
the ADC. The total lumped capacitance of C1 and C2 is approxi-
mately 9 pF for the 10 V input range and approximately 13 pF
for all other input ranges.
Table 10. LSB Sizes for Each Analog Input Range
AD7366-5
AD7367-5
Input
Range
Full-Scale
Range
LSB Size
(mV)
Full-Scale
Range
LSB Size
(mV)
10 V
5 V
20 V/4096
10 V/4096
4.88
2.44
2.44
20 V/16384
10 V/16384
10 V/16384
1.22
0.61
0.61
0 V to +10V 10 V/4096
011...111
011...110
V
DD
000...001
000...000
111...111
D
C2
R1
V
0
IN
C1
D
100...010
100...001
100...000
V
SS
Figure 18. Equivalent Analog Input Structure
–FSR/2 + 1LSB
+FSR/2 – 1LSB
The AD7366-5/AD7367-5 can handle true bipolar input voltages.
The analog input can be set to one of three ranges: 10 V, 5 V, or
0 V to +10 V. The logic levels on Pin RANGE0 and Pin RANGE1
determine which input range is selected as outlined in Table 8.
These range bits should not be changed during the acquisition
time prior to a conversion, but can change at any other time.
0V
ANALOG INPUT
Figure 19. Transfer Characteristic
Track-and-Hold
The track-and-hold on the analog input of the AD7366-5/
AD7367-5 allows the ADC to accurately convert an input sine
wave of full-scale amplitude to 12-/14-bit accuracy. The input
bandwidth of the track-and-hold is greater than the Nyquist
rate of the ADC. The AD7366-5/AD7367-5 can handle
frequencies up to 35 MHz.
Table 8. Analog Input Range Selection
RANGE0
RANGE1
Range Selected
0
1
0
1
0
0
1
1
10 V
5 V
0 V to +10 V
Do not program
The track-and-hold enters its tracking mode once the BUSY
CS
signal goes low after the
falling edge. The time required to
The parts require VDD and VSS dual supplies for the high voltage
analog input structures. These supplies must be greater than or
equal to 5 V (see Table 7 for the requirements on these supplies).
The AD7366-5/AD7367-5 require a low voltage 4.75 V to 5.25 V
AVCC supply to power the ADC core, a 4.75 V to 5.25 V DVCC
supply for digital power, and a 2.7 V to 5.25 V VDRIVE supply for
interface power.
acquire an input signal depends on how quickly the sampling
capacitor is charged. With zero source impedance, 140 ns is
sufficient to acquire the signal to the 12-bit level for the AD7366-5
and the 14-bit level for the AD7367-5. The acquisition time for
the 10 V, 5 V, and 0 V to +10 V ranges to settle to within ½ LSB
is typically 140 ns. The ADC goes back into hold mode on the
CNVST
falling edge of
.
Channel selection is made via the ADDR pin as shown in Table 9.
The logic level on the ADDR pin is latched on the rising edge of
the BUSY signal for the next conversion, not the one in progress.
When power is first supplied to the AD7366-5/AD7367-5, the
default channel selection is VA1 and VB1.
The acquisition time required is calculated using the following
formula:
t
ACQ = 10 × ((RSOURCE + R) × C)
where:
C is the sampling capacitance.
R is the resistance seen by the track-and-hold amplifier looking
at the input.
Table 9. Channel Selection
ADDR
Channels Selected
0
1
VA1, VB1
VA2, VB2
RSOURCE should include any extra source impedance on the
analog input.
Rev. B | Page 17 of 28
AD7366-5/AD7367-5
TYPICAL CONNECTION DIAGRAM
Unlike other bipolar ADCs, the AD7366-5/AD7367-5 do not
have a resistive analog input structure. On the AD7366-5/
AD7366-5, the bipolar analog signal is sampled directly onto
the sampling capacitor. This gives the devices high analog input
impedance. The analog input impedance can be calculated from
the following formula:
Figure 20 shows a typical connection diagram for the AD7366-5/
AD7367-5. In this configuration, the AGND pin is connected
to the analog ground plane of the system, and the DGND pin
is connected to the digital ground plane of the system. The
analog inputs on the AD7366-5/AD7367-5 accept bipolar
single-ended signals. The AD7366-5/AD7367-5 can operate
with either an internal or an external reference. In Figure 20, the
AD7366-5/AD7367-5 is configured to operate with the internal
2.5 V reference. A 680 nF decoupling capacitor is required when
operating with the internal reference.
Z = 1/(fS × CS)
where:
fS is the sampling frequency.
CS is the sampling capacitor value.
CS depends on the analog input range chosen (see the Analog
Inputs section). When operating at 500 kSPS, the analog input
impedance is typically 260 kꢀ for the 10 V range. As the
sampling frequency is reduced, the analog input impedance
further increases. As the analog input impedance increases, the
current required to drive the analog input therefore, decreases
(see Figure 7 for more information).
The AVCC and DVCC pins are connected to a 5 V supply voltage.
The VDD and VSS are the dual supplies for the high voltage analog
input structures. The voltage on these pins must be greater than
or equal to 5 V (see Table 7 for more information). The VDRIVE pin
is connected to the supply voltage of the microprocessor. The
voltage applied to the VDRIVE input controls the voltage of the
serial interface. VDRIVE can be set to 3 V or 5 V.
+
0.1µF
+5V SUPPLY
+5V TO +16.5V
SUPPLY
+
+
+
+
+
10µF
0.1µF
0.1µF
10µF
V
DV
AV
CC CC
+3V OR +5V SUPPLY
+
DD
V
DRIVE
V
V
A1
A2
0.1µF
10µF
AD7366-5/
AD7367-5
CS
ANALOG INPUTS ±10V,
±5V, AND 0V TO +10V
SCLK
CNVST
D
D
A
B
OUT
OUT
V
V
B1
B2
BUSY
ADDR
V
REFSEL
DRIVE
D
D
A
B
V
CAP
SERIAL
INTERFACE
+
RANGE0
RANGE1
680nF
CAP
+
680nF
AGND
SS
DGND
–16.5V TO –5V
SUPPLY
0.1µF
10µF
+
+
Figure 20. Typical Connection Diagram for 10 V Range Using Internal Reference
Rev. B | Page 18 of 28
AD7366-5/AD7367-5
VDRIVE
DRIVER AMPLIFIER CHOICE
The AD7366-5/AD7367-5 also have a VDRIVE feature to control
the voltage at which the serial interface operates. VDRIVE allows
the ADC to easily interface to both 3 V and 5 V processors. For
example, if the AD7366-5/AD7367-5 is operated with a VCC of
5 V, the VDRIVE pin could be powered from a 3 V supply, allowing
a large dynamic range with low voltage digital processors. Thus,
the AD7366-5/AD7367-5 could be used with the 10 V input
range while still being able to interface to 3 V digital parts.
Each AD7366-5/AD7367-5 has a total of four analog inputs,
which operate in single-ended mode. Both ADC analog inputs
can be programmed to one of the three analog input ranges. In
applications where the signal source is high impedance, it is
recommended to buffer the signal before applying it to the
ADC analog inputs. Figure 21 shows the configuration of the
AD7366-5/AD7367-5 in single-ended mode.
In applications where the THD and SNR are critical specifi-
cations, the analog input of the AD7366-5/AD7367-5 should be
driven from a low impedance source. Large source impedances
significantly affect the ac performance of the ADC and can
necessitate the use of an input buffer amplifier.
REFERENCE
The AD7366-5/AD7367-5 can operate with either the internal
2.5 V on-chip reference or an externally applied reference. The
logic state of the REFSEL pin determines whether the internal
reference is used. The internal reference is selected for both ADCs
when the REFSEL pin is tied to logic high. If the REFSEL pin is
tied to GND, an external reference can be supplied through the
DCAPA and DCAPB pins. On power-up, the REFSEL pin must be
tied to either a low logic or high logic state for the part to operate.
Suitable reference sources for the AD7366-5/AD7367-5 include
the AD780, AD1582, ADR431, REF193, and ADR391.
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance depends on the amount of THD that can be tolerated
in the application. The THD increases as the source impedance
increases and performance degrades. Figure 7 shows THD vs.
the analog input frequency for various source impedances.
Depending on the input range and analog input configuration
selected, the AD7366-5/AD7367-5 can handle source
impedances as illustrated in Figure 7.
The internal reference circuitry consists of a 2.5 V band gap
reference and a reference buffer. When operating the AD7366-5/
AD7367-5 in internal reference mode, the 2.5 V internal reference
is available at the DCAPA and DCAPB pins, which should be
decoupled to AGND using a 680 nF capacitor. It is recommended
that the internal reference be buffered before applying it elsewhere
in the system. The internal reference is capable of sourcing up
to 150 μA with an analog input range of 10 V and 70 ꢁA for
both the 5 V range and 0 V to +10 V range
Due to the programmable nature of the analog inputs on the
AD7366-5/AD7367-5, the choice of op amp used to drive the
inputs is a function of the particular application and depends
on the selected analog input voltage ranges.
The driver amplifier must be able to settle for a full-scale step to
a 14-bit level, 0.0061%, in less than the specified acquisition time
of the AD7366-5/AD7367-5. An op amp such as the AD8021
meets this requirement when operating in single-ended mode.
The AD8021 needs an external compensating NPO type of
capacitor. The AD8022 can also be used in high frequency
applications where a dual version is required. For lower frequency
applications, recommended op amps are the AD797, AD845,
and AD8610.
If the internal reference operation is required for the ADC
conversion, the REFSEL pin must be tied to logic high on power-
up. The reference buffer requires 70 ꢁs to power up and charge
the 680 nF decoupling capacitor during the power-up time.
The AD7366-5/AD7367-5 is specified for a 2.5 V to 3 V reference
range. When a 3 V reference is selected, the ranges are 12 V,
6 V, and 0 V to +12 V. For these ranges, the VDD and VSS supply
must be greater than or equal to the +12 V and −12 V, respectively.
V+
10µF
+5V
+10V/+5V
0.1µF
+
AGND
AD8021
V
A1
V
DV /AV
CC CC
DD
–10V/–5V
1kꢀ
AD7366-5/
AD7367-5*
15pF
V
1kꢀ
SS
0.1µF
10µF
C
= 10pF
COMP
V–
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 21. Typical Connection Diagram with the AD8021
Driving the Analog Input in Single-Ended Mode
Rev. B | Page 19 of 28
AD7366-5/AD7367-5
MODES OF OPERATION
The mode of operation for the AD7366-5/AD7367-5 is selected
The BUSY signal remains high for the duration of the conversion.
CS
CNVST
by the (logic) state of the
signal at the end of a conver-
The
pin must be brought low to bring the data bus out of
sion. There are two possible modes of operation: normal mode
and shutdown mode. These modes of operation are designed to
provide flexible power management options, which can be
chosen to optimize the power dissipation/throughput rate
ratio for differing application requirements.
three-state; subsequently 12 SCLK cycles are required to read
the conversion result from the AD7366-5, while 14 SCLK cycles
are required to read from the AD7367-5. The DOUT lines return
CS
CS
to three-state only when
is brought high. If
is left low for
a further 12 SCLK cycles for the AD7366-5 or 14 SCLK cycles
for the AD7367-5, the result from the other on-chip ADC is
also accessed on the same DOUT line, as shown in Figure 27 and
Figure 28 (see the Serial Interface section).
NORMAL MODE
Normal mode is intended for applications needing fast
throughput rates because the user does not have to worry
about any power-up times (with the AD7366-5/AD7367-5
remaining fully powered at all times). Figure 22 shows the
normal mode of operation for the AD7366-5, while Figure 23
illustrates normal mode for the AD7367-5.
After 24 SCLK cycles have elapsed for the AD7366-5 and 28 SCLK
cycles have elapsed for the AD7367-5, the DOUT line returns to
th
th
CS
three-state when
is brought high (not on the 24 or 28 SCLK
CS
falling edge). If
is brought high prior to this, the DOUT line
CS
returns to three-state at that point. Thus,
must be brought
CNVST
The conversion is initiated on the falling edge of
described in the Circuit Information section. To ensure that
CNVST
as
high once the read is completed because the bus does not
automatically return to three-state upon completion of the
dual result read.
the part remains fully powered up at all times,
at a logic high state prior to the BUSY signal going low. If
CNVST
must be
Once a data transfer is complete and DOUTA and DOUTB have
returned to three-state, another conversion can be initiated after
the quiet time, tQUIET, has elapsed by bringing
is at a logic low state when the BUSY signal goes low,
the analog circuitry powers down and the part ceases converting.
CNVST
low again.
t1
CNVST
tQUIET
t2
BUSY
tCONVERT
t3
CS
SCLK
SERIAL READ OPERATION
1
12
Figure 22. Normal Mode Operation for the AD7366-5
t1
CNVST
BUSY
tQUIET
t2
tCONVERT
t3
CS
SCLK
SERIAL READ OPERATION
1
14
Figure 23. Normal Mode Operation for the AD7367-5
Rev. B | Page 20 of 28
AD7366-5/AD7367-5
POWER-UP TIMES
SHUTDOWN MODE
As described in the Shutdown Mode section, the AD7366-5/
AD7367-5 have one power-down mode. This section deals with
the power-up time required when coming out of this mode. It
should be noted that these power-up times apply with the
recommended capacitors in place on the DCAPA and DCAPB pins.
Shutdown mode is intended for use in applications where slow
throughput rates are required. Shutdown mode is suited to
applications where a series of conversions performed at a
relatively high throughput rate are followed by a long period of
inactivity and, thus, shutdown. When the AD7366-5/AD7367-5
are in full power-down, all analog circuitry is powered down.
CNVST
To power up from shutdown,
must be brought high and
remain high for a minimum of 70 μs, as shown in Figure 24.
CNVST
The falling edge of
initiates the conversion. The BUSY
When power supplies are first applied to the AD7366-5/AD7367-5,
output subsequently goes high to indicate that the conversion is
in progress. Once the conversion is completed, the BUSY output
CNVST
the ADC can power up with
logic state. Before attempting a valid conversion,
be brought high and remain high for the recommended power-
CNVST
in either the low or high
CNVST
must
CNVST
returns low. If the
signal is at logic low when BUSY
goes low, the part enters shutdown at the end of the conversion
phase. While the part is in shutdown mode, the digital output
code from the last conversion on each ADC can still be read
up time of 70 μs.
can then be brought low to initiate a
conversion. With the AD7366-5/AD7367-5, no dummy conversion
is required before valid data can be read from the DOUT pins.
CS
from the DOUT pins. To read the DOUT data,
low as described in the Serial Interface section. The DOUT pins
CS
must be brought
If it is intended to place the part in shutdown mode when the
supplies are first applied, the AD7366-5/AD7367-5 must be
return to three-state once
is brought back to logic high.
CNVST
powered up, and a conversion initiated. However,
To exit full power-down and to power up the AD7366-5/
should remain in the logic low state, and when the BUSY signal
goes low, the part enters shutdown.
CNVST
AD7367-5, a rising edge of
required power-up time has elapsed,
low again to initiate another conversion, as shown in Figure 24
is required. After the
CNVST
may be brought
Once supplies are applied to the AD7366-5/AD7367-5, sufficient
time must be allowed for any external reference to power up
and to charge the various reference buffer decoupling capacitors
to their final values.
tPOWER-UP
ENTERS SHUTDOWN
CNVST
BUSY
t2
tCONVERT
t3
CS
SCLK
SERIAL READ OPERATION
12
1
Figure 24. Autoshutdown Mode for AD7366-5
Rev. B | Page 21 of 28
AD7366-5/AD7367-5
SERIAL INTERFACE
Figure 25 and Figure 26 show the detailed timing diagram for
serial interfacing to the AD7366-5 and the AD7367-5. On the
CS
On the rising edge of , the conversion is terminated, and
CS
DOUTA and DOUTB return to three-state. If
is not brought high
CNVST
falling edge of
, the AD7366-5/AD7367-5 simultaneously
but is instead held low for an additional 14 SCLK cycles, the
data from the other DOUT pin follows on the selected DOUT pin.
Note that the second serial result from the AD7366-5 is
preceded by two zeros. See Figure 27 and Figure 28, where
DOUTA is shown. In this case, the DOUT line in use returns to
convert the selected channels. These conversions are performed
CNVST
using the on-chip oscillator. After the falling edge of
,
the BUSY signal goes high, indicating that the conversion has
started. The BUSY signal returns low when the conversion has
CS
been completed. The data can now be read from the DOUT pins.
three-state on the rising edge of
.
CS
CS
The
and SCLK signals are required to transfer data from the
If the falling edge of SCLK coincides with the falling edge of
,
AD7366-5/AD7367-5. The AD7366-5/AD7367-5 have two
output pins corresponding to each ADC. Data can be read from
the AD7366-5/ AD7367-5 using both DOUTA and DOUTB.
Alternatively, a single output pin of the user’s choice can be used.
The SCLK input signal provides the clock source for the serial
the falling edge of SCLK is not acknowledged by the AD7366-5/
AD7367-5, and the next falling edge of SCLK is the first registered
CS
after the falling edges of the
.
CS
The
pin can be brought low before the BUSY signal goes low,
CS
indicating the end of a conversion. When is at a logic low state,
the data bus is brought out of three-state. This feature can be
used to ensure that the MSB is valid on the falling edge of BUSY
CS
interface. The
goes low to access data from the AD7366-
CS
5/AD7367-5. The falling edge of
takes the bus out of three-
state and clocks out the MSB of the conversion result. The data
stream consists of 12 bits of data for the AD7366-5 and 14 bits of
data for the AD7367-5, MSB first. The first bit of the conversion
CS
by bringing
goes low. The dotted
illustrates this feature.
low a minimum of t4 before the BUSY signal
CS
line in Figure 22 and Figure 23
CS
result is valid on the first SCLK falling edge after the
falling
edge. The subsequent 11-bits/ 13-bits of data for the AD7366-
5/AD7367-5, respectively, are clocked out on the falling edge of
the SCLK signal. A minimum of 12 clock pulses must be
provided to the AD7366-5 to access each conversion result, and
a minimum of 14 clock pulses must be provided to the AD7367-
5 to access the conversion result. Figure 25 shows how a 12
SCLK read is used to access the conversion results for the
AD7366-5, and Figure 26 illustrates the case for the AD7367-5
with a 14 SCLK read.
CS
Alternatively, the
pin can be tied to a low logic state continu-
ously. In this case, the DOUT pins never enter three-state, and the
data bus is continuously active. Under these conditions, the MSB
of the conversion result for the AD7366-5/AD7367-5 is available
on the falling edge of the BUSY signal. The next most significant
bit is available on the first SCLK falling edge after the BUSY
signal has gone low. This mode of operation enables the user to
read the MSB as soon as it is made available by the converter.
CS
t8
3
4
5
12
SCLK
1
2
t9
t7
t5
t6
t4
D
D
A
B
OUT
DB10
DB9
DB8
DB2
DB1
DB0
THREE-STATE
OUT
THREE-
STATE
DB11
Figure 25. Serial Interface Timing Diagram for the AD7366-5
CS
t8
3
4
5
14
SCLK
1
2
t9
t7
t5
t6
t4
D
D
A
OUT
DB12
DB11
DB10
DB2
DB1
DB0
B
THREE-STATE
OUT
THREE-
STATE
DB13
Figure 26. Serial Interface Timing Diagram for the AD7367-5
Rev. B | Page 22 of 28
AD7366-5/AD7367-5
CS
t8
SCLK
3
4
5
1
2
10
11
12
13
14
26
t7
t4
t5
t6
DB10
DB9
DB1
DB0
A
DB11
B
DB1
DB0
0
0
D
A
B
B
A
A
A
OUT
THREE-
STATE
THREE-
STATE
DB11
A
Figure 27. Reading Data from Both ADCs on One DOUT Line with 24 SCLKs for the AD7366-5
CS
t8
SCLK
3
4
5
1
2
12
13
14
15
28
t7
t3
t5
t6
DB12A
DB11A
DB1A
DB0A
DB13B
DB12B
DB1B
DB0B
D
A
OUT
THREE-
STATE
THREE-
STATE
DB13A
Figure 28. Reading Data from Both ADCs on One DOUT Line with 28 SCLKs for the AD7367-5
Rev. B | Page 23 of 28
AD7366-5/AD7367-5
MICROPROCESSOR INTERFACING
The serial interface on the AD7366-5/AD7367-5 allows the
parts to be directly connected to a range of different micro-
processors. This section explains how to interface the AD7366-5/
AD7367-5 with some more common microcontrollers and DSP
serial interface protocols.
Table 11. SPORT0 Control Register Setup
Setting
Description
TFSW = RFSW = 1
Alternate framing.
INVRFS = INVTFS = 1 Active low frame signal.
DTYPE = 00
SLEN = 1111
Right justify data.
16-bit data-word (or can be set to 1101
for 14-bit data-word).
AD7366-5/AD7367-5 TO ADSP-218x
The ADSP-218x family of DSPs interfaces directly to the
AD7366-5/AD7367-5 with no glue logic required. The VDRIVE
pin of the AD7366-5/AD7367-5 takes the same supply voltage
as that of the ADSP-218x. This allows the ADC to operate at a
higher supply voltage than its serial interface and therefore, the
ADSP-218x, if necessary. The connection diagram in Figure 29
shows both DOUTA and DOUTB of the AD7366-5/AD7367-5
connected to both serial ports of the ADSP-218x. The SPORT0
and SPORT1 control registers should be set up as shown in
Table 11 and Table 12.
ISCLK = 1
TFSR = RFSR = 1
IRFS = 0
Internal serial clock.
Frame every word.
ITFS = 1
Table 12. SPORT1 Control Register Setup
Setting
TFSW = RFSW = 1
INVRFS = INVTFS = 1 Active low frame signal.
DTYPE = 00
SLEN = 1111
Description
Alternate framing.
Right justify data.
16-bit data-word (or can be set to 1101
for 14-bit data-word).
Eꢁternal serial clock.
Frame every word.
ADSP-218x*
AD7366-5/
AD7367-5*
SCLK
SCLK0
ISCLK = 0
TFSR = RFSR = 1
IRFS = 0
SCLK1
TFS0
RFS0
RFS1
DR0
CS
ITFS = 1
The ADSP-218x has the TFS0 and RFS0 of the SPORT0 and the
RFS1 of SPORT1 tied together. TFS0 is set as an output, and both
RFS0 and RFS1 are set as inputs. The DSP operates in alternate
framing mode, and the SPORT control registers are set up as
described in Table 11 and Table 12. The frame synchronization
D
D
A
B
OUT
DR1
OUT
BUSY
IRQn
CNVST
FLn
V
DRIVE
CS
signal generated on the TFS0 is tied to
.
V
The AD7366-5/AD7367-5 BUSY line provides an interrupt to
the ADSP-218x when the conversion is complete. The conversion
results can then be read from the AD7366-5/AD7367-5 using a
DD
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 29. Interfacing the AD7366-5/AD7367-5 to the ADSP-218x
IRQn
read operation. When an interrupt is received on
from the
BUSY signal, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS and, therefore, the
reading of data.
Rev. B | Page 24 of 28
AD7366-5/AD7367-5
AD7366-5/AD7367-5 TO TMS320VC5506
AD7366-5/AD7367-5 TO ADSP-BF53x
The serial interface on the TMS320VC5506 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
The ADSP-BF53x family of DSPs interfaces directly to the
AD7366-5/AD7367-5 with no glue logic required. The availability
of secondary receive registers on the serial ports of the Blackfin®
DSPs means that only one serial port is necessary to read from
both DOUTA and DOUTB pins simultaneously. Figure 30 shows
DOUTA and DOUTB of the AD7366-5/AD7367-5 connected to
Serial Port 0 of the ADSP-BF53x. The SPORT0 Receive
CS
AD7366-5/AD7367-5. The
input allows easy interfacing
between the TMS320VC5506 and the AD7366-5/AD7367-5
with no glue logic required. The serial ports of the TMS320VC5506
are set up to operate in burst mode with internal CLKX0 (Tx
serial clock on Serial Port 0) and FSX0 (Tx frame sync from
Serial Port 0). The connection diagram is shown in Figure 31.
The serial port control registers (SPC) must be setup as shown
in Table 15.
Configuration 1 register and SPORT0 Receive Configuration 2
register should be set up as outlined in Table 13 and Table 14.
ADSP-BF53x*
SPORT0
AD7366-5/
AD7367-5*
SERIAL
DEVICE A
(PRIMARY)
TMS320VC5506*
AD7366-5/
AD7367-5*
D
A
DR0PRI
RCLKO
OUT
SCLK
SCLK
CLKX0
CLKR0
CLKX1
CLKR1
DR0
CS
BUSY
RFS0
RXINPUTS
PFn
CNVST
D
D
A
B
OUT
D
B
DR0SEC
OUT
DR1
OUT
SERIAL
DEVICE B
V
DRIVE
CS
FSX0
FSR0
FSR1
INTn
(SECONDARY)
V
DD
*ADDITIONAL PINS OMITTED FOR CLARITY.
BUSY
Figure 30. Interfacing the AD7366-5/AD7367-5 to the ADSP-BF53x
CNVST
XF
V
DRIVE
Table 13. SPORT0 Receive Configuration 1 Register
(SPORT0_RCR1) Setup
V
*ADDITIONAL PINS OMITTED FOR CLARITY.
DD
Setting
Description
Figure 31. Interfacing the AD7366-5/AD7367-5 to the TMS320VC5506
RCKFE = 1
LRFS = 1
RFSR = 1
Sample data with falling edge of RSCLK.
Active low frame signal.
Frame every word.
Internal RFS used.
Table 15. Serial Port Control Register Setup
SPC
FO
FSM
MCM
TXM
IRFS = 1
SPC0
SPC1
0
0
1
1
1
0
1
0
RLSBIT = 0
RDTYPE = 00
IRCLK = 1
RSPEN = 1
SLEN = 1111
Receive MSB first.
Zero fill.
Internal receive clock.
Receive enabled.
16-bit data-word (or can be set to 1101 for
14-bit data-word).
The VDRIVE pin of the AD7366-5/AD7367-5 takes the same
supply voltage as that of the TMS320VC5506. This allows the
ADC to operate at a higher voltage than its serial interface and,
therefore, the TMS320VC5506, if necessary.
TFSR = RFSR = 1
As with the previous interfaces, conversion can be initiated
from the TMS320VC5506 or from an external source, and the
processor is interrupted when the conversion sequence is
complete.
Table 14. SPORT0 Receive Configuration 2 Register
(SPORT0_RCR2) Setup
Setting
Description
RXSE = 1
Secondary side enabled.
SLEN = 1111
16-bit data-word (or can be set to 1101 for
14-bit data-word).
Rev. B | Page 25 of 28
AD7366-5/AD7367-5
Normal operation of the ESSI is selected by making MOD = 0 in
the CRB register. Set the word length to 16 by setting Bit WL1 = 1
and Bit WL0 = 0 in the CRA register. The FSP bit in the CRB
register should be set to 1 so that the frame sync is negative.
AD7366-5/AD7367-5 TO DSP563xx
The connection diagram in Figure 32 shows how the AD7366-5/
AD7367-5 can be connected to the enhanced synchronous
serial interface (ESSI) of the DSP563xx family of DSPs from
Motorola. There are two on-board ESSIs, and each is operated in
synchronous mode (Bit SYN = 1 in the CRB register) with
internally generated word length frame sync for both Tx and Rx
(Bit FSL1 = 0 and Bit FSL0 = 0 in the CRB register).
In Figure 32, the serial clock is taken from the ESSI0 so the SCK0
pin must be set as an output (SCKD = 1) while the SCK1 pin is set
as an input (SCKD = 0). The frame sync signal is taken from SC02
on ESSI0, so SCD2 = 1, while on ESSI1, SCD2 = 0; therefore, SC12
is configured as an input. The VDRIVE pin of the AD7366-5/
AD7367-5 takes the same supply voltage as that of the DSP563xx.
This allows the ADC to operate at a higher voltage than its
serial interface and, therefore, the DSP563xx, if necessary.
DSP563xx*
SCK0
AD7366-5/
AD7367-5*
SCLK
SCK1
SRD0
SRD1
SC02
D
D
A
OUT
B
OUT
CS
SC12
IRQn
PBn
BUSY
CNVST
V
DRIVE
V
*ADDITIONAL PINS OMITTED FOR CLARITY.
DD
Figure 32. Interfacing the AD7366-5/AD7367-5 to the DSP563xx
Rev. B | Page 26 of 28
AD7366-5/AD7367-5
APPLICATION HINTS
To avoid radiating noise to other sections of the board, com-
ponents such as clocks with fast switching signals, should be
shielded with digital ground and should never be run near the
analog inputs. Avoid crossover of digital and analog signals. To
reduce the effects of feedthrough within the board, traces should
be run at right angles to each other. A microstrip technique is
the best method, but its use may not be possible with a double-
sided board. In this technique, the component side of the board
is dedicated to ground planes, and signals are placed on the
other side.
LAYOUT AND GROUNDING
The printed circuit board that houses the AD7366-5/AD7367-5
should be designed so that the analog and digital sections are
confined to their own separate areas of the board. This design
facilitates the use of ground planes that can be easily separated.
To provide optimum shielding for ground planes, a minimum
etch technique is generally the best option. All AGND pins on
the AD7366-5/AD7367-5 should be connected to the AGND
plane. Digital and analog ground pins should be joined in only
one place. If the AD7366-5/AD7367-5 are in a system where
multiple devices require an AGND and DGND connection, the
connection should still be made at only one point. A star point
should be established as close as possible to the ground pins on
the AD7366-5/AD7367-5.
Good decoupling is also important. All analog supplies should
be decoupled with 10 ꢁF tantalum capacitors in parallel with
0.1 ꢁF capacitors to AGND. To achieve the best results from
these decoupling components, they must be placed as close as
possible to the device, ideally right up against the device. The
0.1 ꢁF capacitors should have a low effective series resistance
(ESR) and low effective series inductance (ESI), such as is typical
of common ceramic and surface mount types of capacitors. These
low ESR, low ESI capacitors provide a low impedance path to
ground at high frequencies to handle transient currents due to
internal logic switching.
Good connections should be made to the power and ground
planes. This can be done with a single via or multiple vias for
each supply and ground pin.
Avoid running digital lines under the AD7366-5/AD7367-5
devices because this couples noise onto the die. However, the
analog ground plane should be allowed to run under the
AD7366-5/AD7367-5 to avoid noise coupling. The power
supply lines to the AD7366-5/AD7367-5 should use as large
a trace as possible to provide low impedance paths and reduce
the effects of glitches on the power supply line.
EVALUATING THE AD7366-5/AD7367-5
Evaluation boards for the AD7366 and AD7367, the
EVAL-AD7366CBZ and EVAL-AD7367CBZ, can also be
used to evaluate the performance of the AD7366-5 and
AD7367-5, respectively. These evaluation boards can be
used in conjunction with EVAL-CONTROL BRD2 to
provide a full-featured evaluation platform.
Rev. B | Page 27 of 28
AD7366-5/AD7367-5
OUTLINE DIMENSIONS
7.90
7.80
7.70
24
13
12
4.50
4.40
4.30
6.40 BSC
1
PIN 1
0.65
BSC
1.20
MAX
0.15
0.05
0.75
0.60
0.45
8°
0°
0.30
0.19
0.20
0.09
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 33. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD7366BRUZ-5
AD7366BRUZ-5-RL7
AD7366BRUZ-5500RL7
AD7367BRUZ-5
AD7367BRUZ-5-RL7
AD7367BRUZ-5500RL7
Temperature Range
Package Description
Package Option
RU-24
RU-24
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
RU-24
RU-24
RU-24
RU-24
1 Z = RoHS Compliant Part.
©2007-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06842-0-7/11(B)
Rev. B | Page 28 of 28
相关型号：
AD7366BRUZ-5500RL7
2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO24, ROHS COMPLIANT, MO-153AD, TSSOP-24
ADI
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