AD7376AN1M [ADI]
+-15 V Operation Digital Potentiometer; ±15 V操作数字电位计
| 型号： | AD7376AN1M |
| 厂家： | 
ADI |
| 描述： | +-15 V Operation Digital Potentiometer |
| 文件： | 总12页 (文件大小：338K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
؎15 V Operation
Digital Potentiometer
a
AD7376*
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
128 Position
Potentiom eter Replacem ent
10 k⍀, 50 k⍀, 100 k⍀, 1 M⍀
Pow er Shutdow n: Less than 1 A
3-Wire SPI Com patible Serial Data Input
+5 V to +30 V Single Supply Operation
؎5 V to ؎15 V Dual Supply Operation
Midscale Preset
AD7376
V
DD
SDO
SDI
Q
A
W
B
7-BIT
SERIAL
REGISTER
7
7
7-BIT
LATCH
D
CK
R
SHDN
V
SS
CLK
CS
APPLICATIONS
Mechanical Potentiom eter Replacem ent
Instrum entation: Gain, Offset Adjustm ent
Program m able Voltage-to-Current Conversion
Program m able Filters, Delays, Tim e Constants
Line Im pedance Matching
GND
SHDN
RS
to an end-to-end open circuit condition on the A terminal and
shorts the wiper to the B terminal, achieving a microwatt power
shutdown state. When shutdown is returned to logic high, the
previous latch settings put the wiper in the same resistance
setting prior to shutdown as long as power to VDD is not re-
moved. T he digital interface is still active in shutdown so that
code changes can be made that will produce a new wiper posi-
tion when the device is taken out of shutdown.
Pow er Supply Adjustm ent
GENERAL D ESCRIP TIO N
T he AD7376 provides a single channel, 128-position digitally-
controlled variable resistor (VR) device. T his device performs the
same electronic adjustment function as a potentiometer or vari-
able resistor. T hese products were optimized for instrument and
test equipment applications where a combination of high voltage
with a choice between bandwidth or power dissipation are avail-
able as a result of the wide selection of end-to-end terminal resis-
tance values. T he AD7376 contains a fixed resistor with a wiper
contact that taps the fixed resistor value at a point determined by
a digital code loaded into the SPI-compatible serial-input regis-
ter. T he resistance between the wiper and either endpoint of the
fixed resistor varies linearly with respect to the digital code trans-
ferred into the VR latch. T he variable resistor offers a completely
programmable value of resistance between the A terminal and the
wiper or the B terminal and the wiper. T he fixed A to B terminal
resistance of 10 kΩ, 50 kΩ, 100 kΩ or 1 MΩ has a nominal tem-
perature coefficient of –300 ppm/°C.
T he AD7376 is available in both surface mount (SOL-16) and
the 14-lead plastic DIP package. For ultracompact solutions
selected models are available in the thin T SSOP package. All
parts are guaranteed to operate over the extended industrial
temperature range of –40°C to +85°C. For operation at lower
supply voltages (+3 V to +5 V), see the AD8400/AD8402/
AD8403 products.
1
SDI
(DATA IN)
D
D
X
X
0
tDS
tDH
1
0
SDO
(DATA OUT)
D'
D'
X
X
tPD_MAX
tCH
1
0
tCS1
CLK
T he VR has its own VR latch which holds its programmed resis-
tance value. T he VR latch is updated from an internal serial-to-
parallel shift register which is loaded from a standard 3-wire
serial-input digital interface. Seven data bits make up the data
word clocked into the serial data input register (SDI). Only the
last seven bits of the data word loaded are transferred into the
7-bit VR latch when the CS strobe is returned to logic high. A
serial data output pin (SDO) at the opposite end of the serial
register allows simple daisy-chaining in multiple VR applications
without additional external decoding logic.
tCSH0
tCL
tCSH
tCSS
1
tCSW
tS
CS
0
V
DD
0V
V
OUT
؎1 LSB ERROR BAND
؎1 LSB
Figure 1. Detail Tim ing Diagram
T he reset (RS) pin forces the wiper to the midscale position by
loading 40H into the VR latch. T he SHDN pin forces the resistor
T he last seven data bits clocked into the serial input register will
be transferred to the VR 7-bit latch when CS returns to logic
high. Extra data bits are ignored.
*Patent Number: 5495245
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w .analog.com
© Analog Devices, Inc., 1997
AD7376–SPECIFICATIONS
(V /V = ؎15 V ؎ 10% or ؎ 5 V ؎ 10%, V = +V , V = V /0 V, –40؇C < T < +85؇C
unless otherwise noted.)
DD SS
A
DD
B
SS
A
ELECTRICAL CHARACTERISTICS
P aram eter
Sym bol
Conditions
Min
Typ1
Max
Units
DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)
Resistor Differential NL2
Resistor Nonlinearity2
Nominal Resistor T olerance
Resistance Temperature Coefficient
Wiper Resistance
R-DNL
R-INL
∆R
RWB, VA = NC
RWB, VA = NC
–1
–1
–30
±0.25 +1
LSB
LSB
%
ppm/°C
Ω
±0.5
+1
30
T
A = +25°C
R
AB/∆T
VAB = VDD, Wiper = No Connect
IW = ±15 V/RNOMINAL
IW = ±5 V/RNOMINAL
–300
120
RW
RW
200
Wiper Resistance
200
Ω
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)
Resolution
N
INL
DNL
∆VW/∆T
VWFSE
VWZSE
7
–1
–1
Bits
LSB
LSB
ppm/°C
LSB
Integral Nonlinearity3
Differential Nonlinearity3
Voltage Divider Temperature Coefficient
Full-Scale Error
±0.5
±0.1
5
–0.5
+0.5
+1
+1
Code = 40H
Code = 7FH
Code = 00H
–2
0
+0
+1
Zero-Scale Error
LSB
RESIST OR T ERMINALS
Voltage Range4
VA, B, W
CA, B
CW
IA_SD
RW_SD
ICM
VSS
VDD
V
Capacitance5 A, B
f = 1 MHz, Measured to GND, Code = 40H
f = 1 MHz, Measured to GND, Code = 40H
VA = VDD, VB = 0 V, SHDN = 0
VA = VDD, VB = 0 V, SHDN = 0, VDD = +15 V
VA = VB = VW
45
60
0.01
170
1
pF
pF
µA
Ω
Capacitance5 W
Shutdown Supply Current6
Shutdown Wiper Resistance
Common-Mode Leakage
1
400
nA
DIGIT AL INPUT S AND OUT PUT S
Input Logic High
Input Logic Low
VIH
VIL
VOH
VOL
IIL
VDD = +5 V or +15 V
VDD = +5 V or +15 V
RL = 2.2 kΩ to +5 V
IOL = 1.6 mA, VLOGIC = +5 V, VDD = +15 V
VIN = 0 V or +15 V
2.4
4.9
V
V
V
V
µA
pF
0.8
Output Logic High
Output Logic Low7
Input Current
0.4
±1
Input Capacitance5
CIL
5
POWER SUPPLIES
Power Supply Range
Power Supply Range
Supply Current
VDD/VSS
VDD
IDD
IDD
ISS
PDISS
PSS
PSS
Dual Supply Range
Single Supply Range, VSS = 0
±4.5
4.5
±16.5
28
0.0001 0.01
V
V
VIH = +5 V or VIL = 0 V, VDD = +5 V
VIH = +5 V or VIL = 0 V, VDD = +15 V
VIH = +5 V or VIL = 0 V, VSS = –5 V or –15 V
VIH = +5 V or VIL = 0 V, VDD = +15 V, VSS = –15 V
∆VDD = +5 V ± 10%, or ∆VSS = –5 V ± 10%
∆VDD = +15 V ± 10% or ∆VSS = –15 V ± 10%
mA
mA
mA
mW
%/%
%/%
Supply Current
0.75
0.02
11
0.05
0.01
2
0.1
30
0.15
0.02
Supply Current
Power Dissipation8
Power Supply Sensitivity
DYNAMIC CHARACTERISTICS5, 9, 10
Bandwidth –3 dB
Bandwidth –3 dB
Bandwidth –3 dB
T otal Harmonic Distortion
VW Settling T ime
BW_10K
BW_50K
RAB = 10 kΩ, Code = 40H
RAB = 50 kΩ, Code = 40H
520
125
60
0.005
4
kHz
kHz
kHz
%
µs
nV√Hz
BW_100K RAB = 100 kΩ, Code = 40H
T HDW
tS
VA = 1 V rms, VB = 0 V, f = 1 kHz
VA = 10 V, VB = 0 V, ±1 LSB Error Band
RWB = 25 kΩ, f = 1 kHz, RS = 0
Resistor Noise Voltage
eN_WB
14
INT ERFACE T IMING CHARACT ERIST ICS (Applies to All Parts [Notes 5, 11])
Input Clock Pulsewidth
Data Setup T ime
t
CH, tCL
Clock Level High or Low
120
30
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDS
tDH
tPD
tCSS
tCSW
tRS
tCSH
tCS1
Data Hold T ime
CLK to SDO Propagation Delay12
CS Setup T ime
RL = 2.2 kΩ, CL < 20 pF
10
100
120
150
120
120
120
CS High Pulsewidth
Reset Pulsewidth
CLK Rise to CS Rise Hold T ime
CS Rise to Clock Rise Setup
–2–
REV. 0
AD7376
NOT ES
11T ypicals represent average readings at +25°C, VDD = +15 V, and VSS = –15 V.
12Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-
tions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 27. T est Circuit.
13INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL
specification limits of ±1 LSB maximum are Guaranteed Monotonic operating conditions. See Figure 26. T est Circuit.
14Resistor terminals A, B, W have no limitations on polarity with respect to each other.
15Guaranteed by design and not subject to production test.
16Measured at the A terminal. A terminal is open circuit in shutdown mode.
17
I
P
= 200 µA for the 50 kΩ version operating at VDD = +5 V.
OL
18
is calculated from (IDD × VDD ). CMOS logic level inputs result in minimum power dissipation.
DISS
19Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. T he lowest R value results in the fastest settling time and highest band-
width. T he highest R value results in the minimum overall power consumption.
10All dynamic characteristics use VDD = +15 V and VSS = –15 V.
11See timing diagram for location of measured values. All input control voltages are specified with t R = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both VDD = +5 V or +15 V.
12Propagation delay depends on value of VDD , RL and CL see Applications section.
Specifications subject to change without notice.
P IN CO NFIGURATIO NS
ABSO LUTE MAXIMUM RATINGS
(T A = +25°C, unless otherwise noted)
P D IP & TSSO P -14
SO L-16
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +30 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –16.5 V
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +44 V
VA, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, VDD
AX – BX, AX – WX, BX – WX . . . . . . . . . . . . . . . . . . . ±20 mA
Digital Input Voltages to GND . . . . . . . . . . 0 V, VDD + 0.3 V
Digital Output Voltage to GND . . . . . . . . . . . . . . 0 V, +30 V
Operating T emperature Range . . . . . . . . . . . –40°C to +85°C
Maximum Junction T emperature (TJ MAX) . . . . . . . +150°C
Storage T emperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . (TJ MAX – T A)/θJA
T hermal Resistance θJA
1
2
3
4
5
6
7
8
A
B
16
W
A
B
1
2
3
4
5
6
7
14
13 NC
12
W
15 NC
V
V
DD
14
13
12
11
10
9
V
V
SS
SS
DD
AD7376
TOP VIEW
(Not to Scale)
AD7376
TOP VIEW
(Not to Scale)
GND
SDO
GND
11 SDO
10
CS
SHDN
CS
SHDN
SDI
SDI
NC
9
8
RS
RS
CLK
NC
NC
CLK
NC
NC = NO CONNECT
NC = NO CONNECT
P-DIP (N-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
SOIC (SOL-16) . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
T SSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240°C/W
O RD ERING GUID E
Tem perature
Range
P ackage
D escription
P ackage
O ptions
Model
k⍀
AD7376AN10
AD7376AR10
AD7376ARU10
AD7376AN50
AD7376AR50
AD7376ARU50
AD7376AN100
AD7376AR100
AD7376ARU100
AD7376AN1M
AD7376AR1M
AD7376ARU1M
10
10
10
50
50
50
100
100
100
1,000
1,000
1,000
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
PDIP-14
SOL-16
T SSOP-14
PDIP-14
SOL-16
T SSOP-14
PDIP-14
SOL-16
T SSOP-14
PDIP-14
SOL-16
N-14
R-16
RU-14
N-14
R-16
RU-14
N-14
R-16
RU-14
N-14
R-16
T SSOP-14
RU-14
Die Size: 101.6 mil × 127.6 mil, 2.58 mm × 3.24 mm
Number T ransistors: 840
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7376 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
–Typical Performance Characteristics
AD7376
0.5
100
0.25
0.4
0.20
0.15
0.10
0.05
T
= –55؇C
A
0.3
T
A
= +25؇C
75
T
= –55؇C
A
T
= +25؇C
0.2
A
0.1
T
= +85؇C
A
50
0
0
–0.05
–0.10
–0.15
–0.20
–0.25
V
V
V
V
= +15V
DD
–0.1
–0.2
–0.3
–0.4
–0.5
= –15V
SS
T
= +85؇C
A
= 2.5V
= 0V
A
B
25
0
V
= +15V
= –15V
= 50k⍀
DD
SS
R
= 50k⍀
V
AB
R
R
R
WB
WA
AB
0
32
64
96
128
0
16
32
48
64 80
96 112 128
0
16
32
48
64 80
96 112 128
CODE – Decimal
CODE – Decimal
CODE – Decimal
Figure 3. Resistance Step Position
Nonlinearity Error vs. Code
Figure 4. Relative Resistance Step
Change from Ideal vs. Code
Figure 2. Wiper To End Term inal
Percent Resistance vs. Code
1.5
50
14
I
= 100A, T = +25؇C
A
w
01
H
DATA = 40
H
10
V
V
= +15V
H
DD
1.2
0.9
0.6
12
49
48
47
46
45
= –15V
20
H
SS
R
= 50k⍀ NOMINAL
AB
10
40
H
8
T
= +25؇C
A
6
4
V
V
= +15V
DD
= –15V
SS
R
= 50k⍀
AB
CODE = 70
0.3
0
H
2
0
7F
H
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
5
10
15
20
25
30
–55 –35 –15
5
25 45 65 85 105 125
I
– mA
SUPPLY VOLTAGE (V - V ) – Volts
WA
DD
SS
TEMPERATURE – ؇C
Figure 6. Resistance Linearity vs.
Conduction Current
Figure 7. Resistance Nonlinearity
Error vs. Supply Voltage
Figure 5. Nom inal Resistance vs.
Tem perature
1000
900
20
15
1.0
V
V
= 2.5V
= 0V
R
= 50k⍀
A
AB
800
700
600
500
400
300
200
100
0
B
10
5
0.8
0.6
0.4
CODE = 40
H
R
= 50k⍀
AB
V
V
= +5V
= 0V
DD
SS
0
–5
V
V
V
V
= +15V
= –15V
DD
SS
–10
–15
V
V
= +5V
= +2.5V
DD
A
B
= –5V
= 0V
SS
–20
–25
–30
–55؇C < T < +85؇C
0.2
0
A
V
V
= +15V
= –15V
R
= 50k⍀
DD
SS
AB
–55 –35 –15
5
25 45 65 85 105 125
0
16
32 48 64
80
96 112 128
5
10
15
20
DD
25
30
CODE – Decimal
TEMPERATURE – ؇C
SUPPLY VOLTAGE (V - V ) – Volts
SS
Figure 10. Wiper Contact
Resistance vs. Tem perature
Figure 9. ∆VWB/∆T Potentiom eter
Mode Tem pco
Figure 8. Potentiom eter Divider
Nonlinearity Error vs. Supply
Voltage
–4–
REV. 0
AD7376
0.25
0.20
0.15
0.10
0.05
0
40
35
30
25
20
15
10
0.25
0.20
0.15
0.10
0.05
0
V
= +15V
= –15V
= 50k⍀
DD
SS
V
T
= +25؇C
R
A
AB
T
= –55؇C
A
–0.05
–0.10
–0.15
–0.20
–0.25
–0.05
–0.10
–0.15
–0.20
–0.25
V
V
V
V
= +15V
DD
SS
V
V
V
V
= +15V
= –15V
DD
SS
= –15V
5
0
= +2.5V
A
= +2.5V
T
= +85؇C
A
B
A
= 0V
B
= 0V
R
= 50k⍀
AB
–5
R
= 50k⍀
AB
–10
0
16
32 48
64
80
96 112 128
0
16
32
48
64 80
96 112 128
0
16
32
48
64 80
96 112 128
CODE – Decimal
CODE – Decimal
CODE – Decimal
Figure 11. Potentiom eter Divider
Nonlinearity Error vs. Code
Figure 13. ∆RWB/∆T Rheostat Mode
Tem pco
Figure 12. Potentiom eter Divider
Differential Nonlinearity Error
vs. Code
R
= 10k⍀
CODE = 7F
CODE = 40
CODE = 7F
R
= 1M⍀
H
AB
H
AB
s
0
–6
0
–6
259.8
CODE = 40
H
H
H
V
V
= +15V
= —15V
CODE = 20
CODE = 10
DD
SS
CODE = 20
CODE = 10
H
–12
–18
–24
–30
–36
–42
–48
–12
–18
H
H
H
CODE = 08
CODE = 04
H
CODE = 08
CODE = 04
CODE = 02
–24
–30
CODE = 3F
40
3F
H
H
H
H
H
H
V
A
V
B
= 2.5V
= 0V
CODE = 02
CODE = 01
H
H
–36
–42
–48
f = 100 kHz
CODE = 01
H
B
CODE = 00
s
H
50m
H 5
O
w
L
V
V
V
= +15V
= –15V
= 50mVrms
DD
SS
AMPL
A
B
V
V
V
= +15V
= –15V
A
B
DD
SS
W
W
5S/DIV
OP275
= 50mVrms
OP275
1k
AMPL
R
= 1M⍀
AB
1k
10k
100k
FREQUENCY – Hz
1M
100
10k
100k
FREQUENCY – Hz
Figure 14. 10 kΩ Gain vs. Frequency
Figure 16. Midscale Transition Glitch
Figure 15. 1 MΩ Gain vs. Frequency
vs. Code
vs. Code
1.0
R
= 50k⍀
CODE = 7F
CODE = 40
AB
H
s
0
–6
A2
1.6 V
DLY
27.08
V
V
V
= +15V
= –15V
DD
128kHz
H
H
12
0
SS
20
V
V
= +15V
= ؎10V p–p
A
DD
–12
–18
–24
–30
–36
–42
–48
–54
CODE = 3F
V
V
H
0.1
= –15V
10
08
CODE = 40
H
SS
H
= 12V
= 0V
A
NON-INVERTING
MODE TEST
CKT FIG 36
R
= 50k⍀
AB
B
H
AMP = 50mV
f = 1 MHz
04
H
V
V
= +15V
= –15V
= 1M⍀
DD
02
SS
0.010
H
5
0
R
L
01
H
B
5V
5V
s
H 2
A
w
L
O
NON-INVERTING
MODE TEST
CKT FIG 35
OP275
B
0.001
2S/DIV
1k
10k
100k
1M
0.0005
FREQUENCY – Hz
10
100
1k
10k
200k
FREQUENCY – Hz
Figure 18. Large Signal Settling Tim e
Figure 17. 50 kΩ Gain vs. Frequency
vs. Code
Figure 19. Total Harm onic Distortion
Plus Noise vs. Frequency
REV. 0
–5–
AD7376
CODE = 7F
H
s
A2
2.9 V
DLY
0
–6
235.2
0
–6
40H
V
V
= +15V
= –15V
DD
SS
20H
10H
08H
04H
02H
01H
–12
–18
–12
–18
–24
–30
–36
–42
10k⍀
V
V
V
= +15V
= –15V
–24
–30
DD
SS
50k⍀
100k⍀
= 1M⍀
= 50mVrms
AMPL
–36
–42
–48
CODE = 40
H
R
B
AB
20m
s
O2
H
w
L
V
V
V
= +15V
= –15V
AMPL
DD
SS
A
A
B
W
W
–48
–54
= 50mVrms
B
OP275
10k
OP275
R
= 100k⍀
AB
1k
10k
100k
1M
100k
FREQUENCY – Hz
1k
1M
FREQUENCY – Hz
Figure 20. 100 kΩ Gain vs. Frequency
vs. Code
Figure 22. Clock Feedthrough
Figure 21. –3 dB Bandwidth vs.
Nom inal Resistance
0.1
90
+PSRR
T = +25؇C
A
R
= 10k⍀
50k⍀
400
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
AB
V
V
= +15V؎10%
= –15V
DD
SS
80
70
V
V
= +5V
= –5V
DD
SS
350
300
250
–PSRR
1M⍀
V
= +15V
DD
SS
100k⍀
60
50
V
= –15V؎10%
V
V
= +15V
= –15V
DD
SS
–PSRR
V
V
V
= +15V
DD
SS
V
= +5V
DD
SS
200
150
= –15V
= 50mVrms
V
= –5V؎10%
40
30
AMPL
CODE = 40
H
+PSRR
100
50
0
V
V
= +5V؎10%
= –5V
DD
SS
A
20
10
W
–0.8
–0.9
SEE FIGURE 38 TEST CIRCUIT
B
OP275
10
100
1k
10k
100k
10
100
1k
10k
100k
1M
–15
–10
–5
0
5
10
15
FREQUENCY – Hz
FREQUENCY – Hz
V
– Volts
B
Figure 23. Gain Flatness vs Fre-
quency vs. Nom inal Resistance RAB
Figure 24. Power Supply Rejection
vs. Frequency
Figure 25. Increm ental Wiper
Contact Resistance vs.
Com m on-Mode Voltage
10
4.0
1.0
I
@V = +15V, V
= +5V
DD
DD
LOGIC
3.5
3.0
2.5
2.0
1.5
1.0
0.5
V
V
= +15V
= –15V
I
@V = +15V, V
= 0V
DD
SS
V
= +15V,
= –15V
= +2.5V
= 0
DD
DD
LOGIC
DD
SS
V
V
1.0
0.1
A
0.1
0.010
0.001
I
I
@V = –15V, V
= +15V
SS
SS
LOGIC
V
B
T
= +25؇C
DATA = 55
A
H
@V = +5V, V
= +0.8V
DD
DD
LOGIC
DATA = 3F
H
0.010
0.001
I
@V = +5V, V
= +5V
DD
DD
LOGIC
R
= 50k⍀
AB
0.0
1k
–55 –35 –15
5
25 45 65 85 105 125
10k
100k
1M
10M
–55 –35 –15
5
25 45 65 85 105 125
TEMPERATURE – ؇C
CLOCK FREQUENCY – Hz
TEMPERATURE – ؇C
Figure 26. Supply Current (IDD, ISS
vs. Tem perature
)
Figure 28. IDD Supply Current vs.
Input Clock Frequency
Figure 27. IA_SD Shutdown Current vs.
Tem perature
–6–
REV. 0
AD7376
3.5
3.0
I
MS
I
= 1V/R
NOMINAL
W
A
B
V
DUT
W
2.5
2.0
W
V+
V+
V
DD
V
MS
V
=
W
- (V + I [RAW||
R
])
V
V
V
= +5V
= 0V
= 0V
W2
W1
W
BW
A
B
R
I
W
1.5
1.0
WHERE V = V WHEN I = 0
W1
MS
W
SS
AND V = V WHEN I = 1/R
W2
MS
W
Figure 33. Wiper Resistance Test Circuit
0.5
0
5
10
15
20
25
30
SUPPLY VOLTAGE (V ) – Volts
DD
V
A
Figure 29. Input Logic Threshold Voltage vs.
VDD Supply Voltage
V+ = V ؎10% OR V ؎10%
DD
SS
V
A
DD
⌬
⌬
V
MS
W
PSRR (dB) = 20LOG
(
%
MS
(
V+
V+
⌬
V
B
V
MS
PSS (%/%) =
⌬
V+%
1600
1200
800
Figure 34. Power Supply Sensitivity Test Circuit
(PSS, PSRR)
V
V
= +15V
= –15V
A
B
DD
SS
DUT
+18V
OP275
–18V
W
400
0
V
IN
V
OUT
V
V
= +5V
DD
SS
= 0V OR –5V
0
5
10
15
V
LOGIC
Figure 35. Inverting Program m able Gain Test Circuit
Figure 30. Supply Current (IDD) vs. Logic Voltage
+18V
P ARAMETRIC TEST CIRCUITS
V
OUT
OP275
V+ = V
DD
A
1LSB = V+/128
DUT
V
IN
W
W
V+
–18V
B
B
V
MS
DUT
A
Figure 36. Noninverting Program m able Gain Test Circuit
Figure 31. Potentiom eter Divider Nonlinearity Error Test
Circuit (INL, DNL)
NO CONNECT
+18V
A
W
I
W
A
B
V
IN
DUT
DUT
W
V
B
OP275
–18V
OUT
V
MS
Figure 32. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)
Figure 37. Gain vs. Frequency Test Circuit
REV. 0
–7–
AD7376
0.1V
P RO GRAMMING TH E VARIABLE RESISTO R
Rheostat O per ation
R
=
SW
I
SW
CODE = OO
H
DUT
T he nominal resistance of the RDAC between terminals A and
B are available with values of 10 kΩ, 50 kΩ, 100 kΩ and 1 MΩ.
T he final three characters of the part number determine the
nominal resistance value, e.g., 10 kΩ = 10; 50 kΩ = 50; 100 kΩ
= 100; 1 MΩ = 1M. T he nominal resistance (RAB) of the VR
has 128 contact points accessed by the wiper terminal, plus the
B terminal contact. T he 7-bit data word in the RDAC latch is
decoded to select one of the 128 possible settings. The wiper’s first
connection starts at the B terminal for data 00H. T his B–termi-
nal connection has a wiper contact resistance of 120 Ω. T he
second connection (10 kΩ part) is the first tap point located
at 198 Ω (= RBA [nominal resistance]/128 + RW = 78 Ω + 120 Ω)
for data 01H. T he third connection is the next tap point repre-
senting 156 + 120 = 276 Ω for data 02H. Each LSB data value
increase moves the wiper up the resistor ladder until the last tap
point is reached at 10041 Ω. T he wiper does not directly con-
nect to the B terminal. See Figure 40 for a simplified diagram of
the equivalent RDAC circuit.
W
I
SW
B
0.1V
V
TO V
DD
SS
Figure 38. Increm ental ON Resistance Test Circuit
NC
A
B
V
I
DD
DUT
CM
W
V
GND
SS
V
CM
NC
Figure 39. Com m on-Mode Leakage Current Test Circuit
T he general transfer equation that determines the digitally pro-
grammed output resistance between W and B is:
R
WB(D) = (D)/128 × RBA + RW
(1)
O P ERATIO N
where D is the data contained in the 7-bit VR latch, and RBA is
T he AD7376 provides a 128-position digitally-controlled vari-
able resistor (VR) device. Changing the programmed VR set-
tings is accomplished by clocking in a 7-bit serial data word into
the SDI (Serial Data Input) pin, while CS is active low. When
CS returns high the last seven bits are transferred into the RDAC
latch setting the new wiper position. T he exact timing require-
ments are shown in Figure 1.
the nominal end-to-end resistance.
For example, when VB = 0 V and A–terminal is open circuit, the
following output resistance values will be set for the following
VR latch codes (applies to the 10 kΩ potentiometer).
Table I.
D
RWB
(⍀)
T he AD7376 resets to a midscale by asserting the RS pin, sim-
plifying initial conditions at power-up. Both parts have a power
shutdown SHDN pin which places the RDAC in a zero power
consumption state where terminal A is open circuited and the
wiper W is connected to B, resulting in only leakage currents
being consumed in the VR structure. In shutdown mode the
VR latch settings are maintained so that, returning to opera-
tional mode from power shutdown, the VR settings return to
their previous resistance values.
(D EC)
O utput State
127
64
1
10041
5120
276
Full-Scale
Midscale (RS = 0 Condition)
1 LSB
0
198
Zero-Scale (Wiper Contact Resistance)
Note that in the zero-scale condition a finite wiper resistance of
120 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum value of 5 mA to
avoid degradation or possible destruction of the internal switch
contact.
A
SHDN
R
S
Like the mechanical potentiometer the RDAC replaces, it is
totally symmetrical. T he resistance between the wiper W and
terminal A also produces a digitally controlled resistance RWA
When these terminals are used the B–terminal should be tied to
the wiper. Setting the resistance value for RWA starts at a maxi-
mum value of resistance and decreases as the data loaded in the
latch is increased in value. T he general transfer equation for this
operation is:
D 6
.
R
R
D 5
D 4
D 3
D 2
D 1
D 0
S
S
W
RDAC
R
WA(D) = (128-D)/128 × RBA + RW
(2)
LATCH
&
DECODER
where D is the data contained in the 7-bit RDAC latch, and RBA
is the nominal end-to-end resistance. For example, when VA = 0 V
and B–terminal is tied to the wiper W the following output
resistance values will be set for the following RDAC latch codes.
R
S
B
R
= R
/128
NOMINAL
S
Figure 40. AD7376 Equivalent RDAC Circuit
–8–
REV. 0
AD7376
clean transitions to avoid clocking incorrect data into the serial
input register. Standard logic families work well. If mechanical
switches are used for product evaluation they should be de-
bounced by a flip-flop or other suitable means. When CS is
taken active low the clock loads data into the serial register on
each positive clock edge, see T able III. T he last seven bits
clocked into the serial register will be transferred to the 7-bit
RDAC latch, see Figure 41. Extra data bits are ignored. T he
serial-data-output (SDO) pin contains an open drain n-channel
FET . T his output requires a pull-up resistor in order to transfer
data to the next package’s SDI pin. T his allows for daisy chain-
ing several RDACs from a single processor serial data line.
Clock period needs to be increased when using a pull-up resistor
to the SDI pin of the following device in the series. Capacitive
loading at the daisy chain node SDO-SDI between devices must
be accounted for to successfully transfer data. When daisy
chaining is used, the CS should be kept low until all the bits of
every package are clocked into their respective serial registers
insuring that the data bits are in the proper decoding location.
T his would require 14 bits of data when two AD7376 RDACs
are daisy chained. During shutdown (SHDN) the SDO output
pin is forced to the off (logic high state) to disable power dissi-
pation in the pull up resistor. See Figure 42 for equivalent SDO
output circuit schematic.
Table II.
D
RWA
(⍀)
(D EC)
O utput State
127
64
1
74
Full-Scale
Midscale (RS = 0 Condition)
1 LSB
5035
9996
10035
0
Zero-Scale
T he typical distribution of RBA from device to device matching
is process lot dependent having a ±30% variation. The change
in RBA with temperature has a –300 ppm/°C temperature
coefficient.
P RO GRAMMING TH E P O TENTIO METER D IVID ER
Voltage O utput O per ation
T he digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example connecting A–terminal to +5 V and B–terminal to
ground produces an output voltage at the wiper which can be
any value starting at zero volts up to 1 LSB less than +5 V. Each
LSB of voltage is equal to the voltage applied across terminal
AB divided by the 128-position resolution of the potentiometer
divider. T he general equation defining the output voltage with
respect to ground for any given input voltage applied to termi-
nals AB is:
Table III. Input Logic Control Truth Table
VW (D) = D/128 × VAB + VB
CLK CS RS SHDN Register Activity
Operation of the digital potentiometer in the divider mode
results in more accurate operation over temperature. Here the
output voltage is dependent on the ratio of the internal resis-
tors, not the absolute value; therefore, the drift improves to
5 ppm/°C.
L
P
L
L
H
H
H
H
Enables SR, enables SDO pin.
Shifts one bit in from the SDI
pin. T he seventh previously
entered bit is shifted out of the
SDO pin.
X
P
H
H
Loads SR data into 7-bit RDAC
latch.
AD7376
V
DD
SDO
SDI
Q
7-BIT
RDAC
LATCH
A
7-BIT
SERIAL
REGISTER
7
7
X
X
H
X
H
L
H
H
No Operation.
W
B
Sets 7-bit RDAC latch to mid-
scale, wiper centered, and SDO
latch cleared.
D
CK
R
SHDN
SHDN
V
SS
CLK
CS
X
X
H
H
P
H
L
Latches 7-bit RDAC latch to
40H.
GND
RS
H
Opens circuits resistor A–terminal,
connects W to B, turns off SDO
output transistor.
Figure 41. Block Diagram
D IGITAL INTERFACING
T he AD7376 contains a standard three-wire serial input control
interface. T he three inputs are clock (CLK), CS and serial data
input (SDI). T he positive-edge sensitive CLK input requires
NOT E
P = positive edge, X = don’t care, SR = shift register.
REV. 0
–9–
AD7376
V
T he data setup and data hold times in the specification table
determine the data valid time requirements. T he last seven bits
of the data word entered into the serial register are held when
CS returns high. At the same time CS goes high it transfers the
7-bit data to the VR latch.
DD
100⍀
LOGIC
Figure 43. Equivalent ESD Protection Circuit
SHDN
CS
SDO
V
DD
SERIAL
REGISTER
SDI
Q
D
A,B,W
CK RS
V
SS
CLK
RS
Figure 44. Equivalent ESD Protection Analog Pins
Figure 42. Detail SDO Output Schem atic of the AD7376
All digital inputs are protected with a series input resistor and
parallel Zener ESD structure shown in Figure 43. Applies to
digital input pins CS, SDI, SDO, RS, SHDN, CLK
–10–
REV. 0
AD7376
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
14-Lead P lastic D IP
(N-14)
14-Lead TSSO P
(RU-14)
0.795 (20.19)
0.725 (18.42)
0.201 (5.10)
0.193 (4.90)
14
1
8
7
0.280 (7.11)
0.240 (6.10)
14
8
7
0.325 (8.25)
0.195 (4.95)
0.115 (2.93)
0.300 (7.62)
0.060 (1.52)
0.015 (0.38)
PIN 1
0.210 (5.33)
MAX
1
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
0.022 (0.558)
0.014 (0.356)
0.100 0.070 (1.77)
PIN 1
(2.54)
BSC
0.045 (1.15)
0.006 (0.15)
0.002 (0.05)
0.0433
(1.10)
MAX
0.028 (0.70)
0.020 (0.50)
8°
0°
0.0118 (0.30)
0.0075 (0.19)
0.0256
(0.65)
BSC
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
16-Lead Wide Body SO IC
(R-16)
0.4133 (10.50)
0.3977 (10.00)
16
9
1
8
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
PIN 1
x 45°
0.0118 (0.30)
0.0040 (0.10)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
0.0138 (0.35)
REV. 0
–11–
–12–
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