AD7381BCPZ-RL7 [ADI]
Dual, Simultaneous Sampling SAR ADCs, Differential Inputs;
| 型号： | AD7381BCPZ-RL7 |
| 厂家： | 
ADI |
| 描述： | Dual, Simultaneous Sampling SAR ADCs, Differential Inputs |
| 文件： | 总31页 (文件大小：699K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual, Simultaneous Sampling, 16-Bit/14-Bit
SAR ADCs, Differential Inputs
Data Sheet
AD7380/AD7381
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
V
LOGIC
CC
16-bit/14-bit ADC family
Dual simultaneous sampling
Fully differential analog inputs
4 MSPS throughput conversion rate
SNR (typical)
A
A
A+
IN
OVER-
SAMPLING
ADC A
SDOA
A–
IN
REFIO
REFCAP
92.5 dB, VREF = 3.3 V external at AD7380 (16-bit)
85.4 dB, VREF = 3.3 V external at AD7381 (14-bit)
On-chip oversampling function
Resolution boost function
SNR 102.8 dB (typical) with ×32 OSR
INL (maximum)
OSC
GND
REF
LDO
SCLK
SDI
CONTROL
LOGIC
REFCAP
CS
A
A
B+
IN
OVER-
ADC B
GND
SDOB/ALERT
SAMPLING
B–
IN
2.0 LSBs at 16-bit
1.0 LSB at 14-bit
AD7380/AD7381
2.5 V internal reference at 10 ppm/°C
High speed serial interface
−40°C to +125°C operation
16-lead LFCSP, 3 mm × 3 mm
Wide common-mode range
Alert function
Figure 1.
APPLICATIONS
Motor control position feedback
Motor control current sense
Sonar
Power quality
Data acquisition systems
EDFA applications
I and Q demodulation
GENERAL DESCRIPTION
The AD7380/AD7381 are a 16-bit and 14-bit pin-compatible
family of dual simultaneous sampling, high speed, low power,
successive approximation register (SAR) analog-to-digital
converters (ADC) that operate from a 3.0 V to 3.6 V power supply
and feature throughput rates up to 4 MSPS. The analog input
type is differential, accepts a wide common-mode input voltage,
The AD7380/AD7381 are available in a 16-lead lead frame chip
scale package (LFCSP) with operation specified from −40°C to
+125°C.
PRODUCT HIGHLIGHTS
1. Dual simultaneous sampling and conversion with two
complete ADC functions.
2. Pin-compatible product family.
CS
and is sampled and converted on the falling edge of
.
Integrated on-chip oversampling blocks improve dynamic range
and reduce noise at lower bandwidths. A buffered internal 2.5 V
reference is included. Alternatively, an external reference up to
3.3 V can be used.
3. High 4 MSPS throughput rate.
4. Space saving 3 mm × 3 mm LFCSP package.
5. Integrated oversampling block to increase dynamic range,
reduce noise, and reduce SCLK speed requirements.
6. Differential analog inputs with wide common-mode range.
7. Small sampling capacitor reduces amplifier drive burden.
The conversion process and data acquisition use standard
control inputs allowing easy interfacing to microprocessors or
digital signal processors (DSPs). It is compatible with 1.8 V,
2.5 V, and 3.3 V interfaces, using the separate logic supply.
Rev. 0
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AD7380/AD7381
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Resolution Boost ........................................................................ 19
Alert ............................................................................................. 19
Power Modes............................................................................... 20
Internal and External Reference............................................... 20
Software Reset............................................................................. 20
Diagnostic Self-Test ................................................................... 20
Interface ........................................................................................... 21
Reading Conversion Results ..................................................... 21
Low Latency Readback.............................................................. 22
Reading from Device Registers ................................................ 23
Writing to Device Registers ...................................................... 23
CRC.............................................................................................. 24
Registers........................................................................................... 27
Addressing Registers.................................................................. 27
CONFIGURATION1 Register ................................................. 28
CONFIGURATION2 Register ................................................. 29
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 6
Absolute Maximum Ratings............................................................ 8
Thermal Resistance ...................................................................... 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 13
Theory of Operation ...................................................................... 14
Circuit Information.................................................................... 14
Converter Operation.................................................................. 14
Analog Input Structure.............................................................. 14
ADC Transfer Function............................................................. 15
Applications Information .............................................................. 16
Power Supply............................................................................... 16
Modes of Operation ....................................................................... 17
Oversampling.............................................................................. 17
ALERT
Register.......................................................................... 29
ALERT_LOW_THRESHOLD Register .................................. 30
ALERT_HIGH_THRESHOLD Register................................. 30
Outline Dimensions....................................................................... 31
Ordering Guide .......................................................................... 31
REVISION HISTORY
1/2019—Revision 0: Initial Version
Rev. 0 | Page 2 of 31
Data Sheet
AD7380/AD7381
SPECIFICATIONS
VCC = 3.0 V to 3.6 V, VLOGIC = 1.65 V to 3.6 V, reference voltage (VREF) = 2.5 V internal, sampling frequency (fSAMPLE) = 4 MSPS, and
TA = −40°C to +125°C, no oversampling enabled, unless otherwise noted.
Table 1. AD7380
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RESOLUTION
16
Bits
THROUGHPUT
Conversion Rate
DC ACCURACY
4
MSPS
No Missing Codes
Differential Nonlinearity Error
Integral Nonlinearity Error
Gain Error
Gain Error Temperature Drift
Gain Error Match
Offset Error
16
Bits
LSB
LSB
−1.0
−2.0
−0.015
−11
−0.01
−0.2
−0.5
−2
0.7
0.75
0.002
1
0.002
0.01
+1.0
+2.0
+0.015
+11
+0.01
+0.2
+0.5
+2
% FS1
ppm/°C
% FS
mV
mV
µV/°C
mV
At 25°C, VCC = 3.3 V
Offset Temperature Drift
Offset Error Match
AC ACCURACY
0.5
0.1
−0.5
+0.5
Input frequency (fIN) = 1 kHz
VREF = 3.3 V external
Dynamic Range
93.3
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
91.8
95.2
92.5
91.1
98
Oversampled Dynamic Range
Signal-to-Noise Ratio (SNR)
OSR = 4
VREF = 3.3 V external
90
88.5
OSR = 8, RES = 1
OSR = 16, RES = 1
fIN = 100 kHz
101
89
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
−110
−113
−104
92.3
91
fIN = 100 kHz
VREF = 3.3 V external
Signal-to-(Noise + Distortion) (SINAD)
89.5
88
Channel to Channel Isolation
POWER SUPPLIES
−110
VCC Current (IVCC
)
Normal Mode (Operational)
Power Dissipation
21.5
83
26
mA
Total Power (PTOTAL
VCC Power (PVCC
Normal Mode (Operational)
)
107
94
mW
mW
)
71
1 These specifications include full temperature range variation, but they do not include the error contribution from the external reference.
Rev. 0 | Page 3 of 31
AD7380/AD7381
Data Sheet
VCC = 3.0 V to 3.6 V, VLOGIC = 1.65 V to 3.6 V, VREF = 2.5 V internal, fSAMPLE = 4 MSPS, and TA = −40°C to +125°C, no oversampling
enabled, unless otherwise noted.
Table 2. AD7381
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
RESOLUTION
14
Bits
THROUGHPUT
Conversion Rate
4
MSPS
DC ACCURACY
No Missing Codes
Differential Nonlinearity Error
Integral Nonlinearity Error
Gain Error
Gain Error Temperature Drift
Gain Error Match
14
Bits
LSB
LSB
% FS1
ppm/°C
% FS
LSB
µV/°C
LSB
−1.0
−1.0
−0.02
−20
−0.02
−2
0.5
0.3
0.002
+1.0
+1.0
+0.02
+20
+0.02
+2
1
0.002
0.25
0.5
Offset Error
Offset Temperature Drift
Offset Error Match
AC ACCURACY
+3
−1.5
+3
+1.5
0.25
fIN = 1 kHz
Dynamic Range
Oversampled Dynamic Range
Signal-to-Noise Ratio (SNR)
85.4
87
85.4
85
dB
dB
dB
OSR = 4
VREF = 3.3 V external
85
84.5
OSR = 8, RES = 1
OSR = 16, RES = 1
fIN = 100 kHz
92.6
94.5
84.6
−108
−112
−107
−112
−101
85.3
84.9
−110
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
Spurious-Free Dynamic Range (SFDR)
Total Harmonic Distortion (THD)
VREF = 3.3 V
VREF = 3.3 V
fIN = 100 kHz
Signal-to-(Noise + Distortion) (SINAD)
84.5
84
Channel to Channel Isolation
POWER SUPPLIES
IVCC
Normal Mode (Operational)
Power Dissipation
PTOTAL
21.5
83
26
mA
107
94
mW
mW
PVCC
Normal Mode (Operational)
71
1 These specifications include full temperature range variation, but they do not include the error contribution from the external reference.
Rev. 0 | Page 4 of 31
Data Sheet
AD7380/AD7381
Table 3. All Devices
Parameter
Test Conditions/Comments Min
Typ
Max
Unit
ANALOG INPUT
Voltage Range
Absolute Input Voltage
Common-Mode Input Range
(AINx+) – (AINx−)
AINx+, AINx−
AINx+, AINx−
−VREF
−0.1
+VREF
VREF + 0.1
V
V
V
0.2 to VREF
0.2
−
Analog Input Common-Mode Rejection
Ratio (CMRR)
fIN = 500 kHz
−75
dB
DC Leakage Current
Input Capacitance
0.1
18
5
1
µA
pF
pF
When in track mode
When in hold mode
SAMPLING DYNAMICS
Input Bandwidth
At −0.1 dB
At −3 dB
6
25
2
MHz
MHz
ns
Aperture Delay
Aperture Delay Match
Aperture Jitter
16
20
30
ps
ps
REFERENCE INPUT AND OUTPUT
VREF Input Voltage Range
VREF Input Current
External reference
External reference
At 25°C
2.49
3.4
V
mA
V
V
ppm/°C
ppm/V
ppm/mA
µA rms
nV/√Hz
0.47
2.5
0.51
2.502
2.505
10
VREF Output Voltage
2.498
2.495
−40°C to +125°C
VREF Temperature Coefficient
VREF Line Regulation
VREF Load Regulation
VREF Noise
VREF Noise Density
1
−38
−106
7
14
DIGITAL INPUTS (SCLK, SDI, CS)
Logic Levels
Input Low Voltage (VIL)
Input High Voltage (VIH)
Input Low Current (IIL)
Input High Current (IIH)
DIGITAL OUTPUTS (SDOA, SDOB/ALERT)
Output Coding
0.2 × VLOGIC
V
V
µA
µA
0.8 × VLOGIC
−1
−1
+1
+1
Twos complement
Bits
V
V
Output Low Voltage (VOL)
Output High Voltage (VOH)
Sink current (ISINK) = +300 µA
Source current (ISOURCE) =
−300 µA
0.4
VLOGIC − 0.3
Floating-State Leakage Current
Floating-State Output Capacitance
POWER SUPPLIES
1
µA
pF
10
VCC
3.0
3.2
1.65
3.3
3.3
3.6
3.6
3.6
V
V
V
External reference = 3.3 V
SDOA and SDOB at 0x1FFF
VLOGIC
IVCC
Normal Mode (Static)
Shutdown Mode
VLOGIC Current (IVLOGIC
2.3
100
2.8
200
mA
µA
)
Normal Mode (Static)
Normal Mode (Operational)
Shutdown Mode
10
3.5
10
200
3.7
200
nA
mA
nA
Rev. 0 | Page 5 of 31
AD7380/AD7381
Data Sheet
Parameter
Test Conditions/Comments Min
Typ
Max
Unit
Power Dissipation
PVCC
Normal Mode (Static)
Shutdown Mode
PVLOGIC
7.6
330
10
720
mW
µW
SDOA and SDOB at 0x1FFF
Normal Mode (Static)
Normal Mode (Operational)
Shutdown Mode
33
11.5
33
720
13.3
720
nW
mW
nW
TIMING SPECIFICATIONS
VCC = 3.0 V to 3.6 V, VLOGIC = 1.65 V to 3.6 V, VREF = 2.5 V internal, and TA = −40°C to +125°C, unless otherwise noted.
Table 4.1, 2
Parameter Min
Typ
Max
Unit Description
tCYC
tSCLKED
tSCLK
tSCLKH
tSCLKL
tCSH
250
0.4
12.5
5
5
10
10
ns
ns
ns
ns
ns
ns
ns
Time between conversions
falling edge to first SCLK falling edge
CS
SCLK period
SCLK high time
SCLK low time
CS
Interface quiet time prior to conversion
low to SDOx enabled
pulse width
tQUIET
tSDOEN
CS
5.5
8
ns
ns
ns
VLOGIC ≥ 2.25 V
1.65 V ≤ VLOGIC < 2.25 V
SCLK rising edge to SDO hold time
SCLK rising edge to SDO setup time
VLOGIC ≥ 2.25 V
1.65 V ≤ VLOGIC < 2.25 V
CS
rising edge to SDO high impedance
tSDOH
tSDOS
2
5.5
8
45
ns
ns
ns
ns
ns
ns
ns
ns
tSDOT
tSDIS
tSDIH
tSCLKCS
tCONVERT
tACQUIRE
tPOWERUP
1
1
0
SDI setup time prior to SCLK falling edge
SDI hold time after SCLK falling edge
SCLK rising edge to rising edge
CS
190
Conversion time
Acquire time
110
Supply active to conversion
5
11
5
ms
ms
ms
ms
First conversion allowed
Settled to within 1% with internal reference
Settled to within 1% with external reference
Supply active to register read write access allowed
Exiting power-down mode to conversion
Settled to within 1% with internal reference
Settled to within 1% with external reference
Conversion start time for first sample in oversampling (OS) normal mode
Conversion start time for xth sample in OS normal mode
For AD7380 at 3 MSPS
tREGWRITE
tSTARTUP
5
11
10
10
ms
µs
ns
2
tCONVERT0
tCONVERTx
4
7
ns
ns
tCONVERT0 + 320 × x −1
(
)
For AD7381 at 4 MSPS
tCONVERT0 + 250 × x −1
(
)
tALERTS
tALERTC
tALERTS_NOS
200
ns
ns
ns
indication (see Figure 34)
clear (see Figure 34)
CS ALERT
Time from to
12
12
CS ALERT
Time from to
Time from internal conversion with exceeded threshold to
ALERT
indication (see Figure 34)
1 All specifications are 10 pF load.
2 Guaranteed by design.
Rev. 0 | Page 6 of 31
Data Sheet
AD7380/AD7381
t
CYC
t
CSH
t
t
SCLKL
SCLKH
t
QUIET
t
SCLK
t
t
SCLKCS
SCLKED
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
TRISTATE
TRISTATE
TRISTATE
SDOA
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
15
14
14
13
13
12
12
11
10
10
9
9
8
8
7
7
6
5
5
4
3
3
2
2
1
1
0
TRISTATE
SDOB
SDI
DB
15
11
6
4
0
t
t
t
SDOT
SDOH
SDOS
t
SDOEN
DB
DB
14
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
0
15
13
12
11
10
9
8
7
6
5
4
3
2
1
t
t
SDIH
SDIS
Figure 2. Serial Interface Timing Diagram
t
CONVERT
CS
CONVERSION
ACQUIRE
CONVERSION
ACQUIRE
t
ACQUIRE
Figure 3. Internal Conversion Acquire Timing
t
POWERUP
V
CC
CS
Figure 4. Power-Up Time to Conversion
t
REGWRITE
V
CC
CS
SDI
REG WRITE
Figure 5. Power-Up Time to Register Read Write Access
t
STARTUP
CS
SDI
SHUTDOWN
POWERDOWN
NORMAL
NORMAL
MODE
ACCURATE
CONVERSION
MODE
Figure 6. Power-Down to Normal Mode Timing
CS
INTERNAL
CONVERSION
ACQUIRE
CONVERSION
ACQUIRE
CONVERSION
ACQUIRE
CONVERSION
ACQUIRE
tCONVERT2
tCONVERT3
tCONVERT4
1
t
CONVERTx
1
t
t
t
t
.
CONVERTx STANDS FOR CONVERT2, CONVERT3, OR CONVERT4
Figure 7. Conversion Timing During OS Normal Mode
Rev. 0 | Page 7 of 31
AD7380/AD7381
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 5.
Thermal performance is directly linked to printed circuit
board (PCB) design and operating environment. Careful
attention to PCB thermal design is required.
Parameter
Rating
VCC to Ground (GND)
VLOGIC to GND
−0.3 V to +4 V
−0.3 V to +4 V
Analog Input Voltage to GND
−0.3 V to VREF +0.3 V, VCC
0.3 V, 4 V
−0.3 V to VLOGIC + 0.3 V, 4 V
−0.3 V to VLOGIC + 0.3 V, 4 V
+
θ
JA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Digital Input Voltage to GND
Digital Output Voltage to GND
Reference Input and Output (REFIO) −0.3 V to VCC + 0.3 V, 4 V
Input to GND
Table 6. Thermal Resistance
Package Type
CP-16-451
θJA
θJC
Unit
Input Current to Any Pin Except
Supplies
10 mA
55.4
12.7
°C/W
1 Test Condition 1: thermal impedance simulated values are based on
JEDEC 2S2P thermal test board four thermal vias. See JEDEC JESDS1.
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
−40°C to +125°C
−65°C to +150°C
150°C
Pb-Free Soldering Reflow
Temperature
260°C
ESD CAUTION
Electrostatic Discharge (ESD)
Ratings
Human Body Model (HBM)
4 kV
Field Induced Charge Device
Model (FICDM)
1.25 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 8 of 31
Data Sheet
AD7380/AD7381
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD7380/AD7381
TOP VIEW
(Not to Scale)
GND
1
2
3
4
CS
12
V
11 REFIO
LOGIC
10
9
REGCAP
GND
V
REFCAP
CC
NOTES:
1. EXPOSED PAD. FOR CORRECT OPERATION OF THE DEVICE,
THE EXPOSED PAD MUST BE CONNECTED TO GROUND.
Figure 8. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 10
2
3
GND
VLOGIC
REGCAP
Ground Reference Point. This pin is the ground reference point for all circuitry on the device.
Logic Interface Supply Voltage, 1.65 V to 3.6 V. Decouple this pin to GND with a 1 µF capacitor.
Decoupling Capacitor Pin for Voltage Output from Internal Regulator. Decouple this pin to GND with a 1 µF
capacitor. The voltage at this pin is 1.9 V typical.
4
VCC
AINB−, AINB+
Power Supply Input Voltage, 3.0 V to 3.6 V. Decouple this pin to GND using a 1 µF capacitor.
Analog Inputs of ADC B. These analog inputs form a differential pair.
5, 6
7, 8
9
AINA−, AINA+ Analog Inputs of ADC A. These analog inputs form a differential pair.
REFCAP
Decoupling Capacitor Pin for Band Gap Reference. Decouple this pin to GND with a 1 µF capacitor. The
voltage at this pin is 2.5 V typical.
11
REFIO
Reference Input and Output. The on-chip reference of 2.5 V is available as an output on this pin for
external use if the device is configured accordingly. Alternatively, an external reference of 2.5 V to 3.3 V
can be input to this pin. Decoupling is required on this pin for both the internal and external reference
options. A 1 µF capacitor must be applied from this pin to GND.
12
13
14
Chip Select Input. Active low, logic input. This input provides the dual function of initiating conversions on
the AD7380 and the AD7381 and framing the serial data transfer.
Serial Data Output A. This pin functions as a serial data output pin to access the ADC A or ADC B
conversion results or data from any of the on-chip registers.
Serial Data Output B/Alert Indication Output. This pin can operate as a serial data output pin or alert
indication output.
CS
SDOA
SDOB/
ALERT
SDOB. This pin functions as a serial data output pin to access the ADC B conversion results.
ALERT. This pin operates as an alert pin going low to indicate that a conversion result has exceeded a
configured threshold.
15
16
SDI
SCLK
EPAD
Serial Data Input. This input provides the data written to the on-chip control registers.
Serial Clock Input. This serial clock input is for data transfers to and from the ADC.
Exposed Pad. For correct operation of the device, the exposed pad must be connected to ground.
Rev. 0 | Page 9 of 31
AD7380/AD7381
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VREF = 2.5 V internal, VCC = 3.6 V, VLOGIC = 3.3 V, fSAMPLE = 4 MSPS, fIN = 1 kHz, and TA = 25°C, unless otherwise noted.
0
2.0
SNR = 90.92dB
THD = –110.013dB
SNRD = 90.86dB
–20
1.5
–40
1.0
–60
0.5
–80
0
–100
–120
–140
–160
–180
–0.5
–1.0
–1.5
–2.0
0
20
40
60
80
100
FREQUENCY (kHz)
CODE
Figure 12. Typical Differential Nonlinearity (DNL) Error
Figure 9. Fast Fourier Transform (FFT), VREF = 2.5 V Internal
2.0
0
SNR = 92.07dB
THD = –104.40dB
SNRD = 91.83dB
1.5
1.0
–20
V
= 3.3V EXTERNAL
–40
–60
REF
0.5
–80
0
–100
–120
–140
–160
–180
–0.5
–1.0
–1.5
–2.0
0
20
40
60
80
100
CODE
FREQUENCY (kHz)
Figure 13. Typical Integral Nonlinearity (INL) Error
Figure 10. FFT, VREF = 3.3 V External
1.0
0
–20
SNR = 99.84dB
THD = –104.45dB
SNRD = 98.55dB
0.8
0.6
V
= 3.3V EXTERNAL
REF
–40
ROLLING AVERAGE AT OSR = 8x
RESOLUTION BOOST = ENABLED
POSITIVE INL
NEGATIVE INL
0.4
–60
0.2
–80
0
–100
–120
–140
–160
–180
–0.2
–0.4
–0.6
–0.8
–1.0
–40 –25 –10
5
20
35
50
65
95 110 125
80
0
20
40
60
80
100
FREQUENCY (kHz)
TEMPERATURE (°C)
Figure 11. FFT with Oversampling
Figure 14. Linearity Error vs. Temperature
Rev. 0 | Page 10 of 31
Data Sheet
AD7380/AD7381
160000
140000
120000
100000
80000
60000
40000
20000
0
146486
A
+ = A – = V
÷ 2
INx
INx
REF
92.5
90.5
88.5
86.5
84.5
82.5
262143 SAMPLES
97997
EXTERNAL REFERENCE = 3.3V, R = 10Ω
EXTERNAL REFERENCE = 3.3V, R = 33Ω
EXTERNAL REFERENCE = 3.3V, R = 200Ω
INTERNAL REFERENCE = 2.5V, R = 10Ω
INTERNAL REFERENCE = 2.5V, R = 33Ω
INTERNAL REFERENCE = 2.5V, R = 200Ω
13558
–1
4057
2
35
–2
10
3
1
10
100
1000
–4
–3
0
CODE
1
4
5
fIN (kHz)
Figure 15. DC Histogram Codes at Code Center
Figure 18. SNR vs. fIN
–70
–80
–50
–60
EXTERNAL REFERENCE = 3.3V
INTERNAL REFERENCE = 2.5V
EXTERNAL REFERENCE = 3.3V, R = 10Ω
EXTERNAL REFERENCE = 3.3V, R = 33Ω
EXTERNAL REFERENCE = 3.3V, R = 200Ω
INTERNAL REFERENCE = 2.5V, R = 10Ω
INTERNAL REFERENCE = 2.5V, R = 33Ω
INTERNAL REFERENCE = 2.5V, R = 200Ω
–70
–90
–80
–100
–110
–120
–130
–90
–100
–110
–120
1
10
100
1000
–40 –25 –10
5
20
35
50
65
95 110 125
80
fIN (kHz)
TEMPERATURE (°C)
Figure 19. THD vs. fIN
Figure 16. THD vs. Temperature
98
96
94
92
90
88
86
84
82
80
88
86
84
82
80
78
76
EXTERNAL REFERENCE = 3.3V
INTERNAL REFERENCE = 2.5V
EXTERNAL REFERENCE = 3.3V, R = 10Ω
EXTERNAL REFERENCE = 3.3V, R = 33Ω
EXTERNAL REFERENCE = 3.3V, R = 200Ω
INTERNAL REFERENCE = 2.5V, R = 10Ω
INTERNAL REFERENCE = 2.5V, R = 33Ω
INTERNAL REFERENCE = 2.5V, R = 200Ω
1
10
100
1000
–40 –25 –10
5
20
35
50
65
95 110 125
80
fIN (kHz)
TEMPERATURE (°C)
Figure 20. SINAD vs. fIN
Figure 17. SNR vs. Temperature
Rev. 0 | Page 11 of 31
AD7380/AD7381
Data Sheet
50
45
40
35
30
25
20
15
10
5
106
104
102
100
98
I
(SINEWAVE INPUT)
(SINEWAVE INPUT)
(POSITIVE FULL SCALE (PFS) INPUT)
(POSITIVE FULL SCALE (PFS) INPUT)
VCC
I
VLOGIC
I
VCC
I
VLOGIC
96
94
92
90
NORMAL AVERAGING
ROLLING AVERAGE
NORMAL AVERAGING, RES BOOST ENABLED
ROLLING AVERAGE, RES BOOST ENABLED
88
86
84
82
80
0
0
1
2
3
4
0
2
4
8
16
32
OVERSAMPLING RATIO
THROUGHPUT RATE (MSPS)
Figure 21. SNR vs. Oversampling Ratio
Figure 24. Dynamic Current at Different Input Signal vs. Throughput Rate
30
110
100
90
I
I
, INTERNAL REFERENCE = 2.5V
, EXTERNAL REFERENCE = 3.3V
VCC
VCC
25
20
15
10
5
80
70
60
50
0
40
–40 –25 –10
5
20
35
50
65
95 110 125
80
100
1k
1k
100k
1M
TEMPERATURE (°C)
RIPPLE FREQUENCY (Hz)
Figure 22. Supply Current Dynamic vs.Temperature
Figure 25. Power Supply Rejection Ratio (PSRR) vs. Ripple Frequency
500
450
400
350
300
250
200
150
100
50
–40
–50
–60
–70
–80
–90
–100
0
–110
–40 –25 –10
5
20
35
50
65
95 110 125
80
100
1k
1k
100k
1M
RIPPLE FREQUENCY (Hz)
TEMPERATURE (°C)
Figure 26. CMRR vs. Ripple Frequency
Figure 23. Shutdown Current vs. Temperature
Rev. 0 | Page 12 of 31
Data Sheet
AD7380/AD7381
TERMINOLOGY
Differential Nonlinearity (DNL)
Signal-to-Noise Ratio (SNR)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels (dB).
Integral Nonlinearity (INL)
INL is the deviation of each individual code from a line drawn
from negative full scale through positive full scale. The point
used as negative full scale occurs ½ LSB before the first code
transition. Positive full scale is defined as a level 1½ LSB beyond
the last code transition. The deviation is measured from the
middle of each code to the true straight line.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in dB, between the rms amplitude of the
input signal and the peak spurious signal.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Gain Error
The first transition (from 100 … 000 to 100 … 001) occurs at a
level ½ LSB above nominal negative full scale. The last
transition (from 011 … 110 to 011 … 111) occurs for an analog
voltage 1½ LSB below the nominal full scale. The gain error is
the deviation of the difference between the actual level of the
last transition and the actual level of the first transition from the
difference between the ideal levels.
Signal-to-(Noise + Distortion) (SINAD) Ratio
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components that are less than
the Nyquist frequency, including harmonics but excluding dc.
The value for SINAD is expressed in dB.
Common-Mode Rejection Ratio (CMRR)
CMRR is the ratio of the power in the ADC output at the
frequency, f, to the power of a 200 mV p-p sine wave applied to
Gain Error Drift
The gain error change due to a temperature change of 1°C.
the common-mode voltage of A
INx+ and AINx− of frequency, f.
Gain Error Matching
CMRR (dB) = 10log(PADC_IN/PADC_OUT
)
Gain error matching is the difference in negative full-scale error
between the input channels and the difference in positive full-
scale error between the input channels.
where:
ADC_IN is the common-mode power at the frequency, f, applied
to the AINx+ and AINx− inputs.
ADC_OUT is the power at the frequency, f, in the ADC output.
P
Zero Error
P
Zero error is the difference between the ideal midscale voltage,
0 V, and the actual voltage producing the midscale output code,
0 LSB.
Aperture Delay
Aperture delay is the measure of the acquisition performance
and is the time between the falling edge of the
when the input signal is held for a conversion.
input and
CS
Zero Error Drift
The zero error change due to a temperature change of 1°C.
Aperture Jitter
Aperture jitter is the variation in aperture delay.
Zero Error Matching
Zero error matching is the difference in zero error between the
input channels.
Rev. 0 | Page 13 of 31
AD7380/AD7381
Data Sheet
THEORY OF OPERATION
DACs are used to add and subtract fixed amounts of charge
CIRCUIT INFORMATION
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC output code. The output impedances of the
sources driving the AINX+ and AINX− pins must be matched.
Otherwise, the two inputs have different settling times, resulting
in errors.
The AD7380/AD7381 are high speed, dual simultaneous
sampling, fully differential 16-bit/14-bit, SAR ADCs. The
AD7380/AD7381 operate from a 3.0 V to 3.6 V power supply
and feature throughput rates up to 4 MSPS.
The AD7380/AD7381 contain two SAR ADCs and a serial
interface with two separate data output pins. The device is
housed in a 16-lead LFCSP, offering the user considerable space-
saving advantages over alternative solutions.
CAPACITIVE
DAC
Data is accessed from the device via the serial interface. The
interface can operate with two or one serial outputs. The
AD7380/AD7381 have an on-chip 2.5 V internal reference, VREF. If
an external reference is desired, the internal reference can be
disabled, and a reference value ranging from 2.5 V to 3.3 V can
be supplied. If the internal reference is used elsewhere in the
system, the reference output must be buffered. The differential
analog input range for the AD7380/AD7381 is the common-
COMPARATOR
C
C
B
A
S
A
A
+
–
INx
SW1
SW2
CONTROL
LOGIC
SW3
S
A
B
INx
V
REF
CAPACITIVE
DAC
Figure 28. ADC Conversion Phase
mode voltage (VCM
)
VREF/2.
ANALOG INPUT STRUCTURE
The AD7380/AD7381 feature on-chip oversampling blocks to
improve performance. Normal averaging and rolling average
oversampling modes and power-down options that allow power
saving between conversions are also available. Configuration of
the devices are implemented via the standard serial interface
(see the Interface section).
Figure 29 shows the equivalent circuit of the analog input structure
of the AD7380/AD7381. The four diodes provide ESD protection
for the analog inputs. Care must be taken to ensure that the
analog input signals never exceed the supply rails by more than
300 mV. Exceeding the limit causes these diodes to become
forward-biased and start conducting into the substrate. These
diodes can conduct up to 10 mA without causing irreversible
damage to the device.
CONVERTER OPERATION
The AD7380/AD7381 have two SAR ADCs, each based around
two capacitive digital-to-analog converters (DACs). Figure 27
and Figure 28 show simplified schematics of one of these ADCs
in acquisition and conversion phases, respectively. The ADC
comprises control logic, an SAR, and two capacitive DACs. In
Figure 27 (the acquisition phase), SW3 is closed, SW1 and SW2
are in Position A, the comparator is held in a balanced
condition, and the sampling capacitor (CS) arrays can acquire
the differential signal on the input.
The C1 capacitors in Figure 29 are typically 3 pF and can primarily
be attributed to pin capacitance. The R1 resistors are lumped
components made up of the on resistance of the switches. The
value of these resistors is typically about 200 Ω. The C2 capacitors
are sampling capacitors of the ADC with a capacitance of 15 pF
typically.
V
DD
D
D
C2
R1
CAPACITIVE
DAC
A
+
IN
C1
COMPARATOR
C
C
B
A
S
A
A
+
–
INx
SW1
SW2
CONTROL
LOGIC
SW3
V
DD
S
A
B
INx
D
D
C2
R1
A
–
IN
V
REF
CAPACITIVE
DAC
C1
Figure 27. ADC Acquisition Phase
Figure 29. Equivalent Analog Input Circuit,
Conversion Phase—Switches Open, Track Phase—Switches Closed
When the ADC starts a conversion (see Figure 28), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected when the
conversion begins. The control logic and charge redistribution
Rev. 0 | Page 14 of 31
Data Sheet
AD7380/AD7381
ADC TRANSFER FUNCTION
The AD7380/AD7381 can use a 2.5 V to 3.3 V reference, VREF
The AD7380/AD7381 convert the differential voltage of the
analog inputs (AINA+, AINA−, AINB+, and AINB−) into a digital
output.
.
011 ... 111
011 ... 110
011 ... 101
The conversion result is MSB first, twos complement. The LSB
size is (2 × VREF)/2N, where N is the ADC resolution. The ADC
resolution is determined by the resolution of the device chosen,
and if resolution boost mode is enabled. Table 8 outlines the
LSB size expressed in volts for different resolutions and reference
voltages options.
100 ... 010
100 ... 001
100 ... 000
The ideal transfer characteristic for the AD7380/AD7381 is
shown in Figure 30.
–FSR
–FSR – 1LSB
+FSR – 1LSB
–FSR – 0.5LSB
+FSR – 1.5LSB
Figure 30. ADC Ideal Transfer Function (FSR = Full-Scale Range)
Table 8. LSB Size
Resolution 2.5 V Reference
3.3 V Reference
Unit
µV
µV
14-bit
16-bit
18-bit
305.2
76.3
19.1
402.8
100.7
25.2
µV
Rev. 0 | Page 15 of 31
AD7380/AD7381
Data Sheet
APPLICATIONS INFORMATION
Figure 31 shows an example of a typical application circuit for
interface, respectively. Decouple both the VCC supply and the
the AD7380/AD7381. Decouple the VCC,
V
LOGIC, REGCAP, and
VLOGIC supply separately with a 1 µF capacitor. Additionally,
REFIO pins with suitable decoupling capacitors as shown.
there is an internal low dropout (LDO) regulator that supplies the
AD7380/AD7381. The on-chip regulator provides a 1.9 V
supply for internal use on the devices only. Decouple the
REGCAP pin with a 1 µF capacitor to GND.
The exposed pad is a ground reference point for circuitry on the
device and must be connected to the board ground.
A differential resistor capacitor (RC) filter must be placed on
the analog inputs to ensure performance is achieved.
Power-Up
The AD7380/AD7381 are robust to power supply sequencing.
The performance of the AD7380/AD7381 device may be
impacted by noise on the digital interface. This impact is
dependent on board layout and design. Keep a minimal
distance of the digital line to the digital interface or place a
100 Ω resistor in series and close to the SDOA pin and
SDOB pin to reduce noise from the digital interface coupling of
the AD7380/AD7381.
VCC and VLOGIC can be applied in any sequence. An external
reference must be applied after VCC and VLOGIC are applied.
The AD7380/AD7381 require a tPOWERUP time from applying VCC
and VLOGIC until the ADC conversion results are stable.
Applying
pulses or interfacing with the AD7380/AD7381
CS
prior to the setup time elapsing does not have a negative impact
on ADC operation. Conversion results are not guaranteed to
meet data sheet specifications during this time, however, and
must be ignored.
POWER SUPPLY
The AD7380/AD7381 have two independent power supplies,
V
CC and VLOGIC, that supply the analog circuitry and digital
3.3V
3.3V
1µF
1µF
68pF
V
V
33Ω
CC
LOGIC
A
A
A+
A–
IN
330pF
AD7380/AD7381
33Ω
IN
68pF
REF
SDI
SDOA
SDOB
100Ω
100Ω
REFIO
GND
EXPOSED
PAD
1µF
SCLK
CS
68pF
33Ω
33Ω
A
A
B+
B–
IN
REGCAP
330pF
68pF
1µF
IN
GND
Figure 31. Typical Application Circuit
Rev. 0 | Page 16 of 31
Data Sheet
AD7380/AD7381
MODES OF OPERATION
The AD7380/AD7381 have several on-chip configuration
registers for controlling the operational mode of the device.
latency before the register gets updated. The oversampling ratio
of the digital filter is controlled using the oversampling bits,
OSR[2:0], which provides the oversampling bit decoding to
select the different oversample rates. The output result is
decimated to 16-bit resolution for the AD7380 and a 14-bit
resolution for the AD7381. If additional resolution is required,
this can be achieved by configuring the resolution boost bit in
the CONFIGURATION1 register. See the Resolution Boost
section for further details.
OVERSAMPLING
Oversampling is a common method used in analog electronics
to improve the accuracy of the ADC result. Multiple samples of
the analog input are captured and averaged to reduce the noise
component from quantization noise and thermal noise (kTC) of
the ADC. The AD7380/AD7381 offer an oversampling function
on-chip and have two user configurable oversampling modes,
normal averaging and rolling average.
The number of samples, n, defined by the OSR[2:0] bits are
taken, added together, and the result is divided by n. The initial
The oversampling functionality is configured by
programming the OS_MODE bit and OSR[2:0] bits in the
CONFIGURATION1 register.
CS
ADC conversion is initiated by the falling edge of , and the
AD7380/AD7381 control all subsequent samples in the
oversampling sequence internally. The sampling rate of the
additional n samples is at 3 MSPS for the AD7380 and 4 MSPS
for AD7381 in oversampling mode. The oversampled
conversion result is ready for read back on the next serial interface
access. After the technique is applied, the sample data used in
the calculation is discarded. This process is repeated every time
the application needs a new conversion result and initiates by
Normal Averaging Oversampling
Normal oversampling mode can be used in applications where
slower output data rates are allowable and where higher SNR or
dynamic range is desirable. Normal averaging involves taking a
number of samples, adding the samples together, and dividing
the result by the number of samples taken. This result is then
output from the device. The sample data is cleared after the
process is completed.
CS
the falling edge of
.
As the output data rate is reduced by the oversampling ratio,
the SPI SCLK frequency required to transmit the data is also
reduced accordingly.
Normal oversampling mode is configured by setting the
OS_MODE bit to Logic 0 and having a valid nonzero value in
the OSR[2:0] bits. Writing to the OSR[2:0] bits has a two cycle
Table 9. AD7380/AD7381 Normal Averaging Oversampling Performance Overview
AD7380
AD7381
SNR (dB typical)
VREF = 2.5 V
VREF = 3.3 V
SNR (dB typical)
Oversampling
Ratio
Output Data Rate
Output Data Rate
RES = 0 RES = 1 RES = 0 RES = 1 (kSPS maximum)
RES = 0 RES = 1 (kSPS maximum)
Disabled
2
4
8
16
32
90.8
92.6
94.3
95.8
96.3
96.5
90.8
93.6
96.5
99.2
100.4
100.5
92.5
94.0
95.4
96.3
96.8
97.0
92.5
95.5
98.2
100.5
102.0
102.8
3000
1500
750
375
187.5
93.75
85.2
84.7
85.2
85.5
85.7
85.9
85.2
88
91.1
93
94.6
95.6
4000
2000
1000
500
250
125
CS
INTERNAL
S
ACQ
S
S
ACQ
S
ACQ
S
S
ACQ
1
2
n
1
2
n
DON’T CARE
DON’T CARE
t0 RESULT
t0 RESULT
SDOA
SDOB
CONVERT START AT t1
Figure 32. Normal Averaging Oversampling Operation
Rev. 0 | Page 17 of 31
AD7380/AD7381
Data Sheet
In rolling average oversampling mode, all ADC conversions are
Rolling Average Oversampling
CS
controlled and initiated by the falling edge of . After a
Rolling oversampling mode can be used in applications where
higher output data rates are required and where higher SNR or
dynamic range is desirable. Rolling averaging involves taking a
number of samples, adding the samples together, and dividing
the result by the number of samples taken. This result is then
output from the device. The sample data is not cleared after the
process is completed. The rolling oversampling mode uses a
first in, first out (FIFO) buffer of the most recent samples in the
averaging calculation, allowing the ADC throughput rate and
output data rate to stay the same.
conversion is complete, the result is loaded into the FIFO. The
FIFO length is 8, regardless of the oversampling ratio set. The
FIFO is filled on the first conversion after a power-on reset, the
first conversion after a software controlled hard or soft reset, or
the first conversion after the REFSEL bit is toggled. A new
conversion result is shifted into the FIFO on completion of
every ADC conversion, regardless of the status of the OSR[2:0] bits
and the OS_MODE bit. This conversion allows a seamless
transition from no oversampling to rolling average
oversampling, or different rolling average oversampling ratios
without waiting for the FIFO to fill.
Rolling oversampling mode is configured by setting the
OS_MODE bit to Logic 1 and having a valid nonzero value in
the OSR[2:0] bits. The oversampling ratio of the digital filter is
controlled using the oversampling bits, OSR[2:0] (see Table 10).
The output result is decimated to 16-bit resolution for the AD7380
and a 14-bit result for the AD7381. If additional resolution is
required, this resolution can be achieved by configuring the
resolution boost bit in the CONFIGURATION1 register. See the
Resolution Boost section for further details.
The number of samples, n, defined by the OSR[2:0] bits are
taken from the FIFO, added together, and the result is divided
falling edges is the cycle time which
can be controlled by the user, depending on the desired data
output rate.
CS
by n. The time between
Table 10. AD7380/AD7381 Rolling Averaging Oversampling Performance Overview
AD7380
AD7381
SNR (dB typical)
VREF = 2.5 V
VREF = 3.3 V
SNR (dB typical)
Oversampling
Ratio
Output Data Rate (kSPS
Output Data Rate (kSPS
RES = 0 RES = 1 RES = 0 RES = 1 maximum)
RES = 0 RES = 1 maximum)
Disabled
91
92
94
95.5
91
93
96
98.6
92.5
93.2
94.8
95.9
92.5
94.5
97.2
99.6
4000
4000
4000
4000
85
84.5
85
85
87.7
91
4000
4000
4000
4000
2
4
8
85.5
93
VDD
CS
INTERNAL
S
ACQ
S
ACQ
S
ACQ
S
ACQ
S
ACQ
S
ACQ
S
7
ACQ
...
1
2
3
4
5
6
SDI
ENABLE OS = 4
(FIFO
ENABLE OS = 2
(FIFO
+
+
(FIFO
+
(FIFO + FIFO +
1 2
1
1
1
FIFO )/2
FIFO )/2
FIFO )/2
FIFO + FIFO )/4
2
2
2
3
4
SDOA
SDOB
DON’T CARE
FIFO
S1
S2
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
7
S
6
S
5
S
4
S
3
S
2
S
1
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
2
1
4
3
2
1
5
4
3
2
1
6
5
4
3
2
1
–
1
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Figure 33. Rolling Average Oversampling Operation
Rev. 0 | Page 18 of 31
Data Sheet
AD7380/AD7381
The register contains two status bits per ADC, one corresponding
to the high limit, and the other to the low limit. A logical OR of
alert signals for all ADCs creates a common alert value. This
RESOLUTION BOOST
The default conversion result output data size for the AD7380 is
16-bits and for the AD7381 is 14-bits. When the on-chip
oversampling function is enabled, the performance of the ADC
can exceed the 16-bit level for the AD7380 or the 14-bit level for
the AD7381. To accommodate the performance boost achievable, it
is possible to enable an additional two bits of resolution. If the RES
bit in the CONFIGURATION1 register is set to Logic 1 and the
AD7380/AD7381 are in a valid oversampling mode, the
conversion result size for the AD7380 is 18-bits and for the
AD7381 is 16-bits. In this mode, 18 SCLKs are required to
propagate the data for the AD7380 and 16 SCLKs are required
for the AD7381.
ALERT
value can be configured to drive out on the
function of
pin is configured as
ALERT
the SDOB/ pin. The SDOB/
ALERT
ALERT
by configuring the following bits in the
CONFIGURATION1 register and the
CONFIGURATION2 register:
•
•
•
Set the SDO bit to 1.
Set the ALERT_EN bit to 1.
Set a valid value to the ALERT_HIGH_THRESHOLD
register and the ALERT_LOW_THRESHOLD register.
The alert indication function is available in oversampling, both
rolling average and normal averaging, and in nonoversampling
modes.
ALERT
The alert functionality is an out of range indicator and can be
used as an early indicator of an out of bounds conversion result.
An alert event triggers when the conversion result value register
exceeds the alert high limit value in the
ALERT_HIGH_THRESHOLD register or falls below the alert
low limit value in the ALERT_LOW_THRESHOLD register.
The ALERT_HIGH_THRESHOLD register and the
ALERT_LOW_THRESHOLD register are common to all ADCs.
When setting the threshold limits, the alert high threshold must
always be greater than the alert low threshold. Detailed alert
ALERT
The
function of the SDOB/
pin gets updated at
ALERT
the end of conversion. The alert indication status bits in the
register get updated as well and must be read before the
ALERT
ALERT
end of next conversion. The
SDOB/
function of the
CS
pin is cleared with a falling edge of . Issuing a
ALERT
software reset also clears the alert status in the
register.
ALERT
information is accessible in the
register.
ALERT
t
t
ALERTS
ALERTC
CS
SDOA
NO OVERSAMPLING OR
ROLLING AVARAGES OS
INTERNAL
CONV
ACQ
CONV
ACQ
CONV
ACQ
CONV
ACQ
ALERT
EXCEEDS THRESHOLD
CS
SDOA
NORMAL
OVERSAMPLING
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
C
A
INTERNAL
ALERT
EXCEEDS THRESHOLD
t
t
ALERTC
ALERTS_NO
Figure 34. Alert Operation
Rev. 0 | Page 19 of 31
AD7380/AD7381
Data Sheet
sufficient time must be allowed for the circuitry to turn on
POWER MODES
before starting a conversion. If the internal reference is enabled,
the reference must be allowed to settle for accurate conversions to
happen.
The AD7380/AD7381 have two power modes, normal mode
and shutdown mode. These modes of operation provide flexible
power management options, allowing optimization of the
power dissipation and throughput rate ratio for different
application requirements.
INTERNAL AND EXTERNAL REFERENCE
The AD7380/AD7381 have a 2.5 V internal reference.
Alternatively, if a more accurate reference or higher dynamic
range is required, an external reference can be supplied. An
externally supplied reference can be in the range of 2.5 V to 3.3 V.
Program the PMODE bit in the CONFIGURATION1 register to
configure the power modes in the AD7380/AD7381. Set PMODE
to Logic 0 for normal mode and Logic 1 for shutdown mode.
Normal Mode
Reference selection, internal/external, is configured by the
REFSEL bit in the CONFIGURATION1 register. If REFSEL is
set to 0, the internal reference buffer is enabled. If an external
reference is preferred, the REFSEL bit must be set to 1, and an
external reference must be supplied to the REFIO pin.
Keep the AD7380/AD7381 in normal mode to achieve the
fastest throughput rate. All blocks within the AD7380/AD7381
remain fully powered at all times, and an ADC conversion can
CS
be initiated by a falling edge of , when required. When the
AD7380/AD7381 are not converting, the devices are in static
mode, and power consumption is automatically reduced.
Additional current is required to perform a conversion,
therefore, power consumption on the AD7380/AD7381 scales
with throughput.
SOFTWARE RESET
The AD7380/AD7381 have two reset modes, a soft reset and a
hard reset. A reset is initiated by writing to the RESET[7:0] bits
in the CONFIGURATION2 register.
A soft reset maintains the contents of the configurable registers
but refreshes the interface and the ADC blocks. Any internal
state machines are reinitialized, and the oversampling block and
FIFO are flushed. The
ALERT
and LDO remain powered.
Shutdown Mode
When slower throughput rates and lower power consumption
are required, use shutdown mode by either powering down the
ADC between each conversion or by performing a series of
conversions at a high throughput rate and then powering down
the ADC for a relatively long duration between these burst
conversions. When the AD7380/AD7381 are in shutdown
mode, all analog circuitry powers down, including the internal
reference, if enabled. The serial interface remains active during
shutdown mode to allow the AD7380/AD7381 to exit shutdown
mode.
register is cleared. The reference
A hard reset, in addition to the blocks reset by a soft reset, resets
all user registers to the default status, resets the reference buffer,
and resets the internal oscillator block.
DIAGNOSTIC SELF-TEST
The AD7380/AD7381 run a diagnostic self test after a power-on
reset (POR) or after a software hard reset to ensure correct
configuration is loaded into the device.
To enter shutdown mode, write to the PMODE bit in
theCONFIGURATION1 register. The AD7380/AD7381 shuts
down and current consumption reduces.
The result of the self test is displayed in the SETUP_F bit in the
register. If the SETUP_F bit is set to Logic 1, the
ALERT
To exit shutdown mode and return to normal mode, set the
PMODE bit in the CONFIGURATION1 register to Logic 0. All
register configuration settings remain unchanged entering or
leaving shutdown mode. After exiting shutdown mode,
diagnostic self test has failed. If the test fails, perform a software
hard reset to reset the AD7380/AD7381 registers to the default
status.
t
STARTUP
CS
SDI
SHUTDOWN
POWER-DOWN
NORMAL
NORMAL
MODE
ACCURATE
CONVERSION
MODE
Figure 35. Shutdown Mode Operation
Rev. 0 | Page 20 of 31
Data Sheet
AD7380/AD7381
INTERFACE
The interface to the AD7380/AD7381 is via a serial interface.
READING CONVERSION RESULTS
CS
The interface consists of a , SCLK, SDOA, SDOB, and SDI pins.
CS
The
signal initiates the conversion process. A high to low
CS
CS
The
signal frames a serial data transfer and initiates an ADC
CS
transition on the
signal initiates a simultaneous conversion
of both ADCs, ADC A and ADC B. The AD7380/AD7381 have
conversion process. The falling edge of
puts the track-and-
a one cycle readback latency. Therefore, the conversion results
CS
hold into hold mode, at which point the analog input is sampled,
and the bus is taken out of three-state.
are available on the next SPI access. Then, take the
signal
low, and the conversion result clocks out on the serial output
pins. The next conversion is also initiated at this point.
The SCLK signal synchronizes data in and out of the device via
the SDOA, SDOB, and SDI signals. A minimum of 16 SCLKs
are required for a write to or read from a register. The minimum
numbers of SCLKs for a conversion read is dependent on the
resolution of the device and the configuration settings, see
Table 11.
The conversion result is shifted out of the device as a 16-bit
result for the AD7380 and a 14-bit result for the AD7381. The
CS
MSB of the conversion result is shifted out on the
falling
edge. The remaining data is shifted out of the device under the
control of the SCLK input. The data is shifted out on the rising
edge of the SCLK, and the data bits are valid on both the falling
The ADC conversion operation is driven internally by an on-
board oscillator and is independent of the SCLK signal.
CS
edge and the rising edge. After the final SCLK falling edge, take
high again to return the SDOx pins to a high impedance state.
The AD7380/AD7381 have two serial output signals, SDOA
and SDOB. To achieve the highest throughput of the device, use
both SDOA and SDOB, 2-wire mode, to read the conversion
results. If a reduced throughput is required or oversampling is
used, it is possible to use 1-wire mode, SDOA signal only, for
reading conversion results. Programming the SDO bit in the
CONFIGURATION2 register configures 2-wire or 1-wire mode.
The number of SCLK cycles to propagate the conversion results
on the SDOx pins is dependent on the serial mode of operation
configured and if resolution boost mode is enabled, see Figure 36
and Table 11 for details. If CRC reading is enabled, this requires
additional SCLK pulses to propagate the CRC information, see
the CRC section for more details.
Configuring the cyclic redundancy check (CRC) operation for
SPI reads or SPI writes alters the operation of the interface. The
relevant sections of this data sheet must be consulted to ensure
correct operation.
CS
As the
signal initiates a conversion, as well as framing the
data, any data access must be completed within a single frame.
CS
1
SCLK
SDOx
1
2
3
n–2
n–1
n
CONVERSION RESULT
1
CONSULT TABLE 11 FOR n, THE NUMBER OF SCLK PULSES REQUIRED
Figure 36. Reading Conversion Result
Table 11. Number of SCLKs, n, Required for Reading Conversion Results
Interface Configuration
Resolution Boost Mode
CRC Read
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
AD7380
16
24
18
26
AD7381
14
22
16
24
2-Wire
Disabled
Enabled
Disabled
Enabled
1-Wire
32
40
36
44
28
36
32
40
Rev. 0 | Page 21 of 31
AD7380/AD7381
Data Sheet
Serial 2-Wire Mode
it is possible to enable an additional two bits of resolution in the
conversion output data. If the RES bit in the
CONFIGURATION1 register is set to Logic 1 and the
AD7380/AD7381 are in a valid oversampling mode, the
conversion result size for the AD7380 is 18-bit and 16-bit for
the AD7381.
Configure 2-wire mode by setting the SDO bit in the
CONFIGURATION1 register to 0. In 2-wire mode, the
conversion result for ADC A is output on the SDOA pin, and the
conversion result for ADC B is output on the SDOB pin. See
Figure 37.
When the resolution boost mode is enabled, 18 SCLKs are
required for the AD7380 and 16 SCLKs are required for the
AD7381 to propagate the data.
Serial 1-Wire Mode
In applications where slower throughput rates are allowed, or
normal averaging oversampling is used, the serial interface can
be configured to operate in 1-wire mode. In 1-wire mode, the
conversion results from ADC A and ADC B are output on the
serial output, SDOA. Additional SCLK cycles are required to
propagate all the data. ADC A data is output first, followed by
ADC B conversion results. See Figure 38.
LOW LATENCY READBACK
The interface on the AD7380/AD7381 has a one cycle latency as
shown in Figure 39. For applications that operate at lower
throughput rates, the latency of reading the conversion result
can be reduced. After the conversion time elapses, tCONVERT, a
CS
CS
second
pulse after the initial
pulse that initiates the
Resolution Boost Mode
conversion, can be used to readback the conversion result. This
operation is shown in Figure 39.
The default resolution and output data size for the AD7380 is
16-bits and for the AD7381 is 14-bits. Enabling the on-chip
oversampling function reduces noise and improves the device
performance. To accommodate the performance boost achievable,
S
S
S
S
3
0
1
2
CS
SDOA
SDOB
SDI
DON’T CARE
DON’T CARE
NOP
ADC A S
ADC B S
NOP
ADC A S
ADC B S
NOP
0
0
1
1
Figure 37. Reading Conversion Results for 2-Wire Mode
S
S
S
S
3
0
1
2
CS
DON’T CARE
NOP
ADC A S ADC B S
ADC A S ADC B S
SDOA
SDI
0
0
1
1
NOP
NOP
Figure 38. Read Conversion Results for 1-Wire Mode
CS
CNV
DON’T CARE
RESULT
ACQ
CNV
DON’T CARE
ACQ
n
n
INTERNAL
SDOA
SDOB
RESULT
n
n+1
SCLK
TARGET SAMPLE PERIOD
Figure 39. Low Throughput Low Latency
Rev. 0 | Page 22 of 31
Data Sheet
AD7380/AD7381
READING FROM DEVICE REGISTERS
WRITING TO DEVICE REGISTERS
All the registers in the device can be read over the serial interface.
A register read is performed by issuing a register read command
followed by an additional SPI command that can be either a
valid command or NOP. The format for a read command is
shown in Table 14. Bit D15 must be set to 0 to select a read
command. Bits[D14:D12] contain the register address, and the
subsequent twelve bits, Bits[D11:D0], are ignored.
All the read/write registers in the AD7380/AD7381 can be
written to over the serial interface. The length of an SPI write
access is determined by the CRC write function. An SPI access
is 16-bit if CRC write is disabled and is 24-bit when CRC write
is enabled. The format for a write command is shown in Table 15.
Bit D15 must be set to 1 to select a write command. Bits[D14:D12]
contain the register address, and the subsequent twelve bits,
Bits[D11:D0], contain the data to be written to the selected register.
S
S
S
S
S
0
1
2
3
4
CS
NOP
READ REG 1
READ REG 2
REG 1DATA
NOP
NOP
SDI
SDOA
SDOB
INVALID
INVALID
RESULT S
REG 2DATA
RESULT S
3
0
RESULT S
RESULT S
3
0
Figure 40. Register Read
S
S
S
S
3
0
1
2
CS
NOP
WRITE REG 1
WRITE REG 2
NOP
SDI
SDOA
SDOB
INVALID
RESULT S
RESULT S
RESULT S
2
0
1
Figure 41. Register Write
Rev. 0 | Page 23 of 31
AD7380/AD7381
Data Sheet
CRC Polynomial
CRC
For CRC checksum calculations, the following polynomial is
always used: x8 + x2 + x + 1.
The AD7380/AD7381 have CRC checksum modes that can be
used to improve interface robustness by detecting errors in data
transmissions. The CRC feature is independently selectable for
SPI interface reads and SPI interface writes. For example, the
CRC function for SPI writes can be enabled to prevent
unexpected changes to the device configuration but disabled on
SPI reads, thus maintaining a higher throughput rate. The CRC
feature is controlled by programming of the CRC_W and
CRC_R bits in the CONFIGURATION1 register.
The following is an example of how to generate the checksum
on a conversion read. The 16-bit data conversion result of the
two channels are combined to produce a 32-bit data. The
8 MSBs of the 32-bit data are inverted and then left shifted by
eight bits to create a number ending in eight logic zeros. The
polynomial is aligned such that its MSB is adjacent to the
leftmost Logic 1 of the data. An exclusive or (XOR) function is
applied to the data to produce a new, shorter number. The
polynomial is again aligned such that its MSB is adjacent to the
leftmost Logic 1 of the new result, and the procedure is repeated.
This process repeats until the original data is reduced to a value
less than the polynomial, which is the 8-bit checksum. For
example, our polynomial is 100000111.
CRC Read
If enabled, a CRC is appended to the conversion result or
register reads and consists of an 8-bit word. The CRC is
calculated in the conversion result for ADC A and ADC B and
is output on SDOA. A CRC is also calculated and appended to
register read outputs.
Let the original data of two channels be 0xAAAA and 0x5555,
that is, 1010 1010 1010 1010 and 0101 0101 0101 0101. The data
of the two channels is then appended including eight zeros on
the right. The data then becomes 1010 1010 1010 1010 0101
0101 0101 0101 0000 0000.
The CRC read function can be used in 2-wire SPI mode, 1-wire
SPI mode, and resolution boost mode.
CRC Write
To enable the CRC write function, the CRC_W bit in the
CONFIGURATION1 register must be set to 1. To set the
CRC_W bit to 1 to enable the CRC feature, the request frame
must have a valid CRC appended to the frame.
Table 12 shows the CRC calculation of 16-bit two-channel data.
In the final XOR operation, the reduced data is less than the
polynomial. Therefore, the remainder is the CRC for the
assumed data.
After the CRC feature is enabled, all register write requests are
ignored unless accompanied by a valid CRC command,
requiring a valid CRC to both enable and disable the CRC write
feature.
The same process is followed for the AD7381, but instead of
dealing with 32-bit data (combined result of two channels), it is
28-bit data. For reading data like the registers, CRC computation is
based from a 16-bit register data, and the same process is
performed as described for a 32-bit data.
Rev. 0 | Page 24 of 31
Data Sheet
AD7380/AD7381
Table 12. Example CRC Calculation for 2 16-Bit Data
Data
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
x
0
x
0
x
0
x
0
x
0
x
0
x
0
x
0
Process Data 0
1
0
1
0
1
0
1
1
0
1
0
1
0
1 0 0 0 0 0 1 1 1
1 0 1 0 0 0 1 1 0
1 0 0 0 0 0 1 1 1
1 0 0 0 0 0 1 1 0
1 0 0 0 0 0 1 1 1
1 1 0 0 1 0 1 0 1
1 0 0 0 0 0 1 1 1
1 0 0 1 0 0 1 0 0
1 0 0 0 0 0 1 1 1
1 0 0 0 1 1 1 0 1
1 0 0 0 0 0 1 1 1
1 1 0 1 0 0 1 0 1
1 0 0 0 0 0 1 1 1
1 0 1 0 0 0 1 0 0
1 0 0 0 0 0 1 1 1
1 0 0 0 0 1 1 1 0
1 0 0 0 0 0 1 1 1
1 0 0 1 0 0 0 0 0
1 0 0 0 0 0 1 1 1
1 0 0 1 1 1 0 0
CRC
Rev. 0 | Page 25 of 31
AD7380/AD7381
Data Sheet
16 + 8 = 24 BITS
RESULT A
CRC
SDOA
SDOB
A,B
2-WIRE 16-BIT
1-WIRE 16-BIT
RESULT B
16 + 16 + 8 = 40 BITS
RESULT B
RESULT A
CRC
SDOA
A,B
16 + 8 = 24 BITS
RESULT A
RESULT B
CRC
A,B
SDOA
SDOB
2-WIRE 18-BIT
1-WIRE 18-BIT
18 + 18 + 8 = 44 BITS
RESULT B
RESULT A
CRC
A,B
SDOA
16 + 8 = 24 BITS
REGISTER X
CRC
REGISTER READ RESULT
REGISTER READ REQUEST
REGISTER WRITE
SDOA
SDI
REG X
REG X
REG X
16 + 8 = 24 BITS
REGISTER X
CRC
16 + 8 = 24 BITS
WRITE REGISTER X
CRC
SDI
Figure 42. CRC Operation
Rev. 0 | Page 26 of 31
Data Sheet
REGISTERS
AD7380/AD7381
The AD7380/AD7381 have user programmable on-chip registers for configuring the device. Table 13 shows a complete overview of the
registers available on the AD7380/AD7381. The registers are either read/write (R/W) or read only (R). Any read request to a write only
register is ignored. Any write request to a read only register is ignored. Writes to any other register address are considered a no operation
command (NOP) and are ignored. Any read request to a register address, other than those listed in Table 13, are considered an NOP, and
the data transmitted in the next SPI frame are the conversion results.
Table 13. Register Summary
Bit 15
Bit 7
Bit 14
Bit 6
Bit 13
Bit 5
Bit 12
Bit 4
Bit 11
Bit 3
Bit 10
Bit 2
Bit 9
Bit 8
Hex. No.
Register Name
Bits
Bit 1
Bit 0
Reset
R/W
0x1
CONFIGURATION1
[15:8]
[7:0]
ADDRESSING
CRC_W
RESERVED
OS_MODE
REFSEL
OSR[2]
PMODE
0x0000
R/W
OSR[1:0]
CRC_R
ALERT_EN
RES
0x2
0x3
0x4
0x5
CONFIGURATION2
ALERT
[15:8]
[7:0]
ADDRESSING
RESERVED
SDO
0x0000
0x0000
0x0800
0x07FF
R/W
R/W
R/W
R/W
RESET
[15:8]
[7:0]
ADDRESSING
AL_B_HIGH
RESERVED
RESERVED
CRCW_F
SETUP_F
RESERVED
AL_B_LOW
AL_A_HIGH
AL_A_LOW
ALERT_LOW_THRESHOLD
ALERT_HIGH_THRESHOLD
[15:8]
[7:0]
ADDRESSING
ALERT_LOW[11:8]
ALERT_LOW[7:0]
ALERT_HIGH[7:0]
[15:8]
[7:0]
ADDRESSING
ALERT_HIGH[11:8]
ADDRESSING REGISTERS
A serial register transfer on the AD7380/AD7381 consists of 16 SCLK cycles. The 4 MSBs written to the device are decoded to determine
which register is addressed. The 4 MSBs consist of the register address (REGADDR), Bits[2:0], and the read/write bit (WR). The register
address bits determine which on-chip register is selected. The read/write bit determines if the remaining 12 bits of data on the SDI input
are loaded into the addressed register, if the addressed register is a valid write register. If the WR bit is 1, the bits load into the register
addressed by the register select bits. If the WR bit is 0, the command is seen as a read request. The addressed register data is available to
be read during the next read operation.
Table 14. Addressing Register Format
MSB
D15
WR
LSB
D0
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
REGADDR[2:0]
DATA[11:0]
Table 15. Bit Descriptions for Addressing Registers
Bit
Mnemonic
Description
D15
WR
If a 1 is written to this bit, Bits[11:0] of this register are written to the register specified by REGADDR[2:0], if it
is a valid address. Alternatively, if a 0 is written, the next data sent out on the SDO pin is a read from the
designated register, if it is a valid address.
D14 to D12 REGADDR[2:0] When WR = 1, the contents of REGADDR[2:0] determine the register for selection as outlined in Table 13.
When WR = 0, and REGADDR[2:0] contains a valid register address, the contents on the requested register
are output on the SDOA pin during the next interface access.
When WR = 0, and REGADDR[2:0] contains 0x0, 0x6, or 0x7, the contents on the SDI line are ignored. The
next interface access results in the conversion results being read back.
D11 to D0
DATA[11:0]
These bits are written into the corresponding register specified by the REGADDR[2:0] bits when the WR bit is
equal to 1 and the REGADDR[2:0] bits contain a valid address.
Rev. 0 | Page 27 of 31
AD7380/AD7381
Data Sheet
CONFIGURATION1 REGISTER
Address: 0x1, Reset: 0x0000, Name: CONFIGURATION1
Table 16. Bit Descriptions for CONFIGURATION1
Bits
Bit Name
Description
Reset Access
[15:12] ADDRESSING Addressing. Bits[15:12] define the address of the relevant register. See the Addressing Registers
section for further details.
0x0
R/W
[11:10] RESERVED
Reserved.
0x0
0x0
R
9
OS_MODE
Oversampling Mode. Sets the oversampling mode of the ADC.
0: normal average.
R/W
1: rolling average.
[8:6]
OSR
Oversampling Ratio. Sets the oversampling ratio for all the ADCs in the relevant mode. Normal 0x0
averaging mode supports oversampling ratios of ×2, ×4, ×8, ×16, and ×32. Rolling average
mode supports oversampling ratios of ×2, ×4, and ×8.
R/W
000: disabled.
001: 2×.
010: 4×.
011: 8×.
100: 16×.
101: 32×.
110: disabled.
111: disabled.
5
CRC_W
CRC Write. Controls the CRC functionality for the SDI interface. When setting this bit from a 0
to a 1, the command must be followed by a valid CRC to set this configuration bit. If a valid
CRC is not received, the entire frame is ignored. If the bit is set to 1, it requires a CRC to clear it to 0.
0x0
R/W
0: no CRC function.
1: CRC function.
4
3
CRC_R
CRC Read. Controls the CRC functionality for the SDOx interface.
0: no CRC function.
1: CRC function.
0x0
0x0
R/W
R/W
ALERT_EN
Enable Alert Indicator on ADC Data. This register function when SDO = 1, otherwise the
ALERT_EN bit is ignored.
0: SDOB.
1:
ALERT
.
2
RES
Resolution. Sets the size of the conversion result data. If OSR = 0, these bits are ignored, and
the resolution is set to default resolution.
0x0
R/W
0: normal resolution.
1: 2-bit higher resolution.
1
0
REFSEL
PMODE
Reference Select. Selects the ADC reference source.
0: selects internal reference.
1: selects external reference.
Power-Down Mode. Sets the power modes.
0: normal mode.
0x0
0x0
R/W
R/W
1: power-down mode.
Rev. 0 | Page 28 of 31
Data Sheet
AD7380/AD7381
CONFIGURATION2 REGISTER
Address: 0x2, Reset: 0x0000, Name: CONFIGURATION2
Table 17. Bit Descriptions for CONFIGURATION2
Bits
Bit Name
Description
Reset Access
[15:12] ADDRESSING Addressing. Bits[15:12] define the address of the relevant register. See the Addressing Registers
section for further details.
0x0
R/W
[11:9]
8
RESERVED
SDO
Reserved.
0x0
0x0
R
SDO. Conversion results serial data output.
0: two wire, conversion data are output on both SDOA and SDOB.
1: one wire, conversion data are output on SDOA only.
Reset.
R/W
[7:0]
RESET
0x0
R/W
Set to 0x3C to perform a soft reset, which refreshes some blocks, and register contents remain
unchanged. Clears ALERT register and flushes any oversampling stored variables or active
state machine.
Set to 0xFF to perform a hard reset, which resets all possible blocks in the device. Register
contents are set to defaults. All other values are ignored.
ALERT REGISTER
ALERT
Address: 0x3, Reset: 0x0000, Name:
ALERT
Table 18. Bit Descriptions for
Bits Bit Name Description
Reset Access
[15:12] ADDRESSING Addressing. Bits[15:12] define the address of the relevant register. See the Addressing Registers
section for further details.
0x0
R
[11:10] RESERVED
Reserved.
0x0
0x0
R
R
9
CRCW_F
CRC Error. Indicates that a register write command failed due to a CRC error. This fault bit is
sticky and remains set until the register is read.
0: no CRC error.
1: CRC error.
8
SETUP_F
Load Error. The SETUP_F indicates that the device configuration data did not load correctly on
0x0
R
ALERT
startup. This bit does not clear on an
register read. A hard reset via the
CONFIGURATION2 register is required to clear this bit and restart the device setup again.
0: no setup error.
1: setup error.
Reserved.
[7:6]
5
RESERVED
0x0
0x0
R
R
AL_B_HIGH
Alert B High. The alert indication high bits indicate if a conversion result for the respective
input channel exceeds the value set in the ALERT_HIGH_THRESHOLD register. This fault bit is
sticky and remains set until the register is read.
1: alert indication.
0: no alert indication.
4
AL_B_LOW
RESERVED
Alert B Low. The alert indication low bits indicate if a conversion result for the respective input
channel exceeds the value set in the ALERT_LOW_THRESHOLD register. This fault bit is sticky
and remains set until the register is read.
1: alert indication.
0: no alert indication.
Reserved.
0x0
0x0
R
R
[3:2]
Rev. 0 | Page 29 of 31
AD7380/AD7381
Data Sheet
Bits
Bit Name
Description
Reset Access
1
AL_A_HIGH
Alert A High. The alert indication high bits indicate if a conversion result for the respective
input channel exceeds the value set in the ALERT_HIGH_THRESHOLD register. This fault bit is
sticky and remains set until the register is read.
0x0
R
1: alert indication.
0: no alert indication.
0
AL_A_LOW
Alert A Low. The alert indication low bits indicate if a conversion result for the respective input
channel exceeds the value set in the ALERT_LOW_THRESHOLD register. This fault bit is sticky
and remains set until the register is read.
0x0
R
1: alert indication.
0: no alert indication.
ALERT_LOW_THRESHOLD REGISTER
Address: 0x4, Reset: 0x0800, Name: ALERT_LOW_THRESHOLD
Table 19. Bit Descriptions for ALERT_LOW_THRESHOLD
Bits
Bit Name
Description
Reset Access
0x0 R/W
[15:12] ADDRESSING Addressing. Bits[15:12] define the address of the relevant register. See the Addressing Registers
section for further details.
[11:0]
ALERT_LOW
Alert Low. The D[11:0] bits from ALERT_LOW move to the MSBs of the internal ALERT_LOW
register, D[15:4]. The remaining bits, D[3:0] of the internal register are fixed at 0x0. Sets alert
when the converter result is below ALERT_LOW_THRESHOLD and alert disabled when it is
above ALERT_LOW_THRESHOLD.
0x800 R/W
ALERT_HIGH_THRESHOLD REGISTER
Address: 0x5, Reset: 0x07FF, Name: ALERT_HIGH_THRESHOLD
Table 20. Bit Descriptions for ALERT_HIGH_THRESHOLD
Bits
Bit Name
Description
Reset Access
[15:12] ADDRESSING Addressing. Bits[15:12] define the address of the relevant register. See the Addressing Registers
section for further details.
0x0
R/W
[11:0]
ALERT_HIGH Alert High. The D[11:0] bits from ALERT_HIGH move to the MSBs of the internal ALERT_HIGH
register, D[15:4]. The remaining bits, D[3:0], of the internal register (ALERT_HIGH_INT) are fixed
at 0xF. Sets alert when the converter result is above the ALERT_HIGH_THRESHOLD register
and alert disabled when the converter result is below the ALERT_HIGH_THRESHOLD register.
0x7FF R/W
Rev. 0 | Page 30 of 31
Data Sheet
AD7380/AD7381
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
3.10
3.00 SQ
2.90
0.30
0.25
0.18
PIN 1
INDICATOR
AREA
PIN 1
IONS
INDICATOR AR E A OP T
(SEE DETAIL A)
13
16
12
1
0.45
0.50
BSC
*
1.20
EXPOSED
PAD
1.10 SQ
1.00
9
4
8
5
0.55 REF
0.45
0.40
0.35
TOP VIEW
BOTTOM VIEW
0.80
0.75
0.70
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.05 MAX
0.02 NOM
COPLANARITY
SECTION OF THIS DATA SHEET.
0.08
SEATING
PLANE
0.15 REF
*
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-4
WITH EXCEPTION TO THE EXPOSED PAD
Figure 43. 16-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-16-45)
Dimensions shown in millimeters
ORDERING GUIDE
Marking
Package Option Code
Model1, 2
Resolution Temperature Range
Package Description
AD7380BCPZ-RL
AD7380BCPZ-RL7
AD7381BCPZ-RL
AD7381BCPZ-RL7
EVAL-AD7380FMCZ
EVAL-AD7381FMCZ
16-Bit
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
AD7380 Evaluation Board
CP-16-45
CP-16-45
CP-16-45
CP-16-45
C95
C95
C93
C93
16-Bit
14-Bit
14-Bit
AD7381 Evaluation Board
1 Z = RoHS Compliant Part.
2 The EVAL-AD7380FMCZ and the EVAL-AD7381FMCZ are compatible with the EVAL-SDP-CH1Z high speed controller board.
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16871-0-1/19(0)
Rev. 0 | Page 31 of 31
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