AD7400AYRWZREEL7 [ADI]
Isolated Sigma-Delta Modulator; 隔离式Σ-Δ调制器
| 型号： | AD7400AYRWZREEL7 |
| 厂家： | 
ADI |
| 描述： | Isolated Sigma-Delta Modulator |
| 文件： | 总19页 (文件大小：321K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Isolated Sigma-Delta Modulator
Preliminary Technical Data
AD7400A
FEATURES
GENERAꢀ DESCRIPTION
10 MHz clock rate
Second-order modulator
16 bits no missing codes
2 ꢀSB INꢀ typical at 16 bits
3.5 µV/°C maximum offset drift
On-board digital isolator
On-board reference
ꢀow power operation: 18 mA maximum at 5.25 V
−40°C to +125°C operating range
16-lead SOIC, 8-lead gull-wing surface mount DIP packages
AD7401A, external clock version
Safety and regulatory approvals
Uꢀ recognition
The AD7400A1 is a second-order, Σ-Δ modulator that converts
an analog input signal into a high speed, 1-bit data stream with
on-chip digital isolation based on Analog Devices, Inc.
iCoupler® technology. The AD7400A operates from a 5 V power
supply and accepts a differential input signal of ±±00 mV
(±ꢀ±0 mV full scale). The analog input is continuously sampled
by the analog modulator, eliminating the need for external
sample-and-hold circuitry. The input information is contained
in the output stream as a density of ones with a data rate of
10 MHz. The original information can be reconstructed with an
appropriate digital filter. The serial I/O can use a 5 V or a ꢀ V
supply (VDD±).
The serial interface is digitally isolated. High speed CMOS,
combined with monolithic air core transformer technology,
means the on-chip isolation provides outstanding performance
characteristics superior to alternatives such as optocoupler
devices. The part contains an on-chip reference. The AD7400A
is offered in a 16-lead SOIC and 8-lead gull-wing surface mount
DIP and has an operating temperature range of −40°C to
+1±5°C.
3750 V rms for 1 minute per Uꢀ 1577
CSA Component Acceptance Notice #5A
VDE Certificate of Conformity
DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01
DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000
VIORM = 891 V peak
APPꢀICATIONS
AC motor controls
Data acquisition systems
A/D + opto-isolator replacements
FUNCTIONAꢀ BꢀOCK DIAGRAM
V
V
DD2
DD1
AD7400A
V
V
+
IN
T/H
Σ-∆ ADC
–
IN
UPDATE
WATCHDOG
ENCODE
DECODE
BUF
MDAT
REF
CONTROL LOGIC
UPDATE
WATCHDOG
ENCODE
MCLKOUT
DECODE
GND
GND
1
2
Figure 1.
1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Other patents pending.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2008 Analog Devices, Inc. All rights reserved.
AD7400A
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................9
Terminology.................................................................................... 1±
Theory of Operation ...................................................................... 1ꢀ
Circuit Information.................................................................... 1ꢀ
Analog Input ............................................................................... 1ꢀ
Differential Inputs...................................................................... 14
Digital Filter ................................................................................ 14
Application Information................................................................ 17
Grounding and Layout .............................................................. 17
Evaluating the AD7400A Performance................................... 17
Insulation Lifetime..................................................................... 17
Outline Dimensions....................................................................... 18
Ordering Guide ....................... Error! Bookmark not defined.
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... ±
Specifications..................................................................................... ꢀ
Timing Specifications .................................................................. 4
Insulation and Safety-Related Specifications............................ 5
Regulatory Information............................................................... 5
DIN EN 60747-5-± (VDE 0884 Part ±) Insulation
Characteristics .............................................................................. 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
REVISION HISTORY
Rev. PrA | Page 2 of 19
Preliminary Technical Data
SPECIFICATIONS
AD7400A
VDD1 = 4.5 V to 5.±5 V, VDD± = ꢀ V to 5.5 V, VIN+ = −±00V to +±00mV, and VIN− = 0 V (single-ended); TA = TMIN to TMAX
,
fMCLK = 10 MHz, tested with Sincꢀ filter, ±56 decimation rate, as defined by Verilog code, unless otherwise noted.1
Table 1.
Parameter
Y Version1, 2
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
16
15
25
0.9
0.5
50
3.5
1
120
1
23
110
Bits min
LSB max
LSB max
LSB max
mꢀ max
µꢀ typ
µꢀ/°C max
µꢀ/°C typ
µꢀ/ꢀ typ
mꢀ max
µꢀ/°C typ
µꢀ/ꢀ typ
Filter output truncated to 16 bits
−40°C to +85°C; 2 LSB typical
>85°C to 105°C
Integral Nonlinearity3
Differential Nonlinearity3
Offset Error3
Guaranteed no missing codes to 16 bits
TA = 25°C
−40°C to +105°C
Offset Drift vs. Temperature3
Offset Drift vs. ꢀDD1
Gain Error3
Gain Error Drift vs. Temperature3
Gain Error Drift vs. ꢀDD1
−40°C to +105°C
3
ANALOG INPUT
Input ꢀoltage Range
Dynamic Input Current
200
7
mꢀ min/mꢀ max
µA max
For specified performance; full range 320 mꢀ
ꢀIN+ = 400 mꢀ, ꢀIN− = 0 ꢀ
0.5
10
µA typ
pF typ
ꢀIN+ = ꢀIN− = 0 ꢀ
Input Capacitance
DYNAMIC SPECIFICATIONS
ꢀIN+ = 35 Hz, 400 mꢀ p-p sine
−40°C to +85°C
>85°C to 105°C
Signal-to-(Noise + Distortion) Ratio (SINAD)3
70
65
79
71
−88
−88
11.5
25
dB min
dB min
dB typ
dB min
dB typ
dB typ
Bits
Signal-to-Noise Ratio (SNR)3
−40°C to +105°C
Total Harmonic Distortion (THD)3
Peak Harmonic or Spurious Noise (SFDR)3
Effective Number of Bits (ENOB)3
Isolation Transient Immunity3
kꢀ/µs min
kꢀ/µs typ
30
LOGIC OUTPUTS
Output High ꢀoltage, ꢀOH
Output Low ꢀoltage, ꢀOL
POWER REQUIREMENTS
ꢀDD1
ꢀDD2 − 0.1
0.4
ꢀ min
ꢀ max
IO = −200 µA
IO = +200 µA
4.5/5.25
ꢀ min/ꢀ max
ꢀ min/ꢀ max
mA max
mA max
mA max
ꢀDD2
3/5.5
12
6
4
IDD1
ꢀDD1 = 5.25 ꢀ
ꢀDD2 = 5.5 ꢀ
ꢀDD2 = 3.3 ꢀ
5
IDD2
4
1 Temperature range is −40°C to +125°C except where specified.
2 All voltages are relative to their respective ground.
3 See the Terminology section.
4 See Figure 15.
5 See Figure 16.
Rev. PrA | Page 3 of 19
AD7400A
Preliminary Technical Data
TIMING SPECIFICATIONS
VDD1 = 4.5 V to 5.±5 V, VDD± = ꢀ V to 5.5 V, TA = TMAX to TMIN, unless otherwise noted.1
Table 2.
Parameter
ꢀimit at TMIN, TMAX
Unit
Description
2
fMCLKOUT
10
9/11
40
10
0.4 × tMCLKOUT
0.4 × tMCLKOUT
MHz typ
MHz min/MHz max
ns max
ns min
ns min
Master clock output frequency
Master clock output frequency
Data access time after MCLK rising edge
Data hold time after MCLK rising edge
Master clock low time
3
t1
3
t2
t3
t4
ns min
Master clock high time
1 Sample tested during initial release to ensure compliance.
2 Mark space ratio for clock output is 40/60 to 60/40.
3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 ꢀ or 2.0 ꢀ.
200µA
I
OL
TO OUTPUT
PIN
+1.6V
C
L
25pF
200µA
I
OH
Figure 2. Load Circuit for Digital Output Timing Specifications
t4
MCLKOUT
MDAT
t1
t2
t3
Figure 3. Data Timing
Rev. PrA | Page 4 of 19
Preliminary Technical Data
INSUꢀATION AND SAFETY-REꢀATED SPECIFICATIONS
Table 3.
AD7400A
Parameter
Symbol Value
Unit Conditions
Input-to-Output Withstand Momentary Withstand ꢀoltage
Minimum External Air Gap (Clearance)
ꢀISO
L(I01)
3750 min
7.46 min
ꢀ
mm
1-minute duration
Measured from input terminals to output
terminals, shortest distance through air
Minimum External Tracking (Creepage)
L(I02)
CTI
8.1 min
mm
Measured from input terminals to output
terminals, shortest distance path along body
Insulation distance through insulation
DIN IEC 112/ꢀDE 0303 Part 1
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
0.017 min mm
>175
IIIa
ꢀ
Material group (DIN ꢀDE 0110, 1/89, Table 1)
REGUꢀATORY INFORMATION
Table 4.
Uꢀ1
CSA
Approved under CSA Component
VDE2
Recognized Under 1577
Certified according to DIN EN 60747-5-2
(ꢀDE 0884 Part 2): 2003-012
Component Recognition Program1 Acceptance Notice #5A
3750 ꢀ rms Isolation ꢀoltage
Reinforced insulation per
CSA 60950-1-03 and IEC 60950-1,
630 ꢀrms maximum working
voltage
Basic insulation, 891 ꢀ peak
Complies with DIN EN 60747-5-2 (ꢀDE 0884 Part 2): 2003-01,
DIN EN 60950 (ꢀDE 0805): 2001-12; EN 60950: 2000
Reinforced insulation, 891 ꢀ peak
File E214100
File 205078
File 2471900-4880-0001
1 In accordance with UL 1577, each AD7400A is proof tested by applying an insulation test voltage ≥ 4500 ꢀ rms for 1 second (current leakage detection limit = 7.5 µA).
2 In accordance with DIN EN 60747-5-2, each AD7400A is proof tested by applying an insulation test voltage ≥ 1671 ꢀ peak for 1 second (partial discharge detection
limit = 5 pC).
Rev. PrA | Page 5 of 19
AD7400A
Preliminary Technical Data
DIN EN 60747-5-2 (VDE 0884 PART 2) INSUꢀATION CHARACTERISTICS
This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by means
of protective circuits.
Table 5.
Description
Symbol Characteristic Unit
INSTALLATION CLASSIFICATION PER DIN ꢀDE 0110
For Rated Mains ꢀoltage ≤ 300 ꢀ rms
I–Iꢀ
For Rated Mains ꢀoltage ≤ 450 ꢀ rms
I–II
For Rated Mains ꢀoltage ≤ 600 ꢀ rms
I–II
CLIMATIC CLASSIFICATION
40/105/21
2
POLLUTION DEGREE (DIN ꢀDE 0110, Table 1)
MAXIMUM WORKING INSULATION ꢀOLTAGE
INPUT-TO-OUTPUT TEST ꢀOLTAGE, METHOD B1
ꢀIORM × 1.875 = ꢀPR, 100% Production Test, tm = 1 sec, Partial Discharge < 5 pC
INPUT-TO-OUTPUT TEST ꢀOLTAGE, METHOD A
After Environmental Test Subgroup 1
ꢀIORM × 1.6 = ꢀPR, tm = 60 sec, Partial Discharge < 5 pC
After Input and/or Safety Test Subgroup 2/3
ꢀIORM × 1.2 = ꢀPR, tm = 60 sec, Partial Discharge < 5 pC
HIGHEST ALLOWABLE OꢀERꢀOLTAGE (TRANSIENT OꢀERꢀOLTAGE, tTR = 10 sec)
SAFETY-LIMITING ꢀALUES (MAXIMUM ꢀALUE ALLOWED IN THE EꢀENT OF A FAILURE, ALSO SEE Figure 4)
Case Temperature
ꢀIORM
891
ꢀ peak
ꢀ peak
ꢀ peak
ꢀ peak
ꢀ peak
ꢀPR
ꢀPR
1671
1426
1069
6000
ꢀTR
TS
IS1
IS2
RS
150
265
335
>109
°C
Side 1 Current
Side 2 Current
mA
mA
Ω
INSULATION RESISTANCE AT TS, ꢀIO = 500 ꢀ
350
300
250
SIDE #2
200
150
SIDE #1
100
50
0
0
50
100
150
200
CASE TEMPERATURE (°C)
Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN EN 60747-5-2
Rev. PrA | Page 6 of 19
Preliminary Technical Data
AD7400A
ABSOLUTE MAXIMUM RATINGS
TA = ±5°C, unless otherwise noted. All voltages are relative to
their respective ground.
Table 6.
Parameter
ꢀDD1 to GND1
ꢀDD2 to GND2
Analog Input ꢀoltage to GND1
Output ꢀoltage to GND2
Input Current to Any Pin Except Supplies1
Operating Temperature Range
Storage Temperature Range
Junction Temperature
SOIC Package
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
−0.3 ꢀ to +6.5 ꢀ
−0.3 ꢀ to +6.5 ꢀ
−0.3 ꢀ to ꢀDD1 + 0.3 ꢀ
−0.3 ꢀ to ꢀDD2 + 0.3 ꢀ
10 mA
−40°C to +125°C
−65°C to +150°C
150°C
Table 7. Maximum Continuous Working Voltage1
Parameter
Max Unit Constraint
AC ꢀoltage,
Bipolar Waveform
AC ꢀoltage,
Unipolar Waveform
565
891
891
ꢀPK
ꢀPK
ꢀ
50-year minimum lifetime
θJA Thermal Impedance
θJC Thermal Impedance
Resistance (Input-to-Output), RI-O
89.2°C/W
55.6°C/W
1012 Ω
Maximum CSA/ꢀDE
approved working voltage
Maximum CSA/ꢀDE
DC ꢀoltage
2
Capacitance (Input-to-Output), CI-O
1.7 pF typ
approved working voltage
1 Refers to continuous voltage magnitude imposed across the isolation
barrier. See the Insulation Lifetime section for more details.
Pb-Free Temperature, Soldering
Reflow
ESD
260 (+0)°C
1.5 kꢀ
1 Transient currents of up to 100 mA do not cause SCR to latch up.
2 f = 1 MHz.
ESD CAUTION
Rev. PrA | Page 7 of 19
AD7400A
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
DD1
1
2
3
4
8
7
6
5
V
DD2
V
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DD1
2
AD7400A
TOP VIEW
(Not to Scale)
V
+
-
MCLKIN
MDAT
IN
V
+
NC
V
IN
AD7400A
V
IN
V
–
TOP VIEW
IN
DD2
GND
GND
2
1
(Not to Scale)
NC
NC
NC
DD1
MCLKOUT
NC
NC = NO CONNECT
Figure 6 Pin Configuration (NS-8)
MDAT
NC
V
GND
GND
2
1
NC = NO CONNECT
Figure 5. Pin Configuration (RW-16)
Table 8. Pin Function Descriptions
Mnemonic
Description
ꢀDD1
Supply ꢀoltage, 4.5 ꢀ to 5.25 ꢀ. This is the supply voltage for the isolated side of the AD7400A and
is relative to GND1.
ꢀIN+
Positive Analog Input. Specified range of 200 mꢀ.
ꢀIN−
NC
Negative Analog Input. Normally connected to GND1.
No Connect.
GND1
GND2
MDAT
Ground 1. This is the ground reference point for all circuitry on the isolated side.
Ground 2. This is the ground reference point for all circuitry on the nonisolated side.
Serial Data Output. The single bit modulator output is supplied to this pin as a serial data stream.
The bits are clocked out on the rising edge of the MCLKOUT output and valid on the following
MCLKOUT rising edge.
MCLKOUT
ꢀDD2
Master Clock Logic Output. 10 MHz typical. The bit stream from the modulator is valid on the rising edge
of MCLKOUT.
Supply ꢀoltage. 3 ꢀ to 5.5 ꢀ. This is the supply voltage for the nonisolated side and is relative to GND2.
Rev. PrA | Page 8 of 19
Preliminary Technical Data
AD7400A
TYPICAL PERFORMANCE CHARACTERISTICS
TA = ±5°C, using ±0 kHz brickwall filter, unless otherwise noted.
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
100
V
= V
= 5V
200mV p-p SINEWAVE ON V
DD1
NO DECOUPLING
DD1
DD2
90
80
70
60
50
40
30
20
V
= V = 4.5V TO 5.25V
DD1
DD2
10
0
0.195
0.215
0.235
0.255
0.275
0.295
0.315
0
100 200 300 400 500 600 700 800 900 1000
SUPPLY RIPPLE FREQUENCY (kHz)
± INPUT AMPLITUDE (V)
Figure 10. SINAD vs. VIN
Figure 7. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
(1 MHz Filter Used)
0.5
0.4
–90
–80
–70
V
V
+ = –200mV TO +200mV
– = 0V
IN
IN
0.3
V
= V = 4.5V
DD2
DD1
0.2
–60
–50
–40
–30
–20
–10
0
0.1
0
V
= V
= 5.25V
DD2
DD1
V
= V = 5V
DD2
DD1
–0.1
–0.2
–0.3
–0.4
0
10000
20000
30000
CODE
40000
50000
60000
0
500
1000
1500
2000
2500
3000
3500
4000
INPUT FREQUENCY (Hz)
Figure 8. SINAD vs. Analog Input Frequency for Various Supply Voltages
Figure 11. Typical DNL, 200 mV Range
(Using Sinc3 Filter, 256 Decimation Rate)
0.8
0.6
0
V
V
+ = –200mV TO +200mV
– = 0V
8192 POINT FFT
IN
IN
–20
–40
fIN = 35Hz
SINAD = 79.6991dB
THD = –92.6722dB
DECIMATION BY 256
0.4
–60
0.2
–80
–100
–120
–140
–160
–180
0
–0.2
–0.4
–0.6
0
10000
20000
30000
CODE
40000
50000
60000
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (kHz)
Figure 9. Typical FFT, 200 mV Range
(Using Sinc3 Filter, 256 Decimation Rate)
Figure 12. Typical INL, 200 mV Range
(Using Sinc3 Filter, 256 Decimation Rate)
Rev. PrA | Page 9 of 19
AD7400A
Preliminary Technical Data
100
0.0036
0.0035
0.0034
0.0033
0.0032
0.0031
0.0030
V
= V
= 5V
DD2
DD1
I
@ +25°C
DD2
V
= V = 4.5V
DD2
DD1
I
@ +85°
C
50
DD2
0
I
@ –40°C
DD2
V
= V = 5V
DD2
DD1
–50
–100
–150
–200
V
= V = 5.25V
DD2
DD1
–45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95 105
TEMPERATURE (°C)
V
DC INPUT VOLTAGE (V)
IN
Figure 13. Offset Drift vs. Temperature for Various Supply Voltages
Figure 16. IDD2 vs. VIN at Various Temperatures
9
6
0.20
0.15
0.10
V
=
V
= 4.5V TO 5.25V
DD1
DD2
3
V
= V = 4.5V
DD2
DD1
0.05
0
V
= V = 5V
DD2
DD1
0
–0.05
–0.10
–0.15
–0.20
–3
–6
–9
V
= V
= 5.25V
DD2
DD1
–45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95 105
TEMPERATURE (°C)
V
+ DC INPUT (V)
IN
Figure 14 . Gain Error Drift vs. Temperature for Various Supply Voltages
Figure 17. IIN vs. VIN+ DC Input
0.0099
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
V
= V = 5V
DD2
DD1
0.0098
0.0097
0.0096
0.0095
0.0094
0.0093
0.0092
0.0091
0.0090
0.0089
T
= +85°C
A
T
= +25°C
A
T
= –40°C
A
0.1
1
10
100
1000
10000
V
DC INPUT VOLTAGE (V)
RIPPLE FREQUENCY (kHz)
IN
Figure 18. CMRR vs. Common-Mode Ripple Frequency
Figure 15. IDD1 vs. VIN at Various Temperatures
Rev. PrA | Page 10 of 19
Preliminary Technical Data
AD7400A
1.0
11.0
10.8
10.6
10.4
10.2
10.0
9.8
BANDWIDTH = 100kHz
0.8
0.6
0.4
0.2
0
V
= V = 4.5V
DD2
DD1
V
= V = 5.25V
DD2
9.6
DD1
9.4
V
= V = 5V
DD2
DD1
9.2
9.0
TEMPERATURE (°C)
V
DC INPUT (V)
IN
Figure 19. RMS Noise Voltage vs. VIN DC Input
Figure 20. MCLKOUT vs. Temperature for Various Supplies
Rev. PrA | Page 11 of 19
AD7400A
Preliminary Technical Data
TERMINOLOGY
Differential Nonlinearity
Total Harmonic Distortion (THD)
Differential nonlinearity is the difference between the measured
and the ideal 1 LSB change between any two adjacent codes
in the ADC.
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7400A, it is defined as
±
V±± +Vꢀ± +V4± +V5± +V6
THD(dB) = ±0log
Integral Nonlinearity
V1
Integral nonlinearity is the maximum deviation from a straight
line passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are specified negative
full scale, −±00 mV (VIN+ − VIN−), Code 1±,±88 for the 16-bit
level, and specified positive full scale, +±00 mV (VIN+ − VIN−),
Code 5ꢀ,±48 for the 16-bit level.
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise
Offset Error
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/±, excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is a
noise peak.
Offset is the deviation of the midscale code (Code ꢀ±,768 for
the 16-bit level) from the ideal VIN+ − VIN− (that is, 0 V).
Gain Error
This includes both positive full-scale gain error and negative
full-scale gain error. Positive full-scale gain error is the
deviation of the specified positive full-scale code (5ꢀ,±48 for the
16-bit level) from the ideal VIN+ − VIN− (+±00 mV) after the
offset error is adjusted out. Negative full-scale gain error is the
deviation of the specified negative full-scale code (1±,±88 for
the 16-bit level) from the ideal VIN+ − VIN− (−±00 mV) after the
offset error is adjusted out. Gain error includes reference error.
Common-Mode Rejection Ratio (CMRR)
CMRR is defined as the ratio of the power in the ADC output at
±±00 mV frequency, f, to the power of a ±00 mV p-p sine wave
applied to the common-mode voltage of VIN+ and VIN− of
frequency fS as
Signal-to-(Noise + Distortion) Ratio (SINAD)
CMRR (dB) = 10log(Pf/PfS)
where:
This ratio is the measured ratio of signal-to-(noise + distortion)
at the output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/±), excluding dc. The ratio is
dependent on the number of quantization levels in the digitization
process; the more levels, the smaller the quantization noise. The
theoretical signal-to-(noise + distortion) ratio for an ideal N-bit
converter with a sine wave input is given by
Pf is the power at frequency f in the ADC output.
PfS is the power at frequency fS in the ADC output.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but
not converter linearity. PSRR is the maximum change in the
specified full-scale (±±00 mV) transition point due to a change
in power supply voltage from the nominal value (see Figure 7).
Signal-to-(Noise + Distortion) = (6.0±N + 1.76) dB
Therefore, for a 1±-bit converter, this is 74 dB.
Isolation Transient Immunity
Effective Number of Bits (ENOB)
The ENOB is defined by
The isolation transient immunity specifies the rate of rise/fall of
a transient pulse applied across the isolation boundary beyond
which clock or data is corrupted. (It was tested using a transient
pulse frequency of 100 kHz.)
ENOB = (SINAD − 1.76)/6.0±
Rev. PrA | Page 12 of 19
Preliminary Technical Data
AD7400A
THEORY OF OPERATION
A differential input of ꢀ±0 mV results in a stream of ideally all
ones. This is the absolute full-scale range of the AD7400A,
while ±00 mV is the specified full-scale range, as shown in Table
9.
CIRCUIT INFORMATION
The AD7400A isolated Σ-Δ modulator converts an analog input
signal into a high speed (10 MHz typ), single-bit data stream;
the time average of the modulator’s single-bit data is directly
proportional to the input signal. Figure ±ꢀ shows a typical
application circuit where the AD7400A is used to provide
isolation between the analog input, a current sensing resistor,
and the digital output, which is then processed by a digital filter
to provide an N-bit word.
Table 9. Analog Input Range
Analog Input
Voltage Input
+640 mꢀ
+320 mꢀ
+200 mꢀ
0 mꢀ
Full-Scale Range
Positive Full Scale
Positive Specified Input Range
Zero
ANAꢀOG INPUT
Negative Specified Input Range
Negative Full Scale
−200 mꢀ
−320 mꢀ
The differential analog input of the AD7400A is implemented
with a switched capacitor circuit. This circuit implements a
second-order modulator stage that digitizes the input signal
into a 1-bit output stream. The sample clock (MCLKOUT)
provides the clock signal for the conversion process as well as
the output data-framing clock. This clock source is internal on
the AD7400A. The analog input signal is continuously sampled
by the modulator and compared to an internal voltage
reference. A digital stream that accurately represents the
analog input over time appears at the output of the converter
(see Figure ±1).
To reconstruct the original information, this output needs to be
digitally filtered and decimated. A Sincꢀ filter is recommended
because this is one order higher than that of the AD7400A
modulator. If a ±56 decimation rate is used, the resulting
16-bit word rate is ꢀ9 kHz, assuming a 10 MHz internal clock
frequency. Figure ±± shows the transfer function of the
AD7400A relative to the 16-bit output.
65535
MODULATOR OUTPUT
+FS ANALOG INPUT
53248
SPECIFIED RANGE
–FS ANALOG INPUT
ANALOG INPUT
Figure 21. Analog Input vs. Modulator Output
12288
A differential signal of 0 V results (ideally) in a stream of ones
and zeros at the MDAT output pin. This output is high 50% of
the time and low 50% of the time. A differential input of
±00 mV produces a stream of ones and zeros that are high
81.±5% of the time. A differential input of −±00 mV produces a
stream of ones and zeros that are high 18.75% of the time.
0
–320mV
–200mV
ANALOG INPUT
+200mV +320mV
Figure 22. Filtered and Decimated 16-Bit Transfer Characteristic
ISOLATED
5V
NONISOLATED
5V/3V
AD7400
V
V
V
DD
DD1
DD2
3
SINC FILTER
Σ-∆
MOD/
CS
V
V
+
–
MDAT
MDAT
MCLK
IN
ENCODER
DECODER
ENCODER
+
SCLK
INPUT
CURRENT
MCLKOUT
IN
SDAT
R
SHUNT
DECODER
GND
GND
GND
1
2
Figure 23. Typical Application Circuit
Rev. PrA | Page 13 of 19
AD7400A
Preliminary Technical Data
DIGITAꢀ FIꢀTER
DIFFERENTIAꢀ INPUTS
A Sincꢀ filter is recommended for use with the AD7400A. This
filter can be implemented on an FPGA or a DSP. The following
Verilog code provides an example of a Sincꢀ filter implementation
on a Xilinx® Spartan-II ±.5 V FPGA. This code can possibly be
compiled for another FPGA, such as an Altera® device. Note
that the data is read on the negative clock edge in this case;
although, it can be read on the positive edge, if preferred. Figure ±9
shows the effect of using different decimation rates with various
filter types.
The analog input to the modulator is a switched capacitor
design. The analog signal is converted into charge by highly
linear sampling capacitors. A simplified equivalent circuit
diagram of the analog input is shown in Figure ±4. A signal
source driving the analog input must be able to provide the
charge onto the sampling capacitors every half MCLKOUT cycle
and settle to the required accuracy within the next half cycle.
φA
1kΩ
φB
/*`Data is read on negative clk edge*/
module DEC256SINC24B(mdata1, mclk1, reset,
DATA);
V
+
IN
2pF
2pF
φA
φB
input mclk1;
input reset;
input mdata1;
filtered*/
/*used to clk filter*/
/*used to reset filter*/
/*ip data to be
1kΩ
V
–
IN
φA φB φA φB
MCLKOUT
output [15:0] DATA;
/*filtered op*/
Figure 24. Analog Input Equivalent Circuit
integer location;
integer info_file;
Since the AD7400A samples the differential voltage across its
analog inputs, low noise performance is attained with an input
circuit that provides low common-mode noise at each input.
The amplifiers used to drive the analog inputs play a critical role in
attaining the high performance available from the AD7400A.
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [23:0]
reg [15:0]
reg [7:0]
ip_data1;
acc1;
acc2;
acc3;
When a capacitive load is switched onto the output of an op
amp, the amplitude momentarily drops. The op amp tries to
correct the situation and, in the process, hits its slew rate limit.
This nonlinear response, which can cause excessive ringing, can
lead to distortion. To remedy the situation, a low-pass RC filter
can be connected between the amplifier and the input to the
AD7400A. The external capacitor at each input aids in
supplying the current spikes created during the sampling process,
and the resistor isolates the op amp from the transient nature of the
load.
acc3_d1;
acc3_d2;
diff1;
diff2;
diff3;
diff1_d;
diff2_d;
DATA;
word_count;
The recommended circuit configuration for driving the differential
inputs to achieve best performance is shown in Figure ±5. A
capacitor between the two input pins sources or sinks charge
to allow most of the charge that is needed by one input to be
effectively supplied by the other input. The series resistor again
isolates any op amp from the current spikes created during the
sampling process. Recommended values for the resistors and
capacitor are ±± Ω and 47 pF, respectively.
reg word_clk;
reg init;
R
V
+
IN
C
AD7400A
R
V
–
IN
Figure 25. Differential Input RC Network
Rev. PrA | Page 14 of 19
Preliminary Technical Data
AD7400A
/*Perform the Sinc ACTION*/
Z = one sample delay
WORD_CLK = output word rate
*/
always @ (mdata1)
if(mdata1==0)
ip_data1 <= 0;
to a -1 for 2's comp */
else
/* change from a 0
always @ (posedge word_clk or posedge reset)
if(reset)
begin
ip_data1 <= 1;
/*ACCUMULATOR (INTEGRATOR)
Perform the accumulation (IIR) at the speed
of the modulator.
acc3_d2 <= 0;
diff1_d <= 0;
diff2_d <= 0;
diff1 <= 0;
diff2 <= 0;
diff3 <= 0;
end
MCLKOUT
ACC1+
+
ACC2+
+
ACC3
IP_DATA1
Z
Z
Z
+
Figure 26. Accumulator
else
begin
Z = one sample delay
diff1 <= acc3 - acc3_d2;
diff2 <= diff1 - diff1_d;
diff3 <= diff2 - diff2_d;
acc3_d2 <= acc3;
diff1_d <= diff1;
diff2_d <= diff2;
end
MCLKOUT = modulators conversion bit rate
*/
always @ (negedge mclk1 or posedge reset)
if (reset)
begin
/*initialize acc registers on reset*/
acc1 <= 0;
acc2 <= 0;
acc3 <= 0;
/* Clock the Sinc output into an output
register
end
WORD_CLK
else
begin
DIFF3
DATA
/*perform accumulation process*/
acc1 <= acc1 + ip_data1;
acc2 <= acc2 + acc1;
acc3 <= acc3 + acc2;
end
Figure 28. Clocking Sinc Output into an Output Register
WORD_CLK = output word rate
*/
always @ (posedge word_clk)
begin
/*DECIMATION STAGE (MCLKOUT/ WORD_CLK)
*/
DATA[15] <= diff3[23];
DATA[14] <= diff3[22];
DATA[13] <= diff3[21];
DATA[12] <= diff3[20];
DATA[11] <= diff3[19];
DATA[10] <= diff3[18];
DATA[9] <= diff3[17];
DATA[8] <= diff3[16];
DATA[7] <= diff3[15];
DATA[6] <= diff3[14];
DATA[5] <= diff3[13];
DATA[4] <= diff3[12];
DATA[3] <= diff3[11];
DATA[2] <= diff3[10];
DATA[1] <= diff3[9];
DATA[0] <= diff3[8];
always @ (posedge mclk1 or posedge reset)
if (reset)
word_count <= 0;
else
word_count <= word_count + 1;
always @ (word_count)
word_clk <= word_count[7];
/*DIFFERENTIATOR ( including decimation
stage)
Perform the differentiation stage (FIR) at a
lower speed.
DIFF1
DIFF2
DIFF3
+
–
+
–
+
–
ACC3
–1
–1
–1
Z
Z
Z
end
WORD_CLK
endmodule
Figure 27. Differentiator
Rev. PrA | Page 15 of 19
AD7400A
Preliminary Technical Data
90
80
70
60
50
40
30
20
10
3
2
SINC
SINC
1
SINC
0
1
10
100
DECIMATION RATE
1k
Figure 29. SNR vs. Decimation Rate for Different Filter Types
Rev. PrA | Page 16 of 19
Preliminary Technical Data
AD7400A
APPLICATION INFORMATION
GROUNDING AND ꢀAYOUT
These tests subjected populations of devices to continuous
cross-isolation voltages. To accelerate the occurrence of failures,
the selected test voltages were values exceeding those of normal
use. The time to failure values of these units were recorded and
used to calculate acceleration factors. These factors were then
used to calculate the time to failure under normal operating
conditions. The values shown in Table 7 are the lesser of the
following two values:
Supply decoupling with a value of 100 nF is strongly recom-
mended on both VDD1 and VDD±. Decoupling on one or both
VDD1 pins does not significantly affect performance. In
applications involving high common-mode transients, care
should be taken to ensure that board coupling across the
isolation barrier is minimized. Furthermore, the board layout
should be designed so that any coupling that occurs equally
affects all pins on a given component side. Failure to ensure this
could cause voltage differentials between pins to exceed the
absolute maximum ratings of the device, thereby leading to
latch-up or permanent damage. Any decoupling used should be
placed as close to the supply pins as possible.
•
The value that ensures at least a 50-year lifetime of
continuous use.
•
The maximum CSA/VDE approved working voltage.
It should also be noted that the lifetime of the AD7400A varies
according to the waveform type imposed across the isolation
barrier. The iCoupler insulation structure is stressed differently
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure ꢀ0, Figure ꢀ1, and Figure ꢀ± illustrate the different
isolation voltage waveforms.
Series resistance in the analog inputs should be minimized to
avoid any distortion effects, especially at high temperatures. If
possible, equalize the source impedance on each analog input to
minimize offset. Beware of mismatch and thermocouple effects
on the analog input PCB tracks to reduce offset drift.
RATED PEAK VOLTAGE
EVAꢀUATING THE AD7400A PERFORMANCE
0V
A simple standalone AD7400A evaluation board is available
with split ground planes and a board split beneath the
AD7400A package to ensure isolation. This board allows access
to each pin on the device for evaluation purposes. External
supplies and all other circuitry (such as a digital filter) must be
provided by the user.
Figure 30. Bipolar AC Waveform
RATED PEAK VOLTAGE
0V
INSUꢀATION ꢀIFETIME
Figure 31. Unipolar AC Waveform
All insulation structures, subjected to sufficient time and/or
voltage, are vulnerable to breakdown. In addition to the testing
performed by the regulatory agencies, Analog Devices has
carried out an extensive set of evaluations to determine the
lifetime of the insulation structure within the AD7400A.
RATED PEAK VOLTAGE
0V
Figure 32. DC Waveform
Rev. PrA | Page 17 of 19
AD7400A
Preliminary Technical Data
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
16
1
9
8
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
0.75 (0.0295)
0.25 (0.
0098)
1.27 (0.0500)
BSC
45°
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 33. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
9.90 (0.390)
9.65 (0.380)
9.40 (0.370)
9.90 (0.390)
9.65 (0.380)
9.40 (0.370)
8
1
5
4
6.60 (0.260)
6.35 (0.250)
6.10 (0.240)
IN 1
MOLDED P
INDICATOR
1.40 (0.056)
1.08 (0.043)
0.76 (0.003)
2.54 (0.100)
BSC
7.87 (0.310)
7.62 (0.300)
7.37 (0.290)
4.19 (0.165)
MAX
0.255 (0.075)
0.010 (0.003)
0.64 (0.025)
0.51 (0.020)
0.38 (0.015)
1.19 (0.047)
MAX
12° NOM
LEAD COPLANARITY
0.102 (0.004) MAX
1.78 (0.070)
MAX
0.885 (0.035)
0.635 (0.025)
0.385 (0.015)
CONTROLLING DIMENSIONS ARE IN MILLIMETER; INCHES DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 34 8-Lead Dual In Line Gull-wing Surface Mount Package [PDIP_SMD]
(NS-8)
Dimensions shown in millimeters and (inches)
Rev. PrA | Page 18 of 19
Preliminary Technical Data
AD7400A
Model
AD7400AYRWZ1
Temperature Range Package Description
−40°C to +125°C 16-Lead Standard Small Outline Package (SOIC_W)
Package Option
RW-16
AD7400AYRWZ-
REELError! Bookmark
not defined.
−40°C to +125°C
16-Lead Standard Small Outline Package (SOIC_W)
RW-16
AD7400AYRWZ-
−40°C to +125°C
16-Lead Standard Small Outline Package (SOIC_W)
RW-16
REEL7Error! Bookmark
not defined.
AD7400AYNSZError!
−40°C to +125°C
−40°C to +125°C
8-Lead Dual In Line Gull-wing Surface Mount Package (PDIP_SMD)
8-Lead Dual In Line Gull-wing Surface Mount Package (PDIP_SMD)
NS-8
NS-8
Bookmark not defined.
AD7400AYNSZ-
REELError! Bookmark
not defined.
AD7400AYNSZ-
−40°C to +125°C
8-Lead Dual In Line Gull-wing Surface Mount Package (PDIP_SMD)
Standalone Evaluation Board
NS-8
REEL7Error! Bookmark
not defined.
EꢀAL-AD7400AEBZError!
Bookmark not defined.
1 Z = Pb-free part.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR07077-0-1/08(PrA)
Rev. PrA | Page 19 of 19
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