AD7402-8BRIZ-RL [ADI]
16-Bit, Isolated Sigma-Delta Modulator;
| 型号： | AD7402-8BRIZ-RL |
| 厂家： | 
ADI |
| 描述： | 16-Bit, Isolated Sigma-Delta Modulator |
| 文件： | 总20页 (文件大小：519K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Bit, Isolated Sigma-Delta Modulator
Data Sheet
AD7402
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VDD1
REF
VDD2
10 MHz internal clock rate
16 bits, no missing codes
Signal-to-noise ratio (SNR): 87 dB typical
Effective number of bits (ENOB): 13.5 bits typical
Typical offset drift vs. temperature: 1.7 µV/°C
On-board digital isolator
AD7402
MCLKOUT
(10MHz)
CLK
ENCODER
CLK
DECODER
BUF
CLOCK
VIN+
VIN–
DATA
ENCODER
CLK
DECODER
On-board reference
MDAT
Σ-Δ ADC
Full-scale analog input range: 320 mV
−40°C to +105°C operating range
High common-mode transient immunity: >25 kV/µs
8-lead, wide-body SOIC, with increased creepage package
Slew rate limited output for low electromagnetic
interference (EMI)
GND1
GND2
Figure 1.
Safety and regulatory approvals
UL recognition
5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE Certificate of Conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
V
IORM = 1250 VPEAK
APPLICATIONS
Shunt current monitoring
AC motor controls
Power and solar inverters
Wind turbine inverters
Data acquisition systems
Analog-to-digital and opto-isolator replacements
GENERAL DESCRIPTION
The AD74021 is a high performance, second-order, Σ-Δ modulator
that converts an analog input signal into a high speed, single-bit
data stream, with on-chip digital isolation based on Analog
Devices, Inc., iCoupler® technology. The AD7402 operates from
a 4.5 V to 5.5 V (VDD1) power supply and accepts a differential
input signal of 250 mV ( 320 mV full scale). The differential
input is ideally suited to shunt voltage monitoring in high
voltage applications where galvanic isolation is required.
information can be reconstructed with an appropriate digital
filter to achieve 87 dB signal to noise ratio (SNR) at 39 kSPS. The
serial input/output can use a 3 V to 5.5 V or a 3.3 V supply (VDD2).
The serial interface is digitally isolated. High speed complementary
metal oxide semiconductor (CMOS) technology, combined with
monolithic transformer technology, means the on-chip isolation
provides outstanding performance characteristics, superior to
alternatives such as optocoupler devices. The AD7402 device is
offered in an 8-lead, wide body SOIC package and has an
operating temperature range of −40°C to +105°C.
The analog input is continuously sampled by a high performance
analog modulator, and converted to a ones density, digital
output stream with a data rate of 10 MHz. The original
1 Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329.
Rev. A
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AD7402
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 13
Circuit Information.................................................................... 13
Analog Input............................................................................... 13
Differential Inputs...................................................................... 14
Digital Output............................................................................. 14
Applications Information.............................................................. 15
Current Sensing Applications................................................... 15
Voltage Sensing Applications.................................................... 15
Input Filter .................................................................................. 15
Digital Filter ................................................................................ 16
Power Supply Considerations................................................... 19
Grounding and Layout .............................................................. 19
Insulation Lifetime..................................................................... 19
Outline Dimensions....................................................................... 20
Ordering Guide .......................................................................... 20
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Package Characteristics ............................................................... 5
Insulation and Safety-Related Specifications............................ 5
Regulatory Information............................................................... 5
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Insulation
Characteristics .............................................................................. 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 12
REVISION HISTORY
6/15—Rev. 0 to Rev. A
Changes to Figure 1.......................................................................... 1
Changes to Ordering Guide .......................................................... 20
2/15—Revision 0: Initial Version
Rev. A | Page 2 of 20
Data Sheet
AD7402
SPECIFICATIONS
VDD1 = 4.5 V to 5.5 V, V DD2 = 3 V to 5.5 V, VIN+ = −250 mV to +250 mV, VIN− = 0 V, TA = −40°C to +105°C, tested with sinc3 filter, 256
decimation rate, as defined by Verilog code, unless otherwise noted. All voltages are relative to their respective ground.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
Integral Nonlinearity (INL)1
Differential Nonlinearity (DNL)1
Offset Error1
Offset Drift vs. Temperature
Offset Drift vs. VDD1
Gain Error1
16
Bits
LSB
0.99 LSB
0.75 mV
Filter output truncated to 16 bits
Guaranteed no missed codes to 16 bits
1
5
0.2
1.7
85
0.2
18
5
µV/°C
µV/V
% FSR
ppm/°C
µV/°C
mV/V
0.5
32
20
Gain Error Drift vs. Temperature
11
0.2
Gain Error Drift vs. VDD1
ANALOG INPUT
Input Voltage Range
−320
+320 mV
Input Common-Mode Voltage Range
Dynamic Input Current
−200 to +300
19
0.05
14
28
µA
µA
pF
VIN+ = 250 mV, VIN− = 0 V
VIN+ = 0 V, VIN− = 0 V
Input Capacitance
DYNAMIC SPECIFICATIONS
Signal-to-(Noise + Distortion) Ratio (SINAD)1
Signal-to-Noise Ratio (SNR)1
Total Harmonic Distortion (THD)1
Peak Harmonic or Spurious Noise (SFDR)1
Effective Number of Bits (ENOB)1
Noise Free Code Resolution1
ISOLATION TRANSIENT IMMUNITY1
LOGIC OUTPUTS
VIN+ = 35 Hz
74
86
82
87
−84
−84
13.5
dB
dB
dB
dB
Bits
Bits
kV/µs
12
14
25
30
Output High Voltage, VOH
Output Low Voltage, VOL
POWER REQUIREMENTS
VDD1
VDD2
IDD1
VDD2 − 0.1
V
V
IO = −200 µA
IO = +200 µA
0.4
4.5
3
5.5
5.5
31
7
5.5
209
V
V
mA
mA
mA
mW
26
6
4.5
VDD1 = 5.5 V
VDD2 = 5.5 V
VDD2 = 3.3 V
IDD2
POWER DISSIPATION
VDD1 = VDD2 = 5.5 V
1 See the Terminology section.
Rev. A | Page 3 of 20
AD7402
Data Sheet
TIMING SPECIFICATIONS
VDD1 = 4.5 V to 5.5 V, VDD2 = 3 V to 5.5 V, TA = −40°C to +105°C, unless otherwise noted.
Table 2.
Parameter1
Min
Typ
Max
10.6
10
Unit
MHz
ns
ns
ns
Description
2
fMCLKOUT
9.4
10
Master clock output frequency
Data access time after MCLKOUT rising edge
Data hold time after MCLKOUT falling edge
Master clock low time
3
t1
3
t2
44
33
33
t3
t4
ns
Master clock high time
1 Sample tested during initial release to ensure compliance.
2 Mark space ratio for clock output is 45/55 to 55/45.
3 Defined as the time required for the output to cross 0.8 V or 2.0 V for VDD2 = 3 V to 3.6 V, or when the output crosses 0.8 V or 0.7 × VDD2 for VDD2 = 4.5 V to 5.5 V, as
outlined in Figure 2. Measured with a 200 μA load and a 25 pF load capacitance.
t4
1
2.0V OR 0.7V × V
0.8V
DD2
MCLKOUT
MDAT
t1
t2
t3
1
2.0V OR 0.7V × V
0.8V
DD2
1
SEE NOTE 3 OF TABLE 2 FOR FURTHER DETAILS.
Figure 2. Data Timing
Rev. A | Page 4 of 20
Data Sheet
AD7402
PACKAGE CHARACTERISTICS
Table 3.
Parameter
Resistance (Input to Output)1
Capacitance (Input to Output)1
Symbol Min Typ Max Unit Test Conditions/Comments
RI-O
CI-O
1012
Ω
pF
2.2
f = 1 MHz
IC Junction to Ambient Thermal Resistance θJA
105
°C/W Thermocouple located at center of package underside,
test conducted on 4-layer board with thin traces
1 The device is considered a 2-terminal device: Pin 1 to Pin 4 are shorted together, and Pin 5 to Pin 8 are shorted together.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 4.
Parameter
Symbol
VISO
L(I01)
Value
Unit Test Conditions/Comments
Input-to-Output Momentary Withstand Voltage
Minimum External Air Gap (Clearance)
5000 min
8.1 min1, 2
V
1-minute duration
mm
Measured from input terminals to output
terminals, shortest distance through air
Minimum External Tracking (Creepage)
L(I02)
CTI
8.1 min1
mm
Measured from input terminals to output
terminals, shortest distance path along body
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
0.034 min
>400
II
mm
V
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table I)
1 In accordance with IEC 60950-1 guidelines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes ≤2000 meters.
2 Consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained.
REGULATORY INFORMATION
Table 5.
UL1
CSA
VDE2
Recognized under 1577
Component Recognition
Program1
Approved under CSA Component Acceptance Notice 5A
Certified according to DIN V VDE V 0884-10
(VDE V 0884-10):2006-122
5000 V rms Isolation Voltage
Single Protection
Basic insulation per CSA 60950-1-07 and IEC 60950-1,
810 V rms (1145 VPEAK) maximum working voltage3
Reinforced insulation per DIN V VDE V 0884-10
(VDE V 0884-10):2006-12, 1250 VPEAK
Reinforced insulation per CSA 60950-1-07 and
IEC 60950-1, 405 V rms (583 VPEAK) maximum working
voltage3
Reinforced insulation per IEC 60601-1, 250 V rms
(353 VPEAK) maximum working voltage
File E214100
File 205078
File 2471900-4880-0001
1 In accordance with UL 1577, each AD7402-8 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 15 µA).
2 In accordance with DIN V VDE V 0884-10, each AD7402-8 is proof tested by applying an insulation test voltage ≥ 2344 VPEAK for 1 second (partial discharge detection limit = 5 pC).
3 Rating is calculated for a pollution degree of 2 and a Material Group III. The AD7402 RI-8-1 package material is rated by CSA to a CTI of >400 V and therefore
Material Group II.
Rev. A | Page 5 of 20
AD7402
Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
means of protective circuits.
Table 6.
Description
Symbol
Characteristic Unit
INSTALLATION CLASSIFICATION PER DIN VDE 0110
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 450 V rms
For Rated Mains Voltage ≤ 600 V rms
For Rated Mains Voltage ≤ 1000V rms
I to IV
I to IV
I to IV
I to IV
40/105/21
2
CLIMATIC CLASSIFICATION
POLLUTION DEGREE (DIN VDE 0110, TABLE 1)
MAXIMUM WORKING INSULATION VOLTAGE
INPUT TO OUTPUT TEST VOLTAGE, METHOD B1
VIORM × 1.875 = VPR, 100% Production Test, tm = 1 Second, Partial Discharge < 5 pC
INPUT TO-OUTPUT TEST VOLTAGE, METHOD A
After Environmental Test Subgroup 1
VIORM × 1.6 = VPR, tm = 60 Seconds, Partial Discharge < 5 pC
After Input and/or Safety Test Subgroup 2/Safety Test Subgroup 3
VIORM × 1.2 = VPR, tm = 60 Seconds, Partial Discharge < 5 pC
HIGHEST ALLOWABLE OVERVOLTAGE (TRANSIENT OVERVOLTAGE, tTR = 10 Seconds)
SURGE ISOLATION VOLTAGE
VIORM
VPD(M)
1250
2344
VPEAK
VPEAK
VPR(M)
2000
1500
8000
12000
VPEAK
VPEAK
VPEAK
VPEAK
VIOTM
VIOSM
1.2 μs Rise Time, 50 μs, 50% Fall Time
SAFETY LIMITING VALUES (MAXIMUM VALUE ALLOWED IN THE EVENT OF A FAILURE, SEE Figure 3)
Case Temperature
Side 1 (PVDD1) and Side 2 (PVDD2) Power Dissipation
INSULATION RESISTANCE AT TS, VIO = 500 V
TS
PSO
RIO
150
1.19
>109
°C
W
Ω
2
1
0
0
50
100
150
200
AMBIENT TEMPERATURE (°C)
Figure 3. Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN V VDE V 0884-10
Rev. A | Page 6 of 20
Data Sheet
AD7402
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. All voltages are relative to
their respective ground.
1
Table 8. Maximum Continuous Working Voltage
Parameter
Max
Unit
Constraint
AC Voltage
Bipolar Waveform
Table 7.
Parameter
1250
VPEAK
20-year minimum
lifetime (VDE
Rating
VDD1 to GND1
VDD2 to GND2
−0.3 V to +6.5 V
−0.3 V to +6.5 V
−1 V to VDD1 + 0.3 V
−0.3 V to VDD2 + 0.3 V
10 mA
−40°C to +105°C
−65°C to +150°C
150°C
approved working
voltage)
20-year minimum
lifetime
Analog Input Voltage to GND1
Output Voltage to GND2
Input Current to Any Pin Except Supplies1
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Pb-Free Temperature, Soldering
Reflow
Unipolar Waveform 1250
DC Voltage 1250
VPEAK
VPEAK
20-year minimum
lifetime
1 Refers to continuous voltage magnitude imposed across the isolation barrier.
ESD CAUTION
260°C
2 kV
1250 V
4000 V
ESD
FICDM2
HBM3
1 Transient currents of up to 100 mA do not cause silicon controlled rectifier
(SCR) to latch up.
2 JESD22-C101; RC network: 1 Ω, package capacitance (CPKG); Class: IV.
3 ESDA/JEDEC JS-001-2011; RC network: 1.5 kΩ, 100 pF; Class: 3A.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 7 of 20
AD7402
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDD1
1
2
3
4
8
7
6
5
VDD2
AD7402-8
VIN+
MCLKOUT
MDAT
TOP VIEW
(Not to Scale)
VIN–
GND1
GND2
Figure 4. Pin Configuration
Table 9. Pin Function Descriptions
Pin No. Mnemonic Description
1
2
3
4
5
6
VDD1
VIN+
VIN−
GND1
GND2
MDAT
Supply Voltage, 4.5 V to 5.5 V. This is the supply voltage for the isolated side of the AD7402 and is relative to GND1.
Positive Analog Input.
Negative Analog Input. Normally connected to GND1.
Ground 1. This is the ground reference point for all circuitry on the isolated side.
Ground 2. This is the ground reference point for all circuitry on the nonisolated side.
Serial Data Output. The single bit modulator output is supplied to this pin as a serial data stream. The bits are
clocked out on the rising edge of the MCLKOUT input and are valid on the following MCLKOUT falling edge.
7
8
MCLKOUT
VDD2
Master Clock Logic Output, 10 MHz (Typical). The bit stream from the modulator is valid on the falling edge of
MCLKOUT.
Supply Voltage, 3 V to 5.5 V. This is the supply voltage for the nonisolated side and is relative to GND2.
Rev. A | Page 8 of 20
Data Sheet
AD7402
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VDD1 = 5 V, VDD2 = 5 V, using sinc3 filter with a 256 oversampling ratio (OSR), unless otherwise noted.
0
0
fIN = 35.8Hz
–20
200mV p-p SINE WAVE ON VDD1
1nF DECOUPLING
–20
SNR = 87.4dB
SINAD = 86dB
THD = –92dB
–40
–40
–60
–60
–80
–100
–120
–140
–160
–180
–80
–100
–120
–140
0
5
10
FREQUENCY (kHz)
15
10k
100k
1M
SUPPLY RIPPLE FREQUENCY (Hz)
Figure 5. PSRR vs. Supply Ripple Frequency
Figure 8. Fast Fourier Transform (FFT)
2.0
1.5
0
–20
SINC3 OSR = 256 FILTER
UNFILTERED
1.0
–40
0.5
–60
0
–80
–0.5
–1.0
–1.5
–2.0
–100
–120
–140
0
10
20
30
40
50
60
70
10k
100k
1M
CODE (k)
COMMON-MODE RIPPLE FREQUENCY (Hz)
Figure 6. CMRR vs. Common-Mode Ripple Frequency
Figure 9. Typical DNL Error
90
80
70
60
50
40
30
20
10
0
2.5
2.0
5.5V
5V
4.5V
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
0
10
20
30
40
50
60
70
10
100
1k
ANALOG INPUT FREQUENCY (Hz)
CODE (k)
Figure 7. SINAD vs. Analog Input Frequency
Figure 10. Typical INL Error
Rev. A | Page 9 of 20
AD7402
Data Sheet
0.3
0.2
800
700
600
500
400
300
200
100
0
VIN+ = VIN– = 0V
1M SAMPLES
676225
0.1
0
–0.1
–0.2
–0.3
V
V
V
V
V
V
= 5.5V, V
= 5.5V, V
= 4.5V, V
= 4.5V, V
= 5.0V, V
= 5.0V, V
= 5.5V
= 5.0V
= 5.5V
= 3.0V
= 5.0V
= 3.3V
DD1
DD1
DD1
DD1
DD1
DD1
DD2
DD2
DD2
DD2
DD2
DD2
159024
32767
161448
1401
1902
–40 –25 –10
5
20
35
50
65
80
95
32766
32768
CODE
32769
32770
TEMPERATURE (°C)
Figure 11. Histogram of Codes at Code Center
Figure 14. Offset vs. Temperature
100
1.5
1.0
fIN = 35Hz
V
V
V
V
V
V
= 5.5V, V
= 5.5V, V
= 4.5V, V
= 4.5V, V
= 5.0V, V
= 5.0V, V
= 5.5V
= 5.0V
= 5.5V
= 3.0V
= 5.0V
= 3.3V
DD1
DD1
DD1
DD1
DD1
DD1
DD2
DD2
DD2
DD2
DD2
DD2
90
80
70
60
0.5
0
–0.5
–1.0
–1.5
SNR
SINAD
–40 –25 –10
5
20
35
50
65
80
95
–40 –25 –10
5
20
35
50
65
80
95
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. SNR and SINAD vs. Temperature
Figure 15. Gain Error vs. Temperature
–60
–70
35
30
25
20
15
10
5
fIN = 35Hz
T
T
T
= –40°C
= +25°C
= +105°C
A
A
A
–80
–90
–100
–110
–120
THD
SFDR
0
4.50
–40 –25 –10
5
20
35
50
65
80
95
4.75
5.00
(V)
5.25
5.50
TEMPERATURE (°C)
V
DD1
Figure 13. THD and SFDR vs. Temperature
Figure 16. IDD1 vs. VDD1 at Various Temperatures
Rev. A | Page 10 of 20
Data Sheet
AD7402
27.0
6
T
T
T
T
= –40°C
= +25°C
= +85°C
= +105°C
A
A
A
A
T
T
= –40°C
= +85°C
T
T
= +25°C
= +105°C
A
A
A
A
26.5
26.0
25.5
25.0
24.5
24.0
23.5
23.0
5
4
–250
–250
–125
0
125
250
–125
0
125
250
VIN+ DC INPUT (mV)
VIN+ DC INPUT (mV)
Figure 19. IDD2 vs. VIN+ DC Input at Various Temperatures
Figure 17. IDD1 vs. VIN+ DC Input at Various Temperatures
10
9
8
7
6
5
4
3
2
1
0
30
T
T
T
= –40°C
= +25°C
= +105°C
A
A
A
20
10
0
–10
–20
–30
3.0
3.5
4.0
4.5
5.0
5.5
–320
–240
–160
–80
0
80
160
240
320
V
(V)
VIN+ DC INPUT (mV)
DD2
Figure 18. IDD2 vs. VDD2 at Various Temperatures
Figure 20. IIN+ vs. VIN+ DC Input
10.5
10.4
10.3
10.2
10.1
10
V
V
V
= 4.5V
= 5.0V
= 5.5V
DD1
DD1
DD1
9.9
9.8
9.7
9.6
–40 –25 –10
5
20
35
50
65
80
95
TEMPERATURE (°C)
Figure 21. Clock Frequency vs. Temperature for Various Supply Voltages
Rev. A | Page 11 of 20
AD7402
Data Sheet
TERMINOLOGY
Differential Nonlinearity (DNL)
Total Harmonic Distortion (THD)
DNL is the difference between the measured and the ideal
1 LSB change between any two adjacent codes in the ADC.
THD is the ratio of the rms sum of harmonics to the
fundamental. For the AD7402, it is defined as
2
V22 +V32 +V42 +V52 +V6
Integral Nonlinearity (INL)
THD(dB) = 20log
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are specified negative full
scale, −250 mV (VIN+ − VIN−), Code 7168 for the 16-bit level,
and specified positive full scale, +250 mV (VIN+ − VIN−),
Code 58,368 for the 16-bit level.
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second
through the sixth harmonics.
Peak Harmonic or Spurious Noise (SFDR)
Offset Error
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2, excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is
a noise peak.
Offset error is the deviation of the midscale code (32,768 for the
16-bit level) from the ideal VIN+ − VIN− (that is, 0 V).
Gain Error
The gain error includes both positive full-scale gain error and
negative full-scale gain error. Positive full-scale gain error is the
deviation of the specified positive full-scale code (58,368 for the
16-bit level) from the ideal VIN+ − VIN− (250 mV) after the offset
error is adjusted out. Negative full-scale gain error is the
deviation of the specified negative full-scale code (7168 for the
16-bit level) from the ideal VIN+ − VIN− (−250 mV) after the
offset error is adjusted out.
Effective Number of Bits (ENOB)
ENOB is defined by
ENOB = (SINAD − 1.76)/6.02 bits
Noise Free Code Resolution
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD is the measured ratio of signal to noise and distortion at
the output of the ADC. The signal is the rms value of the sine
wave, and noise is the rms sum of all nonfundamental signals
up to half the sampling frequency (fS/2), including harmonics,
but excluding dc.
Noise free code resolution represents the resolution in bits for
which there is no code flicker. The noise free code resolution for
an N-bit converter is defined as
Noise Free Code Resolution (Bits) = log2(2N/Peak-to-Peak Noise)
The peak-to-peak noise in LSBs is measured with VIN+ = VIN− = 0 V.
Common-Mode Rejection Ratio (CMRR)
Signal-to-Noise Ratio (SNR)
CMRR is defined as the ratio of the power in the ADC output at
250 mV frequency, f, to the power of a +250 mV peak-to-peak
sine wave applied to the common-mode voltage of VIN+ and VIN−
of frequency, fS, as
SNR is the measured ratio of signal to noise at the output of the
ADC. The signal is the rms amplitude of the fundamental. Noise
is the sum of all nonfundamental signals up to half the sampling
frequency (fS/2), excluding dc.
CMRR (dB) = 10 log(Pf/PfS)
The ratio is dependent on the number of quantization levels in the
digitization process: the greater the number of levels, the smaller
the quantization noise. The theoretical signal-to-noise ratio for
an ideal N-bit converter with a sine wave input is given by
where:
Pf is the power at frequency, f, in the ADC output.
PfS is the power at frequency, fS, in the ADC output.
Signal-to-Noise Ratio = (6.02N + 1.76) dB
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but
not the linearity of the converter. PSRR is the maximum change
in the specified full-scale ( 250 mV) transition point due to a
change in power supply voltage from the nominal value.
Therefore, for a 12-bit converter, the SNR is 74 dB.
Isolation Transient Immunity
The isolation transient immunity specifies the rate of rise and
fall of a transient pulse applied across the isolation boundary,
beyond which clock or data is corrupted. The AD7402 was
tested using a transient pulse frequency of 100 kHz.
Rev. A | Page 12 of 20
Data Sheet
AD7402
THEORY OF OPERATION
A differential signal of 0 V ideally results in a stream of alter-
CIRCUIT INFORMATION
nating 1s and 0s at the MDAT output pin. This output is high
50% of the time and low 50% of the time. A differential input of
250 mV produces a stream of 1s and 0s that are high 89.06% of
the time. A differential input of −250 mV produces a stream of
1s and 0s that are high 10.94% of the time.
The AD7402 isolated Σ-Δ modulator converts an analog input
signal into a high speed (10 MHz maximum), single-bit data
stream; the time average single-bit data from the modulator is
directly proportional to the input signal. Figure 22 shows a
typical application circuit where the AD7402 is used to provide
isolation between the analog input, a current sensing resistor or
shunt, and the digital output, which is then processed by a
digital filter to provide an N-bit word.
A differential input of 320 mV ideally results in a stream of all
1s. A differential input of −320 mV ideally results in a stream of
all 0s. The absolute full-scale range is 320 mV and the specified
full-scale performance range is 250 mV, as shown in Table 10.
ANALOG INPUT
Table 10. Analog Input Range
The differential analog input of the AD7402 is implemented
with a switched capacitor circuit. This circuit implements a
second-order modulator stage that digitizes the input signal
into a single-bit output stream. The sample clock (MCLKOUT)
provides the clock signal for the conversion process as well as
the output data framing clock. This clock source is internal on
the AD7402. The analog input signal is continuously sampled
by the modulator and compared to an internal voltage
reference. A digital stream that accurately represents the
analog input over time appears at the output of the converter
(see Figure 23).
Analog Input
Voltage Input (mV)
Positive Full-Scale Value
Positive Specified Performance Input
Zero
+320
+250
0
Negative Specified Performance Input
Negative Full-Scale Value
−250
−320
FLOATING
POWER SUPPLY
+400V
NONISOLATED
5V/3.3V
GATED
DRIVE
CIRCUIT
AD7402
VDD1
VDD2
VDD
SINC3 FILTER*
5.1V
220pF
CS
10Ω
MDAT
MDAT
MCLK
VIN+
SCLK
Σ-Δ
MOD/
ENCODER
R
SHUNT
10Ω
DECODER
MCLKOUT
MOTOR
VIN–
SDAT
220pF
100nF
FLOATING
POWER SUPPLY
10µF 1nF
GND1
GND2
GND
GATED
DRIVE
CIRCUIT
*THIS FILTER IS IMPLEMENTED
WITH AN FPGA OR DSP
–400V
Figure 22. Typical Application Circuit
MODULATOR OUTPUT
+FS ANALOG INPUT
–FS ANALOG INPUT
ANALOG INPUT
Figure 23. Analog Input vs. Modulator Output
Rev. A | Page 13 of 20
AD7402
Data Sheet
To reconstruct the original information, this output must be
digitally filtered and decimated. A sinc3 filter is recommended
because it is one order higher than that of the AD7402 modulator,
which is a second-order modulator. If a 256 decimation rate is
used, the resulting 16-bit word rate is 39 kSPS. See the Digital
Filter section for more detailed information on the sinc filter
implementation. Figure 24 shows the transfer function of the
AD7402 relative to the 16-bit output.
DIFFERENTIAL INPUTS
The analog input to the modulator is a switched capacitor
design. The analog signal is converted into charge by highly
linear sampling capacitors. A simplified equivalent circuit
diagram of the analog input is shown in Figure 25. A signal
source driving the analog input must provide the charge onto the
sampling capacitors every half MCLKOUT cycle and settle to the
required accuracy within the next half cycle.
φA
65535
300Ω
φB
VIN+
VIN–
1.9pF
1.9pF
58368
φA
φB
300Ω
SPECIFIED RANGE
φA φB φA φB
MCLKIN
7168
Figure 25. Analog Input Equivalent Circuit
Because the AD7402 samples the differential voltage across its
analog inputs, low noise performance is attained with an input
circuit that provides low common-mode noise at each input.
0
–320mV
DIGITAL OUTPUT
–250mV
ANALOG INPUT
+250mV +320mV
The AD7402 MDAT output driver is a slew rate limited driver.
This driver lowers electromagnetic emissions, thus minimizing
electromagnetic interference, both conducted and radiated.
Figure 24. Filtered and Decimated 16-Bit Transfer Function
Rev. A | Page 14 of 20
Data Sheet
AD7402
APPLICATIONS INFORMATION
90
85
80
75
70
65
60
CURRENT SENSING APPLICATIONS
The AD7402 is ideally suited for current sensing applications
where the voltage across a shunt resistor (RSHUNT) is monitored.
The load current flowing through an external shunt resistor
produces a voltage at the input terminals of the AD7402. The
AD7402 provides isolation between the analog input from the
current sensing resistor and the digital outputs. By selecting the
appropriate shunt resistor value, a variety of current ranges can
be monitored.
fIN = 35Hz
V
V
= 5V
= 5V
= 25°C
DD1
DD2
11-BIT
ENOB
T
A
12-BIT
ENOB
13-BIT
ENOB
14-BIT
ENOB
Choosing RSHUNT
The shunt resistor (RSHUNT) values used in conjunction with the
AD7402 are determined by the specific application
0
50
100
150
200
250
requirements in terms of voltage, current, and power. Small
resistors minimize power dissipation, whereas low inductance
resistors prevent any induced voltage spikes, and good tolerance
devices reduce current variations. The final values chosen are a
compromise between low power dissipation and accuracy.
Higher value resistors use the full performance input range of
the ADC, thus achieving maximum SNR performance. Low
value resistors dissipate less power but do not use the full
performance input range. The AD7402, however, delivers
excellent performance, even with lower input signal levels,
allowing low value shunt resistors to be used while maintaining
system performance.
VIN+ AC INPUT SIGNAL AMPLITUDE (mV)
Figure 26. SINAD vs. VIN+ AC Input Signal Amplitude
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
DC INPUT
100k SAMPLES PER DATA POINT
To choose a suitable shunt resistor, first determine the current
through the shunt. The shunt current for a 3-phase induction
motor can be expressed as
–250
–170
–90
–10
70
150
230
RMS NOISE (LSB)
PW
IRMS
=
Figure 27. RMS Noise vs. VIN+ DC Input Signal Amplitude
1.73V EF PF
RSHUNT must be able to dissipate the I2R power losses. If the
power dissipation rating of the resistor is exceeded, its value
may drift or the resistor may be damaged, resulting in an open
circuit. This open circuit can result in a differential voltage
across the terminals of the AD7402, in excess of the absolute
maximum ratings. If ISENSE has a large high frequency
component, choose a resistor with low inductance.
where:
RMS is the motor phase current (A rms)
PW is the motor power (Watts)
V is the motor supply voltage (V ac)
EF is the motor efficiency (%)
PF is the power efficiency (%)
I
To determine the shunt peak sense current, ISENSE, consider the
motor phase current and any overload that may be possible in
the system. When the peak sense current is known, divide the
voltage range of the AD7402 ( 250 mV) by the peak sense
current to yield a maximum shunt value.
VOLTAGE SENSING APPLICATIONS
The AD7402 can also be used for isolated voltage monitoring.
For example, in motor control applications, it can be used to
sense the bus voltage. In applications where the voltage being
monitored exceeds the specified analog input range of the
AD7402, a voltage divider network can be used to reduce the
voltage being monitored to the required range.
If the power dissipation in the shunt resistor is too large, the
shunt resistor can be reduced and less of the ADC input range can
be used. Figure 26 shows the SINAD performance characteristics
and the ENOB of resolution for the AD7402 for different input
signal amplitudes. Figure 27 shows the rms noise performance
for dc input signal amplitudes. The AD7402 performance at
lower input signal ranges allows smaller shunt values to be used
while still maintaining a high level of performance and overall
system efficiency.
INPUT FILTER
In a typical use case for directly measuring the voltage across a
shunt resistor, the AD7402 can be connected directly across the
shunt resistor with a simple RC low-pass filter on each input.
Rev. A | Page 15 of 20
AD7402
Data Sheet
The recommended circuit configuration for driving the
differential inputs to achieve best performance is shown in
Figure 28. An RC low-pass filter is placed on both the analog
input pins. Recommended values for the resistors and capacitors
are 10 Ω and 220 pF, respectively. If possible, equalize the
source impedance on each analog input to minimize offset.
higher the decimation rate, the greater the system accuracy, as
illustrated in Figure 31. However, there is a trade-off between
accuracy and throughput rate and, therefore, higher decimation
rates result in lower throughput solutions.
100
fIN = 35Hz
90
80
70
60
50
40
30
C
R
VIN+
AD7402
R
VIN–
C
SINC1
SINC2
Figure 28. RC Low-Pass Filter Input Network
20
SINC3
SINC4
10
The input filter configuration for the AD7402 is not limited to
the low-pass structure shown in Figure 28. The differential RC
filter configuration shown in Figure 29 also achieves excellent
performance. Recommended values for the resistors and
capacitor are 22 Ω and 47 pF, respectively.
0
10
100
DECIMATION RATE
Figure 31. SNR vs. Decimation Rate for Different Sincx Filter Orders
A sinc3 filter is recommended for use with the AD7402. This
filter can be implemented on a field programmable gate array
(FPGA) or a digital signal processor (DSP).
R
V
IN+
C
AD7402
R
V
IN–
Equation 1 describes the transfer function of a sinc filter.
Figure 29. Differential RC Filter Network
N
1
DR
(
1− Z −DR
)
(1)
(2)
H(z) =
(
1− Z −1
)
Figure 30 compares the typical performance for the input filter
structures outlined in Figure 28 and Figure 29 for different
resistor and capacitor values.
where DR is the decimation rate and N is the sinc filter order.
The throughput rate of the sinc filter is determined by the
modulator clock and the decimation rate selected.
95
90
fIN = 35Hz
85
MCLK
Throughput =
DR
80
75
70
65
60
where MCLK is the modulator clock frequency
As the decimation rate increases, the data output size from the
sinc filter increases. The output data size is expressed in
Equation 3. The 16 most significant bits are used to return a
16-bit result.
55
10Ω, 220pF
DIFFERENTIAL 22Ω, 47pF
DIFFERENTIAL 22Ω, 10nF
Data size = N × log2 DR
(3)
50
For a sinc3 filter, the −3 dB filter response point can be derived
from the filter transfer function, Equation 1, and is 0.262 times
the throughput rate. The filter characteristics for a third-order
sinc filter are summarized in Table 11.
45
10
100
DECIMATION RATE
Figure 30. SNR vs. Decimation Rate for Different Filter Structures for Different
Resistor and Capacitor Values
Table 11. Sinc3 Filter Characteristics for 10 MHz
Decimation Throughput Output Data Filter Response
DIGITAL FILTER
The output of the AD7402 is a continuous digital bit stream. To
reconstruct the original input signal information, this output bit
stream needs to be digitally filtered and decimated. A sinc filter
is recommended due to its simplicity. A sinc3 filter is
recommended because it is one order higher than that of the
AD7402 modulator, which is a second-order modulator. The type
of filter selected, the decimation rate, and the modulator clock used
determines the overall system resolution and throughput rate. The
Ratio (DR)
Rate (kHz)
312.5
156.2
78.1
39.1
19.55
Size (Bits)
(kHz)
81.8
40.9
20.4
10.2
5.1
32
64
128
256
15
18
21
24
27
512
Rev. A | Page 16 of 20
Data Sheet
AD7402
acc3 <= 37'd0;
The following Verilog code provides an example of a sinc3 filter
implementation on a Xilinx® Spartan®-6 FPGA. Note that the
data is read on the negative clock edge. It is recommended to
read in the data on the negative clock edge. The code is
end
else
begin
/*perform accumulation process */
acc1 <= acc1 + ip_data1;
acc2 <= acc2 + acc1;
acc3 <= acc3 + acc2;
end
configurable to accommodate decimation rates from 32 to 4096.
module dec256sinc24b
(
input mclk1, /* used to clk filter */
input reset, /* used to reset filter */
end
input mdata1, /* input data to be filtered
*/
output reg [15:0] DATA, /* filtered output
*/
output reg data_en,
input [15:0] dec_rate
);
/*decimation stage (MCLKOUT/WORD_CLK) */
always @ (negedge mclk1, posedge reset)
begin
if (reset)
word_count <= 16'd0;
else
begin
/* Data is read on negative clk edge */
if ( word_count == dec_rate -
1 )
reg [36:0] ip_data1;
reg [36:0] acc1;
reg [36:0] acc2;
reg [36:0] acc3;
reg [36:0] acc3_d2;
reg [36:0] diff1;
reg [36:0] diff2;
reg [36:0] diff3;
reg [36:0] diff1_d;
reg [36:0] diff2_d;
word_count <= 16'd0;
else
word_count <= word_count
+ 16'b1;
end
end
always @ ( negedge mclk1, posedge reset )
begin
if ( reset )
word_clk <= 1'b0;
reg [15:0] word_count;
else
begin
reg word_clk;
reg enable;
if ( word_count == dec_rate/2 -
1 )
word_clk <= 1'b1;
else if ( word_count ==
/*Perform the Sinc action*/
always @ (mdata1)
if(mdata1==0)
ip_data1 <= 37'd0;
/* change 0 to a -1 for twos
complement */
dec_rate - 1 )
word_clk <= 1'b0;
end
end
else
/*Differentiator (including decimation
stage)
ip_data1 <= 37'd1;
Perform the differentiation stage (FIR) at a
lower speed.
Z = one sample delay WORD_CLK = output word
rate */
/*Accumulator (Integrator)
Perform the accumulation (IIR) at the speed
of the modulator.
Z = one sample delay MCLKOUT = modulators
conversion bit rate */
DIFF1
DIFF2
DIFF3
+
–
+
–
+
–
MCLKIN
ACC3
ACC2+
+
ACC1+
+
ACC3+
–1
–1
–1
Z
Z
Z
IP_DATA1
Z
Z
Z
+
WORD_CLK
Figure 32. Accumulator
Figure 33. Differentiator
always @ (negedge mclk1, posedge reset)
begin
always @ (negedge word_clk, posedge reset)
begin
if (reset)
begin
/* initialize acc registers on reset
if(reset)
begin
acc3_d2 <= 37'd0;
diff1_d <= 37'd0;
diff2_d <= 37'd0;
*/
acc1 <= 37'd0;
acc2 <= 37'd0;
Rev. A | Page 17 of 20
AD7402
Data Sheet
diff1 <= 37'd0;
diff2 <= 37'd0;
diff3 <= 37'd0;
end
default:begin
DATA <= (diff3[24:8] ==
17'h10000) ? 16'hFFFF : diff3[23:8];
end
endcase
end
else
begin
end
diff1 <= acc3 - acc3_d2;
diff2 <= diff1 - diff1_d;
diff3 <= diff2 - diff2_d;
acc3_d2 <= acc3;
/* Synchronize Data Output*/
always@ (negedge mclk1, posedge reset )
begin
diff1_d <= diff1;
if ( reset )
diff2_d <= diff2;
begin
data_en <= 1'b0;
enable <= 1'b1;
end
end
else
begin
end
if ( (word_count == dec_rate/2
- 1) && enable )
begin
/* Clock the Sinc output into an output
register
WORD_CLK = output word rate */
data_en <= 1'b1;
enable <= 1'b0;
end
WORD_CLK
else if ( (word_count ==
dec_rate - 1) && ~enable )
begin
DIFF3
DATA
Figure 34. Clocking Sinc3 Output into an Output Register
data_en <= 1'b0;
enable <= 1'b1;
end
always @ (negedge word_clk )
begin
else
data_en <= 1'b0;
case ( dec_rate )
16'd32:begin
DATA <= (diff3[15:0] ==
16'h8000) ? 16'hFFFF : {diff3[14:0], 1'b0};
end
end
end
endmodule
16'd64:begin
DATA <= (diff3[18:2] ==
17'h10000) ? 16'hFFFF : diff3[17:2];
end
16'd128:begin
DATA <= (diff3[21:5] ==
17'h10000) ? 16'hFFFF : diff3[20:5];
end
16'd256:begin
DATA <= (diff3[24:8] ==
17'h10000) ? 16'hFFFF : diff3[23:8];
end
16'd512:begin
DATA <= (diff3[27:11] ==
17'h10000) ? 16'hFFFF : diff3[26:11];
end
16'd1024:begin
DATA <= (diff3[30:14] ==
17'h10000) ? 16'hFFFF : diff3[29:14];
end
16'd2048:begin
DATA <= (diff3[33:17] ==
17'h10000) ? 16'hFFFF : diff3[32:17];
end
16'd4096:begin
DATA <= (diff3[36:20] ==
17'h10000) ? 16'hFFFF : diff3[35:20];
Rev. A | Page 18 of 20
Data Sheet
AD7402
POWER SUPPLY CONSIDERATIONS
INSULATION LIFETIME
The AD7402 requires a 5 V VDD1 supply, and there are various
means of achieving this. One method is to use an isolated dc-to-
dc converter such as the ADuM6000. This method provides a 5 V
regulated dc supply across the isolation barrier. Note that the
inherent isolation of the ADuM6000 is lower than the AD7402.
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the AD7402.
ISOLATION
BARRIER
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are
determined. These factors allow calculation of the time to
failure at the actual working voltage. The values shown in Table 8
summarize the peak voltage for 20 years of service life for a
bipolar, ac operating condition and the maximum VDE
approved working voltages.
5V ISO
5V DIGITAL
VDD1
VDD2
These tests subjected the AD7402 to continuous cross isolation
voltages. To accelerate the occurrence of failures, the selected
test voltages were values exceeding those of normal use. The
time to failure values of these units were recorded and used to
calculate the acceleration factors. These factors were then used
to calculate the time to failure under the normal operating
conditions. The values shown in Table 8 are the lesser of the
following two values:
Figure 35. ADuM6000 Isolated 5 V DC-to-DC Regulator Example
Another method is to regulate a dc supply on the high voltage
side of the isolation barrier using a step-down dc-to-dc regulator,
such as the ADP2441.
ISOLATION
BARRIER
ADP2441
4.5V TO 36V
5V VDD1
VDD2 5V DIGITAL
The value that ensures at least a 20-year lifetime of
continuous use.
DC-TO-DC
SWITCHING
REGULATOR
The maximum VDE approved working voltage.
Figure 36. ADP2441 Step-Down DC-to-DC Regulator Example
Note that the lifetime of the AD7402 varies according to the
waveform type imposed across the isolation barrier. The
iCoupler insulation structure is stressed differently, depending
on whether the waveform is bipolar ac, unipolar ac, or dc.
Figure 37, Figure 38, and Figure 39 illustrate the different
isolation voltage waveforms.
GROUNDING AND LAYOUT
It is recommended to decouple the VDD1 supply with a 10 μF
capacitor in parallel with a 1 nF capacitor to GND1. Decouple
the VDD2 supply with a 100 nF value to GND2. In applications
involving high common-mode transients, ensure that board
coupling across the isolation barrier is minimized.
RATED PEAK VOLTAGE
Furthermore, design the board layout so that any coupling that
occurs equally affects all pins on a given component side.
Failure to ensure equal coupling can cause voltage differentials
between pins to exceed the absolute maximum ratings of the
device, thereby leading to latch-up or permanent damage. Place
any decoupling used as close to the supply pins as possible.
0V
Figure 37. Bipolar AC Waveform, 50 Hz or 60 Hz
RATED PEAK VOLTAGE
Minimize series resistance in the analog inputs to avoid any
distortion effects, especially at high temperatures. If possible,
equalize the source impedance on each analog input to minimize
offset. Check for mismatch and thermocouple effects on the analog
input printed circuit board (PCB) tracks to reduce offset drift.
0V
Figure 38. Unipolar AC Waveform, 50 Hz or 60 Hz
RATED PEAK VOLTAGE
0V
Figure 39. DC Waveform
Rev. A | Page 19 of 20
AD7402
Data Sheet
OUTLINE DIMENSIONS
6.05
5.85
5.65
8
1
5
4
7.60
7.50
7.40
10.51
10.31
10.11
PIN 1
MARK
0.75
0.50 45°
0.25
2.45
2.35
2.25
2.65
2.50
2.35
1.04
BSC
8°
0°
0.30
0.33
0.27
0.20
SEATING
PLANE
0.20
0.10
COPLANARITY
0.10
0.51
0.41
0.31
1.27 BSC
0.75
0.58
0.40
Figure 40. 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Wide Body
(RI-8-1)
Dimensions shown in millimeters
ORDERING GUIDE
Temperature
Range
Package
Option
Model1
Package Description
AD7402-8BRIZ
AD7402-8BRIZ-RL
AD7402-8BRIZ-RL7
EVAL-AD7402-8FMCZ
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Evaluation Board
RI-8-1
RI-8-1
RI-8-1
1 Z = RoHS Compliant Part.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12898-0-6/15(A)
Rev. A | Page 20 of 20
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