AD743JR-16-REEL [ADI]
Ultralow Noise BiFET Op Amp; 超低噪声BiFET运算放大器
| 型号： | AD743JR-16-REEL |
| 厂家： | 
ADI |
| 描述： | Ultralow Noise BiFET Op Amp |
| 文件： | 总12页 (文件大小：309K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Noise
BiFET Op Amp
a
AD743
CO NNECTIO N D IAGRAMS
8-P in P lastic Mini-D IP (N)
FEATURES
ULTRALOW NOISE PERFORMANCE
2.9 nV/ √Hz at 10 kHz
0.38 V p-p, 0.1 Hz to 10 Hz
6.9 fA/ √Hz Current Noise at 1 kHz
and
16-P in SO IC (R) P ackage
8-P in Cer dip (Q ) P ackages
1
2
3
4
5
6
NC
1
2
3
4
8
16 NC
NULL
–IN
NC
+V
AD743
EXCELLENT DC PERFORMANCE
0.5 m V m ax Offset Voltage
250 pA m ax Input Bias Current
1000 V/ m V m in Open-Loop Gain
OFFSET
NULL
15
NC
7
6
5
S
AD743
–IN
NC
+IN
NC
+V
14
13
+IN
OUT
–V
S
NULL
S
TOP VIEW
AC PERFORMANCE
2.8 V/ s Slew Rate
4.5 MHz Unity-Gain Bandw idth
THD = 0.0003% @ 1 kHz
Available in Tape and Reel in Accordance w ith
EIA-481A Standard
12 OUTPUT
NC = NO CONNECT
OFFSET
11
–V
S
NULL
NC
NC
7
8
10
9
NC
NC
NC = NO CONNECT
APPLICATIONS
P RO D UCT H IGH LIGH TS
Sonar Pream plifiers
1. T he low offset voltage and low input offset voltage drift of
the AD743 coupled with its ultralow noise performance
mean that the AD743 can be used for upgrading many
applications now using bipolar amplifiers.
High Dynam ic Range Filters (>140 dB)
Photodiode and IR Detector Am plifiers
Accelerom eters
2. T he combination of low voltage and low current noise make
the AD743 ideal for charge sensitive applications such as
accelerometers and hydrophones.
P RO D UCT D ESCRIP TIO N
T he AD743 is an ultralow noise precision, FET input,
monolithic operational amplifier. It offers a combination of the
ultralow voltage noise generally associated with bipolar input op
amps and the very low input current of a FET -input device.
Furthermore, the AD743 does not exhibit an output phase
reversal when the negative common-mode voltage limit is
exceeded.
3. T he low input offset voltage and low noise level of the
AD743 provide >140 dB dynamic range.
4. T he typical 10 kHz noise level of 2.9 nV/√Hz permits a three
op amp instrumentation amplifier, using three AD743s, to be
built which exhibits less than 4.2 nV/√Hz noise at 10 kHz
and which has low input bias currents.
T he AD743’s guaranteed, maximum input voltage noise of
4.0 nV/√Hz at 10 kHz is unsurpassed for a FET -input
monolithic op amp, as is the maximum 1.0 µV p-p, 0.1 Hz to
10 Hz noise. T he AD743 also has excellent dc performance with
250 pA maximum input bias current and 0.5 mV maximum
offset voltage.
1000
OP27 &
RESISTOR
R
SOURCE
( — )
E
O
R
100
SOURCE
T he AD743 is specifically designed for use as a preamp in
capacitive sensors, such as ceramic hydrophones. It is available
in five performance grades. T he AD743J and AD743K are rated
over the commercial temperature range of 0°C to +70°C. T he
AD743A and AD743B are rated over the industrial temperature
range of –40°C to +85°C. T he AD743S is rated over the
military temperature range of –55°C to +125°C and is available
processed to MIL-ST D-883B, Rev. C.
AD743 + RESISTOR
AD743 & RESISTOR
OR
OP27 & RESISTOR
)
(
10
RESISTOR NOISE ONLY
(– – –)
T he AD743 is available in 8-pin plastic mini-DIP, 8-pin cerdip,
16-pin SOIC, or in chip form.
1
100
10M
1M
10k
100k
1k
SOURCE RESISTANCE – Ω
Input Noise Voltage vs. Source Resistance
REV. C
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
AD743–SPECIFICATIONS (@ +25؇C and ؎15 V dc, unless otherwise noted)
AD 743J
Typ
AD 743K/B
Typ
AD 743S
Typ
Model
Conditions
Min
Max
Min
Max
Min
Max Units
INPUT OFFSET VOLT AGE1
Initial Offset
Initial Offset
vs. T emp.
vs. Supply (PSRR)
vs. Supply (PSRR)
0.25
1.0/0.8
1.5
0.1
0.5/0.25
1.0/0.50
0.25
1.0
2.0
mV
mV
µV/°C
dB
T MIN to T MAX
T
MIN to TMAX
2
96
1
106
100
2
96
12 V to 18 V2
T MIN to T MAX
90
88
100
98
90
88
dB
INPUT BIAS CURRENT 3
Either Input
VCM = 0 V
150
400
150
250
150
400
pA
Either Input
@ T MAX
Either Input
Either Input, VS = ±5 V
VCM = 0 V
VCM = +10 V
VCM = 0 V
8.8/25.6
600
200
5.5/16
400
125
413
600
200
nA
pA
pA
250
30
250
30
300
30
INPUT OFFSET CURRENT
Offset Current
VCM = 0 V
VCM = 0 V
40
150
30
75
40
150
102
pA
nA
@ T MAX
2.2/6.4
1.1/3.2
FREQUENCY RESPONSE
Gain BW, Small Signal
Full Power Response
Slew Rate, Unity Gain
Settling T ime to 0.01%
T otal Harmonic
G = –1
VO = 20 V p-p
G = –1
4.5
25
2.8
6
4.5
25
2.8
6
4.5
25
2.8
6
MHz
kHz
V/µs
µs
f = 1 kHz
G = –1
Distortion4 (Figure 16)
0.0003
0.0003
0.0003
%
INPUT IMPEDANCE
Differential
Common Mode
1 ϫ 1010||20
3 ϫ 1011||18
1 ϫ 1010||20
1 ϫ 1010||20
3 ϫ 1011||18
Ω||pF
Ω||pF
3 ϫ 1011||18
INPUT VOLT AGE RANGE
Differential5
Common-Mode Voltage
Over Max Operating Range6
Common-Mode
±20
+13.3, –10.7
±20
+13.3, –10.7
±20
+13.3, –10.7
V
V
V
–10
+12
–10
+12
–10
+12
Rejection Ratio
VCM = ±10 V
T MIN to T MAX
80
78
95
90
88
102
80
78
95
dB
dB
INPUT VOLT AGE NOISE
0.1 Hz to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
0.38
5.5
3.6
3.2
2.9
0.38
5.5
3.6
3.2
2.9
1.0
10.0
6.0
5.0
4.0
0.38
5.5
3.6
3.2
2.9
µV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
5.0
4.0
5.0
4.0
f = 10 kHz
INPUT CURRENT NOISE
OPEN LOOP GAIN
f = 1 kHz
6.9
6.9
6.9
fA/√Hz
VO = ±10 V
RLOAD ≥ 2 kΩ
T MIN to T MAX
RLOAD = 600 Ω
1000
800
4000
1200
2000
1800
4000
1200
1000
800
4000
1200
V/mV
V/mV
V/mV
OUT PUT CHARACT ERIST ICS
Voltage
RLOAD ≥ 600 Ω
RLOAD ≥ 600 Ω
T MIN to T MAX
RLOAD ≥ 2 kΩ
Short Circuit
+13, –12
+13, –12
+13, –12
V
V
V
V
+13.6, –12.6
+13.6, –12.6
+13.6, –12.6
+12, –10
±12
20
+12, –10
±12
20
+12, –10
±12
20
+13.8, –13.1
40
+13.8, –13.1
40
+13.8, –13.1
40
Current
mA
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
±15
±15
±15
V
V
±4.8
±18
10.0
±4.8
±18
10.0
±4.8
±18
8.1
50
8.1
50
8.1
50
10.0 mA
T RANSIST OR COUNT
NOT ES
# of T ransistors
1Input offset voltage specifications are guaranteed after 5 minutes of operation at TA = +25°C.
2T est conditions: +VS = 15 V, –VS = 12 V to 18 V and +VS = 12 V to +18 V, –VS = 15 V.
3Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at TA = +25°C. For higher temperature, the current doubles every 10°C.
4Gain = –1, RL = 2 kΩ, CL = 10 pF.
5Defined as voltage between inputs, such that neither exceeds ±10 V from common.
6T hc AD743 does not exhibit an output phase reversal when the negative common-mode limit is exceeded.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
–2–
REV. C
AD743
ABSO LUTE MAXIMUM RATINGS1
O RD ERING GUID E
Tem perature Range
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18 V
Internal Power Dissipation2
P ackage
O ption*
Model
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Output Short Circuit Duration . . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS
Storage T emperature Range (Q) . . . . . . . . . . –65°C to +150°C
Storage T emperature Range (N, R) . . . . . . . . –65°C to +125°C
Operating T emperature Range
AD743J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
AD743A/B . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
AD743S . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
AD743JN
AD743KN
AD743JR-16
AD743KR-16
AD743BQ
AD743SQ/883B
AD743JR-16-REEL
AD743KR-16-REEL
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–55°C to +125°C
0°C to +70°C
0°C to +70°C
N-8
N-8
R-16
R-16
Q-8
Q-8
T ape & Reel
T ape & Reel
Lead T emperature Range (Soldering 60 seconds) . . . . . 300°C
NOT ES
*N = Plastic DIP; R = Small Outline IC; Q = Cerdip.
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
28-pin plastic package:
8-pin cerdip package:
θJA = 100°C/Watt, θJC = 50°C/Watt
θJA = 110°C/Watt, θJC = 30°C/Watt
16-pin plastic SOIC package: θJA = 100°C/Watt, θJC = 30°C/Watt
ESD SUSCEP TIBILITY
An ESD classification per method 3015.6 of MIL-ST D-883C
has been performed on the AD743. T he AD743 is a class 1
device, passing at 1000 V and failing at 1500 V on null pins 1
and 5, when tested, using an IMCS 5000 automated ESD
tester. Pins other than null pins fail at greater than 2500 V.
METALIZATIO N P H O TO GRAP H
Contact factory for latest dimensions.
D imensions shown in inches and (mm).
REV. C
–3–
AD743–Typical Characteristics (@ +25؇C, V = +15 V)
S
20
15
10
20
35
RLOAD = 10kΩ
RLOAD = 10kΩ
30
25
20
15
10
POSITIVE
SUPPLY
+VIN
15
10
NEGATIVE
SUPPLY
–VIN
5
0
5
0
5
0
0
5
10
10
100
LOAD RESISTANCE – Ω
10k
20
15
1k
0
20
5
10
15
SUPPLY VOLTAGE ± VOLTS
SUPPLY VOLTAGE ± VOLTS
Figure 2. Output Voltage Swing vs.
Supply Voltage
Figure 1. Input Voltage Swing
vs. Supply Voltage
Figure 3. Output Voltage Swing vs.
Load Resistance
10–6
10–7
12
200
100
9
6
10
–8
10
10–9
1
0.1
–10
10
3
0
–11
10
–12
10
0.01
10k
100k
1M
10M
100M
0
20
40 60 80 100
140
0
5
10
–60 –40 –20
120
15
20
FREQUENCY – Hz
SUPPLY VOLTAGE ± VOLTS
TEMPERATURE – °C
Figure 6. Output Im pedance vs.
Frequency (Closed Loop Gain = –1)
Figure 5. Input Bias Current vs.
Tem perature
Figure 4. Quiescent Current vs.
Supply Voltage
7.0
6.0
80
300
70
60
50
40
30
+ OUTPUT
CURRENT
200
100
0
5.0
4.0
3.0
2.0
– OUTPUT
CURRENT
20
10
0
–60 –40 –20
0
20
40
60 80 100 120 140
3
9
–12
–9
–6
–3
0
6
12
–40 –20
0
20
40
60 80 100 120 140
–60
COMMON MODE VOLTAGE – Volts
TEMPERATURE – °C
TEMPERATURE – °C
Figure 9. Gain Bandwidth Product
vs. Tem perature
Figure 8. Short Circuit Current
Lim it vs. Tem perature
Figure 7. Input Bias Current vs.
Com m on-Mode Voltage
–4–
REV. C
AD743
100
80
100
80
150
140
130
3.5
3.0
PHASE
60
60
GAIN
40
20
40
20
120
100
2.5
2.0
0
0
–20
100M
–20
100
80
1M
FREQUENCY – Hz
10M
1k
10k
100k
10
5
SUPPLY VOLTAGE ± VOLTS
15
20
0
–60 –40 –20
0
20
60 80 100 120 140
40
TEMPERATURE – °C
Figure 10. Open-Loop Gain and
Phase vs. Frequency
Figure 11. Slew Rate vs.
Tem perature (Gain = –1)
Figure 12. Open-Loop Gain vs.
Supply Voltage, RLOAD = 2K
120
120
35
30
25
20
15
100
80
100
80
VCM = ±10V
+ SUPPLY
60
60
RL= 2kΩ
40
20
40
20
– SUPPLY
10
5
0
0
100
0
100
1M
FREQUENCY – Hz
10M
100M
1k
10k
100k
1M
1k
10k
100k
1k
10k
FREQUENCY – Hz
100k
1M
FREQUENCY – Hz
Figure 13. Com m on-Mode Rejec-
tion vs. Frequency
Figure 14. Power Supply Rejection
vs. Frequency
Figure 15. Large Signal Frequency
Response
–70
–80
100
1k
CLOSED-LOOP GAIN = 1
–90
100
10
–100
GAIN = +10
–110
10
–120
1.0
0.1
CLOSED-LOOP GAIN = 10
GAIN = –1
–130
–140
10
100
1k
10k
100k
1.0
FREQUENCY – Hz
1
1
100
1k
10k
100k
10
10
100
1k
10k
100k
1M
10M
FREQUENCY – Hz
FREQUENCY – Hz
Figure 16. Total Harm onic Distor-
tion vs. Frequency
Figure 17. Input Noise Voltage
Spectral Density
Figure 18. Input Noise Current
Spectral Density
REV. C
–5–
AD743–Typical Characteristics (@ +25°C, V = +15 V)
S
69
63
57
51
45
39
33
27
21
15
9
3
3.3
3.8
2.5
2.7
2.9
3.1
3.5
Figure 22b. Unity-Gain Follower
Sm all Signal Pulse Response
Hz
INPUT VOLTAGE NOISE – nV
Figure 19. Typical Noise Distribution
@ 10 kHz (602 Units)
100pF
2kΩ
+V
7
S
0.1µF
1µF
2kΩ
2
3
V
IN
V
L
OUT
6
AD743
C
100pF
SQUARE WAVE
INPUT
4
0.1µF
1µF
–V
S
Figure 23a. Unity-Gain Inverter
Figure 20. Offset Null Configuration
Figure 23b. Unity-Gain Inverter
Large Signal Pulse Response
Figure 21. Unity-Gain Follower
Figure 22a. Unity-Gain Follower
Large Signal Pulse Response
Figure 23c. Unity-Gain Inverter
Sm all Signal Pulse Response
–6–
REV. C
AD743
O P AMP P ERFO RMANCE: JFET VS. BIP O LAR
D ESIGNING CIRCUITS FO R LO W NO ISE
T he AD743 is the first monolithic JFET op amp to offer the low
input voltage noise of an industry-standard bipolar op amp
without its inherent input current errors. T his is demonstrated
in Figure 24, which compares input voltage noise vs. input
source resistance of the OP27 and the AD743 op amps. From
this figure, it is clear that at high source impedance the low
current noise of the AD743 also provides lower total noise. It is
also important to note that with the AD743 this noise reduction
extends all the way down to low source impedances. T he lower
dc current errors of the AD743 also reduce errors due to offset
and drift at high source impedances (Figure 25).
An op amp’s input voltage noise performance is typicaly divided
into two regions: flatband and low frequency noise. T he AD743
offers excellent performance with respect to both. T he figure of
2.9 nV/√Hz @ 10 kHz is excellent for JFET input amplifier.
T he 0.1 Hz to 10 Hz noise is typically 0.38 µV p-p. T he user
should pay careful attention to several design details in order to
optimize low frequency noise performance. Random air currents
can generate varying thermocouple voltages that appear as low
frequency noise: therefore sensitive circuitry should be well
shielded from air flow. Keeping absolute chip temperature low
also reduces low frequency noise in two ways: first, the low
frequency noise is strongly dependent on the ambient
temperature and increases above +25°C. Secondly, since the
gradient of temperature from the IC package to ambient is
greater, the noise generated by random air currents, as
previously mentioned, will be larger in magnitude. Chip
temperature can be reduced both by operation at reduced
supply voltages and by the use of a suitable clip-on heat sink, if
possible.
1000
OP27 &
RESISTOR
( — )
R
SOURCE
E
O
R
100
SOURCE
AD743 + RESISTOR
AD743 & RESISTOR
OR
)
(
Low frequency current noise can be computed from the
~
OP27 & RESISTOR
magnitude of the dc bias current (In =
) and increases
2qIB∆f
10
below approximately 100 Hz with a 1/f power spectral density.
For the AD743 the typical value of current noise is 6.9 fA/√Hz
~
RESISTOR NOISE ONLY
(– – –)
at 1 kHz. Using the formula, In =
to compute the
4kT /R∆f ,
Johnson noise of a resistor, expressed as a current, one can see
that the current noise of the AD743 is equivalent to that of a
3.45 ϫ 108 Ω source resistance.
1
100
10M
1M
10k
100k
1k
SOURCE RESISTANCE – Ω
At high frequencies, the current noise of a FET increases
proportionately to frequency. T his noise is due to the “real” part
of the gate input impedance, which decreases with frequency.
T his noise component usually is not important, since the voltage
noise of the amplifier impressed upon its input capacitance is an
apparent current noise of approximately the same magnitude.
Figure 24. Total Input Noise Spectral Density @ 1 kHz vs.
Source Resistance
100
ADOP27G
In any FET input amplifier, the current noise of the internal
bias circuitry can be coupled externally via the gate-to-source
capacitances and appears as input current noise. T his noise is
totally correlated at the inputs, so source impedance matching
will tend to cancel out its effect. Both input resistance and input
capacitance should be balanced whenever dealing with source
capacitances of less than 300 pF in value.
10
1.0
AD743 KN
LO W NO ISE CH ARGE AMP LIFIERS
As stated, the AD743 provides both low voltage and low current
noise. T his combination makes this device particularly suitable
in applications requiring very high charge sensitivity, such as
capacitive accelerometers and hydrophones. When dealing with
a high source capacitance, it is useful to consider the total input
charge uncertainty as a measure of system noise.
0.1
100
1M
10M
1k
10k
100k
SOURCE RESISTANCE – Ω
Figure 25. Input Offset Voltage vs. Source Resistance
Charge (Q) is related to voltage and current by the simply stated
fundamental relationships:
dQ
Q = CV and I =
dt
As shown, voltage, current and charge noise can all be directly
related. T he change in open circuit voltage (∆V) on a capacitor
will equal the combination of the change in charge (∆Q/C) and
the change in capacitance with a built in charge (Q/∆C).
REV. C
–7–
AD743
Figures 26 and 27 show two ways to buffer and amplify the
output of a charge output transducer. Both require using an
amplifier which has a very high input impedance, such as the
AD743. Figure 26 shows a model of a charge amplifier circuit.
Here, amplification depends on the principle of conservation of
charge at the input of amplifier A1, which requires that the
charge on capacitor CS be transferred to capacitor CF, thus
yielding an output voltage of ∆Q/CF. T he amplifiers input
voltage noise will appear at the output amplified by the noise
gain (1 + (CS/CF)) of the circuit.
Figure 28 shows that these two circuits have an identical
frequency response and the same noise performance (provided
that CS/CF = R1/ R2). One feature of the first circuit is that a
“T ” network is used to increase the effective resistance of RB
and improve the low frequency cutoff point by the same factor.
–100
–110
–120
–130
–140
TOTAL OUTPUT
NOISE
–150
–160
–170
–180
–190
NOISE DUE TO
–200
RB ALONE
NOISE DUE TO
IB ALONE
–210
–220
10M
1k
1
10
100
10k
100k
100M
FREQUENCY – Hz
Figure 28. Noise at the Outputs of the Circuits of Figures
26 and 27. Gain = 10, CS = 3000 pF, RB = 22 MΩ
However, this does not change the noise contribution of RB
which, in this example, dominates at low frequencies. T he graph
of Figure 29 shows how to select an RB large enough to minimize
this resistor’s contribution to overall circuit noise. When the
equivalent current noise of RB ((√4kT)/R) equals the noise of IB
Figure 26. A Charge Am plifier Circuit
(
), there is diminishing return in making RB larger.
2qIB
5.2 x 1010
5.2 x 109
5.2 x 108
Figure 27. Model for a High Z Follower with Gain
5.2 x 107
5.2 x 106
T he second circuit, Figure 27, is simply a high impedance
follower with gain. Here the noise gain (1 + (R1/R2)) is the
same as the gain from the transducer to the output. Resistor RB,
in both circuits, is required as a dc bias current return.
1pA
10pA
INPUT BIAS CURRENT
10nA
100pA
1nA
T here are three important sources of noise in these circuits.
Amplifiers A1 and A2 contribute both voltage and current noise,
while resistor RB contributes a current noise of:
Figure 29. Graph of Resistance vs. Input Bias Current
where the Equivalent Noise √4kT/R, Equals the Noise
of the Bias Current
2qIB
T
RB
~
4k
∆f
N =
T o maximize dc performance over temperature, the source
resistances should be balanced on each input of the amplifier.
T his is represented by the optional resistor RB in Figures 26 and
27. As previously mentioned, for best noise performance care
should be taken to also balance the source capacitance designated
by CB. T he value for CB in Figure 26 would be equal to CS, in
Figure 27. At values of CB over 300 pF, there is a diminishing
impact on noise; capacitor CB can then be simply a large bypass
of 0.01 µF or greater.
where:
k = Boltzman’s Constant = 1.381 x 10–23 Joules/Kelvin
T = Absolute T emperature, Kelvin (0°C = +273.2 Kelvin)
∆f = Bandwidth – in Hz (Assuming an Ideal “Brick Wall”
Filter)
T his must be root-sum-squared with the amplifier’s own current
noise.
–8–
REV. C
AD743
300
200
H O W C H IP P AC KAG E TYP E AND P O WER D ISSIP ATIO N
AFFE C T INP UT BIAS C URRE NT
As with all JFET input amplifiers, the input bias current of the
AD743 is a direct function of device junction temperature, IB
approximately doubling every 10°C. Figure 30 shows the
relationship between bias current and junction temperature for
the AD743. T his graph shows that lowering the junction
temperature will dramatically improve IB.
TA = +25°C
θ
JA = 165°C/W
–6
10
θJ A = 115°C/W
θJA = 0°C/W
100
–7
10
V
T
= ±15V
S
A
+
=
25°C
–8
10
0
5
10
SUPPLY VOLTAGE – ±Volts
15
–9
10
Figure 32. Input Bias Current vs. Supply Voltage for
Various Values of θJ A
–10
0
–11
10
–12
10
–60
–20
0
20
40 60
80 100 120 140
–40
JUNCTION TEMPERATURE – °C
Figure 30. Input Bias Current vs. J unction Tem perature
T he dc thermal properties of an IC can be closely approximated
by using the simple model of Figure 31 where current represents
power dissipation, voltage represents temperature, and resistors
represent thermal resistance (θ in °C/Watt).
T
θJC
θCA
J
Figure 33. A Breakdown of Various Package Therm al
Resistances
θJA
P
T
IN
A
RED UC ED P O WER SUP P LY O P ERATIO N FO R
LO WER IB
Reduced power supply operation lowers IB in two ways: first, by
lowering both the total power dissipation and second, by
reducing the basic gate-to-junction leakage (Figure 32). Figure
34 shows a 40 dB gain piezoelectric transducer amplifier, which
operates without an ac coupling capacitor, over the –40°C to
+85°C temperature range. If the optional coupling capacitor is
used, this circuit will operate over the entire –55°C to +125°C
military temperature range.
WHERE:
PIN = DEVICE DISSIPATION
TA = AMBIENT TEMPERATURE
TJ = JUNCTION TEMPERATURE
= THERMAL RESISTANCE – JUNCTION TO CASE
θJC
θCA= THERMAL RESISTANCE – CASE TO AMBIENT
Figure 31. A Device Therm al Model
From this model T J = T A + θJA Pin. T herefore, IB can be
determined in a particular application by using Figure 30
together with the published data for θJA and power dissipation.
T he user can modify θJA by use of an appropriate clip-on heat
sink such as the Aavid # 5801. θJA is also a variable when using
the AD743 in chip form. Figure 32 shows bias current vs.
supply voltage with θJA as the third variable. T his graph can be
used to predict bias current after θJA has been computed. Again
bias current will double for every 10°C. T he designer using the
AD743 in chip form (Figure 33) must also be concerned with
both θJC and θCA, since θJC can be affected by the type of die
mount technology used.
T ypically, θJC’s will be in the 3°C to 5°C/watt range; therefore,
for normal packages, this small power dissipation level may be
ignored. But, with a large hybrid substrate, θJC will dominate
proportionately more of the total θJA.
Figure 34. A Piezoelectric Transducer
AD743
AN INP UT-IMP ED ANCE-CO MP ENSATED ,
SALLEN-KEY FILTER
T he simple high pass filter of Figure 35 has an important source
of error which is often overlooked. Even 5 pF of input capacitance
in amplifier “A” will contribute an additional 1% of passband
amplitude error, as well as distortion, proportional to the C/V
characteristics of the input junction capacitance. T he addition
of the network designated “Z” will balance the source
impedance–as seen by “A”–and thus eliminate these errors.
Figure 36b. An Accelerom eter Circuit Em ploying a
DC Servo Am plifier
A dc servo-loop (Figure 36b) can be used to assure a dc output
which is <10 mV, without the need for a large compensating
resistor when dealing with bias currents as large as 100 nA. For
optimal low frequency performance, the time constant of the
servo loop (R4C2 = R5C3) should be:
Figure 35. An Input Im pedance Com pensated
Sallen-Key Filter
TWO H IGH P ERFO RMANCE
ACCELERO METER AMP LIFIERS
Two of the most popular charge-out transducers are hydrophones
and accelerometers. Precision accelerometers are typically
calibrated for a charge output (pC/g).* Figures 36a and 36b
show two ways in which to configure the AD743 as a low noise
charge amplifier for use with a wide variety of piezoelectric
accelerometers. T he input sensitivity of these circuits will be
determined by the value of capacitor C1 and is equal to:
R2
R3
Time Constant ≥ 10 R1 1 +
C1
A LO W NO ISE H YD RO P H O NE AMP LIFIER
Hydrophones are usually calibrated in the voltage-out mode.
T he circuits of Figures 37a and 37b can be used to amplify the
output of a typical hydrophone. Figure 37a shows a typical dc
coupled circuit. T he optional resistor and capacitor serve to
counteract the dc offset caused by bias currents flowing through
resistor R1. Figure 37b, a variation of the original circuit, has a
low frequency cutoff determined by an RC time constant equal
to:
∆QOUT
C1
∆VOUT
=
T he ratio of capacitor C1 to the internal capacitance (CT) of the
transducer determines the noise gain of this circuit (1 + CT /C1).
T he amplifiers voltage noise will appear at its output amplified
by this amount. T he low frequency bandwidth of these circuits
will be dependent on the value of resistor R1. If a “T ” network
is used, the effective value is: R1 (1 + R2/R3).
1
Time Constant =
2π × CC ×100Ω
Figure 36a. A Basic Accelerom eter Circuit
*pC = Picocoulombs
g = Earth's Gravitational Constant
Figure 37a. A Basic Hydrophone Am plifier
–10–
REV. C
AD743
Where the dc gain is 1 and the gain above the low frequency
cutoff (1/(2πCC(100 Ω))) is the same as the circuit of Figure
37a. T he circuit of Figure 37c uses a dc servo loop to keep the
dc output at 0 V and to maintain full dynamic range for IB’s up
to 100 nA. T he time constant of R7 and C2 should be larger
than that of R1 and CT for a smooth low frequency response.
The transducer shown has a source capacitance of 7500 pF. For
smaller transducer capacitances (≤300 pF), lowest noise can be
achieved by adding a parallel RC network (R4 = R1, C1 = CT )
in series with the inverting input of the AD743.
BALANCING SO URCE IMP ED ANCES
As mentioned previously, it is good practice to balance the
source impedances (both resistive and reactive) as seen by the
inputs of the AD743. Balancing the resistive components will
optimize dc performance over temperature because balancing
will mitigate the effects of any bias current errors. Balancing
input capacitance will minimize ac response errors due to the
amplifier’s input capacitance and, as shown in Figure 38, noise
performance will be optimized. Figure 39 shows the required
external components for noninverting (A) and inverting (B)
configurations.
Figure 37b. An AC-Coupled, Low Noise
Hydrophone Am plifier
Figure 38. RTI Voltage Noise vs. Input Capacitance
Figure 37c. A Hydrophone Am plifier Incorporating a
DC Servo Loop
Figure 39. Optional External Com ponents for Balancing Source Im pedances
REV. C
–11–
AD743
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
8-P in P lastic Mini-D IP (N)
8-P in Cer dip (Q ) P ackages
16-P in SO IC (R) P ackage
–12–
REV. C
相关型号：
AD743KR
IC OP-AMP, 500 uV OFFSET-MAX, 4.5 MHz BAND WIDTH, PDSO16, SOIC-16, Operational Amplifier
ADI
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