AD7441BRTZ-R2 [ADI]
Pseudo Differential Input, 1 MSPS, 10-/12-Bit ADCs in an 8-Lead SOT-23; 伪差分输入， 1 MSPS ， 10位/ 12位ADC，采用8引脚SOT- 23
| 型号： | AD7441BRTZ-R2 |
| 厂家： | 
ADI |
| 描述： | Pseudo Differential Input, 1 MSPS, 10-/12-Bit ADCs in an 8-Lead SOT-23 |
| 文件： | 总24页 (文件大小：513K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Pseudo Differential Input, 1 MSPS,
10-/12-Bit ADCs in an 8-Lead SOT-23
AD7441/AD7451
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
Fast throughput rate: 1 MSPS
DD
Specified for VDD of 2.7 V to 5.25 V
Low power at maximum throughput rate:
4 mW maximum at 1 MSPS with VDD = 3 V
9.25 mW maximum at 1 MSPS with VDD = 5 V
Pseudo differential analog input
Wide input bandwidth:
V
V
IN+
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
T/H
IN–
V
REF
70 dB SINAD at 100 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
SCLK
High speed serial interface:
SDATA
AD7441/AD7451
CONTROL LOGIC
SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible
Power-down mode: 1 μA maximum
8-lead SOT-23 and MSOP packages
CS
APPLICATIONS
GND
Figure 1.
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
PRODUCT HIGHLIGHTS
GENERAL DESCRIPTION
1. Operation with 2.7 V to 5.25 V Power Supplies.
The AD7441/AD74511 are, respectively, 10-/12-bit high speed,
low power, single-supply, successive approximation (SAR),
analog-to-digital converters (ADCs) that feature a pseudo
differential analog input. These parts operate from a single
2.7 V to 5.25 V power supply and achieve very low power
dissipation at high throughput rates of up to 1 MSPS.
2. High Throughput with Low Power Consumption.
With a 3 V supply, the AD7441/AD7451 offer 4 mW maxi-
mum power consumption for a 1 MSPS throughput rate.
3. Pseudo Differential Analog Input.
4. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock,
allowing the power to be reduced as the conversion time
is reduced through the serial clock speed increase. These
parts also feature a shutdown mode to maximize power
efficiency at lower throughput rates.
The AD7441/AD7451 contain a low noise, wide bandwidth,
differential track-and-hold (T/H) amplifier that handles input
frequencies up to 3.5 MHz. The reference voltage for these
devices is applied externally to the VREF pin and can range from
100 mV to VDD, depending on the power supply and what suits
the application.
5. Variable Voltage Reference Input.
6. No Pipeline Delays.
The conversion process and data acquisition are controlled
CS
using
with microprocessors or DSPs. The input signals are sampled
CS
and the serial clock, allowing the device to interface
CS
7. Accurate Control of Sampling Instant via
Once-Off Conversion Control.
Input and
on the falling edge of
The SAR architecture of these parts ensures that there are no
pipeline delays.
when the conversion is initiated.
8. ENOB > 10 Bits Typically with 500 mV Reference.
1 Protected by U.S. Patent Number 6,681,332.
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2010 Analog Devices, Inc. All rights reserved.
AD7441/AD7451
TABLE OF CONTENTS
Features .............................................................................................. 1
ADC Transfer Function............................................................. 13
Typical Connection Diagram ................................................... 14
Analog Input ............................................................................... 14
Analog Input Structure.............................................................. 14
Digital Inputs .............................................................................. 15
Reference ..................................................................................... 15
Serial Interface............................................................................ 16
Modes of Operation ....................................................................... 18
Normal Mode.............................................................................. 18
Power-Down Mode.................................................................... 18
Power vs. Throughput Rate....................................................... 20
Microprocessor and DSP Interfacing ...................................... 20
Grounding and Layout Hints.................................................... 22
Evaluating Performance ............................................................ 22
Outline Dimensions....................................................................... 23
Ordering Guide .......................................................................... 24
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 7
Timing Diagrams.......................................................................... 7
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 13
Circuit Information.................................................................... 13
Converter Operation.................................................................. 13
REVISION HISTORY
3/10—Rev. C to Rev. D
2/04—Rev. 0 to Rev. A
Changes to IDD Normal Mode (Operational) Parameter..................6
Updated Outline Dimensions............................................................23
Changes to Ordering Guide ...............................................................24
Updated Format.....................................................................Universal
Changes to General Description ....................................................... 1
Changes to Table 1 Footnotes ............................................................ 4
Changes to Table 2 Footnotes ............................................................ 6
Changes to Table 3 Footnotes ............................................................ 7
Changes to Table 5 .............................................................................. 9
Updated Figures 7, 8, and 9.............................................................. 13
Changes to Figure 23......................................................................... 16
Changes to Reference Section.......................................................... 17
3/07—Rev. B to Rev. C
Changes to Table 5.................................................................................9
Updated Layout....................................................................................12
Changes to Terminology Section.......................................................12
Updated Outline Dimensions............................................................23
Changes to Ordering Guide ...............................................................24
9/03—Revision 0: Initial Version
2/05—Rev. A to Rev. B
Changes to Ordering Guide ...............................................................24
Rev. D | Page 2 of 24
AD7441/AD7451
SPECIFICATIONS
VDD = 2.7 V to 5.25 V; fSCLK = 18 MHz; fS = 1 MSPS; VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted. Temperature ranges for A, B
versions: −40°C to +85°C.
Table 1. AD7451
Parameter
Test Conditions/Comments
fIN = 100 kHz
VDD = 2.7 V to 5.25 V
VDD = 2.7 V to 3.6 V
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V; −78 dB typ
VDD = 4.75 V to 5.25 V; −80 dB typ
VDD = 2.7 V to 3.6 V; −80 dB typ
VDD = 4.75 V to 5.25 V; −82 dB typ
fa = 90 kHz; fb = 110 kHz
A Version
B Version
Unit
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)1
Signal-to-(Noise + Distortion) (SINAD)1
70
69
70
−73
−75
−73
−75
70
69
70
−73
−75
−73
−75
dB min
dB min
dB min
dB max
dB max
dB max
dB max
Total Harmonic Distortion (THD)1
Peak Harmonic or Spurious Noise1
Intermodulation Distortion (IMD)1
Second-Order Terms
Third-Order Terms
Aperture Delay1
Aperture Jitter1
Full-Power Bandwidth1, 2
−80
−80
5
50
20
−80
−80
5
50
20
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
@ −3 dB
@ −0.1 dB
2.5
2.5
DC ACCURACY
Resolution
12
12
1
0.95
3.5
3
Bits
Integral Nonlinearity (INL)1
Differential Nonlinearity (DNL)1
Offset Error1
1.5
0.95
3.5
3
LSB max
LSB max
LSB max
LSB max
Guaranteed no missed codes to 12 bits
Gain Error1
ANALOG INPUT
Full-Scale Input Span
Absolute Input Voltage
VIN+
VIN+ − VIN–
VREF
VREF
V
VREF
VREF
V
V
V
3
VIN–
VDD = 2.7 V to 3.6 V
VDD = 4.75 V to 5.25 V
−0.1 to +0.4
−0.1 to +1.5
1
−0.1 to +0.4
−0.1 to +1.5
1
DC Leakage Current
Input Capacitance
REFERENCE INPUT
VREF Input Voltage4
DC Leakage Current
VREF Input Capacitance
LOGIC INPUTS
μA max
pF typ
When in track-and-hold
30/10
30/10
1ꢀ tolerance for specified performance
When in track-and-hold
2.5
1
10/30
2.5
1
10/30
V
μA max
pF typ
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
1
2.4
0.8
1
V min
V max
μA max
pF max
Typically 10 nA, VIN = 0 V or VDD
5
Input Capacitance, CIN
10
10
LOGIC OUTPUTS
Output High Voltage, VOH
VDD = 4.75 V to 5.25 V; ISOURCE = 200 μA
VDD = 2.7 V to 3.6 V; ISOURCE = 200 μA
ISINK = 200 μA
2.8
2.4
0.4
1
10
Straight
2.8
2.4
0.4
1
10
Straight
V min
V min
V max
μA max
pF max
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance5
Output Coding
(natural) binary
(natural) binary
Rev. D | Page 3 of 24
AD7441/AD7451
Parameter
Test Conditions/Comments
A Version
B Version
Unit
CONVERSION RATE
Conversion Time
888 ns with an 18 MHz SCLK
Sine wave input
Full-scale step input
16
16
SCLK cycles
ns max
ns max
Track-and-Hold Acquisition Time1
250
290
1
250
290
1
Throughput Rate
POWER REQUIREMENTS
VDD
MSPS max
2.7/5.25
2.7/5.25
V min/max
6, 7
IDD
Normal Mode (Static)
Normal Mode (Operational)
SCLK on or off
0.5
1.95
1.45
1
0.5
1.95
1.45
1
mA typ
mA max
mA max
μA max
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
SCLK on or off
Full Power-Down Mode
Power Dissipation
Normal Mode (Operational)
VDD = 5 V; 1.55 mW typical for 100 ksps6
VDD = 3 V; 0.6 mW typical for 100 ksps6
VDD = 5 V; SCLK on or off
9.25
4
5
9.25
4
5
mW max
mW max
μW max
μW max
Full Power-Down
VDD = 3 V; SCLK on or off
3
3
1 See Terminology section.
2 Analog inputs with slew rates exceeding 27 V/μs (full-scale input sine wave > 3.5 MHz) within the acquisition time can cause the converter to return an incorrect result.
3 A small dc input is applied to VIN– to provide a pseudo ground for VIN+
.
4 The AD7451 is functional with a reference input in the range of 100 mV to VDD
5 Guaranteed by characterization.
.
6 See the Power vs. Throughput Rate section.
7 Measured with a full-scale dc input.
Rev. D | Page 4 of 24
AD7441/AD7451
VDD = 2.7 V to 5.25 V; fSCLK = 18 MHz; fS = 1 MSPS; VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted. Temperature range for
B version: −40°C to +85°C.
Table 2. AD7441
Parameter
Test Conditions/Comments
B Version
Unit
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)1
Total Harmonic Distortion (THD)1
fIN = 100 kHz
61
dB min
dB max
dB max
dB max
dB max
2.7 V to 3.6 V; −77 dB typical
4.75 V to 5.25 V; −79 dB typical
2.7 V to 3.6 V; −80 dB typical
4.75 V to 5.25 V; −82 dB typical
fa = 90 kHz, fb = 110 kHz
−72
−73
−72
−74
Peak Harmonic or Spurious Noise1
Intermodulation Distortion (IMD)1
Second-Order Terms
Third-Order Terms
Aperture Delay1
Aperture Jitter1
Full-Power Bandwidth1, 2
−80
−80
5
50
20
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
@ −3 dB
@ −0.1 dB
2.5
DC ACCURACY
Resolution
10
0.5
0.5
1
Bits
Integral Nonlinearity (INL)1
Differential Nonlinearity (DNL)1
Offset Error1
LSB max
LSB max
LSB max
LSB max
Guaranteed no missed codes to 10 bits
Gain Error1
1
ANALOG INPUT
Full-Scale Input Span
Absolute Input Voltage
VIN+
VIN+ − VIN–
VREF
V
VREF
V
V
V
3
VIN–
VDD = 2.7 V to 3.6 V
VDD = 4.75 V to 5.25 V
−0.1 to +0.4
−0.1 to +1.5
1
DC Leakage Current
Input Capacitance
REFERENCE INPUT
VREF Input Voltage4
DC Leakage Current
VREF Input Capacitance
LOGIC INPUTS
μA max
pF typ
When in track-and-hold
30/10
1ꢀ tolerance for specified performance 2.5
1
When in track-and-hold
V
μA max
pF typ
10/30
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
1
V min
V max
μA max
pF max
Typically 10 nA, VIN = 0 V or VDD
5
Input Capacitance, CIN
10
LOGIC OUTPUTS
Output High Voltage, VOH
VDD = 4.75 V to 5.25 V; ISOURCE = 200 μA
VDD = 2.7 V to 3.6 V; ISOURCE = 200 μA
ISINK = 200 μA
2.8
2.4
0.4
1
V min
V min
V max
μA max
pF max
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance5
Output Coding
10
Straight (natural) binary
Rev. D | Page 5 of 24
AD7441/AD7451
Parameter
Test Conditions/Comments
B Version
Unit
CONVERSION RATE
Conversion Time
888 ns with an 18 MHz SCLK
Sine wave input
Step input
16
SCLK cycles
ns max
ns max
Track-and-Hold Acquisition Time1
250
290
1
Throughput Rate
POWER REQUIREMENTS
VDD
MSPS max
2.7/5.25
V min/max
6, 7
IDD
Normal Mode (Static)
Normal Mode (Operational)
SCLK on or off
0.5
1.95
1.45
1
mA typ
mA max
mA max
μA max
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
SCLK on or off
Full Power-Down Mode
Power Dissipation
Normal Mode (Operational)
VDD = 5 V; 1.55 mW typ for 100 ksps6
VDD = 3 V; 0.6 mW typ for 100 ksps6
VDD = 5 V; SCLK on or off
9.25
4
5
mW max
mW max
μW max
μW max
Full Power-Down
VDD = 3 V; SCLK on or off
3
1 See the Terminology section.
2 Analog inputs with slew rates exceeding 27 V/μs (full-scale input sine wave > 3.5 MHz) within the acquisition time can cause the converter to return an incorrect result.
3 A small dc input is applied to VIN– to provide a pseudo ground for VIN+
.
4 The AD7441 is functional with a reference input in the range 100 mV to VDD
5 Guaranteed by characterization.
.
6 See the Power vs. Throughput Rate section.
7 Measured with a full-scale dc input.
Rev. D | Page 6 of 24
AD7441/AD7451
TIMING SPECIFICATIONS1
VDD = 2.7 V to 5.25 V; fSCLK = 18 MHz; fS = 1 MSPS; VREF = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter Limit at TMIN, TMAX
Unit
Description
2
fSCLK
10
kHz min
MHz max
18
tCONVERT
16 × tSCLK
888
60
tSCLK = 1/fSCLK
ns max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
μs max
Minimum quiet time between end of a serial read and next falling edge of CS
Minimum CS pulse width
tQUIET
t1
10
CS falling edge to SCLK falling edge setup time
Delay from CS falling edge until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK high pulse width
SCLK low pulse width
SCLK edge to data valid hold time
SCLK falling edge to SDATA, three-state enabled
SCLK falling edge to SDATA, three-state enabled
Power-up time from full power-down
t2
10
3
t3
20
t4
t5
t6
t7
40
0.4 tSCLK
0.4 tSCLK
10
10
35
4
t8
5
tPOWER-UP
1
1 Guaranteed by characterization. All input signals are specified with tRISE = tFALL = 5 ns (10ꢀ to 90ꢀ of VDD) and timed from a voltage level of 1.6 V. See Figure 2, Figure 3,
and the Serial Interface section.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 4 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V and the time required for an output to
cross 0.4 V or 2.0 V for VDD = 3 V.
4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time (t8) quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
5 See the Power-Up Time section.
TIMING DIAGRAMS
t1
CS
tCONVERT
t2
t3
B
t5
1
2
3
4
5
13
14
t6
15
16
SCLK
t8
t7
t4
tQUIET
0
0
0
0
DB11
DB10
DB2
DB1
DB0
SDATA
4 LEADING ZEROS
THREE-STATE
Figure 2. AD7451 Serial Interface Timing Diagram
t1
CS
tCONVERT
t2
t3
B
t5
1
2
3
4
5
13
14
t6
15
16
SCLK
t8
t7
t4
tQUIET
0
0
0
0
DB9
DB8
DB0
0
0
SDATA
4 LEADING ZEROS
2 TRAILING ZEROS THREE-STATE
Figure 3. AD7441 Serial Interface Timing Diagram
Rev. D | Page 7 of 24
AD7441/AD7451
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
VIN+ to GND
VIN– to GND
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
10 mA
Digital Input Voltage to GND
Digital Output Voltage to GND
VREF to GND
1.6mA
I
OL
Input Current to any Pin Except Supplies1
TO OUTPUT
PIN
1.6V
Operating Temperature Range
Commercial (A, B Version)
−40°C to +85°C
C
L
25pF
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
−65°C to +150°C
150°C
205.9°C/W (MSOP)
211.5°C/W (SOT-23)
43.74°C/W (MSOP)
91.99°C/W (SOT-23)
200µA
I
OH
Figure 4. Load Circuit for Digital Output Timing Specifications
ESD CAUTION
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
ESD
215°C
220°C
1 kV
1 Transient currents of up to 100 mA do not cause SCR latch-up.
Rev. D | Page 8 of 24
AD7441/AD7451
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
V
1
2
3
4
8
7
6
5
V
V
1
2
3
4
8
7
6
5
V
V
V
REF
DD
DD
REF
IN+
IN–
AD7441/
AD7451
TOP VIEW
(Not to Scale)
AD7441/
AD7451
TOP VIEW
(Not to Scale)
V
SCLK
SDATA
CS
SCLK
SDATA
CS
IN+
IN–
V
GND
GND
Figure 5. 8-Lead MSOP Pin Configuration
Figure 6. 8-Lead SOT-23 Pin Configuration
Table 5. Pin Function Descriptions
Pin. No.
MSOP SOT-23
Mnemonic
Description
1
8
VREF
Reference Input for the AD7441/AD7451. An external reference in the range of 100 mV to VDD must be
applied to this input. The specified reference input is 2.5 V. This pin is decoupled to GND with a capacitor
of at least 0.1 μF.
2
3
7
6
VIN+
VIN–
Noninverting Analog Input.
Inverting Input. This pin sets the ground reference point for the VIN+ input. Connect to ground or to a dc
offset to provide a pseudo ground.
4
5
6
5
4
3
GND
CS
Analog Ground. Ground reference point for all circuitry on the AD7441/AD7451. All analog input signals
and any external reference signal are referred to this GND voltage.
Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on
the AD7441/AD7451 and framing the serial data transfer.
Serial Data, Logic Output. The conversion result from the AD7441/AD7451 is provided on this output as
a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream of
the AD7451 consists of four leading zeros followed by the 12 bits of conversion data that are provided
MSB first; the data stream of the AD7441 consists of four leading zeros, followed by the 10 bits of con-
version data, followed by two trailing zeros. In both cases, the output coding is straight (natural) binary.
SDATA
7
8
2
1
SCLK
VDD
Serial Clock, Logic Input. SCLK provides the serial clock for accessing data from the part. This clock input
is also used as the clock source for the conversion process.
Power Supply Input. VDD is 2.7 V to 5.25 V. This supply is decoupled to GND with a 0.1 μF capacitor and a
10 μF tantalum capacitor.
Rev. D | Page 9 of 24
AD7441/AD7451
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, fS = 1 MSPS, fSCLK = 18 MHz, VDD = 2.7 V to 5.25 V, VREF = 2.5 V, unless otherwise noted.
75
1.0
V
= 5.25V
DD
0.8
0.6
0.4
0.2
0
V
= 4.75V
70
65
60
55
DD
V
= 3.6V
DD
V
= 2.7V
DD
–0.2
–0.4
–0.6
–0.8
–1.0
10
100
FREQUENCY (kHz)
1000
0
1024
2048
3072
4096
CODE
Figure 7. SINAD vs. Analog Input Frequency for the AD7451 for
Various Supply Voltages
Figure 10. Typical DNL for the AD7451 for VDD = 5 V
1.0
0.8
0.6
0.4
0.2
0
0
100mV p-p SINE WAVE ON V
DD
NO DECOUPLING ON V
DD
–20
–40
–60
V
= 3V
DD
–0.2
V
= 5V
DD
–80
–0.4
–0.6
–0.8
–1.0
–100
–120
0
100 200 300 400 500 600 700 800 900 1000
SUPPLY RIPPLE FREQUENCY (kHz)
0
1024
2048
3072
4096
CODE
Figure 11. Typical INL for the AD7451 for VDD = 5 V
Figure 8. PSRR vs. Supply Ripple Frequency Without Supply Decoupling
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
0
8192 POINT FFT
9949
CODES
fSAMPLE = 1MSPS
fIN = 100kSPS
SINAD = 71dB
THD = –82dB
SFDR = –83dB
–20
–40
–60
–80
–100
–120
–140
27 CODES
2047 2048
24 CODES
2049 2050
0
100
200
300
400
500
2046
2051
CODES
FREQUENCY (kHz)
Figure 12. Histogram of 10,000 Conversions of a DC Input for the AD7451
Figure 9. AD7451 Dynamic Performance for VDD = 5 V
Rev. D | Page 10 of 24
AD7441/AD7451
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
0
–20
8192 POINT FFT
fSAMPLE = 1MSPS
fIN = 100kSPS
SINAD = 61.7dB
THD = –81.7dB
SFDR = –82dB
–40
–60
–80
POSITIVE DNL
NEGATIVE DNL
–100
–120
–140
–0.5
–1.0
0
1
2
3
4
5
0
0
0
100
200
300
400
500
1024
1024
V
(V)
V
(V)
REF
REF
Figure 13. Change in DNL vs. VREF for VDD = 5 V
Figure 16. AD7441 Dynamic Performance
5
4
0.5
0.4
0.3
3
0.2
0.1
2
0
1
–0.1
–0.2
–0.3
–0.4
–0.5
POSITIVE DNL
NEGATIVE DNL
0
–1
–2
0
1
2
3
4
5
256
512
768
V
(V)
CODE
REF
Figure 17. Typical DNL for the AD7441
Figure 14. Change in INL vs. VREF for VDD = 5 V
0.5
0.4
12
11
10
9
V
= 3V
DD
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
8
V
= 5V
DD
7
6
256
512
768
0
1
2
3
4
5
CODE
V
(V)
REF
Figure 18. Typical INL for the AD7441
Figure 15. ENOB vs. VREF for VDD = 5 V and 3 V
Rev. D | Page 11 of 24
AD7441/AD7451
TERMINOLOGY
Signal-to-(Noise + Distortion) Ratio (SINAD)
Aperture Delay
This is the measured ratio of SINAD at the output of the ADC.
The signal is the rms amplitude of the fundamental. Noise is
the sum of all nonfundamental signals up to half the sampling
frequency (fS/2), excluding dc. The ratio is dependent on the
number of quantization levels in the digitization process: the more
levels, the smaller the quantization noise. The theoretical SINAD
ratio for an ideal N-bit converter with a sine wave input is given by
This is the amount of time from the leading edge of the
sampling clock until the ADC actually takes the sample.
Aperture Jitter
This is the sample-to-sample variation in the effective point in
time at which the actual sample is taken.
Full Power Bandwidth
The full power bandwidth of an ADC is that input frequency
at which the amplitude of the reconstructed fundamental is
reduced by 0.1 dB or 3 dB for a full-scale input.
Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB
Therefore, for 12-bit converters, the SINAD is 74 dB; for 10-bit
converters, the SINAD is 62 dB.
Integral Nonlinearity (INL)
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of harmonics to the
fundamental. In the AD7441/AD7451, THD is
Differential Nonlinearity (DNL)
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
2
2
2
2
2
V2 +V3 +V4 +V5 +V6
THD
(
dB = 20 log
)
V1
where:
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second to
Offset Error
This is the deviation of the first code transition (000…000 to
000…001) from the ideal (that is, AGND + 1 LSB).
the sixth harmonics.
Gain Error
Peak Harmonic or Spurious Noise
This is the deviation of the last code transition (111…110 to
111…111) from the ideal (that is, VREF − 1 LSB) after the offset
error has been adjusted out.
Peak harmonic (spurious noise) is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2, excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
ADCs where the harmonics are buried in the noise floor, it is
a noise peak.
Track-and-Hold Acquisition Time
The track-and-hold acquisition time is the minimum time
required for the track-and-hold amplifier to remain in track
mode for its output to reach and settle to within 0.5 LSB of the
applied input signal.
Intermodulation Distortion
Power Supply Rejection Ratio (PSRR)
With inputs consisting of sine waves at two frequencies, fa and
fb, an active device with nonlinearities creates distortion products
at sum and difference frequencies of mfa nfb where m, n = 0,
1, 2, 3, and so on. Intermodulation distortion terms are those in
which neither m nor n are equal to zero. For example, the second-
order terms include (fa + fb) and (fa − fb), while the third-order
terms include (2fa + fb), (2fa − fb), (fa + 2fb), and (fa − 2fb).
The power supply rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency (f) to the
power of a 100 mV p-p sine wave applied to the ADC VDD
supply of Frequency fS. The frequency of this input varies from
1 kHz to 1 MHz.
PSRR (dB) = 10log(Pf/Pfs)
The AD7441/AD7451 are tested using the CCIF standard where
two input frequencies near the top end of the input bandwidth
are used. In this case, the second-order terms are usually dis-
tanced in frequency from the original sine waves while the
third-order terms are usually at a frequency close to the input
frequencies. As a result, the second- and third-order terms
are specified separately. The calculation of the intermodulation
distortion is as per the THD specification where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in decibels.
where:
Pf is the power at Frequency f in the ADC output.
Pfs is the power at Frequency fs in the ADC output.
Rev. D | Page 12 of 24
AD7441/AD7451
THEORY OF OPERATION
When the ADC starts a conversion (see Figure 20), SW3 opens
and SW1 and SW2 move to Position B, causing the comparator
to become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribu-
tion DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is rebal-
anced, the conversion is complete. The control logic generates
the ADC output code. The output impedances of the sources
driving the VIN+ and VIN– pins must be matched; otherwise the
two inputs have different settling times, resulting in errors.
CIRCUIT INFORMATION
The AD7441/AD7451 are 10-/12-bit, high speed, low power,
single-supply, successive approximation, analog-to-digital con-
verters (ADCs) with a pseudo differential analog input. These
parts operate with a single 2.7 V to 5.25 V power supply and are
capable of throughput rates up to 1 MSPS when supplied with
an 18 MHz SCLK. The AD7441/AD7451 require an external
reference to be applied to the VREF pin.
The AD7441/AD7451 have a SAR ADC, an on-chip differential
track-and-hold amplifier, and a serial interface housed in either
an 8-lead SOT-23 or an MSOP package. The serial clock input
accesses data from the part and provides the clock source for
the SAR ADC. The AD7441/AD7451 feature a power-down
option for reduced power consumption between conversions.
The power-down feature is implemented across the standard
serial interface, as described in the Modes of Operation section.
CAPACITIVE
DAC
C
B
A
S
S
V
V
IN+
SW1
SW2
CONTROL
LOGIC
SW3
A
B
IN–
C
V
REF
CONVERTER OPERATION
COMPARATOR
CAPACITIVE
DAC
The AD7441/AD7451 are SAR ADCs based around two
capacitive DACs. Figure 19 and Figure 20 show simplified
schematics of the ADC in the acquisition and conversion phase,
respectively. The ADC is comprised of control logic, an SAR,
and two capacitive DACs. In Figure 19 (acquisition phase), SW3
is closed, SW1 and SW2 are in Position A, the comparator is
held in a balanced condition, and the sampling capacitor arrays
acquire the differential signal on the input.
Figure 20. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding for the AD7441/AD7451 is straight (natural)
binary. The designed code transitions occur at successive LSB
values (1 LSB, 2 LSB, and so on). The LSB size of the AD7451
is VREF/4096, and the LSB size of the AD7441 is VREF/1024. The
ideal transfer characteristic of the AD7441/AD7451 is shown in
Figure 21.
CAPACITIVE
DAC
C
B
A
S
1LSB = V
1LSB = V
/4096 (AD7451)
/1024 (AD7441)
REF
REF
V
V
IN+
SW1
SW2
111...111
111...110
CONTROL
LOGIC
SW3
A
B
IN–
C
S
111...000
011...111
V
REF
COMPARATOR
CAPACITIVE
DAC
Figure 19. ADC Acquisition Phase
000...010
000...001
000...000
1LSB
V
– 1LSB
0V
REF
ANALOG INPUT
Figure 21. AD7441/AD7451 Ideal Transfer Characteristic
Rev. D | Page 13 of 24
AD7441/AD7451
2.5V
1.25V
0V
R
TYPICAL CONNECTION DIAGRAM
+1.25V
0V
–1.25V
R
Figure 22 shows a typical connection diagram for the device.
In this setup, the GND pin is connected to the analog ground
plane of the system. The VREF pin is connected to the AD780,
a 2.5 V decoupled reference source. The signal source is connected
to the VIN+ analog input via a unity gain buffer. A dc voltage is
connected to the VIN– pin to provide a pseudo ground for the
V
IN+
V
V
3R
IN+
AD7441/
R
AD7451
IN–
V
REF
0.1µF
VIN+ input. The VDD pin is decoupled to AGND with a 10 μF
EXTERNAL
(2.5V)
V
REF
tantalum capacitor in parallel with a 0.1 μF ceramic capacitor.
The reference pin is decoupled to AGND with a capacitor of at
least 0.1 μF. The conversion result is output in a 16-bit word
with four leading zeros followed by the MSB of the 12-bit or
10-bit result. The 10-bit result of the AD7441 is followed by two
trailing zeros.
Figure 23. Op Amp Configuration to Level Shift a Bipolar Input Signal
ANALOG INPUT STRUCTURE
Figure 24 shows the equivalent circuit of the analog input
structure of the AD7441/AD7451. The four diodes provide
ESD protection for the analog inputs. Care must be taken to
ensure that the analog input signals never exceed the supply
rails by more than 300 mV. This causes these diodes to become
forward-biased and start conducting into the substrate. These
diodes can conduct up to 10 mA without causing irreversible
damage to the part. The C1 capacitors (see Figure 24) are
typically 4 pF and can be attributed primarily to pin capaci-
tance. The resistors are lumped components made up of
the on resistance of the switches. The value of these resistors
is typically about 100 Ω. The C2 capacitors are the ADC
sampling capacitors and have a capacitance of 16 pF typically.
2.7V TO 5.25V
SUPPLY
0.1µF
10µF
SERIAL
INTERFACE
V
V
AD7441/
AD7451
DD
V
REF
p-p
SCLK
IN+
SDATA
CS
µC/µP
V
IN–
DC INPUT
VOLTAGE
GND
V
REF
2.5V
AD780
0.1µF
For ac applications, removing high frequency components from
the analog input signal through the use of an RC low-pass filter
on the relevant analog input pins is recommended. In applica-
tions where harmonic distortion and the signal-to-noise ratio
are critical, it is recommended that the analog input be driven
from a low impedance source. Large source impedances
significantly affect the ac performance of the ADC, which can
necessitate the use of an input buffer amplifier. The choice of
the amplifier is a function of the particular application.
Figure 22. Typical Connection Diagram
ANALOG INPUT
The AD7441/AD7451 have a pseudo differential analog input.
The VIN+ input is coupled to the signal source and must have an
amplitude of VREF p-p to make use of the full dynamic range of
the part. A dc input is applied to the VIN–. The voltage applied to
this input provides an offset from ground or a pseudo ground
for the VIN+ input. Pseudo differential inputs separate the analog
input signal ground from the ADC ground, allowing dc common-
mode voltages to be cancelled.
V
DD
D
D
C2
R1
Because the ADC operates from a single supply, it is necessary
to level shift ground-based bipolar signals to comply with the
input requirements. An op amp (for example, the AD8021) can
be configured to rescale and level shift a ground-based (bipolar)
signal so that it is compatible with the input range of the AD7441/
AD7451 (see Figure 23).
V
IN+
C1
V
DD
D
D
C2
R1
V
IN–
When a conversion takes place, the pseudo ground corresponds
to 0, and the maximum analog input corresponds to 4096 for
the AD7451 and 1024 for the AD7441.
C1
Figure 24. Equivalent Analog Input Circuit;
Conversion Phase—Switches Open;
Track Phase—Switches Closed
Rev. D | Page 14 of 24
AD7441/AD7451
DIGITAL INPUTS
When no amplifier is used to drive the analog input, it is
recommended that the source impedance be limited to low
values. The maximum source impedance depends on the
amount of total harmonic distortion that can be tolerated.
The THD increases as the source impedance increases and
performance degrades.
The digital inputs applied to the AD7441/AD7451 are not limited
by the maximum ratings that limit the analog inputs. Instead,
the digital inputs applied, that is,
and are not restricted by the VDD + 0.3 V limits as on the analog
input. The main advantage of the inputs not being restricted to
the VDD + 0.3 V limit is that power supply sequencing issues are
CS
and SCLK, can go to 7 V
Figure 25 shows a graph of THD vs. analog input signal
frequency for different source impedances.
CS
avoided. If
or SCLK are applied before VDD, there is no risk
of latch-up as there would be on the analog inputs if a signal
greater than 0.3 V were applied prior to VDD
0
.
T
= 25°C
A
V
= 5V
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
DD
REFERENCE
An external source is required to supply the reference to the
AD7441/AD7451. This reference input can range from 100 mV
to VDD. The specified reference is 2.5 V for the power supply
range 2.7 V to 5.25 V. The reference input chosen for an appli-
cation must never be greater than the power supply. Errors in
the reference source result in gain errors in the AD7441/AD7451
transfer function and add to the specified full-scale errors of the
part. A capacitor of at least 0.1 μF must be placed on the VREF
pin. Suitable reference sources for the AD7441/AD7451 include
the AD780 and the ADR421. Figure 27 shows a typical connec-
tion diagram for the VREF pin.
200Ω
100Ω
10Ω
62Ω
100k
INPUT FREQUENCY (Hz)
10k
1M
Figure 25. THD vs. Analog Input Frequency for Various Source Impedances
V
DD
Figure 26 shows a graph of THD vs. analog input frequency for
various supply voltages while sampling at 1 MSPS with an SCLK
of 18 MHz. In this case, the source impedance is 10 Ω.
AD7441/
AD7451*
AD780
OPSEL
V
REF
1
2
3
4
8
7
6
5
NC
NC
NC
V
V
DD
IN
–50
2.5V
TEMP
GND
V
OUT
T
= 25°C
A
0.1µF
10nF
0.1µF
0.1µF
TRIM
NC
–55
–60
–65
–70
–75
–80
–85
–90
NC = NO CONNECT
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 27. Typical VREF Connection Diagram for VDD = 5 V
V
= 2.7V
DD
V
= 3.6V
DD
V
= 4.75V
DD
V
= 5.25V
DD
10
100
INPUT FREQUENCY (kHz)
1000
Figure 26. THD vs. Analog Input Frequency for Various Supply Voltages
Rev. D | Page 15 of 24
AD7441/AD7451
Sixteen serial clock cycles are required to perform a conversion
CS
SERIAL INTERFACE
and to access data from the AD7441/AD7451.
going low
Figure 2 and Figure 3 show detailed timing diagrams for the
serial interface of the AD7451 and the AD7441, respectively.
The serial clock provides the conversion clock and also controls
the transfer of data from the device during conversion.
provides the first leading zero to be read in by the DSP or the
microcontroller. The remaining data is then clocked out on the
subsequent SCLK falling edges, beginning with the second leading
zero. Thus, the first falling clock edge on the serial clock pro-
vides the second leading zero. The final bit in the data transfer
is valid on the 16th falling edge, having been clocked out on the
previous (15th) falling edge. Once the conversion is complete
and the data has been accessed after the 16 clock cycles, it is
important to ensure that, before the next conversion is initiated,
enough time is left to meet the acquisition and quiet-time speci-
fications (see the Timing Example 1 and Timing Example 2
sections). To achieve 1 MSPS with an 18 MHz clock, an 18-clock
burst performs the conversion and leaves enough time before the
next conversion for the acquisition and quiet time.
CS
initiates the conversion process and frames the data transfer.
CS
The falling edge of
puts the track-and-hold into hold mode
and takes the bus out of three-state. The analog input is sampled
and the conversion initiated at this point. The conversion requires
16 SCLK cycles to complete.
Once 13 SCLK falling edges have occurred, the track-and-hold
goes back into track mode on the next SCLK rising edge, as
shown at Point B in Figure 2 and Figure 3. On the 16th SCLK
falling edge, the SDATA line goes back into three-state.
CS
If the rising edge of
occurs before 16 SCLKs have elapsed,
In applications with slower SCLKs, it is possible to read in data
on each SCLK rising edge; that is, the first rising edge of SCLK
the conversion is terminated and the SDATA line goes back into
three-state.
CS
after the
falling edge has the leading zero provided, and the
15th SCLK edge has DB0 provided.
The conversion result from the AD7441/AD7451 is provided on
the SDATA output as a serial data stream. The bits are clocked
out on the falling edge of the SCLK input. The data stream of
the AD7451 consists of four leading zeros followed by 12 bits
of conversion data, provided MSB first. The data stream of the
AD7441 consists of four leading zeros, followed by the 10 bits
of conversion data, followed by two trailing zeros, which is also
provided MSB first. In both cases, the output coding is straight
(natural) binary.
Rev. D | Page 16 of 24
AD7441/AD7451
Timing Example 2
Timing Example 1
Having fSCLK = 5 MHz and a throughput rate of 315 kSPS gives a
cycle time of
Having fSCLK = 18 MHz and a throughput rate of 1 MSPS gives a
cycle time of
1/Throughput = 1/315,000 = 3.174 μs
1/Throughput = 1/1,000,000 = 1 μs
A cycle consists of
A cycle consists of
t2 + 12.5 (1/fSCLK) + tACQUISITION = 3.174 μs
t2 + 12.5 (1/fSCLK) + tACQUISITION = 1 μs
Therefore, if t2 is 10 ns, then
Therefore, if t2 = 10 ns, then
10 ns + 12.5 (1/5 MHz) + tACQUISITION = 3.174 μs
10 ns + 12.5 (1/18 MHz) + tACQUISITION = 1 μs
tACQUISITION = 296 ns
t
ACQUISITION = 664 ns
This 664 ns satisfies the requirement of 290 ns for tACQUISITION
.
This 296 ns satisfies the requirement of 290 ns for tACQUISITION
.
From Figure 28, tACQUISITION comprises
From Figure 28, tACQUISITION comprises
2.5 (1/fSCLK) + t8 = tQUIET
2.5 (1/fSCLK) + t8 = tQUIET
where t8 = 35 ns. This allows a value of 129 ns for tQUIET
satisfying the minimum requirement of 60 ns.
,
where t8 = 35 ns. This allows a value of 122 ns for tQUIET
satisfying the minimum requirement of 60 ns.
,
As in this example and with other slower clock values, the signal
can already be acquired before the conversion is complete, but it
is still necessary to leave 60 ns minimum tQUIET between conver-
sions. In Example 2, the signal is fully acquired at approximately
Point C in Figure 28.
CS
10ns
t2
tCONVERT
t5
B
C
1
2
3
4
5
13
14
t6
15
16
SCLK
t8
tQUIET
12.5(1/fSCLK
)
tACQUISITION
1/THROUGHPUT
Figure 28. Serial Interface Timing Example
Rev. D | Page 17 of 24
AD7441/AD7451
MODES OF OPERATION
POWER-DOWN MODE
The operating mode of the AD7441/AD7451 is selected by
CS
controlling the logic state of the
There are two operating modes: normal mode and power-down
CS
signal during a conversion.
This mode is intended for use in applications where slower
throughput rates are required; either the ADC is powered
down between each conversion or a series of conversions can
be performed at a high throughput rate and the ADC is then
powered down for a relatively long duration between these
bursts of conversions. When the AD7441/AD7451 are in
power-down mode, all analog circuitry is powered down.
For the AD7441/AD7451 to enter power-down mode, the
mode. The point at which
is initiated determines whether the part enters power-down mode.
CS
is pulled high after the conversion
Similarly, if already in power-down,
controls whether the
device returns to normal operation or remains in power-down.
These modes provide flexible power management options that
can optimize the power dissipation/throughput rate ratio for
differing application requirements.
CS
conversion process must be interrupted by bringing
high
anywhere after the second falling edge of SCLK and before
the 10th falling edge of SCLK, as shown in Figure 30.
NORMAL MODE
This mode is intended for fastest throughput rate performance.
The user does not have to worry about any power-up times with
the AD7441/AD7451 remaining fully powered up all the time.
Figure 29 shows the general diagram of the operation of the
AD7441/AD7451 in this mode. The conversion is initiated
CS
Once
part enters power-down, the conversion that was initiated by
CS
has been brought high in this window of SCLKs, the
the falling edge of
three-state. The time from the rising edge of
three-state enabled is never greater than t8 (see the Timing
CS
is terminated, and SDATA goes back into
CS
to SDATA
CS
on the falling edge of
ensure that the part remains fully powered up,
low until at least 10 SCLK falling edges elapse after the falling
CS
(see the Serial Interface section). To
Specifications section). If
is brought high before the second
CS
must remain
SCLK falling edge, the part remains in normal mode and does
not power down. This avoids accidental power-down due to
glitches on the
edge of
CS
.
CS
line.
If
is brought high any time after the 10th SCLK falling edge,
To exit power-down mode and power up the AD7441/AD7451
again, a dummy conversion is performed. On the falling edge
of , the device begins to power up and continues to do so
but before the 16th SCLK falling edge, the part remains pow-
ered up, however the conversion is terminated and SDATA goes
back into three-state. Sixteen serial clock cycles are required to
complete the conversion and access the complete conversion
CS
CS
as long as
is held low until after the falling edge of the 10th
SCLK. The device is fully powered up after 1 μs has elapsed and,
as shown in Figure 31, valid data results from the next
conversion.
CS
result.
can idle high until the next conversion or can idle
low until sometime prior to the next conversion. Once a data
transfer is complete—that is, when SDATA has returned to
three-state—another conversion can be initiated after the
CS
CS
quiet time, tQUIET, elapses again bringing
low.
1
2
10
SCLK
CS
THREE-STATE
SDATA
1
10
16
SCLK
Figure 30. Entering Power-Down Mode
SDATA
4 LEADING ZEROS + CONVERSION RESULT
Figure 29. Normal Mode Operation
Rev. D | Page 18 of 24
AD7441/AD7451
tPOWER-UP
PART BEGINS
TO POWER UP
THIS PART IS FULLY POWERED
UP WITH V FULLY ACQUIRED
IN
CS
SCLK
A
1
10
16
1
10
16
SDATA
INVALID DATA
VALID DATA
Figure 31. Exiting Power-Down Mode
CS
For example, when a 5 MHz SCLK frequency is applied to the
ADC, the cycle time is 3.2 μs (that is, 1/(5 MHz) × 16). In one
dummy cycle, 3.2 μs, the part is powered up, and VIN is acquired
fully. However, after 1 μs with a five MHz SCLK, only five SCLK
cycles elapse. At this stage, the ADC is fully powered up and the
If
AD7441/AD7451 again go back into power-down. This avoids
CS
is brought high before the 10th falling edge of SCLK, the
accidental power-up due to glitches on the
CS
line or an inad-
is low. So although
CS
vertent burst of eight SCLK cycles while
the device may begin to power up on the falling edge of , it
CS
signal acquired. Therefore, in this case, the
can be brought
CS
again powers down on the rising edge of
before the 10th SCLK falling edge.
as long as it occurs
high after the 10th SCLK falling edge and brought low again
after a time, tQUIET, to initiate the conversion.
Power-Up Time
When power supplies are first applied to the AD7441/AD7451,
the ADC can power up either in power-down mode or normal
mode. For this reason, it is best to allow a dummy cycle to elapse
to ensure that the part is fully powered up before attempting a
valid conversion. Likewise, if the user wants the part to power
up in power-down mode, then the dummy cycle can be used to
ensure the device is in power-down mode by executing a cycle
such as that shown in Figure 30. Once supplies are applied to
the AD7441/AD7451, the power-up time is the same as that
when powering up from power-down mode. It takes approxi-
mately 1 μs to power up fully in normal mode. It is not necessary
to wait 1 μs before executing a dummy cycle to ensure the
desired mode of operation. Instead, the dummy cycle can
occur directly after power is supplied to the ADC. If the first
valid conversion is then performed directly after the dummy
conversion, care must be taken to ensure that adequate
acquisition time has been allowed.
The power-up time of the AD7441/AD7451 is typically 1 μs,
which means that with any frequency of SCLK up to 18 MHz,
one dummy cycle is always sufficient to allow the device to
power up. Once the dummy cycle is complete, the ADC is fully
powered up and the input signal is acquired properly. The quiet
time, tQUIET, must still be allowed—from the point at which the
bus goes back into three-state after the dummy conversion to
CS
the next falling edge of
.
When running at the maximum throughput rate of 1 MSPS,
the AD7441/AD7451 power up and acquire a signal within
0.5 LSB in one dummy cycle, that is, 1 μs. When powering up
from the power-down mode with a dummy cycle, as in Figure 31,
the track-and-hold, which was in hold mode while the part was
powered down, returns to track mode after the first SCLK edge
CS
the part receives after the falling edge of . This is shown as
Point A in Figure 31.
As mentioned earlier, when powering up from the power-down
mode, the part returns to track mode upon the first SCLK edge
Although at any SCLK frequency one dummy cycle is sufficient
to power up the device and acquire VIN, it does not necessarily
mean that a full dummy cycle of 16 SCLKs must always elapse
to power up the device and acquire VIN fully; 1 μs is sufficient to
power up the device and acquire the input signal.
CS
applied after the falling edge of . However, when the ADC
powers up initially after supplies are applied, the track-and-
hold is already in track mode. This means (assuming one has
the facility to monitor the ADC supply current) that if the ADC
powers up in the desired mode of operation, a dummy cycle is
not required to change mode. Thus, a dummy cycle is also not
required to place the track-and-hold into track.
Rev. D | Page 19 of 24
AD7441/AD7451
For optimum power performance in throughput rates above
320 kSPS, it is recommended that the serial clock frequency be
reduced.
POWER VS. THROUGHPUT RATE
By using the power-down mode on the device when not con-
verting, the average power consumption of the ADC decreases
at lower throughput rates. Figure 32 shows how, as the through-
put rate is reduced, the device remains in its power-down state
longer and the average power consumption reduces accordingly.
For example, if the AD7441/AD7451 are operated in continuous
sampling mode with a throughput rate of 100 kSPS and an SCLK
of 18 MHz, and the device is placed in the power-down mode
between conversions, then the power consumption during
normal operation equals 9.25 mW maximum (for VDD = 5 V).
MICROPROCESSOR AND DSP INTERFACING
The serial interface on the AD7441/AD7451 allows the part to
be connected directly to a range of different microprocessors.
This section explains how to interface the AD7441/AD7451
with some of the more common microcontroller and DSP serial
interface protocols.
AD7441/AD7451 to ADSP-21xx
The ADSP-21xx family of DSPs is interfaced directly to the
AD7441/AD7451 without any glue logic required. The SPORT
control register is set up as follows:
If the power-up time is one dummy cycle (1 μs) and the remain-
ing conversion time is another cycle (1 μs), then the AD7441/
AD7451 can be said to dissipate 9.25 mW for 2 μs during each
conversion cycle. (This power consumption figure assumes a
very short time to enter power-down mode. This power figure
increases as the burst of clocks used to enter power-down mode
is increased). The AD7441/AD7451 consume just 5 μW for the
remaining 8 μs.
TFSW = RFSW = 1
INVRFS = INVTFS = 1
DTYPE = 00
Alternate framing
Active low frame signal
Right justify data
SLEN = 1111
ISCLK = 1
16-bit data-words
Internal serial clock
Frame every word
Calculate the power numbers in Figure 32 as follows:
If the throughput rate = 100 kSPS, then the cycle time = 10 μs,
and the average power dissipated during each cycle is
TFSR = RFSR = 1
IRFS = 0
(2/10) × 9.25 mW = 1.85 mW
For the same scenario, if VDD = 3 V, the power dissipation
during normal operation is 4 mW maximum.
ITFS = 1
To implement power-down mode, SLEN is set to 1001 to issue
an 8-bit SCLK burst.
The AD7441/AD7451 can now be said to dissipate 4 mW for
2 μs during each conversion cycle.
The connection diagram is shown in Figure 33. ADSP-21xx has
the TFS and RFS of the SPORT tied together, with TFS set as an
output and RFS set as an input. The DSP operates in alternate
framing mode, and the SPORT control register is set up as
described. The frame synchronization signal generated on the
The average power dissipated during each cycle with a
throughput rate of 100 kSPS is, therefore,
(2/10) × 4 mW = 0.8 mW
100
CS
TFS is tied to , and, as with all signal processing applications,
equidistant sampling is necessary. However, in this example,
the timer interrupt is used to control the sampling rate of the
ADC, and, under certain conditions, equidistant sampling
cannot be achieved.
V
= 5V
DD
10
1
V
= 3V
DD
ADSP-21xx*
AD7441/
AD7451*
0.1
0.01
SCLK
SDATA
CS
SCLK
DR
RFS
TFS
0
50
100
150
200
250
300
350
THROUGHPUT (kSPS)
Figure 32. Power vs. Throughput Rate for Power-Down Mode
*ADDITIONAL PINS REMOVED FOR CLARITY.
Figure 33. Interfacing to the ADSP-21xx
Rev. D | Page 20 of 24
AD7441/AD7451
AD7441/AD7451 to DSP56xxx
The timer registers, for example, are loaded with a value that
provides an interrupt at the required sample interval. When an
interrupt is received, a value is transmitted with TFS/DT (ADC
control word). The TFS is used to control the RFS and, there-
fore, the reading of data. The frequency of the serial clock is set
in the SCLKDIV register. When the instruction to transmit with
TFS is given, that is, AX0 = TX0, the state of the SCLK is checked.
The DSP waits until the SCLK has gone high, low, and high
before starting transmission. If the timer and SCLK values are
chosen such that the instruction to transmit occurs on or near
the rising edge of SCLK, then the data can either be transmitted
or wait until the next clock edge.
The connection diagram in Figure 35 shows how the AD7441/
AD7451 can be connected to the SSI (synchronous serial interface)
of the DSP56xxx family of DSPs from Motorola. The SSI is
operated in synchronous mode (SYN bit in CRB = 1) with
internally generated 1-bit clock period frame sync for both Tx
and Rx (Bit FSL1 = 1 and Bit FSL0 = 0 in CRB). Set the word
length to 16 by setting Bit WL1 = 1 and Bit WL0 = 0 in CRA. To
implement the power-down mode on the AD7441/AD7451, the
word length can be changed to eight bits by setting B it WL1 = 0
and Bit WL0 = 0 in CRA. Note that for signal processing applica-
tions, the frame synchronization signal from the DSP56xxx must
provide equidistant sampling.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value of 3,
an SCLK of 2 MHz is obtained and eight master clock periods
elapse for every one SCLK period. If the timer registers are
loaded with the value 803, 100.5 SCLKs occur between inter-
rupts and subsequently between transmit instructions. This
situation results in nonequidistant sampling, because the
transmit instruction occurs on an SCLK edge. If the number
of SCLKs between interrupts is a whole integer figure of N,
equidistant sampling is implemented by the DSP.
AD7441/
AD7451*
DSP56xxx*
SCLK
SCLK
SDATA
CS
SRD
SR2
*ADDITIONAL PINS REMOVED FOR CLARITY.
Figure 35. Interfacing to the DSP56xxx
AD7441/AD7451 to TMS320C5x/C54x
The serial interface on the TMS320C5x/C54x uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices such as the
CS
AD7441/AD7451. The
input allows easy interfacing between
the TMS320C5x/C54x and the AD7441/AD7451 without any
glue logic required. The serial port of the TMS320C5x/C54x is
set up to operate in burst mode with internal CLKx (Tx serial
clock) and FSx (Tx frame sync). The serial port control register
(SPC) must have the following setup: FO = 0, FSM = 1, MCM = 1,
and TXM = 1. The format bit, FO, can be set to 1 to set the word
length to eight bits in order to implement the power-down
mode on the AD7441/AD7451. The connection diagram is
shown in Figure 34. Note that for signal processing applications,
the frame synchronization signal from the TMS320C5x/ C54x
must provide equidistant sampling.
TMS320C5x/
AD7441/
C54x*
AD7451*
SCLK
CLKx
CLKR
DR
SDATA
CS
FSx
FSR
*ADDITIONAL PINS REMOVED FOR CLARITY.
Figure 34. Interfacing to the TMS320C5x/C54x
Rev. D | Page 21 of 24
AD7441/AD7451
In this technique, the component side of the board is dedicated
to ground planes while signals are placed on the solder side.
Good decoupling is also important. All analog supplies must
be decoupled with 10 μF tantalum capacitors in parallel with
0.1 μF capacitors to GND. To achieve the best from these
decoupling components, they must be placed as close as
possible to the device.
GROUNDING AND LAYOUT HINTS
The printed circuit board that houses the AD7441/AD7451
must be designed so that the analog and digital sections are
separated and confined to certain areas of the board. This
facilitates the use of ground planes that can be easily separated.
A minimum etch technique is generally best for ground planes,
as it gives the best shielding. Digital and analog ground planes
must be joined in only one place: a star ground point estab-
lished as close to the GND pin on the AD7441/AD7451 as
possible.
EVALUATING PERFORMANCE
The evaluation board package includes a fully assembled and
tested evaluation board, documentation, and software for con-
trolling the board from a PC via the evaluation board controller.
The evaluation board controller can be used in conjunction with
the AD7441 and the AD7451 evaluation boards, as well as with
many other Analog Devices, Inc. evaluation boards ending with
the CB designator, to demonstrate and evaluate the ac and dc
performance of the AD7441 and the AD7451.
Avoid running digital lines under the device, as this couples
noise onto the die. The analog ground plane must be allowed to
run under the AD7441/AD7451 to avoid noise coupling. The
power supply lines to the AD7441/AD7451 must use as large
a trace as possible to provide low impedance paths and reduce
the effects of glitches on the power supply line.
The software allows the user to perform ac (fast Fourier transform)
and dc (histogram of codes) tests on the AD7441/AD7451. See
the AD7441/AD7451 application note that accompanies the
evaluation kit for more information.
Fast switching signals like clocks must be shielded with digital
grounds to avoid radiating noise to other sections of the board,
and clock signals must never run near the analog inputs. Avoid
crossover of digital and analog signals. Traces on opposite sides
of the board must run at right angles to each other. This reduces
the effects of feedthrough on the board. A microstrip technique is
by far the best but is not always possible with a double-sided board.
Rev. D | Page 22 of 24
AD7441/AD7451
OUTLINE DIMENSIONS
3.00
2.90
2.80
8
1
7
6
3
5
4
3.00
2.80
2.60
1.70
1.60
1.50
2
PIN 1
INDICATOR
0.65 BSC
1.95
BSC
1.30
1.15
0.90
0.22 MAX
0.08 MIN
1.45 MAX
0.95 MIN
0.60
0.45
0.30
0.15 MAX
0.05 MIN
8°
4°
0°
SEATING
PLANE
0.60
BSC
0.38 MAX
0.22 MIN
COMPLIANT TO JEDEC STANDARDS MO-178-BA
Figure 36. 8-Lead Small Outline Transistor Package [SOT-23]
(RJ-8)
Dimensions shown in millimeters
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.15
0.05
0.23
0.09
6°
0°
0.40
0.25
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 37. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Rev. D | Page 23 of 24
AD7441/AD7451
ORDERING GUIDE
Model1
AD7451ARTZ-REEL7
AD7451ARMZ
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Linearity Error (LSB)2
Package Description
8-Lead SOT-23
8-Lead MSOP
Package Option
Branding
C3T
C3T
1.5
1.5
1
RJ-8
RM-8
RM-8
RJ-8
RJ-8
RM-8
AD7451BRMZ
8-Lead MSOP
C3U
AD7441BRTZ-R2
AD7441BRTZ-REEL7
AD7441BRMZ
0.5
0.5
0.5
8-Lead SOT-23
8-Lead SOT-23
8-Lead MSOP
C4M
C4M
C4M
EVAL-AD7451CBZ3
EVAL-CONTROL BRD24
Evaluation Board
Controller Board
1 Z = RoHS Compliant Part.
2 Linearity error here refers to integral nonlinearity error.
3 This can be used as a standalone evaluation board or in conjunction with the evaluation board controller for evaluation/demonstration purposes.
4 The evaluation board controller is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
To order a complete evaluation kit, you must order the ADC evaluation board (EVAL-AD7451CB or EVAL-AD7441CB), the EVAL-CONTROL BRD2, and a 12 V ac
transformer. See the AD7451/AD7441 application note that accompanies the evaluation kit for more information.
©2003–2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03153-0-3/10(D)
Rev. D | Page 24 of 24
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