AD7453BRM [ADI]
IC 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8, MSOP-8, Analog to Digital Converter;
| 型号： | AD7453BRM |
| 厂家： | 
ADI |
| 描述： | IC 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8, MSOP-8, Analog to Digital Converter |
| 文件： | 总20页 (文件大小：254K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Pseudo Differential, 555 kSPS,
12-Bit ADC in an 8-Lead SOT-23
AD7453
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Specified for VDD of 2.7 V to 5.25 V
Low Power at Max Throughput Rate:
3.3 mW Max at 555 kSPS with VDD = 3 V
7.25 mW Max at 555 kSPS with VDD = 5 V
Pseudo Differential Analog Input
Wide Input Bandwidth:
70 dB SINAD at 100 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
V
DD
V
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
IN+
T/H
V
IN–
V
REF
High Speed Serial Interface—SPI®/QSPI™/
MICROWIRE™/DSP Compatible
Power-Down Mode: 1 A Max
8-Lead SOT-23 Package
SCLK
SDATA
CS
AD7453
CONTROL LOGIC
APPLICATIONS
Transducer Interface
Battery-Powered Systems
Data Acquisition Systems
Portable Instrumentation
Motor Control
GND
Communications
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7453 is a 12-bit, high speed, low power, successive
approximation (SAR) analog-to-digital converter that features a
pseudo differential analog input. This part operates from a
single 2.7 V to 5.25 V power supply and features throughput
rates up to 555 kSPS.
1. Operation with 2.7 V to 5.25 V Power Supplies.
2. High Throughput with Low Power Consumption.
With a 3 V supply, the AD7453 offers 3.3 mW max power
consumption for a 555 kSPS throughput rate.
3. Pseudo Differential Analog Input.
The part contains a low noise, wide bandwidth, differential
track-and-hold amplifier (T/H) that can handle input frequen-
cies in excess of 1 MHz. The reference voltage for the AD7453
is applied externally to the VREF pin and can range from
100 mV to 3.5 V, depending on the power supply and what
suits the application.
4. Flexible Power/Serial Clock Speed Management.
The conversion rate is determined by the serial clock, allow-
ing the power to be reduced as the conversion time is reduced
through the serial clock speed increase. This part also features
a shutdown mode to maximize power efficiency at lower
throughput rates.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the device to interface
with microprocessors or DSPs. The input signals are sampled
on the falling edge of CS; the conversion is also initiated at
this point.
5. Variable Voltage Reference Input.
6. No Pipeline Delay.
7. Accurate control of the sampling instant via a CS input and
once-off conversion control.
The SAR architecture of this part ensures that there are no
pipeline delays.
8. ENOB > 10-bits Typically with 500 mV Reference.
The AD7453 uses advanced design techniques to achieve very
low power dissipation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
(VDD = 2.7 V to 5.25 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.5 V, FIN = 100 kHz,
AD7453–SPECIFICATIONS TA = TMIN to TMAX, unless otherwise noted.)
Parameter
Test Conditions/Comments
A Version1
B Version1
Unit
DYNAMIC PERFORMANCE
Signal to Noise Ratio (SNR)2
Signal to (Noise + Distortion)
(SINAD)2
f
IN = 100 kHz
VDD = 2.7 V to 5.25 V
70
70
dB min
VDD = 2.7 V to 3.6 V
VDD = 4.75 V to 5.25 V
69
70
–73
–75
–73
–75
69
70
–73
–75
–73
–75
dB min
dB min
dB max
dB max
dB max
dB max
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise2
VDD = 2.7 V to 3.6 V; –78 dB typ
VDD = 4.75 V to 5.25 V; –80 dB typ
VDD = 2.7 V to 3.6 V; –80 dB typ
VDD = 4.75 V to 5.25 V; –82 dB typ
fa = 90 kHz; fb = 110 kHz
Intermodulation Distortion (IMD)2
Second-Order Terms
Third-Order Terms
–80
–80
5
50
20
–80
–80
5
50
20
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
Aperture Delay2
Aperture Jitter2
Full-Power Bandwidth2, 3
@ –3 dB
@ –0.1 dB
2.5
2.5
DC ACCURACY
Resolution
12
12
±1
±0.95
±3.5
±3
Bits
Integral Nonlinearity (INL)2
Differential Nonlinearity (DNL)2
Offset Error2
±1.5
±0.95
±3.5
±3
LSB max
LSB max
LSB max
LSB max
Guaranteed no missed codes to 12 bits
Gain Error2
ANALOG INPUT
Full-Scale Input Span
Absolute Input Voltage
VIN+
VIN+ – VIN–
VREF
VREF
V
VREF
VREF
V
V
V
4
VIN–
VDD = 2.7 V to 3.6 V
VDD = 4.75 V to 5.25 V
–0.1 to +0.4
–0.1 to +1.5
±1
–0.1 to +0.4
–0.1 to +1.5
±1
DC Leakage Current
Input Capacitance
mA max
pF typ
When in track/hold
30/10
30/10
REFERENCE INPUT
V
REF Input Voltage
±1% tolerance for specified performance
2.55
±1
10/30
2.55
±1
10/30
V
DC Leakage Current
VREF Input Capacitance
mA max
pF typ
When in track/hold
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
±1
10
2.4
0.8
±1
10
V min
V max
mA max
pF max
Typically 10 nA, VIN = 0 V or VDD
6
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
VDD = 4.75 V to 5.25 V,
ISOURCE = 200 mA
2.8
2.8
V min
V
DD = 2.7 V to 3.6 V,
ISOURCE = 200 mA
ISINK = 200 mA
2.4
0.4
±1
10
2.4
0.4
±1
10
V min
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance6
Output Coding
V max
mA max
pF max
Straight (natural) binary
CONVERSION RATE
Conversion Time
1.6 ms with a 10 MHz SCLK
Sine wave input
Full-scale step input
16
16
SCLK cycles
ns max
ns max
Track-and-Hold Acquisition Time2
250
290
555
250
290
555
Throughput Rate
kSPS max
–2–
REV. 0
AD7453
Unit
Parameter
Test Conditions/Comments
A Version1
B Version1
POWER REQUIREMENTS
VDD
IDD
2.7/5.25
2.7/5.25
V min/max
7, 8
Normal Mode (Static)
Normal Mode (Operational)
SCLK on or off
0.5
1.5
1.2
1
0.5
1.5
1.2
1
mA typ
mA max
mA max
mA max
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
SCLK on or off
Full Power-Down Mode
Power Dissipation
Normal Mode (Operational)
VDD = 5 V; 1.55 mW typ for 100 kSPS7
VDD = 3 V; 0.64 mW typ for 100 kSPS7
VDD = 5 V; SCLK on or off
7.25
3.3
5
7.25
3.3
5
mW max
mW max
mW max
mW max
Full Power-Down Mode
VDD = 3 V; SCLK on or off
3
3
NOTES
1Temperature ranges as follows: A, B versions: –40∞C to +85∞C.
2See Terminology section.
3Analog inputs with slew rates exceeding 27 V/s (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by
the converter.
4A small dc input is applied to VIN– to provide a pseudo ground for VIN+
.
5The AD7453 is functional with a reference input in the range 100 mV to 3.5 V.
6Sample tested @ 25∞C to ensure compliance.
7See Power Versus Throughput Rate section.
8Measured with a midscale dc input.
Specifications subject to change without notice.
REV. 0
–3–
AD7453
(VDD = 2.7 V to 5.25 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.5 V, TA = TMIN to TMAX
unless otherwise noted.)
,
TIMING SPECIFICATIONS1, 2
Parameter
Limit at TMIN, TMAX
Unit
Description
3
fSCLK
10
kHz min
10
MHz max
tCONVERT
tQUIET
16 ¥ tSCLK
1.6
60
tSCLK = 1/fSCLK
ms max
ns min
Minimum Quiet Time between the End of a Serial Read and the Next Falling
Edge of CS
t1
10
10
20
40
0.4 tSCLK
0.4 tSCLK
10
10
35
1
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
ms max
Minimum CS Pulse Width
t24
t34
t4
t5
t6
CS Falling Edge to SCLK Falling Edge Setup Time
Delay from CS Falling Edge Until SDATA Three-State Disabled
Data Access Time After SCLK Falling Edge
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Edge to Data Valid Hold Time
SCLK Falling Edge to SDATA Three-State Enabled
SCLK Falling Edge to SDATA Three-State Enabled
Power-Up Time from Full Power-Down
t75
t8
6
tPOWER-UP
NOTES
1Sample tested at 25∞C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2See Figure 1 and the Serial Interface section.
3Mark/Space ratio for the SCLK input is 40/60 to 60/40.
4Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with V DD = 5 V and time for an output to cross
0.4 V or 2.0 V for VDD = 3 V.
5t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
6See Power-Up Time section.
Specifications subject to change without notice.
t1
CS
tCONVERT
t2
t3
B
t5
1
2
3
4
5
13
14
t6
15
16
SCLK
t8
t7
t4
tQUIET
THREE-STATE
0
0
0
0
DB11
DB10
DB2
DB1
DB0
SDATA
4 LEADING ZEROS
Figure 1. AD7453 Serial Interface Timing Diagram
–4–
REV. 0
AD7453
ABSOLUTE MAXIMUM RATINGS1
(TA = 25∞C, unless otherwise noted.)
I
OL
1.6mA
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VIN+ to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
TO
OUTPUT
PIN
1.6V
C
VIN– to GND . . . . . . . . . . . . . . . . . . .
–0.3 V to VDD + 0.3 V
L
25pF
Digital Input Voltage to GND . . . . . . . . . . . . . –0.3 V to +7 V
Digital Output Voltage to GND . . . . . . –0.3 V to VDD + 0.3 V
VREF to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . . . ±10 mA
Operating Temperature Range
Commercial (A, B Version) . . . . . . . . . . . . . –40∞C to +85∞C
Storage Temperature Range . . . . . . . . . . . . . –65∞C to +150∞C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C
I
OH
200A
Figure 2. Load Circuit for Digital Output Timing
Specifications
JA Thermal Impedance . . . . . . . . . . . . . 211.5∞C/W (SOT-23)
JC Thermal Impedance . . . . . . . . . . . . . 91.99∞C/W (SOT-23)
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . . 215∞C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C
ESD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
ORDERING GUIDE
Temperature
Range
Linearity
Package
Description
Package
Option
Model
Error (LSB)1
Branding
AD7453ART-REEL7
AD7453BRT-R2
AD7453BRT-REEL7
EVAL-AD7453CB2
EVAL-CONTROL BRD23
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
±1.5
±1
±1
8-Lead SOT-23
8-Lead SOT-23
8-Lead SOT-23
Evaluation Board
Controller Board
RT-8
RT-8
RT-8
C0C
C09
C09
NOTES
1Linearity error here refers to integral nonlinearity error.
2This can be used as a standalone evaluation board or in conjunction with the evaluation board controller for evaluation/demonstration purposes.
3The evaluation board controller is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designa-
tors. To order a complete Evaluation Kit, you will need to order the ADC evaluation board, i.e., EVAL-AD7453CB, the EVAL-CONTROL BRD2, and a 12 V ac
transformer. See the AD7453 application note for more information.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7453 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0
–5–
AD7453
PIN CONFIGURATION
8-Lead SOT-23
V
1
2
3
4
8
7
6
5
V
REF
DD
AD7453
TOP VIEW
(Not to Scale)
SCLK
SDATA
CS
V
IN+
V
IN–
GND
PIN FUNCTION DESCRIPTIONS
Mnemonic
Function
VREF
Reference Input for the AD7453. An external reference in the range 100 mV to 3.5 V must be applied to this input.
The specified reference input is 2.5 V. This pin should be decoupled to GND with a capacitor of at least 0.1 mF.
VIN+
VIN–
Noninverting Analog Input.
Inverting Input. This pin sets the ground reference point for the VIN+ input. Connect to ground or to a dc offset to
provide a pseudo ground.
GND
CS
Analog Ground. Ground reference point for all circuitry on the AD7453. All analog input signals and any external
reference signal should be referred to this GND voltage.
Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7453
and framing the serial data transfer.
SDATA
Serial Data. Logic output. The conversion result from the AD7453 is provided on this output as a serial data stream.
The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7453 consists of four
leading zeros followed by the 12 bits of conversion data that are provided MSB first. The output coding is straight
(natural) binary.
SCLK
VDD
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also
used as the clock source for the conversion process.
Power Supply Input. VDD is 2.7 V to 5.25 V. This supply should be decoupled to GND with a 0.1 mF capacitor
and a 10 mF tantalum capacitor.
–6–
REV. 0
AD7453
TERMINOLOGY
Signal to (Noise + Distortion) Ratio
specified separately. The calculation of the intermodulation
distortion is as per the THD specification where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the sum of the fundamentals expressed in dB.
This is the measured ratio of signal to (noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitiza-
tion process; the more levels, the smaller the quantization noise.
The theoretical signal to (noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by
Aperture Delay
This is the amount of time from the leading edge of the sampling
clock until the ADC actually takes the sample.
Aperture Jitter
This is the sample to sample variation in the effective point in
time at which the actual sample is taken.
Signal to Noise + Distortion = 6.02 N + 1.76 dB
(
)
(
)
Full Power Bandwidth
The full power bandwidth of an ADC is that input frequency at
which the amplitude of the reconstructed fundamental is reduced
by 0.1 dB or 3 dB for a full scale input.
Thus, for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of har-
monics to the fundamental. For the AD7453, it is defined as
Integral Nonlinearity (INL)
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function.
2
2
2
2
2
V2 +V3 +V4 +V5 +V6
THD dB = 20log
(
)
Differential Nonlinearity (DNL)
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second to the sixth
harmonics.
Offset Error
This is the deviation of the first code transition (000...000 to
000...001) from the ideal (i.e., AGND + 1 LSB)
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.
Gain Error
This is the deviation of the last code transition (111...110 to
111...111) from the ideal (i.e., VREF – 1 LSB), after the Offset
Error has been adjusted out.
Track-and-Hold Acquisition Time
The track-and-hold acquisition time is the minimum time
required for the track and hold amplifier to remain in track
mode for its output to reach and settle to within 0.5 LSB of
the applied input signal.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n are equal to zero. For
example, the second-order terms include (fa + fb) and (fa – fb),
while the third-order terms include (2fa + fb), (2fa – fb), (fa + 2fb)
and (fa – 2fb).
Power Supply Rejection Ratio (PSRR)
The power supply rejection ratio is defined as the ratio of the
power in the ADC output at full-scale frequency, f, to the power
of a 100 mV p-p sine wave applied to the ADC VDD supply of
frequency fs. The frequency of this input varies from 1 kHz
to 1 MHz.
The AD7453 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second order terms are usually distanced
in frequency from the original sine waves while the third
order terms are usually at a frequency close to the input fre-
quencies. As a result, the second and third-order terms are
PSRR dB = 10log Pf/Pfs
Pf is the power at frequency f in the ADC output; Pfs is the
power at frequency fs in the ADC output.
(
)
(
)
REV. 0
–7–
AD7453–Typical Performance Characteristics
(Default Conditions: TA = 25؇C, fS = 555 kSPS, fSCLK = 10 MHz, VDD = 2.7 V to 5.25 V, VREF = 2.5 V, unless otherwise noted.)
75
1.0
V
= 5.25V
DD
0.8
0.6
70
V
= 4.75V
DD
0.4
0.2
V
= 3.6V
DD
65
60
55
V
= 2.7V
DD
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
CODE
3072
4096
10
100
277
FREQUENCY (kHz)
TPC 4. Typical DNL For the AD7453 for VDD = 5 V
TPC 1. SINAD vs. Analog Input Frequency for
Various Supply Voltages
1.0
0
100mV p-p SINEWAVE ON V
DD
0.8
0.6
NO DECOUPLING ON V
DD
–20
–40
0.4
0.2
0
–0.2
–0.4
–60
V
= 3V
DD
V
= 5V
DD
–100
–120
–140
–0.6
–0.8
–1.0
0
1024
2048
CODE
3072
4096
0
100 200 300 400 500 600 700 800 900 1000
SUPPLY RIPPLE FREQUENCY (kHz)
TPC 5. Typical INL For the AD7453 for VDD = 5 V
TPC 2. PSRR vs. Supply Ripple Frequency without
Supply Decoupling
10000
9000
0
9949
CODES
8192 POINT FFT
f
f
= 555kSPS
= 100kHz
SAMPLE
IN
–20
–40
8000
7000
6000
5000
4000
3000
2000
1000
SINAD = 71dB
THD = –82dB
SFDR = –83dB
–60
–80
–100
–120
–140
27 CODES
2047 2048
24 CODES
2049 2050
0
2046
2051
0
100
200
277
CODES
FREQUENCY (kHz)
TPC 6. Histogram of 10,000 Conversions of a DC Input
TPC 3. Dynamic Performance for VDD = 5 V
–8–
REV. 0
AD7453
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
12
11
10
9
V
= 3V
DD
V
= 5V
DD
POSITIVE DNL
NEGATIVE DNL
8
7
–0.5
–1.0
6
0
0.5
1.0
1.5
2.0
(V)
2.5
3.0
3.5
0
0.5
1.0
1.5
2.0
(V)
2.5
3.0
3.5
V
V
REF
REF
TPC 7. Change in DNL vs. VREF for VDD = 5 V
TPC 9. ENOB vs. VREF for VDD = 5 V
5
4
3
2
1
0
POSITIVE INL
NEGATIVE INL
–1
–2
0
0.5
1.0
1.5
2.0
(V)
2.5
3.0
3.5
V
REF
TPC 8. Change in INL vs. VREF for VDD = 5 V
REV. 0
–9–
AD7453
CIRCUIT INFORMATION
ADC TRANSFER FUNCTION
The AD7453 is a 12-bit, low power, single supply, successive
approximation analog-to-digital converter (ADC) with a pseudo
differential analog input. It operates with a single 2.7 V to
5.25 V power supply and is capable of throughput rates up to
555 kSPS when supplied with a 10 MHz SCLK. It requires an
external reference to be applied to the VREF pin.
The output coding for the AD7453 is straight (natural) binary.
The designed code transitions occur at successive LSB values
(i.e., 1 LSB, 2 LSB, and so on). The LSB size is VREF/4096.
The ideal transfer characteristic of the AD7453 is shown in
Figure 5.
1LSB = V
/4096
REF
The AD7453 has an on-chip differential track-and-hold amplifier,
a successive approximation (SAR) ADC, and a serial interface,
housed in an 8-lead SOT-23 package. The serial clock input
accesses data from the part and provides the clock source for
the successive approximation ADC. The AD7453 features a
power-down option for reduced power consumption between
conversions. The power-down feature is implemented across
the standard serial interface, as described in the Modes of
Operation section.
111...11
111...10
111...00
011...11
000...10
000...01
000...00
1LSB
V
– 1LSB
0V
REF
ANALOG INPUT
CONVERTER OPERATION
Figure 5. Ideal Transfer Characteristic
TYPICAL CONNECTION DIAGRAM
The AD7453 is a successive approximation ADC based around
two capacitive DACs. Figures 3 and 4 show simplified schematics
of the ADC in the acquisition and conversion phase, respectively.
The ADC is comprised of control logic, an SAR, and two capaci-
tive DACs. In Figure 3 (acquisition phase), SW3 is closed and
SW1 and SW2 are in Position A, the comparator is held in a
balanced condition, and the sampling capacitor arrays acquire
the differential signal on the input.
Figure 6 shows a typical connection diagram for the AD7453.
In this setup the GND pin is connected to the analog ground
plane of the system. The VREF pin is connected to the AD780, a
2.5 V decoupled reference source. The signal source, is con-
nected to the VIN+ analog input via a unity gain buffer. A dc
voltage is connected to the VIN– pin to provide a pseudo ground
for the VIN+ input. The VDD pin should be decoupled to AGND
with a 1 mF tantalum capacitor in parallel with a 0.1 mF ceramic
capacitor. The reference pin should be decoupled to AGND
with a capacitor of at least 0.1 mF. The conversion result is
output in a 16-bit word with four leading zeros followed by the
MSB of the 12-bit result.
CAPACITIVE
DAC
C
C
B
S
S
V
IN+
A
SW1
SW2
CONTROL
LOGIC
SW3
A
B
V
IN–
COMPARATOR
V
REF
CAPACITIVE
DAC
+2.7V TO +5.25V
SUPPLY
10F
0.1F
Figure 3. ADC Acquisition Phase
SERIAL
INTERFACE
When the ADC starts a conversion (Figure 4), SW3 will open
and SW1 and SW2 will move to Position B, causing the com-
parator to become unbalanced. Both inputs are disconnected
once the conversion begins. The control logic and the charge
redistribution DACs are used to add and subtract fixed amounts
of charge from the sampling capacitor arrays to bring the com-
parator back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC’s output code. The output impedances of
the sources driving the VIN+ and the VIN– pins must be matched;
otherwise the two inputs will have different settling times, resulting
in errors.
V
DD
AD7453
V
REF
P-TO-P
SCLK
V
IN+
C/P
SDATA
CS
V
IN–
DC INPUT
VOLTAGE
GND
V
REF
2.5V
AD780
0.1F
Figure 6. Typical Connection Diagram
CAPACITIVE
DAC
C
C
B
S
V
IN+
A
A
B
SW1
SW2
CONTROL
LOGIC
SW3
V
IN–
S
COMPARATOR
V
REF
CAPACITIVE
DAC
Figure 4. ADC Conversion Phase
–10–
REV. 0
AD7453
THE ANALOG INPUT
tions where harmonic distortion and the signal-to-noise ratio are
critical, the analog input should be driven from a low imped-
ance source. Large source impedances will significantly affect
the ac performance of the ADC, which may necessitate the use
of an input buffer amplifier. The choice of the op amp will be a
function of the particular application.
The AD7453 has a pseudo differential analog input. The VIN+
input is coupled to the signal source and must have an ampli-
tude of VREF p-p to make use of the full dynamic range of the
part. A dc input is applied to the VIN–. The voltage applied to
this input provides an offset from ground or a pseudo ground
for the VIN+ input. The main benefit of pseudo differential inputs
is that they separate the analog input signal ground from the
ADC’s ground, allowing dc common-mode voltages to be
cancelled.
V
DD
D
D
C2
R1
Because the ADC operates from a single supply, it is necessary
to level shift ground based bipolar signals to comply with the
input requirements. An op amp (for example, the AD8021) can
be configured to rescale and level shift a ground based (bipolar)
signal so that it is compatible with the input range of the AD7453.
See Figure 7.
V
IN+
C1
V
DD
When a conversion takes place, the pseudo ground corresponds
to 0 and the maximum analog input corresponds to 4096.
D
D
C2
R1
V
IN–
5V
R
2.5V
C1
0V
+2.5V
R
0V
V
IN
V
–2.5V
IN+
R
R
AD7453
Figure 8. Equivalent Analog Input Circuit. Conversion
Phase—Switches Open; Track Phase—Switches Closed
V
IN–
V
REF
0.1F
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum source
impedance depends on the amount of total harmonic distortion
(THD) that can be tolerated. The THD increases as the source
impedance increases and performance degrades. Figure 9 shows a
graph of the THD versus analog input signal frequency for
different source impedances.
EXTERNAL
(2.5V)
V
REF
Figure 7. Op Amp Configuration to Level Shift a
Bipolar Input Signal
Analog Input Structure
Figure 8 shows the equivalent circuit of the analog input structure
of the AD7453. The four diodes provide ESD protection for the
analog inputs. Care must be taken to ensure that the analog
input signals never exceed the supply rails by more than 300 mV.
This will cause these diodes to become forward biased and start
conducting into the substrate. These diodes can conduct up to
10 mA without causing irreversible damage to the part. The
capacitors, C1 in Figure 8, are typically 4 pF and can be
attributed primarily to pin capacitance. The resistors are lumped
components made up of the on resistance of the switches. The
value of these resistors is typically about 100 W. The capacitors,
C2, are the ADC’s sampling capacitors and have a capacitance
of 16 pF typically.
0
–10
–20
–30
–40
–50
–60
200⍀
100⍀
–70
–80
–90
10⍀
62⍀
–100
For ac applications, removing high frequency components from
the analog input signal through the use of an RC low-pass filter
on the relevant analog input pins is recommended. In applica-
10
100
INPUT FREQUENCY (kHz)
277
Figure 9. THD vs. Analog Input Frequency for
Various Source Impedances
REV. 0
–11–
AD7453
Figure 10 shows a graph of THD versus analog input frequency
for various supply voltages, while sampling at 555 kSPS with an
SCLK of 10 MHz. In this case the source impedance is 10 W.
V
DD
AD7453*
AD780
OPSEL
V
REF
NC
1
2
3
4
8
7
6
5
NC
NC
2.5V
–50
V
V
DD
IN
T
= 25؇C
A
TEMP
GND
V
–55
–60
–65
OUT
0.1F
10nF
0.1F
0.1F
TRIM
NC
NC = NO CONNECT
*ADDITIONAL PINS OMITTED FOR CLARITY
–70
–75
V
= 2.7V
DD
Figure 11. Typical VREF Connection Diagram for VDD = 5 V
V
= 3.6V
DD
SERIAL INTERFACE
V
= 4.75V
–80
–85
DD
Figure 1 shows a detailed timing diagram of the serial inter-
face of the AD7453. The serial clock provides the conversion
clock and also controls the transfer of data from the device
during conversion. CS initiates the conversion process and
frames the data transfer. The falling edge of CS puts the track-
and-hold into hold mode and takes the bus out of three-state.
The analog input is sampled and the conversion initiated at this
point. The conversion will require 16 SCLK cycles to complete.
V
= 5.25V
DD
–90
10
100
INPUT FREQUENCY (kHz)
277
Figure 10. THD vs. Analog Input Frequency for
Various Supply Voltages
Once 13 SCLK falling edges have occurred, the track-and-hold
will go back into track mode on the next SCLK rising edge, as
shown at Point B in Figure 1. On the 16th SCLK falling edge,
the SDATA line will go back into three-state.
DIGITAL INPUTS
The digital inputs applied to the AD7453 are not limited by the
maximum ratings that limit the analog inputs. Instead the digi-
tal inputs applied, i.e., CS and SCLK, can go to 7 V and are not
restricted by the VDD + 0.3 V limits as on the analog input.
If the rising edge of CS occurs before 16 SCLKs have elapsed,
the conversion will be terminated and the SDATA line will go
back into three-state.
The main advantage of the inputs not being restricted to the
VDD + 0.3 V limit is that power supply sequencing issues are
avoided. If CS or SCLK are applied before VDD, there is no risk
of latch-up as there would be on the analog inputs if a signal
The conversion result from the AD7453 is provided on the
SDATA output as a serial data stream. The bits are clocked out
on the falling edge of the SCLK input. The data stream of the
AD7453 consists of four leading zeros, followed by 12 bits of
conversion data, provided MSB first. The output coding is
straight (natural) binary.
greater than 0.3 V were applied prior to VDD
.
REFERENCE SECTION
An external source is required to supply the reference to the
AD7453. This reference input can range from 100 mV to 3.5 V.
The specified reference is 2.5 V for the power supply range
2.7 V to 5.25 V. The reference input chosen for an application
should never be greater than the power supply. Errors in the
reference source result in gain errors in the AD7453 transfer func-
tion. A capacitor of at least 0.1 mF should be placed on the VREF
pin. Suitable reference sources for the AD7453 include the
AD780 and the ADR421. Figure 11 shows a typical connection
diagram for the VREF pin.
Sixteen serial clock cycles are required to perform a conversion
and to access data from the AD7453. CS going low provides the
first leading zero to be read in by the microcontroller or DSP.
The remaining data is then clocked out on the subsequent SCLK
falling edges, beginning with the second leading zero. Thus the
first falling clock edge on the serial clock provides the second
leading zero. The final bit in the data transfer is valid on the
16th falling edge, having been clocked out on the previous (15th)
falling edge. Once the conversion is complete and the data has
been accessed after the 16 clock cycles, it is important to ensure
that, before the next conversion is initiated, enough time is left
to meet the acquisition and quiet time specifications—see the
timing example that follows.
–12–
REV. 0
AD7453
CS
10ns
t2
tCONVERT
t5
1
2
3
4
5
13
14
t6
15
16
SCLK
t8
tQUIET
tACQUISITION
12.5(1/F
)
SCLK
1/THROUGHPUT
Figure 12. Serial Interface Timing Example
In applications with a slower SCLK, it may be possible to read
in data on each SCLK rising edge, i.e., the first rising edge of
SCLK after the CS falling edge would have the leading zero
provided and the 15th SCLK edge would have DB0 provided.
Normal Mode
This mode is intended for fastest throughput rate performance.
The user does not have to worry about any power-up times with
the AD7453 remaining fully powered up all the time. Figure 13
shows the general diagram of the operation of the AD7453 in
this mode. The conversion is initiated on the falling edge of CS,
as described in the Serial Interface section. To ensure that the
part remains fully powered up, CS must remain low until at least
10 SCLK falling edges have elapsed after the falling edge of CS.
Timing Example 1
Having FSCLK = 10 MHz and a throughput rate of 555 kSPS
gives a cycle time of
1/ Throughput = 1/ 555,000 = 1.8 ms
A cycle consists of
If CS is brought high any time after the 10th SCLK falling edge,
but before the 16th SCLK falling edge, the part will remain pow-
ered up but the conversion will be terminated and SDATA will
go back into three-state. Sixteen serial clock cycles are required
to complete the conversion and access the complete conversion
result. CS may idle high until the next conversion or may idle
low until sometime prior to the next conversion. Once a data
transfer is complete, i.e., when SDATA has returned to three-
state, another conversion can be initiated after the quiet time,
tQUIET, has elapsed by again bringing CS low.
t +12.5 1/ F
2
+ t
= 1.8 ms
(
)
SCLK
ACQ
Therefore if t2 = 10 ns, then
10 ns +12.5 1/18 MHz + t
= 1ms
(
)
ACQ
tACQ = 540 ns
This 540 ns satisfies the requirement of 290 ns for tACQ
From Figure 12, tACQ comprises
.
2.5 1/ F
+ t + t
QUIET
(
)
CS
SCLK
8
where t8 = 35 ns. This allows a value of 255 ns for tQUIET, satis-
fying the minimum requirement of 60 ns.
1
16
10
SCLK
SDATA
4 LEADING ZEROS + CONVERSION RESULT
MODES OF OPERATION
The mode of operation of the AD7453 is selected by controlling
the logic state of the CS signal during a conversion. There are
two possible modes of operation, normal mode and power-down
mode. The point at which CS is pulled high after the conversion
has been initiated determines whether the AD7453 will enter
the power-down mode. Similarly, if already in power-down, CS
controls whether the device will return to normal operation or
remain in power-down. These modes of operation are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput rate
ratio for differing application requirements.
Figure 13. Normal Mode Operation
Power-Down Mode
This mode is intended for use in applications where slower
throughput rates are required; either the ADC is powered down
between each conversion, or a series of conversions may be
performed at a high throughput rate and the ADC is then powered
down for a relatively long duration between these bursts of
several conversions. When the AD7453 is in power-down mode,
REV. 0
–13–
AD7453
all analog circuitry is powered down. For the AD7453 to enter
power-down mode, the conversion process must be interrupted
by bringing CS high anywhere after the second falling edge of
SCLK and before the tenth falling edge of SCLK, as shown in
Figure 14.
Although at any SCLK frequency one dummy cycle is sufficient
to power up the device and acquire VIN, it does not necessarily
mean that a full dummy cycle of 16 SCLKs must always elapse
to power up the device and acquire VIN fully; 1 ms will be suffi-
cient to power up the device and acquire the input signal.
Once CS has been brought high in this window of SCLKs, the
part will enter power-down and the conversion that was initi-
ated by the falling edge of CS will be terminated and SDATA
will go back into three-state. The time from the rising edge of
CS to SDATA three-state enabled will never be greater than t8
(see the Timing Specifications). If CS is brought high before the
second SCLK falling edge, the part will remain in normal
mode and will not power down. This will avoid accidental
power-down due to glitches on the CS line.
For example, if a 5 MHz SCLK frequency was applied to the
ADC, the cycle time would be 3.2 ms (i.e., 1/(5 MHz) ¥ 16). In
one dummy cycle, 3.2 ms, the part would be powered up and
V
IN acquired fully. However after 1 ms with a 5 MHz SCLK,
only five SCLK cycles would have elapsed. At this stage, the
ADC would be fully powered up and the signal acquired. So, in
this case, the CS can be brought high after the 10th SCLK
falling edge and brought low again after a time, tQUIET, to ini-
tiate the conversion.
To exit this mode of operation and power up the AD7453
again, a dummy conversion is performed. On the falling edge of
CS the device will begin to power up, and will continue to
power up as long as CS is held low until after the falling edge of
the 10th SCLK. The device will be fully powered up after 1 msec
has elapsed and, as shown in Figure 15, valid data will result
from the next conversion.
When power supplies are first applied to the AD7453, the ADC
may either power up in the power-down mode or normal
mode. Because of this, it is best to allow a dummy cycle to
elapse to ensure that the part is fully powered up before attempting
a valid conversion. Likewise, if the user wants the part to power
up in power-down mode, then the dummy cycle may be used to
ensure the device is in power-down mode by executing a cycle
such as that shown in Figure 14. Once supplies are applied to
the AD7453, the power-up time is the same as that when pow-
ering up from power-down mode. It takes approximately 1 ms
to power up fully if the part powers up in normal mode. It is
not necessary to wait 1 ms before executing a dummy cycle to
ensure the desired mode of operation. Instead, the dummy
cycle can occur directly after power is supplied to the ADC. If
the first valid conversion is then performed directly after the
dummy conversion, care must be taken to ensure that adequate
acquisition time has been allowed.
If CS is brought high before the 10th falling edge of SCLK, the
AD7453 will again go back into power-down. This avoids
accidental power-up due to glitches on the CS line or an inad-
vertent burst of eight SCLK cycles while CS is low. So although
the device may begin to power up on the falling edge of CS, it
will again power down on the rising edge of CS as long as it
occurs before the 10th SCLK falling edge.
CS
1
2
10
As mentioned earlier, when powering up from the power-down
mode, the part will return to track mode upon the first SCLK
edge applied after the falling edge of CS. However, when the
ADC powers up initially after supplies are applied, the track-and-
hold will already be in track mode. This means (assuming one
has the facility to monitor the ADC supply current) that if
the ADC powers up in the desired mode of operation and thus
a dummy cycle is not required to change mode, then neither is a
dummy cycle required to place the track-and-hold into track.
SCLK
THREE–STATE
SDATA
Figure 14. Entering Power-Down Mode
Power-Up Time
The power-up time of the AD7453 is typically 1 ms, which means
that with any frequency of SCLK up to 10 MHz, one dummy
cycle will always be sufficient to allow the device to power up.
Once the dummy cycle is complete, the ADC will be fully
powered up and the input signal will be acquired properly.
The quiet time, tQUIET, must still be allowed—from the point at
which the bus goes back into three-state after the dummy con-
version to the next falling edge of CS.
POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7453 when not
converting, the average power consumption of the ADC decreases
at lower throughput rates. Figure 16 shows how, as the throughput
rate is reduced, the device remains in its power-down state longer
and the average power consumption reduces accordingly. For
example, if the AD7453 is operated in continuous sampling mode
with a throughput rate of 100 kSPS and an SCLK of 10 MHz,
and the device is placed in the power-down mode between con-
versions, then the power consumption is calculated as follows:
When running at the maximum throughput rate of 555 kSPS,
the AD7453 will power up and acquire a signal within
±0.5 LSB in one dummy cycle. When powering up from the
power-down mode with a dummy cycle, as in Figure 15, the track-
and-hold, which was in hold mode while the part was powered
down, returns to track mode after the first SCLK edge the part
receives after the falling edge of CS. This is shown as Point A in
Figure 15.
Power dissipation during normal operation = 7.25 mW max
(for VDD = 5 V). If the power-up time is one dummy cycle (1.06 ms
if CS is brought high after the 10th SCLK falling edge in the
cycle and then brought low after the quiet time) and the remaining
conversion time is another cycle, i.e., 1.6 ms, then the AD7453
can be said to dissipate 7.25 mW for 2.66 ms* during each
conversion cycle.
*This figure assumes a very short time to enter power-down mode. This will
increase as the burst of clocks used to enter the power down mode is
increased.
–14–
REV. 0
AD7453
tPOWER-UP
PART BEGINS
TO POWER UP
THE PART IS FULLY POWERED
UPWITHV FULLY ACQUIRED
IN
CS
A
1
10
16
1
10
16
SCLK
INVALID DATA
SDATA
VALID DATA
Figure 15. Exiting Power-Down Mode
If the throughput rate = 100 kSPS, then the cycle time = 10 ms and
MICROPROCESSOR AND DSP INTERFACING
the average power dissipated during each cycle is
The serial interface on the AD7453 allows the part to be con-
nected directly to a range of different microprocessors. This
section explains how to interface the AD7453 with some of
the more common microcontroller and DSP serial interface
protocols.
2.66 /10 ¥ 7.25 mW = 1.92 mW
(
)
For the same scenario, if VDD = 3 V, the power dissipation during
normal operation is 3.3 mW max.
AD7453 to ADSP-21xx
The ADSP-21xx family of DSPs are interfaced directly to the
AD7453 without any glue logic required.
The AD7453 can now be said to dissipate 3.3 mW for 2.66 ms*
during each conversion cycle.
The average power dissipated during each cycle with a through-
put rate of 100 kSPS is therefore
The SPORT control register should be set up as follows:
TFSW = RFSW = 1
INVRFS = INVTFS = 1
DTYPE = 00
SLEN = 1111
ISCLK = 1
TFSR = RFSR = 1
IRFS = 0
ITFS = 1
Alternate Framing
Active Low Frame Signal
Right Justify Data
16-Bit Data Words
Internal Serial Clock
Frame Every Word
2.66 /10 ¥ 3.3 mW = 0.88 mW
(
)
This is how the power numbers in Figure 16 are calculated.
100
V
= 5V
DD
10
1
To implement the power-down mode, SLEN should be set to
1001 to issue an 8-bit SCLK burst.
The connection diagram is shown in Figure 17. The ADSP-21xx
has the TFS and RFS of the SPORT tied together, with TFS
set as an output and RFS set as an input. The DSP operates in
alternate framing mode and the SPORT control register is set
up as described. The frame synchronization signal generated on
the TFS is tied to CS, and, as with all signal processing applica-
tions, equidistant sampling is necessary. However, in this example,
the timer interrupt is used to control the sampling rate of the
ADC, and, under certain conditions, equidistant sampling may
not be achieved.
V
= 3V
DD
0.1
0.01
0
50
100
150
200
250
300
350
THROUGHPUT (kSPS)
Figure 16. Power vs. Throughput Rate for Power-
Down Mode
For throughput rates above 320 kSPS, it is recommended that
for optimum power performance, the serial clock frequency is
reduced.
*This figure assumes a very short time to enter power-down mode. This will
increase as the burst of clocks used to enter the power down mode is
increased.
REV. 0
–15–
AD7453
ADSP-21xx*
TMS320C5x/
AD7453
*
AD7453*
C54x*
SCLK
CLKx
SCLK
SCLK
CLKR
DR
SDATA
DR
SDATA
CS
RFS
TFS
CS
FSx
FSR
*ADDITIONAL PINS REMOVED FOR CLARITY
*ADDITIONAL PINS REMOVED FOR CLARITY
Figure 17. Interfacing to the ADSP-21xx
Figure 18. Interfacing to the TMS320C5x/C54x
AD7453 to DSP56xxx
The timer registers, etc., are loaded with a value that will provide
an interrupt at the required sample interval. When an interrupt
is received, a value is transmitted with TFS/DT (ADC control
word). The TFS is used to control the RFS and hence the reading
of data. The frequency of the serial clock is set in the SCLKDIV
register. When the instruction to transmit with TFS is given,
(i.e., AX0 = TX0), the state of the SCLK is checked. The DSP
will wait until the SCLK has gone high, low, and high before
transmission will start. If the timer and SCLK values are chosen
such that the instruction to transmit occurs on or near the rising
edge of SCLK, then the data may be transmitted or it may wait
until the next clock edge.
The connection diagram in Figure 19 shows how the AD7453
can be connected to the SSI (synchronous serial interface) of
the DSP56xxx family of DSPs from Motorola. The SSI is oper-
ated in synchronous mode (SYN bit in CRB = 1) with internally
generated 1-bit clock period frame sync for both Tx and Rx (Bit
FSL1 = 1 and Bit FSL0 = 0 in CRB). Set the word length to
16 by setting Bits WL1 = 1 and WL0 = 0 in CRA. To imple-
ment the power-down mode on the AD7453 the word length
can be changed to eight bits by setting Bits WL1 = 0 and WL0
= 0 in CRA. It should be noted that for signal processing
applications, it is imperative that the frame synchronization
signal from the DSP56xxx provide equidistant sampling.
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3,
then an SCLK of 2 MHz is obtained, and eight master clock
periods will elapse for every 1 SCLK period. If the timer regis-
ters are loaded with the value 803, then 100.5 SCLKs will occur
between interrupts and subsequently between transmit instruc-
tions. This situation will result in non-equidistant sampling as the
transmit instruction is occurring on an SCLK edge. If the num-
ber of SCLKs between interrupts is a whole integer figure of
N, then equidistant sampling will be implemented by the DSP.
DSP56xxx*
AD7453
*
SCLK
SDATA
CS
SCLK
SRD
SR2
*ADDITIONAL PINS REMOVED FOR CLARITY
AD7453 to TMS320C5x/C54x
The serial interface on the TMS320C5x/C54x uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7453. The CS input allows easy interfacing between the
TMS320C5x/C54x and the AD7453 without any glue logic
required. The serial port of the TMS320C5x/C54x is set up to
operate in burst mode with internal CLKX (Tx serial clock) and
FSX (Tx frame sync). The serial port control register (SPC)
must have the following setup: FO = 0, FSM = 1, MCM = 1
and TXM = 1. The format bit, FO, may be set to 1 to set the
word length to 8 bits in order to implement the power-down
mode on the AD7453. The connection diagram is shown in
Figure 18. It should be noted that for signal processing applica-
tions, it is imperative that the frame synchronization signal from
the TMS320C5x/C54x provide equidistant sampling.
Figure 19. Interfacing to the DSP56xxx
–16–
REV. 0
AD7453
APPLICATION HINTS
Grounding and Layout
In this technique the component side of the board is dedicated
to ground planes while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 mF tantalum capacitors in parallel with
0.1 mF capacitors to GND. To achieve the best from these
decoupling components, they must be placed as close as pos-
sible to the device.
The printed circuit board that houses the AD7453 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
etch technique is generally best for ground planes as it gives the
best shielding. Digital and analog ground planes should be
joined in only one place, and the connection should be a star
ground point established as close to the GND pin on the AD7453
as possible.
EVALUATING THE AD7453 PERFORMANCE
The Evaluation Board Package includes a fully assembled and
tested evaluation board, documentation, and software for con-
trolling the board from a PC via the evaluation board controller.
The evaluation board controller can be used in conjunction with
the AD7453 evaluation board, as well as many other Analog
Devices evaluation boards ending with the CB designator, to
demonstrate/evaluate the ac and dc performance of the AD7453.
Avoid running digital lines under the device as this will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD7453 to avoid noise coupling. The power
supply lines to the AD7453 should use as large a trace as pos-
sible to provide low impedance paths and reduce the effects of
glitches on the power supply line.
The software allows the user to perform ac (Fast Fourier Trans-
form) and dc (histogram of codes) tests on the AD7453. See the
evaluation board application note for more information.
Fast switching signals like clocks should be shielded with digital
ground to avoid radiating noise to other sections of the board,
and clock signals should never run near the analog inputs.
Avoid crossover of digital and analog signals. Traces on oppo-
site sides of the board should run at right angles to each other.
This will reduce the effects of feedthrough through the board. A
microstrip technique is by far the best but is not always possible
with a double-sided board.
REV. 0
–17–
AD7453
OUTLINE DIMENSIONS
8-Lead Small Outline Transistor Package [SOT-23]
(RT-8)
Dimensions shown in millimeters
2.90 BSC
8
1
7
2
6
3
5
4
1.60 BSC
PIN 1
2.80 BSC
0.65 BSC
1.95
BSC
1.30
1.15
0.90
1.45 MAX
0.22
0.08
0.60
0.45
0.30
10؇
0؇
0.38
0.22
0.15 MAX
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178BA
–18–
REV. 0
–19–
–20–
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