AD7457BRT-R2 [ADI]
Low Power, Pseudo Differential, 100 kSPS 12-Bit ADC in an 8-Lead SOT-23; 低功耗，伪差分， 100 kSPS的12位ADC，采用8引脚SOT- 23
| 型号： | AD7457BRT-R2 |
| 厂家： | 
ADI |
| 描述： | Low Power, Pseudo Differential, 100 kSPS 12-Bit ADC in an 8-Lead SOT-23 |
| 文件： | 总20页 (文件大小：522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power, Pseudo Differential, 100 kSPS
12-Bit ADC in an 8-Lead SOT-23
AD7457
FEATURES
FUNCTIONAL BLOCK DIAGRAM
V
Specified for VDD of 2.7 V to 5.25 V
DD
Low power:
0.9 mW max at 100 kSPS with VDD = 3 V
3 mW max at 100 kSPS with VDD = 5 V
Pseudo differential analog input
Wide input bandwidth:
70-dB SINAD at 30 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
V
V
12-BIT
SUCCESSIVE
APPROXIMATION
ADC
IN+
T/H
IN–
V
REF
High speed serial interface—SPI®/QSPI™/
MICROWIRE™/DSP compatible
Automatic power-down mode
8-lead SOT-23 package
SCLK
SDATA
CS
AD7457
CONTROL LOGIC
APPLICATIONS
Transducer interface
Battery-powered systems
Data acquisition systems
Portable instrumentation
GND
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7457 is a 12-bit, low power, successive approximation
(SAR) analog-to-digital converter that features a pseudo
differential analog input. This part operates from a single 2.7 V
to 5.25 V power supply and features throughput rates of up to
100 kSPS.
1. Operation with 2.7 V to 5.25 V power supplies.
2. Low power consumption. With a 3 V supply, the AD7457
offers 0.9 mW maximum power consumption for a
100 kSPS throughput rate.
3. Pseudo differential analog input.
The part contains a low noise, wide bandwidth, differential
track-and-hold amplifier (T/H) that can handle input
frequencies in excess of 1 MHz. The reference voltage for the
AD7457 is applied externally to the VREF pin and can range from
100 mV to VDD, depending on what suits the application.
4. Flexible power/serial clock speed management. The
conversion rate is determined by the serial clock, allowing
the power to be reduced as the conversion time is reduced
through the serial clock speed increase. Automatic power-
down after conversion allows the average power
consumption to be reduced.
The conversion process and data acquisition are controlled
CS
using
and the serial clock, allowing the device to interface
with microprocessors or DSPs.
5. Variable voltage reference input.
6. No pipeline delay.
The SAR architecture of this part ensures that there are no
pipeline delays.
CS
7. Accurate control of the sampling instance via the
and once-off conversion control.
input
The AD7457 uses advanced design techniques to achieve very
low power dissipation.
8. ENOB > 10 bits typically with 500 mV reference.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD7457
TABLE OF CONTENTS
Specifications..................................................................................... 3
Analog Input ............................................................................... 12
Analog Input Structure.............................................................. 12
Digital Inputs .............................................................................. 13
Reference Section ....................................................................... 13
Serial Interface............................................................................ 13
Power Consumption .................................................................. 14
Microprocessor Interfacing....................................................... 14
Application Hints ........................................................................... 16
Grounding and Layout .............................................................. 16
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 17
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Functional Descriptions.......................... 7
Terminology ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 11
Circuit Information.................................................................... 11
Converter Operation.................................................................. 11
ADC Transfer Function............................................................. 11
Typical Connection Diagram ................................................... 11
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 20
AD7457
SPECIFICATIONS
VDD = 2.7 V to 5.25 V, fSCLK = 10 MHz, fS = 100 kSPS, VREF = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
Test Conditions/Comments
B Version1
Unit
DYNAMIC PERFORMANCE
Signal to Noise Ratio (SNR)2
Signal to (Noise + Distortion) (SINAD)2
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise2
Intermodulation DIstortion (IMD)2
Second Order Terms
fIN = 30 kHz
71
70
−75
−75
dB min
dB min
dB max
dB max
−84 dB typ
−86 dB typ
fa = 25 kHz; fb = 35 kHz
−80
−80
5
50
20
dB typ
dB typ
ns typ
ps typ
MHz typ
MHz typ
Third Order Terms
Aperture Delay2
Aperture Jitter2
Full-Power Bandwidth2,3
@ −3 dB
@ −0.1 dB
2.5
DC ACCURACY
Resolution
12
1
0.ꢀ5
4.5
2
Bits
Integral Nonlinearity (INL)2
Differential Nonlinearity (DNL)2
Offset Error2
LSB max
LSB max
LSB max
LSB max
Guaranteed no missed codes to 12 bits
Gain Error2
ANALOG INPUT
Full-Scale Input Span
Absolute Input Voltage
VIN+
VIN+ − V IN–
VREF
V
VREF
V
V
V
4
VIN–
VDD = 2.7 V to 3.6 V
VDD = 4.75 V to 5.25 V
−0.1 to +0.4
−0.1 to +1.5
1
DC Leakage Current
Input Capacitance
REFERENCE INPUT
VREF Input Voltage
DC Leakage Current
VREF Input Capacitance
LOGIC INPUTS
µA max
pF typ
When in track/hold
30/10
1ꢁ tolerance for specified performance
When in track/hold
2.55
1
10/30
V
µA max
pF typ
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
2.4
0.8
1
V min
V max
µA max
pF max
Typically 10 nA, VIN = 0 V or VDD
6
Input Capacitance, CIN
10
LOGIC OUTPUTS
Output High Voltage, VOH
VDD = 4.75 V to 5.25 V, ISOURCE = 200 µA
VDD = 2.7 V to 3.6 V, ISOURCE = 200 µA
ISINK = 200 µA
2.8
2.4
0.4
1
10
Straight
V min
V min
V max
µA max
pF max
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance6
Output Coding
natural binary
CONVERSION RATE
Conversion Time
1.6 µs with a 10 MHz SCLK
See Serial Interface section
16
1
100
SCLK cycles
µs max
kSPS max
Track-and-Hold Acquisition Time2
Throughput Rate
Rev. 0 | Page 3 of 20
AD7457
Parameter
Test Conditions/Comments
B Version1
Unit
POWER REQUIREMENTS
VDD
2.7/5.25
V min/max
7,8
IDD
During Conversion6
VDD = 4.75 V to 5.25 V
VDD = 2.7 V to 3.6 V
SCLK on or off
VDD = 4.75 V to 5.25 V
VDD= 2.7 V to 3.6 V
SCLK on or off
1.5
1.2
0.5
0.7
0.33
1
mA max
mA max
mA typ
mA max
mA max
µA max
Normal Mode (Static)
Normal Mode (Operational)
Power-Down
Power Dissipation
Normal Mode (Operational)
VDD = 5 V
VDD = 3 V
VDD = 5 V; SCLK on or off
VDD = 3 V; SCLK on or off
3
0.ꢀ
5
mW max
mW max
µW max
µW max
Power-Down
3
1Temperature ranges as follows: B version: −40°C to +85°C.
2 See Terminology section.
3Analog inputs with slew rates exceeding 27 V/µs (full-scale input sine wave > 3.5 MHz) within the acquisition time may cause an incorrect result to be returned by the
converter.
4 A dc input is applied to VIN– to provide a pseudo ground for VIN+.
5 The AD7457 is functional with a reference input in the range 100 mV to VDD
6 Guaranteed by characterization.
.
7 See Power Consumption section.
8 Measured with a full-scale dc input.
Rev. 0 | Page 4 of 20
AD7457
TIMING SPECIFICATIONS1
VDD = 2.7 V to 5.25 V, fSCLK = 10 MHz, fS = 100 kSPS, VREF = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Limit at TMIN, TMAX
Unit
Description
2
fSCLK
10
10
kHz min
MHz max
tCONVERT
16 × tSCLK
1.6
10
tSCLK = 1/fSCLK
µs max
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs max
µs min
t2
CS
rising edge to SCLK falling edge setup time
3
t3
20
CS
Delay from rising edge until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK high pulse width
3
t4
40
t5
t6
t7
0.4 tSCLK
0.4 tSCLK
10
10
35
SCLK low pulse width
SCLK edge to data valid hold time
SCLK falling edge to SDATA three-state enabled
SCLK falling edge to SDATA three-state enabled
Power-up time from full power-down
Minimum time spent in power-down
4
t8
5
tPOWER-UP
tPOWER-DOWN
1
7.4
1The timing specifications are guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10ꢁ to ꢀ0ꢁ of VDD) and timed from a voltage level of
1.6 V. See Figure 2 and the Serial Interface section.
2Mark/space ratio for the SCLK input is 40/60 to 60/40.
3Measured with the load circuit of Figure 3 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V, and the time required for the output to
cross 0.4 V or 2.0 V for VDD = 3 V.
4t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 3. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish
time of the part and is independent of the bus loading.
5See Power Consumption section.
CONVERT
START
POWER
UP
HOLD
TRACK
TRACK
T
T
POWERUP
POWERUP
T
T
ACQUISTION
ACQUISITION
CS
AUTOMATIC
POWER DOWN
t5
t2
SCLK
t8
t6
t4
t3
T
t7
POWERDOWN
0
0
0
0
DB11 DB10
DB2 DB1 DB0
SDATA
THREE-STATE
THREE-STATE
4 LEADING ZEROS
Figure 2. AD7457 Serial Interface Timing Diagram
Rev. 0 | Page 5 of 20
AD7457
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameters
Rating
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
VDD to GND
VIN+ to GND
VIN– to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
VREF to GND
Input Current to Any Pin except
Supplies1
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
10 mA
Operating Temperature Range
Commercial (B Version)
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 s)
−40°C to +85°C
−65°C to +150°C
150°C
211.5°C/W (SOT-23)
ꢀ1.ꢀꢀ°C/W (SOT-23)
I
OL
1.6mA
TO
OUTPUT
PIN
1.6V
C
25pF
L
I
215°C
220°C
OH
200µA
Infrared (15 s)
1Transient currents of up to 100 mA do not cause SCR latch-up.
Figure 3. Load Circuit for Digital Output Timing Specifications
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 6 of 20
AD7457
PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS
V
1
2
3
4
8
7
6
5
V
V
V
DD
REF
SCLK
SDATA
CS
IN+
AD7457
TOP VIEW
–
IN
(Not to Scale)
GND
Figure 4. 8-Lead SOT-23 Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic Description
1
VDD
Power Supply Input. VDD is 2.7 V to 5.25 V. This supply should be decoupled to GND with a 0.1 µF capacitor and a
10 µF tantalum capacitor.
2
3
SCLK
SDATA
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also
used as the clock source for the conversion process.
Serial Data. Logic output. The conversion result from the AD7457 is provided on this output as a serial data
stream. The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7457 consists of
four leading zeros followed by the 12 bits of conversion data that are provided MSB first. The output coding is
straight (natural) binary.
4
5
6
CS
Chip Select. This input provides the dual function of powering up the device and initiating a conversion on the
AD7457.
Analog Ground. Ground reference point for all circuitry on the AD7457. All analog input signals and any external
reference signal should be referred to this GND voltage.
Inverting Input. This pin sets the ground reference point for the VIN+ input. Connect to ground or to a dc offset to
provide a pseudo ground.
GND
VIN–
7
8
VIN+
VREF
Noninverting Analog Input.
Reference Input for the AD7457. An external reference in the range 100 mV to VDD must be applied to this input.
The specified reference input is 2.5 V. This pin should be decoupled to GND with a capacitor of at least 0.33 µF.
Rev. 0 | Page 7 of 20
AD7457
TERMINOLOGY
As a result, the second and third order terms are specified
separately. The calculation of the intermodulation distortion is
as per the THD specification, where it is the ratio of the rms
sum of the individual distortion products to the rms amplitude
of the sum of the fundamentals expressed in dB.
Signal to (Noise + Distortion) Ratio (SINAD)
The measured ratio of signal to (noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the sum of all nonfundamental signals up
to half the sampling frequency (fS/2), excluding dc. The ratio is
dependent on the number of quantization levels in the digitiza-
tion process; the more levels, the smaller the quantization noise.
The theoretical signal to (noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by
Aperture Delay
The amount of time from the leading edge of the sampling
clock until the ADC actually takes the sample.
Aperture Jitter
Signal to
Noise + Distortion
=
6.02 N + 1.76 dB
The sample-to-sample variation in the effective point in time at
which the actual sample is taken.
Therefore, for a 12-bit converter, the SINAD is 74 dB.
Full-Power Bandwidth
Total Harmonic Distortion (THD)
The full-power bandwidth of an ADC is that input frequency at
which the amplitude of the reconstructed fundamental is
reduced by 0.1 dB or 3 dB for a full-scale input.
The ratio of the rms sum of harmonics to the fundamental. For
the AD7457, it is defined as
V22 + V32 + V42 + V52 + V62
Integral Nonlinearity (INL)
The maximum deviation from a straight line passing through
the endpoints of the ADC transfer function.
THD(dB) = 20 log
V1
where:
Differential Nonlinearity (DNL)
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
V1 is the rms amplitude of the fundamental.
V2, V3, V4, V5, and V6 are the rms amplitudes of the second to the
sixth harmonics.
Offset Error
The deviation of the first code transition (000...000 to 000...001)
from the ideal (that is, AGND + 1 LSB).
Peak Harmonic or Spurious Noise
The ratio of the rms value of the next largest component in the
ADC output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Normally, the value of this specifica-
tion is determined by the largest harmonic in the spectrum, but,
for ADCs where the harmonics are buried in the noise floor, it is
a noise peak.
Gain Error
The deviation of the last code transition (111...110 to 111...111)
from the ideal (that is, VREF − 1 LSB), after the offset error has
been adjusted out.
Track-and-Hold Acquisition Time
Intermodulation Distortion
The minimum time required for the track-and-hold amplifier to
remain in track mode for its output to reach and settle to within
0.5 LSB of the applied input signal.
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities creates distortion
products at sum and difference frequencies of mfa nfb, where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms are
those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa − fb), while the
third order terms include (2fa + fb), (2fa − fb), (fa + 2fb) and
(fa − 2fb).
Power Supply Rejection Ratio (PSRR)
The ratio of the power in the ADC output at full-scale
frequency, f, to the power of a 100 mV p-p sine wave applied to
the ADC VDD supply of frequency fs. The frequency of this
input varies from 1 kHz to 1 MHz.
PSRR
dB
)
=10 log
Pf Pfs
The AD7457 is tested using the CCIF standard, where two input
frequencies near the top end of the input bandwidth are used.
In this case, the second order terms are usually distanced in
frequency from the original sine waves, while the third order
terms are usually at a frequency close to the input frequencies.
Pf is the power at frequency f in the ADC output; Pfs is the
power at frequency fs in the ADC output.
Rev. 0 | Page 8 of 20
AD7457
TYPICAL PERFORMANCE CHARACTERISTICS
Default Conditions: TA = 25°C, fS = 100 kSPS, fSCLK = 10 MHz, VDD = 2.7 V to 5.25 V, VREF = 2.5 V, unless otherwise noted.
1.0
75
0.8
0.6
V
DD
= 5V
0.4
0.2
V
DD
= 3V
70
0
0.2
0.4
–
–
–0.6
–
0.8
1.0
–
65
10
0
1024
2048
CODE
3072
4096
20
30
40
50
FREQUENCY (kHz)
Figure 5. SINAD vs. Analog Input Frequency for VDD = 3 V and 5 V
Figure 8. Typical DNL for the AD7457 for VDD = 5 V
1.0
0
100mV p-p SINEWAVE ON V
NO DECOUPLING ON V
DD
DD
0.8
0.6
–20
–40
0.4
0.2
–60
0
0.2
0.4
V
= 3V
DD
–80
–
–
V
= 5V
DD
–100
–0.6
–120
–140
–
0.8
1.0
–
0
1024
2048
CODE
3072
4096
0
100 200 300 400 500 600 700 800 900 1000
SUPPLY RIPPLE FREQUENCY (kHz)
Figure 6. PSRR vs. Supply Ripple Frequency without Supply Decoupling
Figure 9. Typical INL for the AD7457 for VDD = 5 V
0
10000
9000
8000
7000
6000
5000
4000
3000
9949
CODES
8192 POINT FFT
f
f
= 100kSPS
SAMPLE
= 30kHz
–20
–40
IN
SINAD = 71dB
THD = –82dB
SFDR =–83dB
–60
–80
–100
2000
1000
0
–120
–140
27 CODES
2047 2048
24 CODES
2049 2050
0
30
50
FREQUENCY (kHz)
100
2046
2051
CODES
Figure 7. Dynamic Performance for VDD = 5 V
Figure 10. Histogram of 10,000 Conversions of a DC Input
Rev. 0 | Page ꢀ of 20
AD7457
12
11
10
9
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V
= 3V
DD
V
= 5V
DD
POSITIVE DNL
NEGATIVE DNL
8
7
–
0.5
1.0
6
–
0
0.5
1.0
1.5
2.0
(V)
2.5
3.0
3.5
0
0.5
1.0
1.5
2.0
(V)
2.5
3.0
3.5
V
V
REF
REF
Figure 11. Changes in DNL vs. VREF for VDD = 5 V
Figure 13. ENOB vs. VREF for VDD =3V and 5 V
5
4
3
2
1
0
POSITIVE INL
NEGATIVE INL
–
1
2
–
0
0.5
1.0
1.5
2.0
(V)
2.5
3.0
3.5
V
REF
Figure 12. Change in INL vs. VREF for VDD = 5 V
Rev. 0 | Page 10 of 20
AD7457
THEORY OF OPERATION
CIRCUIT INFORMATION
CAPACITIVE
DAC
The AD7457 is a 12-bit, low power, single supply, successive
approximation analog-to-digital converter (ADC) with a
pseudo differential analog input. It operates with a single 2.7 V
to 5.25 V power supply and is capable of throughput rates up to
100 kSPS. It requires an external reference to be applied to the
C
C
B
S
V
IN+
A
A
SW1
SW2
CONTROL
LOGIC
SW3
V
IN
–
B
S
COMPARATOR
V
REF
CAPACITIVE
DAC
VREF pin.
Figure 15. ADC Conversion Phase
The AD7457 has an on-chip differential track-and-hold
amplifier, a successive approximation (SAR) ADC, and a serial
interface, housed in an 8-lead SOT-23 package. The serial clock
input accesses data from the part and provides the clock source
for the successive approximation ADC. The AD7457 automati-
cally powers down after conversion, resulting in low power
consumption.
ADC TRANSFER FUNCTION
The output coding for the AD7457 is straight (natural) binary.
The designed code transitions occur at successive LSB values
(1 LSB, 2 LSB, and so on). The LSB size is VREF/4096. The ideal
transfer characteristics of the AD7457 are shown in Figure 16.
CONVERTER OPERATION
1LSB = V
REF
/4096
The AD7457 is a successive approximation ADC based around
two capacitive DACs. Figure 14 and Figure 15 show simplified
schematics of the ADC in the acquisition phase and the conver-
sion phase, respectively. The ADC is comprised of control logic,
a SAR, and two capacitive DACs. In Figure 14 (acquisition
phase), SW3 is closed, SW1 and SW2 are in Position A, the
comparator is held in a balanced condition, and the sampling
capacitor arrays acquire the differential signal on the input.
111...11
111...10
111...00
011...11
000...10
000...01
000...00
1LSB
V
–1LSB
0V
REF
ANALOG INPUT
CAPACITIVE
DAC
Figure 16. Ideal Transfer Characteristics
C
B
S
S
V
IN+
A
SW1
SW2
TYPICAL CONNECTION DIAGRAM
CONTROL
LOGIC
SW3
A
B
V
IN
–
Figure 17 shows a typical connection diagram for the AD7457.
In this setup, the GND pin is connected to the analog ground
plane of the system. The VREF pin is connected to the AD780, a
2.5 V decoupled reference source. The signal source is con-
nected to the VIN+ analog input via a unity gain buffer. A dc
voltage is connected to the VIN– pin to provide a pseudo ground
for the VIN+ input. The VDD pin should be decoupled to AGND
with a 10 µF tantalum capacitor in parallel with a 0.1 µF
ceramic capacitor. The reference pin should be decoupled to
AGND with a capacitor of at least 0.33 µF. The conversion result
is output in a 16-bit word with four leading zeros followed by
the MSB of the 12-bit result.
C
COMPARATOR
V
REF
CAPACITIVE
DAC
Figure 14. ADC Acquisition Phase
When the ADC starts a conversion (Figure 15), SW3 opens, and
SW1 and SW2 move to Position B, causing the comparator to
become unbalanced. Both inputs are disconnected once the
conversion begins. The control logic and the charge redistribu-
tion DACs are used to add and subtract fixed amounts of charge
from the sampling capacitor arrays to bring the comparator
back into a balanced condition. When the comparator is
rebalanced, the conversion is complete. The control logic
generates the ADC’s output code. The output impedances of the
sources driving the VIN+ and the VIN– pins must be matched;
otherwise the two inputs have different settling times, resulting
in errors.
Rev. 0 | Page 11 of 20
AD7457
+2.7V TO +5.25V
SUPPLY
ANALOG INPUT STRUCTURE
0.1µF
10µF
Figure 19 shows the equivalent circuit of the analog input
structure of the AD7457. The four diodes provide ESD
protection for the analog inputs. Care must be taken to ensure
that the analog input signals never exceed the supply rails by
more than 300 mV, which causes these diodes to become
forward biased and start conducting into the substrate. These
diodes can conduct up to 10 mA without causing irreversible
damage to the part. The capacitors, C1 in Figure 19, are typically
4 pF and can be attributed primarily to pin capacitance. The
resistors are lumped components made up of the on resistance
of the switches. The value of these resistors is typically about
100 Ω. The capacitors, C2, are the ADC’s sampling capacitors,
which typically have a capacitance of 16 pF.
SERIAL
INTERFACE
V
DD
AD7457
V
REF
P-TO-P
SCLK
V
IN+
µC/µP
SDATA
CS
V
IN–
DC INPUT
VOLTAGE
GND
V
REF
2.5V
AD780
0.33µF
Figure 17. Typical Connection Diagram
ANALOG INPUT
The AD7457 has a pseudo differential analog input. The VIN+
input is coupled to the signal source and should have an
amplitude of VREF p-p to make use of the full dynamic range of
the part. A dc input is applied to the VIN–. The voltage applied to
this input provides an offset from ground or a pseudo ground
for the VIN+ input. Ensure that (VIN− + VIN+) is less than or equal
to VDD to avoid exceeding the maximum ratings of the ADC.
The main benefit of pseudo differential inputs is that they
separate the analog input signal ground from the ADC’s ground,
allowing dc common-mode voltages to be canceled.
For ac applications, removing high frequency components from
the analog input signal through the use of an RC low pass filter
on the relevant analog input pins is recommended. In applica-
tions where harmonic distortion and the signal-to-noise ratio
are critical, the analog input should be driven from a low
impedance source. Large source impedances can significantly
affect the ac performance of the ADC, which may necessitate
the use of an input buffer amplifier. The choice of the op amp is
a function of the particular application.
V
DD
Because the ADC operates from a single supply, it is necessary
to level shift ground-based bipolar signals to comply with the
input requirements. An op amp (for example, the AD8021) can
be configured to rescale and level shift a ground-based (bipolar)
signal, so that it is compatible with the input range of the
AD7457. See Figure 18.
D
D
C2
R1
V
IN+
C1
When a conversion takes place, the pseudo ground corresponds
to 0 and the maximum analog input corresponds to 4096.
V
DD
2.5V
1.25V
0V
R
D
D
C2
R1
+1.25V
R
V
IN–
0V
V
IN
C1
V
–1.25V
IN+
3R
R
AD7457
V
IN–
V
REF
0.33µF
Figure 19. Equivalent Analog Input Circuit. Conversion Phase—Switches
Open; Track Phase—Switches Closed
EXTERNAL
(2.5V)
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance depends on the amount of total harmonic
distortion (THD) that can be tolerated. The THD increases as
the source impedance increases and performance degrades.
Figure 20 shows a graph of the THD versus analog input signal
frequency for different source impedances.
V
REF
Figure 18. Op Amp Configuration to Level Shift a Bipolar Input Signal
Rev. 0 | Page 12 of 20
AD7457
–50
–60
–70
errors in the AD7457 transfer function. A capacitor of at least
T
= 25°C
A
0.33 µF should be placed on the VREF pin. Suitable reference
sources for the AD7457 include the AD780 and the ADR421.
Figure 22 shows a typical connection diagram for the VREF pin.
200
Ω
V
DD
AD7457*
100
Ω
AD780
OPSEL
–80
–90
V
REF
NC
1
2
3
4
8
7
6
5
NC
NC
V
V
DD
IN
2.5V
62Ω
10Ω
TEMP
GND
V
OUT
0.1µF
10µF
0.1µF
0.33µF
TRIM
NC
NC = NO CONNECT
*ADDITIONAL PINS OMITTED FOR CLARITY
10
20
30
40
50
INPUT FREQUENCY (kHz)
Figure 20. THD vs. Analog Input Frequency for Various Source Impedances
Figure 22. Typical VREF Connection Diagram for VDD = 5 V
Figure 21 shows a graph of THD versus analog input frequency
for various supply voltages, while sampling at 100 kSPS with an
SCLK of 10 MHz. In this case, the source impedance is 10 Ω.
SERIAL INTERFACE
Figure 2 shows a detailed timing diagram of the serial interface
of the AD7457. The serial clock provides the conversion clock
and also controls the transfer of data from the device during
conversion.
–50
T
= 25°C
A
–55
–60
–65
–70
–75
CS
The falling edge of
powers up the AD7457 and also puts the
track-and-hold into track. The power-up time is 1 µs minimum
and, in this time, the device also acquires the analog input
CS
signal.
must remain low for the duration of power-up. The
CS
rising edge of
initiates the conversion process, puts the
V
= 2.7V
DD
V
= 3.6V
DD
track-and-hold into hold mode, and takes the serial data bus out
of three-state. The conversion requires 16 SCLK cycles to
complete.
–80
–85
V
= 4.75V
DD
V
= 5.25V
DD
–90
10
On the sixteenth SCLK falling edge, after the time t8, the serial
data bus goes back into three-state and the device automatically
enters full power-down. It remains in power-down until the
20
30
40
50
INPUT FREQUENCY (kHz)
Figure 21. THD vs. Analog Input Frequency for Various Supply Voltages
CS
next falling edge of . For specified performance, the through-
DIGITAL INPUTS
put rate should not exceed 100 kSPS, which means that there
CS
The digital inputs applied to the AD7457 are not limited by the
maximum ratings that limit the analog inputs. Instead the
should be no less than 10 µs between consecutive
edges.
falling
CS
digital inputs applied, that is,
and SCLK, can go to 7 V and
The conversion result from the AD7457 is provided on the
SDATA output as a serial data stream. The bits are clocked out
on the falling edge of the SCLK input. The data stream of the
AD7457 consists of four leading zeros, followed by the 12 bits of
conversion data that are provided MSB first. The output coding
is straight (natural) binary.
are not restricted by the VDD + 0.3 V limits as on the analog
input.
The main advantage of the inputs not being restricted to the
V
DD + 0.3 V limit is that power supply sequencing issues are
CS
avoided. If
or SCLK are applied before VDD, there is no risk
of latch-up as there would be on the analog inputs, if a signal
greater than 0.3 V were applied prior to VDD.
Sixteen serial clock cycles are, therefore, required to perform a
conversion and to access data from the AD7457. A rising edge
CS
of
provides the first leading zero to be read in by the
REFERENCE SECTION
microcontroller or DSP. The remaining data is then clocked out
on the subsequent SCLK falling edges beginning with the
second leading zero. Thus, the first falling clock edge on the
An external source is required to supply the reference to the
AD7457. This reference input can range from 100 mV to VDD.
The specified reference is 2.50 V for the power supply range
2.70 V to 5.25 V. Errors in the reference source result in gain
CS
serial clock after
has gone high provides the second leading
zero. The final bit in the data transfer, before the device goes
Rev. 0 | Page 13 of 20
AD7457
2.5
2.0
1.5
1.0
0.5
0
into power-down, is valid on the sixteenth falling edge of SCLK,
having been clocked out on the previous (fifteenth) falling edge.
T
= 25°C
A
In applications with a slow SCLK, it is possible to read in data
on each SCLK rising edge. In this case, the first falling edge of
CS
SCLK after the
rising edge clocks out the second leading
V
= 5V
DD
zero and can be read in on the following rising edge. If the first
CS
SCLK edge after the
rising edge is a falling edge, the first
CS
leading zero that was clocked out when
went high is missed,
unless it was not read on the first SCLK falling edge. The
fifteenth falling edge of SCLK clocks out the last bit of data,
which can be read in by the following rising SCLK edge.
V
= 3V
DD
0
20
40
60
80
100
THROUGHPUT (kSPS)
POWER CONSUMPTION
Figure 24. Power vs. Throughput Rate for SCLK = 10 MHz for VDD = 3 V and 5 V
The AD7457 automatically enters power-down at the end of
each conversion. When in the power-down mode, all analog
circuitry is powered down and the current consumption is 1 µA.
To achieve the specified power consumption (which is the
lowest), there are a few things the user should keep in mind.
MICROPROCESSOR INTERFACING
The serial interface of the AD7457 allows the part to be con-
nected to a range of different microprocessors. This section
explains how to interface the AD7457 with the ADSP-218x
serial interface.
The conversion time of the device is determined by the serial
clock frequency. The faster the SCLK frequency, the shorter the
conversion time. Therefore, as the clock frequency used is
increased, the ADC is dissipating power for a shorter period of
time (during conversion) and it remains in power-down for a
longer percentage of the cycle time or throughput rate. This can
be seen in Figure 23, which shows typical IDD versus SCLK
frequency for VDD of 3 V and 5 V, when operating the device at
the maximum throughput of 100 kSPS.
AD7457 to ADSP-218x
The ADSP-218x family of DSPs can be interfaced directly to the
AD7457 without any glue logic. The serial clock for the ADC is
provided by the DSP. SDATA from the ADC is connected to the
CS
data receive (DR) input of the serial port and
can be
controlled by a flag (FL0). The connection diagram is shown in
Figure 25.
2.5
AD7457*
ADSP-21xx*
T
= 25°C
A
SCLK
SCLK
SPORT0
DR0
2.0
1.5
1.0
0.5
0
SDATA
RFS
FL0
SPORT1
CS
*ADDITIONAL PINS OMITTED FOR CLARITY
V
= 5V
DD
V
= 3V
DD
Figure 25. AD7457 to ADSP-218x
SPORT0 must be enabled to receive the conversion data and to
provide the SCLK, while SPORT1 must be configured for flags,
and so on.
0
2
4
6
8
10
SCLK Frequency (MHz)
SPORT0 is configured by setting the bits in its control register
as listed in Table 5.
Figure 23. IDD vs. SCLK Frequency for VDD = 3 V and 5 V when Operating at 100
kSPS
Figure 24 shows typical power consumption versus throughput
rate for the maximum SCLK frequency of 10 MHz. In this case,
the conversion time is the same for all throughputs, because the
SCLK frequency is fixed. As the throughput rate decreases, the
average power consumption decreases, because the ADC spends
more time in power-down.
Rev. 0 | Page 14 of 20
AD7457
Table 5. SPORT0 Configuration
CS
The flag to generate the
signal is generated by SPORT1. It is
Bit
Setting
Comment/Description
connected to both the ADC and the RFS input of SPORT0 to
provide the frame sync signal for the DSP.
ISCLK
SLEN
RFSR
1
1111
0
Serial clock generated internally
16 bits of conversion data
Receive frame sync required every
word
TFSR
IRFS
Don’t care
0
Not used
RFS is set to be an input and is
generated externally
ITFS
Don’t care
Not used
RFSW
TFSW
INVRFS
1
Alternate receive framing
Not used
RFS is active high
Not used
Don’t care
0
INVTFS Don’t care
Rev. 0 | Page 15 of 20
AD7457
APPLICATION HINTS
GROUNDING AND LAYOUT
as clocks should be shielded with digital ground to avoid
radiating noise to other sections of the board, and clock signals
should never run near the analog inputs. Avoid crossover of
digital and analog signals. Traces on opposite sides of the board
should run at right angles to each other. This reduces the effects
of feed through the board. A micro strip technique is by far the
best, but is not always possible with a double-sided board.
The printed circuit board that houses the AD7457 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. This facilitates the
use of ground planes that can be easily separated. A minimum
etch technique is generally best for ground planes, because it
gives the best shielding. Digital and analog ground planes
should be joined in only one place, and the connection should
be a star ground point established as close as possible to the
GND pin on the AD7457.
In this technique, the component side of the board is dedicated
to ground planes, while signals are placed on the solder side.
Good decoupling is also important. All analog supplies should
be decoupled with 10 µF tantalum capacitors in parallel with
0.1 µF capacitors to GND. To achieve the best from these
decoupling components, place them as close as possible to the
device.
Avoid running digital lines under the device, because this
couples noise onto the die. The analog ground plane should be
allowed to run under the AD7457 to avoid noise coupling. The
power supply lines to the AD7457 should use as large a trace as
possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals such
Rev. 0 | Page 16 of 20
AD7457
OUTLINE DIMENSIONS
2.90 BSC
8
1
7
2
6
3
5
4
1.60 BSC
PIN 1
2.80 BSC
0.65 BSC
1.95
BSC
1.30
1.15
0.90
1.45 MAX
0.22
0.08
0.60
0.45
0.30
8°
4°
0°
0.38
0.22
0.15 MAX
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178BA
Figure 26. 8-Lead Small Outline Transistor Package [SOT-23] (RT-8)—Dimensions shown in millimeters
ORDERING GUIDE
Model
AD7457BRT-R2
AD7457BRT-REEL7
Temperature Range
–40°C to +85°C
–40°C to +85°C
Linearity Error (LSB)1
Package Description
8-Lead SOT-23
8-Lead SOT-23
Package Option
Branding
COD
COD
1
1
RT-8
RT-8
1 Linearity error here refers to integral nonlinearity error.
Rev. 0 | Page 17 of 20
AD7457
NOTES
Rev. 0 | Page 18 of 20
AD7457
NOTES
Rev. 0 | Page 1ꢀ of 20
AD7457
NOTES
©
2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03157–0–10/03(0)
Rev. 0 | Page 20 of 20
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