AD745AN [ADI]
Ultralow Noise, High Speed, BiFET Op Amp; 超低噪声，高速， BiFET运算放大器
| 型号： | AD745AN |
| 厂家： | 
ADI |
| 描述： | Ultralow Noise, High Speed, BiFET Op Amp |
| 文件： | 总12页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ultralow Noise,
High Speed, BiFET Op Amp
a
AD745
FEATURES
ULTRALOW NOISE PERFORMANCE
2.9 nV/ͱHz at 10 kHz
CONNECTION DIAGRAM
16-Lead SOIC (R) Package
0.38 ꢀV p-p, 0.1 Hz to 10 Hz
6.9 fA/ͱHz Current Noise at 1 kHz
EXCELLENT AC PERFORMANCE
12.5 V/ꢀs Slew Rate
20 MHz Gain Bandwidth Product
THD = 0.0002% @ 1 kHz
Internally Compensated for Gains of +5 (or –4) or
Greater
EXCELLENT DC PERFORMANCE
0.5 mV Max Offset Voltage
250 pA Max Input Bias Current
2000 V/mV Min Open Loop Gain
Available in Tape and Reel in Accordance with
EIA-481A Standard
APPLICATIONS
Sonar
Photodiode and IR Detector Amplifiers
Accelerometers
amplifier for high-speed applications demanding low noise and
high dc precision. Furthermore, the AD745 does not exhibit an
output phase reversal.
The AD745 also has excellent dc performance with 250 pA
maximum input bias current and 0.5 mV maximum offset voltage.
Low Noise Preamplifiers
High Performance Audio
The internal compensation of the AD745 is optimized for higher
gains, providing a much higher bandwidth and a faster slew
rate. This makes the AD745 especially useful as a preamplifier
where low level signals require an amplifier that provides both
high amplification and wide bandwidth at these higher gains.
The AD745 is available in two performance grades. The AD745J
and AD745K are rated over the commercial temperature range
of 0°C to 70°C, and are available in the 16-lead SOIC package.
PRODUCT DESCRIPTION
The AD745 is an ultralow noise, high-speed, FET input opera-
tional amplifier. It offers both the ultralow voltage noise and
high speed generally associated with bipolar input op amps and
the very low input currents of FET input devices. Its 20 MHz
bandwidth and 12.5 V/µs slew rate makes the AD745 an ideal
120
100
80
120
100
80
1000
R
SOURCE
OP37 AND
RESISTOR
E
PHASE
GAIN
O
R
SOURCE
100
10
1
60
60
AD745 AND RESISTOR
OR
OP37 AND RESISTOR
AD745 AND
RESISTOR
40
40
20
20
0
0
RESISTOR NOISE ONLY
1k 10k
–20
100M
–20
100
100
100k
1M
10M
1k
10k
100k
1M
10M
SOURCE RESISTANCE – ꢁ
FREQUENCY – Hz
Figure 1.
Figure 2.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
AD745–SPECIFICATIONS
AD745 ELECTRICAL CHARACTERISTICS
Model
(@ +25ꢂC and ꢃ15 V dc, unless otherwise noted.)
AD745J
Typ
AD745K
Typ
Conditions
Min
Max
Min
Max
Unit
INPUT OFFSET VOLTAGE1
Initial Offset
Initial Offset
vs. Temp.
vs. Supply (PSRR)
vs. Supply (PSRR)
0.25
1.0
1.5
0.1
0.5
1.0
mV
mV
µV/°C
dB
TMIN to TMAX
TMIN to TMAX
12 V to 18 V2
TMIN to TMAX
2
96
2
106
105
90
88
100
98
dB
INPUT BIAS CURRENT3
Either Input
VCM = 0 V
150
400
150
250
pA
Either Input
@ TMAX
Either Input
Either Input, VS
VCM = 0 V
VCM = +10 V
VCM = 0 V
8.8
600
200
5.5
400
125
nA
pA
pA
250
30
250
30
=
5 V
INPUT OFFSET CURRENT
Offset Current
VCM = 0 V
VCM = 0 V
40
150
2.2
30
75
pA
nA
@ TMAX
1.1
FREQUENCY RESPONSE
Gain BW, Small Signal
Full Power Response
Slew Rate
G = –4
VO = 20 V p-p
G = –4
20
20
MHz
kHz
V/µs
µs
120
12.5
5
120
12.5
5
Settling Time to 0.01%
Total Harmonic
f = 1 kHz
G = –4
Distortion4
0.0002
0.0002
%
INPUT IMPEDANCE
Differential
Common Mode
1 × 1010ʈ20
3 × 1011ʈ18
1 × 1010ʈ20
3 × 1011ʈ18
ΩʈpF
ΩʈpF
INPUT VOLTAGE RANGE
Differential5
Common-Mode Voltage
Over Max Operating Range6
Common-Mode
20
20
V
V
V
+13.3, –10.7
+13.3, –10.7
–10
+12
–10
+12
Rejection Ratio
VCM
TMIN to TMAX
=
10 V
80
78
95
90
88
102
dB
dB
INPUT VOLTAGE NOISE
0.1 to 10 Hz
f = 10 Hz
f = 100 Hz
f = 1 kHz
0.38
5.5
3.6
3.2
2.9
0.38
5.5
3.6
3.2
2.9
1.0
10.0
6.0
5.0
4.0
µV p-p
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
5.0
4.0
f = 10 kHz
INPUT CURRENT NOISE
OPEN LOOP GAIN
f = 1 kHz
6.9
6.9
fA/√Hz
VO
= 10 V
RLOAD ≥ 2 kΩ
TMIN to TMAX
RLOAD = 600 Ω
1000
800
4000
1200
2000
1800
4000
1200
V/mV
V/mV
V/mV
OUTPUT CHARACTERISTICS
Voltage
RLOAD ≥ 600 Ω
RLOAD ≥ 600 Ω
TMIN to TMAX
RLOAD ≥ 2 kΩ
Short Circuit
+13, –12
+13, –12
+12, –10
20
V
+13.6, –12.6
+13.6, –12.6
V
V
+12, –10
12
20
V
+13.8, –13.1
40
+13.8, –13.1
40
Current
mA
POWER SUPPLY
Rated Performance
Operating Range
Quiescent Current
15
15
V
V
mA
4.8
18
10.0
4.8
18
10.0
8
8
TRANSISTOR COUNT
NOTES
# of Transistors
50
50
1Input offset voltage specifications are guaranteed after five minutes of operations at TA = 25°C.
2Test conditions: +VS = 15 V, –VS = 12 V to 18 V and +VS = 12 V to +18 V, –VS = 15 V.
3Bias current specifications are guaranteed maximum at either input after five minutes of operation at TA = 25°C. For higher temperature, the current doubles every 10°C.
4Gain = –4, RL = 2 kΩ, CL = 10 pF.
5Defined as voltage between inputs, such that neither exceeds 10 V from common.
6The AD745 does not exhibit an output phase reversal when the negative common-mode limit is exceeded.
All min and max specifications are guaranteed.
Specifications subject to change without notice.
–2–
REV. D
AD745
ABSOLUTE MAXIMUM RATINGS1
ESD SUSCEPTIBILITY
An ESD classification per method 3015.6 of MIL-STD-883C
has been performed on the AD745, which is a class 1 device.
Using an IMCS 5000 automated ESD tester, the two null pins
will pass at voltages up to 1,000 volts, while all other pins will
pass at voltages exceeding 2,500 volts.
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V
Internal Power Dissipation2
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 W
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS
Output Short-Circuit Duration . . . . . . . . . . . . . . . . Indefinite
Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and –VS
Storage Temperature Range (R) . . . . . . . . . –65°C to +125°C
Operating Temperature Range
ORDERING GUIDE
Package
AD745J/K . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Model
Temperature Range
Option*
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C
NOTES
AD745JR-16
AD745KR-16
0°C to 70°C
0°C to 70°C
R-16
R-16
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
*R = Small Outline IC.
216-Pin Plastic SOIC Package: θJA = 100°C/W, θJC = 30°C/W
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD745 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. D
–3–
(@ + 25ꢂC, VS = ꢃ15 V, unless otherwise noted.)
AD745
–Typical Performance Characteristics
20
20
35
30
25
20
15
R
= 10kꢁ
R
= 10kꢁ
LOAD
LOAD
15
10
5
15
10
5
+V
IN
POSITIVE
SUPPLY
NEGATIVE
SUPPLY
–V
IN
10
5
0
0
0
10
100
1k
10k
0
5
10
15
20
0
5
10
15
20
SUPPLYVOLTAGE ꢃ VOLTS
LOAD RESISTANCE –ꢁ
SUPPLYVOLTAGE ꢃ VOLTS
TPC 2. Output Voltage Swing vs.
Supply Voltage
TPC 3. Output Voltage Swing vs.
Load Resistance
TPC 1. Input Voltage Swing vs.
Supply Voltage
–6
200
100
12
9
10
–7
10
10
–8
10
–9
6
10
1
CLOSED LOOP GAIN = –5
–10
10
3
0.1
–11
10
0
–12
10
0.01
0
5
10
15
20
10k
100k
1M
10M
100M
–60 –40 –20
0
20 40 60 80 100 120 140
SUPPLYVOLTAGE ꢃ VOLTS
FREQUENCY – Hz
TEMPERATURE – ꢂC
TPC 4. Quiescent Current vs.
Supply Voltage
TPC 6. Output Impedance vs.
Frequency
TPC 5. Input Bias Current vs.
Temperature
300
–6
–7
–8
–9
10
28
26
10
10
10
24
22
200
100
0
20
18
16
14
–10
10
–11
10
10
–12
–12 –9 –6
–3
0
3
6
9
12
–60 –40 –20
0
20 40 60 80 100 120 140
–60 –40 –20
0
20 40 60 80 100 120 140
COMMON-MODEVOLTAGE –V
TEMPERATURE – ꢂC
TEMPERATURE – ꢂC
TPC 7. Input Bias Current vs.
Common-Mode Voltage
TPC 8. Short Circuit Current Limit vs.
Temperature
TPC 9. Gain Bandwidth Product vs.
Temperature
–4–
REV. D
AD745
120
100
80
14
12
10
8
150
140
130
120
100
80
R
= 2kꢁ
L
PHASE
60
CLOSED-LOOP GAIN = 5
40
GAIN
20
0
–20
100
1k
10k 100k
1M
10M 100M
0
5
10
15
20
–60 –40 –20
0
20 40 60 80 100 110 120
FREQUENCY – Hz
TEMPERATURE – ꢂC
SUPPLYVOLTAGE ꢃ VOLTS
TPC 10. Open-Loop Gain and Phase
vs. Frequency
TPC 11. Slew Rate vs. Temperature
TPC 12. Open-Loop Gain vs.
Supply Voltage
120
110
100
90
120
35
30
25
20
15
10
R
= 2kꢁ
L
100
+SUPPLY
80
60
80
–SUPPLY
V
= ꢃ10V
cm
40
70
60
50
20
0
5
0
100
1k
10k
100k
1M
10M
10k
100k
1M
10M
100
1k
10k 100k
1M
10M 100M
FREQUENCY – Hz
FREQUENCY – Hz
FREQUENCY – Hz
TPC 13. Common-Mode Rejection vs.
Frequency
TPC 14. Power Supply Rejection
vs. Frequency
TPC 15. Large Signal Frequency
Response
–40
–60
1.0
1k
100
10
100
0.1
10
0.01
–80
CLOSED-LOOP GAIN = 5
GAIN = +10
0.001
0.0001
0.00001
–100
–120
–140
GAIN = +100
1.0
0.1
GAIN = –4
1.0
10
100
1k
FREQUENCY – Hz
10k
100k
10
100
1k
10k 100k
1M
10M
1
10
100
1k
10k
100k
FREQUENCY – Hz
FREQUENCY – Hz
TPC 16. Total Harmonic Distortion
vs. Frequency
TPC 17. Input Noise Voltage
Spectral Density
TPC 18. Input Noise Current
Spectral Density
–5–
REV. D
AD745
648
594
540
486
432
378
324
270
216
162
108
54
72
TOTAL UNITS = 760
TOTAL UNITS = 4100
66
60
54
48
42
36
30
24
18
12
6
0
0
–15
2.6 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4
–10
–5
0
5
10
15
INPUTVOLTAGE NOISE @ 10kHz – nV Hz
INPUT OFFSETVOLTAGE DRIFT – ꢀV/ꢂC
TPC 21. Offset Null Configuration,
16-Lead Package Pinout
TPC 19. Distribution of Offset
Voltage Drift. TA = 25°C to 125°C
TPC 20. Typical Input Noise Voltage
Distribution @ 10 kHz
500ns
2µs
100
90
100
90
10
10
0%
0%
50mV
5V
TPC 22a. Gain of 5 Follower,
16-Lead Package Pinout
TPC 22b. Gain of 5 Follower
Large Signal Pulse Response
TPC 22c. Gain of 5 Follower Small
Signal Pulse Response
2µs
500ns
100
90
100
90
10
10
0%
0%
5V
50mV
TPC 23a. Gain of 4 Inverter,
16-Lead Package Pinout
TPC 23b. Gain of 4 Inverter Large
Signal Pulse Response
TPC 23c. Gain of 4 Inverter Small
Signal Pulse Response
–6–
REV. D
AD745
OP AMP PERFORMANCE JFET VERSUS BIPOLAR
The AD745 offers the low input voltage noise of an industry
standard bipolar opamp without its inherent input current
errors. This is demonstrated in Figure 3, which compares input
voltage noise vs. input source resistance of the OP37 and the
AD745 opamps. From this figure, it is clear that at high source
impedance the low current noise of the AD745 also provides
lower total noise. It is also important to note that with the AD745
this noise reduction extends all the way down to low source
impedances. The lower dc current errors of the AD745 also
reduce errors due to offset and drift at high source impedances
(Figure 4).
The 0.1 Hz to 10 Hz noise is typically 0.38 µV p-p. The user
should pay careful attention to several design details to optimize
low frequency noise performance. Random air currents can
generate varying thermocouple voltages that appear as low
frequency noise. Therefore, sensitive circuitry should be well
shielded from air flow. Keeping absolute chip temperature low
also reduces low frequency noise in two ways: first, the low
frequency noise is strongly dependent on the ambient tempera-
ture and increases above 25°C. Second, since the gradient of
temperature from the IC package to ambient is greater, the
noise generated by random air currents, as previously mentioned,
will be larger in magnitude. Chip temperature can be reduced
both by operation at reduced supply voltages and by the use of a
suitable clip-on heat sink, if possible.
The internal compensation of the AD745 is optimized for higher
gains, providing a much higher bandwidth and a faster slew
rate. This makes the AD745 especially useful as a preamplifier,
where low-level signals require an amplifier that provides both
high amplification and wide bandwidth at these higher gains.
Low frequency current noise can be computed from the
magnitude of the dc bias current
~
= 2qIB∆f
In
1000
and increases below approximately 100 Hz with a 1/f power
spectral density. For the AD745 the typical value of current
noise is 6.9 fA/√Hz at 1 kHz. Using the formula:
R
SOURCE
OP37 AND
RESISTOR
E
O
~
R
SOURCE
100
10
1
I n
= 4kT/R∆f
to compute the Johnson noise of a resistor, expressed as a
current, one can see that the current noise of the AD745 is
equivalent to that of a 3.45 × 108 Ω source resistance.
AD745 AND RESISTOR
OR
OP37 AND RESISTOR
AD745 AND
RESISTOR
At high frequencies, the current noise of a FET increases pro-
portionately to frequency. This noise is due to the “real” part of
the gate input impedance, which decreases with frequency. This
noise component usually is not important, since the voltage
noise of the amplifier impressed upon its input capacitance is an
apparent current noise of approximately the same magnitude.
RESISTOR NOISE ONLY
1k 10k
100
100k
SOURCE RESISTANCE – ꢁ
1M
10M
In any FET input amplifier, the current noise of the internal
bias circuitry can be coupled externally via the gate-to-source
capacitances and appears as input current noise. This noise is
totally correlated at the inputs, so source impedance matching
will tend to cancel out its effect. Both input resistance and input
capacitance should be balanced whenever dealing with source
capacitances of less than 300 pF in value.
Figure 3. Total Input Noise Spectral Density @ 1 kHz
vs. Source Resistance
100
OP37G
10
LOW NOISE CHARGE AMPLIFIERS
As stated, the AD745 provides both low voltage and low current
noise. This combination makes this device particularly suitable
in applications requiring very high charge sensitivity, such as
capacitive accelerometers and hydrophones. When dealing with
a high source capacitance, it is useful to consider the total input
charge uncertainty as a measure of system noise.
1.0
AD745 KN
Charge (Q) is related to voltage and current by the simply stated
fundamental relationships:
0.1
100
1k
10k
100k
1M
10M
SOURCE RESISTANCE –ꢁ
dQ
Q = CV and I =
dt
Figure 4. Input Offset Voltage vs. Source Resistance
As shown, voltage, current and charge noise can all be directly
related. The change in open circuit voltage (∆V) on a capacitor
will equal the combination of the change in charge (∆Q/C) and
the change in capacitance with a built-in charge (Q/∆C).
DESIGNING CIRCUITS FOR LOW NOISE
An opamp’s input voltage noise performance is typically divided
into two regions: flatband and low frequency noise. The AD745
offers excellent performance with respect to both. The figure of
2.9 nV/ͱHz @ 10 kHz is excellent for a JFET input amplifier.
REV. D
–7–
AD745
–100
–110
–120
–130
–140
–150
–160
–170
Figures 5 and 6 show two ways to buffer and amplify the output
of a charge output transducer. Both require the use of an ampli-
fier that has a very high input impedance, such as the AD745.
Figure 5 shows a model of a charge amplifier circuit. Here,
amplification depends on the principle of conservation of charge
at the input of amplifier A1, which requires that the charge on
capacitor CS be transferred to capacitor CF, thus yielding an
output voltage of ∆Q/CF. The amplifiers input voltage noise will
appear at the output amplified by the noise gain (1 + (CS/CF))
of the circuit.
TOTAL
OUTPUT
NOISE
–180
–190
–200
NOISE DUETO
C
F
R
ALONE
B
–210
–220
NOISE DUETO
ALONE
R
R1
R2
S
I
B
0.01
0.1
1
10
100
1k
10k
100k
FREQUENCY – Hz
Figure 7. Noise at the Outputs of the Circuits of Figures 5
and 6. Gain = 10, CS = 3000 pF, RB = 22 MΩ
A1
C
S
However, this does not change the noise contribution of RB
which, in this example, dominates at low frequencies. The graph
of Figure 8 shows how to select an RB large enough to minimize
this resistor’s contribution to overall circuit noise. When the
equivalent current noise of RB ((ͱ4 kT)/R) equals the noise of
C
*
R *
B
B
C
C
R1
R2
S
F
=
Figure 5. A Charge Amplifier Circuit
R1
IB 2qIB
, there is diminishing return in making R larger.
(
)
B
C *
B
10
5.2 ꢄ 10
R *
A2
B
R2
C
R
B
S
9
5.2 ꢄ 10
5.2 ꢄ 10
5.2 ꢄ 10
5.2 ꢄ 10
*OPTIONAL, SEETEXT.
8
7
Figure 6. Model for A High Z Follower with Gain
The second circuit, Figure 6, is simply a high impedance fol-
lower with gain. Here the noise gain (1 + (R1/R2)) is the same
as the gain from the transducer to the output. Resistor RB, in
both circuits, is required as a dc bias current return.
There are three important sources of noise in these circuits.
Amplifiers A1 and A2 contribute both voltage and current noise,
while resistor RB contributes a current noise of:
6
1pA
10pA
100pA
1nA
10nA
INPUT BIAS CURRENT
Figure 8. Graph of Resistance vs. Input Bias Current
Where the Equivalent Noise ͙4 kT/R, Equals the Noise
~
T
RB
=
4 k
∆f
N
IB 2qIB
of the Bias Current
(
)
where:
To maximize dc performance over temperature, the source
resistances should be balanced on each input of the amplifier.
This is represented by the optional resistor RB in Figures 5 and 6.
As previously mentioned, for best noise performance care should
be taken to also balance the source capacitance designated by
CB The value for CB in Figure 5 would be equal to CS in
Figure 6. At values of CB over 300 pF, there is a diminishing
impact on noise; capacitor CB can then be simply a large mylar
bypass capacitor of 0.01 µF or greater.
k = Boltzman’s Constant = 1.381 × 10–23 Joules/Kelvin
T = Absolute Temperature, Kelvin (0°C = 273.2 Kelvin)
∆f = Bandwidth – in Hz (Assuming an Ideal “Brick Wall”
Filter)
This must be root-sum-squared with the amplifier’s own current
noise.
Figure 5 shows that these two circuits have an identical frequency
response and the same noise performance (provided that
CS/CF = R1/ R2). One feature of the first circuit is that a “T”
network is used to increase the effective resistance of RB and
improve the low frequency cutoff point by the same factor.
–8–
REV. D
AD745
300
200
100
0
HOW CHIP PACKAGE TYPE AND POWER DISSIPATION
AFFECT INPUT BIAS CURRENT
T
= 25ꢂC
A
As with all JFET input amplifiers, the input bias current of the
AD745 is a direct function of device junction temperature, IB
approximately doubling every 10°C. Figure 9 shows the rela-
tionship between bias current and junction temperature for the
AD745. This graph shows that lowering the junction tempera-
ture will dramatically improve IB.
ꢅ
= 165ꢂC/W
JA
–6
10
ꢅ
= 115ꢂC/W
JA
V
T
= 15V
= 25ꢂC
S
A
–7
–8
–9
10
10
10
ꢅ
= 0ꢂC/W
JA
5
10
SUPPLYVOLTAGE – ꢃVolts
15
Figure 11. Input Bias Current vs. Supply Voltage for
Various Values of θJA
–10
–11
–12
10
10
10
T
J
ꢅ
A
(J TO DIE
MOUNT)
–60 –40 –20
0
20
40
60
80
100 120 140
JUNCTIONTEMPERATURE – ꢂC
ꢅ
B
(DIE MOUNT
TO CASE)
Figure 9. Input Bias Current vs. Junction Temperature
T
A
The dc thermal properties of an IC can be closely approximated
by using the simple model of Figure 10 where current represents
power dissipation, voltage represents temperature, and resistors
represent thermal resistance (θ in °C/watt).
ꢅ
+ ꢅ = ꢅ
B JC
A
CASE
Figure 12. Breakdown of Various Package Thermal
Resistance
ꢅ
ꢅ
CA
T
JC
J
REDUCED POWER SUPPLY OPERATION FOR
LOWER IB
ꢅ
JA
T
P
A
IN
Reduced power supply operation lowers IB in two ways: first, by
lowering both the total power dissipation and, second, by reduc-
ing the basic gate-to-junction leakage (Figure 11). Figure 13
shows a 40 dB gain piezoelectric transducer amplifier, which
operates without an ac coupling capacitor, over the –40°C to
+85°C temperature range. If the optional coupling capacitor,
C1, is used, this circuit will operate over the entire –55°C to
+125°C temperature range.
WHERE:
IN
P
= DEVICE DISSIPATION
T
T
= AMBIENTTEMPERATURE
= JUNCTIONTEMPERATURE
A
J
ꢅ
=THERMAL RESISTANCE – JUNCTIONTO CASE
=THERMAL RESISTANCE – CASETO AMBIENT
JC
ꢅ
CA
Figure 10. Device Thermal Model
100ꢁ
10kꢁ
From this model TJ = TA+θJA PIN. Therefore, IB can be deter-
mined in a particular application by using Figure 9 together with
the published data for θJA and power dissipation. The user can
modify θJA by use of an appropriate clip-on heat sink such as the
Aavid #5801. Figure 11 shows bias current versus supply voltage
with θJA as the third variable. This graph can be used to predict
bias current after θJA has been computed. Again bias current will
double for every 10°C.
C1*
8
CT**
10 ꢁ**
+5V
AD745
TRANSDUCER
C
8
T
10 ꢁ
–5V
*OPTIONAL DC BLOCKING CAPACITOR
**OPTIONAL, SEETEXT
Figure 13. A Piezoelectric Transducer
REV. D
–9–
AD745
TWO HIGH PERFORMANCE ACCELEROMETER
AMPLIFIERS
low frequency performance, the time constant of the servo loop
(R4C2 = R5C3) should be:
Two of the most popular charge-out transducers are hydrophones
and accelerometers. Precision accelerometers are typically cali-
brated for a charge output (pC/g).* Figures 14 and 15 show two
R2
Time Constant ≥10 R1 1+
C1
R3
ways in which to configure the AD745 as a low noise charge
amplifier for use with a wide variety of piezoelectric accelerom-
eters. The input sensitivity of these circuits will be determined
by the value of capacitor C1 and is equal to:
A LOW NOISE HYDROPHONE AMPLIFIER
Hydrophones are usually calibrated in the voltage-out mode.
The circuit of Figures 16 can be used to amplify the output of a
typical hydrophone. If the optional ac coupling capacitor CC is
used, the circuit will have a low frequency cutoff determined by
an RC time constant equal to:
∆QOUT
C1
∆VOUT
=
1
Time Constant ≥ 10 R1
2π × CC × 100 Ω
The ratio of capacitor C1 to the internal capacitance (CT) of the
transducer determines the noise gain of this circuit (1 + CT/C1).
The amplifiers voltage noise will appear at its output amplified
by this amount. The low frequency bandwidth of these circuits
will be dependent on the value of resistor R1. If a “T” network
is used, the effective value is: R1 (1 + R2/R3).
where the dc gain is 1 and the gain above the low frequency
cutoff (1/(2π CC(100 Ω))) is equal to (1 + R2/R3). The circuit
of Figure 17 uses a dc servo loop to keep the dc output at 0 V
and to maintain full dynamic range for IB’s up to 100 nA. The
time constant of R7 and C1 should be larger than that of R1
and CT for a smooth low frequency response.
*
pC = Picocoulombs
g = Earth’s Gravitational Constant
R2
1900ꢁ
C1
1250pF
R3
100ꢁ
R1
R4*
C1*
110Mꢁ
(5 ꢄ 22Mꢁ)
C
R2
9kꢁ
C
R3
1kꢁ
B AND KTYPE 8100 HYDROPHONE AD745
OUTPUT
R1
10 ꢁ
C
T
8
INPUT SENSITIVITY = –179dB RE. 1V/mPa**
OUTPUT
0.8mV/pC
AD745
B AND K
4370 OR
EQUIVALENT
*OPTIONAL DC BLOCKING CAPACITOR
**OPTIONAL, SEETEXT
Figure 16. A Low Noise Hydrophone Amplifier
The transducer shown has a source capacitance of 7500 pF. For
smaller transducer capacitances (≤300 pF), lowest noise can be
achieved by adding a parallel RC network (R4 = R1, C1 = CT)
in series with the inverting input of the AD745.
Figure 14. A Basic Accelerometer Circuit
C1
1250pF
R1
R2
1900ꢁ
110Mꢁ
(5 ꢄ 22Mꢁ)
R2
9kꢁ
R3
100ꢁ
R3
1kꢁ
C2
2.2ꢀF
R4*
10 ꢁ
C1*
OUTPUT
8
R4
18Mꢁ
R4
16Mꢁ
AD745
R5
18Mꢁ
C2
0.27ꢀF
AD711
C3
2.2ꢀF
R1
8
R5
100kꢁ
10 ꢁ
OUTPUT
0.8mV/pC
AD745
AD711K
B AND K
4370 OR
EQUIVALENT
R6
1Mꢁ
C
T
16Mꢁ
DC OUTPUT 1mV FOR IB (AD745) 100nA
Figure 15. An Accelerometer Circuit Employing a DC
Servo Amplifier
*OPTIONAL, SEETEXT
A dc servo loop (Figure 15) can be used to assure a dc output
<10 mV, without the need for a large compensating resistor
when dealing with bias currents as large as 100 nA. For optimal
Figure 17. A Hydrophone Amplifier Incorporating a DC
Servo Loop
–10–
REV. D
AD745
1ꢀF
DESIGN CONSIDERATIONS FOR I-TO-V CONVERTERS
There are some simple rules of thumb when designing an I-V
converter where there is significant source capacitance (as with
a photodiode) and bandwidth needs to be optimized. Consider
the circuit of Figure 18. The high frequency noise gain
(1 + CS/CL) is usually greater than five, so the AD745, with its
higher slew rate and bandwidth is ideally suited to this applica-
tion.
+
+12V
16
1
2
3
4
5
6
7
8
0.01ꢀF
–12V
0.01ꢀF
15
14
13
12
11
10
9
AD1862
20-BIT D/A
CONVERTER
+12V
0.01ꢀF
ANALOG
COMMON
10ꢀF
0.1ꢀF
+
OUTPUT
+12V
Here both the low current and low voltage noise of the AD745 can
be taken advantage of, since it is desirable in some instances to
have a large RF (which increases sensitivity to input current noise)
and, at the same time, operate the amplifier at high noise gain.
3 POLE
LOW
PASS
FILTER
DIGITAL
INPUTS
AD745
3kꢁ
0.1ꢀF
–12V
R
F
TOPVIEW
–12V
INPUT SOURCE: PHOTO DIODE,
ACCELEROMETER, ECT.
C
L
DIGITAL
COMMON
100pF
0.01ꢀF
2000pF
AD745
R
C
S
B
I
S
Figure 19. A High Performance Audio DAC Circuit
An important feature of this circuit is that high frequency en-
ergy, such as clock feedthrough, is shunted to common via a
high quality capacitor and not the output stage of the amplifier,
greatly reducing the error signal at the input of the amplifier and
subsequent opportunities for intermodulation distortions.
Figure 18. A Model for an l-to-V Converter
In this circuit, the RF CS time constant limits the practical band-
width over which flat response can be obtained, in fact:
40
fC
fB
≈
2π RFCS
30
where:
fB = signal bandwidth
fC = gain bandwidth product of the amplifier
20
With CL ≈ 1/(2 πRF CS) the net response can be adjusted to a
provide a two pole system with optimal flatness that has a corner
frequency of fB. Capacitor CL adjusts the damping of the circuit’s
response. Note that bandwidth and sensitivity are directly traded
off against each other via the selection of RF. For example, a
photodiode with CS = 300 pF and RF = 100 kΩ will have a maxi-
mum bandwidth of 360 kHz when capacitor CL ≈ 4.5 pF.
Conversely, if only a 100 kHz bandwidth were required, then
the maximum value of RF would be 360 kΩ and that of capaci-
tor CL still ≈ 4.5 pF.
UNBALANCED
10
BALANCED
2.9nV/ Hz
0
10
100
1k
INPUT CAPACITANCE – pF
Figure 20. RTI Noise Voltage vs. Input Capacitance
In either case, the AD745 provides impedance transformation,
the effective transresistance, i.e., the I/V conversion gain, may
be augmented with further gain. A wideband low noise amplifier
such as the AD829 is recommended in this application.
BALANCING SOURCE IMPEDANCES
As mentioned previously, it is good practice to balance the
source impedances (both resistive and reactive) as seen by the
inputs of the AD745. Balancing the resistive components will
optimize dc performance over temperature because balancing
will mitigate the effects of any bias current errors. Balancing
input capacitance will minimize ac response errors due to the
amplifier’s input capacitance and, as shown in Figure 20, noise
performance will be optimized. Figure 21 shows the required
external components for noninverting (A) and inverting (B)
configurations.
This principle can also be used to apply the AD745 in a high
performance audio application. Figure 19 shows that an I-V
converter of a high performance DAC, here the AD1862, can
be designed to take advantage of the low voltage noise of the
AD745 (2.9 nV/ͱHz) as well as the high slew rate and band-
width provided by decompensation. This circuit, with component
values shown, has a 12 dB/octave rolloff at 728 kHz, with a
passband ripple of less than 0.001 dB and a phase deviation of
less than 2 degrees @ 20 kHz.
REV. D
–11–
AD745
C
R
F
1
C
R
= C || C
F
B
B
S
S
C
= C
= R
R
1
B
S
= R || R
1
C
R
B
B
S
FOR
>> R OR R
2
R
S
1
R
B
OUTPUT
AD745
R
C
S
S
R
OUTPUT
AD745
2
C
R
B
B
INVERTING
CONNECTION
C
R
S
S
NONINVERTING
CONNECTION
Figure 40. Optional External Components for Balancing Source Impedances
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
16-Lead SOIC (R) Package
0.4133 (10.50)
0.3977 (10.00)
16
1
9
8
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
0.050 (1.27)
BSC
ꢄ 45ꢂ
8ꢂ
0ꢂ
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0500 (1.27)
0.0157 (0.40)
0.0125 (0.32)
0.0091 (0.23)
Revision History
Location
Page
Data Sheet changed from REV. C to REV. D.
Deleted 8-Lead Plastic Mini-DIP (N) and 8-Lead Cerdip (Q) Packages from CONNECTION DIAGRAM . . . . . . . . . . . . . . . . . . 1
Edits to PRODUCT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Deleted to METALIZATION PHOTOGRAPH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Deleted text from HOW CHIP PACKAGE TYPE AND POWER DISSIPATION AFFECT INPUT BIAS CURRENT . . . . . . . . 9
Deleted 8-Lead Plastic Mini-DIP (N) and 8-Lead Cerdip (Q) Packages from OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . 12
–12–
REV. D
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