AD7467BRT-RL2 [ADI]
IC 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6, MO-178AB, SOT-23, 6 PIN, Analog to Digital Converter;
| 型号： | AD7467BRT-RL2 |
| 厂家： | 
ADI |
| 描述： | IC 1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6, MO-178AB, SOT-23, 6 PIN, Analog to Digital Converter 光电二极管 转换器 |
| 文件： | 总24页 (文件大小：305K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1.6 V, Micropower
12-/10-/8-Bit ADCs in 6-Lead SOT-23
AD7466/AD7467/AD7468*
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Specified for VDD of 1.6 V to 3.6 V
Low Power:
V
DD
0.62 mW Typ at 100 kSPS with 3 V Supplies
0.48 mW Typ at 50 kSPS with 3.6 V Supplies
0.12 mW Typ at 100 kSPS with 1.6 V Supplies
Fast Throughput Rate: 200 kSPS
Wide Input Bandwidth:
12-/10-/8-BIT
SUCCESSIVE
APPROXIMATION
ADC
T/H
V
IN
71 dB SNR at 30 kHz Input Frequency
Flexible Power/Serial Clock Speed Management
No Pipeline Delays
SCLK
SDATA
CS
CONTROL
LOGIC
High Speed Serial Interface
SPI®/QSPI™/MICROWIRE™/DSP Compatible
Automatic Power Down
AD7466/AD7467/AD7468
Power-Down Mode: 8 nA Typ
6-Lead SOT-23 Package
GND
8-Lead MSOP Package
APPLICATIONS
Battery-Powered Systems
Medical Instruments
Remote Data Acquisition
Isolated Data Acquisition
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The AD7466/AD7467/AD7468 are 12-/10-/8-bit, high speed,
low power, successive approximation ADCs, respectively.
The parts operate from a single 1.6 V to 3.6 V power supply
and feature throughput rates up to 200 kSPS. The parts con-
tain a low noise, wide bandwidth track-and-hold amplifier that
can handle input frequencies in excess of 3 MHz.
1. Specified for supply voltages of 1.6 V to 3.6 V.
2. 12-/10-/8-Bit ADCs in a SOT-23 package.
3. High throughput rate with low power consumption. Power
consumption in normal mode of operation at 100 kSPS and
3 V is 0.9 mW max.
The conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to interface
with microprocessors or DSPs. The input signal is sampled on
the falling edge of CS, and the conversion is also initiated at this
point. There are no pipeline delays associated with the part.
4. Flexible power/serial clock speed management.
The conversion rate is determined by the serial clock, allowing
the conversion time to be reduced through the serial clock
speed increase. Automatic power-down after conversion
allows the average power consumption to be reduced when
in power-down. Current consumption is 0.1 µA max and 8 nA
typically when in power-down.
The AD7466/AD7467/AD7468 use advanced design techniques
to achieve very low power dissipation at high throughput rates.
5. Reference derived from the power supply.
The reference for the part is taken internally from VDD. This
allows the widest dynamic input range to the ADC. Thus, the
analog input range for the part is 0 V to VDD. The conversion
rate is determined by the SCLK.
6. No pipeline delay. The part features a standard successive
approximation ADC with accurate control of the conversions
via a CS input.
*Patent pending
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
AD7466/AD7467/AD7468
(VDD = 1.6 V to 3.6 V, fSCLK = 3.4 MHz, fSAMPLE = 100 kSPS, unless otherwise noted;
AD7466–SPECIFICATIONS1 TA = TMIN to TMAX, unless otherwise noted.)
Parameter
B Version
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
fIN = 30 kHz sine wave
1.8 V ≤ VDD ≤ 2 V
2.5 V ≤ VDD ≤ 3.6 V
VDD = 1.6 V
1.8 V ≤ VDD ≤ 2 V
1.8 V ≤ VDD ≤ 2 V
2.5 V ≤ VDD ≤ 3.6 V
VDD = 1.6 V
Signal-to-Noise + Distortion (SINAD)2
69
dB min
dB min
dB typ
dB min
dB typ
dB min
dB typ
dB typ
dB typ
70
70
Signal-to-Noise Ratio (SNR)2
70
71
71
70.5
–83
–85
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second Order Terms
fa = 29.1 kHz, fb = 29.9 kHz
–84
–86
10
dB typ
Third Order Terms
dB typ
Aperture Delay
Aperture Jitter
ns typ
40
ps typ
Full Power Bandwidth
3.2
1.9
750
450
MHz typ
MHz typ
kHz typ
kHz typ
@ 3 dB, 2.5 V ≤ VDD ≤ 3.6 V
@ 3 dB, 1.6 V ≤ VDD ≤ 2.2 V
@ 0.1 dB, 2.5 V ≤ VDD ≤ 3.6 V
@ 0.1 dB, 1.6 V ≤ VDD ≤ 2.2 V
DC ACCURACY
Maximum specifications apply as typical
figures when VDD = 1.6 V
Resolution
12
Bits
Integral Nonlinearity2
Differential Nonlinearity2
Offset Error2
1.5
LSB max
LSB max
LSB max
LSB max
LSB max
–0.9/+1.5
Guaranteed no missed codes to 12 bits
1
1
2
Gain Error2
Total Unadjusted Error (TUE)2
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to VDD
V
1
µA max
20
pF typ
LOGIC INPUTS
Input High Voltage, VINH
0.7 ꢀ VDD
V min
V min
V max
V max
V max
µA max
µA typ
pF max
1.6 V ≤ VDD < 2.7 V
2
2.7 V ≤ VDD ≤ 3.6 V
Input Low Voltage, VINL
0.2 ꢀ VDD
0.3 ꢀ VDD
0.8
1
1
10
1.6 V ≤ VDD < 1.8 V
1.8 V ≤ VDD < 2.7 V
2.7 V ≤ VDD ≤ 3.6 V
Input Current, IIN, SCLK Pin
Typically 20 nA, VIN = 0 V or VDD
Input Current, IIN, CS Pin
3
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
VDD – 0.2
0.2
1
V min
ISOURCE = 200 µA; VDD = 1.6 V to 3.6 V
ISINK = 200 µA
V max
µA max
pF max
10
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
Throughput Rate
4.70
200
µs max
kSPS max
16 SCLK cycles with SCLK at 3.4 MHz
See Serial Interface section
–2–
REV. 0
AD7466/AD7467/AD7468
AD7466–SPECIFICATIONS1 (continued)
Parameter
B Version
Unit
Test Conditions/Comments
POWER REQUIREMENTS
VDD
1.6/3.6
V min/max
IDD
Digital I/Ps = 0 V or VDD
Normal Mode (Operational)4
300
110
20
µA max
µA typ
µA typ
VDD = 3 V, fSAMPLE = 100 kSPS
VDD = 3 V, fSAMPLE = 50 kSPS
VDD = 3 V, fSAMPLE = 10 kSPS
240
80
16
µA max
µA typ
µA typ
VDD = 2.5 V, fSAMPLE = 100 kSPS
VDD = 2.5 V, fSAMPLE = 50 kSPS
VDD = 2.5 V, fSAMPLE = 10 kSPS
165
50
10
µA max
µA typ
µA typ
VDD = 1.8 V, fSAMPLE = 100 kSPS
VDD = 1.8 V, fSAMPLE = 50 kSPS
VDD = 1.8 V, fSAMPLE = 10 kSPS
Power-Down
0.1
µA max
SCLK on or off, typically 8 nA
Power Dissipation5
Normal Mode (Operational)
0.9
0.6
0.3
0.3
mW max
mW max
mW max
µW max
VDD = 3 V, fSAMPLE = 100 kSPS
VDD = 2.5 V, fSAMPLE = 100 kSPS
V
DD = 1.8 V, fSAMPLE = 100 kSPS
Power-Down
VDD = 3 V
NOTES
1Temperature range for B Version –40°C to +85°C.
2See Terminology section.
3Sample tested at 25°C to ensure compliance.
4See TPC 10.
5See Power Consumption section.
Specifications subject to change without notice.
(VDD = 1.6 V to 3.6 V, fSCLK = 3.4 MHz, fSAMPLE = 100 kSPS, unless otherwise noted;
AD7467–SPECIFICATIONS1 TA = TMIN to TMAX, unless otherwise noted.)
Parameter
B Version
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Maximum/minimum specifications apply
as typical figures when VDD = 1.6 V
fIN = 30 kHz sine wave
Signal-to-Noise + Distortion (SINAD)2
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second Order Terms
61
–72
–74
dB min
dB max
dB max
fa = 29.1 kHz, fb = 29.9 kHz
–83
–83
10
dB typ
dB typ
ns typ
Third Order Terms
Aperture Delay
Aperture Jitter
Full Power Bandwidth
40
ps typ
3.2
1.9
750
450
MHz typ
MHz typ
kHz typ
kHz typ
@ 3 dB, 2.5 V ≤ VDD ≤ 3.6 V
@ 3 dB, 1.6 V ≤ VDD ≤ 2.2 V
@ 0.1 dB, 2.5 V ≤ VDD ≤ 3.6 V
@ 0.1 dB, 1.6 V ≤ VDD ≤ 2.2 V
DC ACCURACY
Maximum specifications apply as typical
figures when VDD = 1.6 V.
Resolution
10
0.5
0.5
0.2
0.2
1
Bits
Integral Nonlinearity2
Differential Nonlinearity2
Offset Error2
LSB max
LSB max
LSB max
LSB max
LSB max
Guaranteed no missed codes to 10 bits
Gain Error2
Total Unadjusted Error (TUE)2
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to VDD
1
20
V
µA max
pF typ
REV. 0
–3–
AD7466/AD7467/AD7468
AD7467–SPECIFICATIONS1 (continued)
Parameter
B Version
Unit
Test Conditions/Comments
LOGIC INPUTS
Input High Voltage, VINH
0.7 ꢀ VDD
2
0.2 ꢀ VDD
0.3 ꢀ VDD
0.8
1
1
V min
V min
V max
V max
V max
µA max
µA typ
pF max
1.6 V ≤ VDD < 2.7 V
2.7 V ≤ VDD ≤ 3.6 V
Input Low Voltage, VINL
1.6 V ≤ VDD < 1.8 V
1.8 V ≤ VDD < 2.7 V
2.7 V ≤ VDD ≤ 3.6 V
Input Current, IIN, SCLK Pin
Input Current, IIN, CS Pin
Input Capacitance, CIN
Typically 20 nA, VIN = 0 V or VDD
3
10
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
VDD – 0.2
0.2
1
V min
ISOURCE = 200 µA; VDD = 1.6 V to 3.6 V
ISINK = 200 µA
V max
µA max
pF max
10
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
Throughput Rate
3.52
275
µs max
kSPS max
12 SCLK cycles with SCLK at 3.4 MHz
See Serial Interface section
POWER REQUIREMENTS
VDD
1.6/3.6
V min/max
IDD
Digital I/Ps = 0 V or VDD
VDD = 3 V, fSAMPLE = 100 kSPS
VDD = 2.5 V, fSAMPLE = 100 kSPS
Normal Mode (Operational)
210
170
140
0.1
µA max
µA max
µA max
µA max
V
DD = 1.8 V, fSAMPLE = 100 kSPS
Power-Down
SCLK on or off, typically 8 nA
Power Dissipation4
Normal Mode (Operational)
0.63
0.42
0.25
mW max
mW max
mW max
VDD = 3 V, fSAMPLE = 100 kSPS
VDD = 2.5 V, fSAMPLE = 100 kSPS
VDD = 1.8 V, fSAMPLE = 100 kSPS
Power-Down
0.3
µW max
VDD = 3 V
NOTES
1Temperature range for B Version –40°C to +85°C.
2See Terminology section.
3Sample tested at 25°C to ensure compliance.
4See Power Consumption section.
Specifications subject to change without notice.
(VDD = 1.6 V to 3.6 V, fSCLK = 3.4 MHz, fSAMPLE = 100 kSPS, unless otherwise noted;
AD7468–SPECIFICATIONS1 TA = TMIN to TMAX, unless otherwise noted.)
Parameter
B Version
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
Maximum/minimum specifications apply
as typical figures when VDD = 1.6 V
f
IN = 30 kHz sine wave
Signal-to-Noise + Distortion (SINAD)2
Total Harmonic Distortion (THD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second Order Terms
49
dB min
dB max
dB max
–66
–66
fa = 29.1 kHz, fb = 29.9 kHz
–77
–77
10
dB typ
Third Order Terms
dB typ
Aperture Delay
ns typ
Aperture Jitter
40
ps typ
Full Power Bandwidth
3.2
1.9
750
450
MHz typ
MHz typ
kHz typ
kHz typ
@ 3 dB, 2.5 V ≤ VDD ≤ 3.6 V
@ 3 dB, 1.6 V ≤ VDD ≤ 2.2 V
@ 0.1 dB, 2.5 V ≤ VDD ≤ 3.6 V
@ 0.1 dB, 1.6 V ≤ VDD ≤ 2.2 V
–4–
REV. 0
AD7466/AD7467/AD7468
AD7468–SPECIFICATIONS1 (continued)
Parameter
B Version
Unit
Test Conditions/Comments
DC ACCURACY
Maximum specifications apply as typical
figures when VDD = 1.6 V
Resolution
8
Bits
Integral Nonlinearity2
Differential Nonlinearity2
Offset Error2
0.2
0.2
0.1
0.1
0.3
LSB max
LSB max
LSB max
LSB max
LSB max
Guaranteed no missed codes to 8 bits
Gain Error2
Total Unadjusted Error (TUE)2
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to VDD
V
1
µA max
pF typ
20
LOGIC INPUTS
Input High Voltage, VINH
0.7 ꢀ VDD
V min
V min
V max
V max
V max
µA max
µA typ
pF max
1.6 V ≤ VDD < 2.7 V
2
2.7 V ≤ VDD ≤ 3.6 V
Input Low Voltage, VINL
0.2 ꢀ VDD
1.6 V ≤ VDD < 1.8 V
0.3 ꢀ VDD
1.8 V ≤ VDD < 2.7 V
0.8
1
2.7 V ≤ VDD ≤ 3.6 V
Input Current, IIN, SCLK Pin
Typically 20 nA, VIN = 0 V or VDD
Input Current, IIN, CS Pin
1
3
Input Capacitance, CIN
10
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3
Output Coding
VDD – 0.2
V min
ISOURCE = 200 µA; VDD = 1.6 V to 3.6 V
ISINK = 200 µA
0.2
1
V max
µA max
pF max
10
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
Throughput Rate
2.94
320
µs max
10 SCLK cycles with SCLK at 3.4 MHz
See Serial Interface section
kSPS max
POWER REQUIREMENTS
VDD
1.6/3.6
V min/max
IDD
Digital I/Ps = 0 V or VDD
VDD = 3 V, fSAMPLE = 100 kSPS
Normal Mode (Operational)
190
155
120
0.1
µA max
µA max
µA max
µA max
V
V
DD = 2.5 V, fSAMPLE = 100 kSPS
DD = 1.8 V, fSAMPLE = 100 kSPS
Power-Down
SCLK on or off, typically 8 nA
Power Dissipation4
Normal Mode (Operational)
0.57
0.4
0.2
0.3
mW max
mW max
mW max
µW max
VDD = 3 V, fSAMPLE = 100 kSPS
V
V
DD = 2.5 V, fSAMPLE = 100 kSPS
DD = 1.8 V, fSAMPLE = 100 kSPS
Power-Down
VDD = 3 V
NOTES
1Temperature range for B Version –40°C to +85°C.
2See Terminology section.
3Sample tested at 25°C to ensure compliance.
4See Power Consumption section.
Specifications subject to change without notice.
REV. 0
–5–
AD7466/AD7467/AD7468
TIMING SPECIFICATIONS1 (VDD = 1.6 V to 3.6 V; TA = TMIN to TMAX, unless otherwise noted.)
Limit at TMIN, TMAX
AD7466/AD7467/AD7468
Parameter
Unit
Description
2
fSCLK
3.4
10
20
MHz max
kHz min3
kHz min3
kHz min3
1.6 V ≤ VDD ≤ 3 V
VDD = 3.3 V
VDD = 3.6 V
150
tCONVERT
16 × tSCLK
12 × tSCLK
10 × tSCLK
AD7466
AD7467
AD7468
Acquisition Time4
tQUIET
Acquisition time/power-up time from power-down
VDD = 1.6 V
1.8 V ≤ VDD ≤ 3.6 V
Minimum quiet time required between bus relinquish and start
of next conversion
780
640
10
ns max
ns max
ns min
t15
t26
t36
t4
10
55
55
140
0.4 tSCLK
0.4 tSCLK
10
60
7
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
ns min
Minimum CS pulsewidth
CS to SCLK setup time
Delay from CS until SDATA three-state disabled
Data access time after SCLK falling edge
SCLK low pulsewidth
SCLK high pulsewidth
SCLK to data valid hold time
SCLK falling edge to SDATA three-state
SCLK falling edge to SDATA three-state
t5
t66
t77
t8
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.4 V.
2Mark/space ratio for the SCLK input is 40/60 to 60/40.
3Minimum fSCLK at which specifications are guaranteed.
4See Terminology section. The acquisition time is the time required for the part to acquire a full-scale step input value within 1 LSB or a 30 kHz ac input value
within 0.5 LSB.
5If VDD = 1.6 V and fSCLK = 3.4 MHz, t2 has to be 192 ns minimum in order to meet the maximum figure for the acquisition time.
6Measured with the load circuit of Figure 1 and defined as the time required for the output to cross the VIH or VIL voltage.
7t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
200A
I
OL
TO OUTPUT
PIN
1.4V
C
50pF
L
200A
I
OH
Figure 1. Load Circuit for Digital Output Timing Specifications
–6–
REV. 0
AD7466/AD7467/AD7468
Figures 2 and 3 show some of the timing parameters from the
Timing Specifications section.
Timing Example 2
The AD7466 can also operate with slower clock frequencies.
From Figure 3, assuming VDD = 1.8 V, fSCLK = 2 MHz, and a
throughput of 50 kSPS gives a cycle time of tCONVERT + t8 +
tQUIET = 20 µs. With tCONVERT = t2 + 15(1/fSCLK) = 55 ns + 7.5 µs
= 7.55 µs, and t8 = 60 ns max, this leaves tQUIET to be 12.39 µs,
which satisfies the requirement of 10 ns for tQUIET. The part is
fully powered up and the signal is fully acquired at Point A,
which means the acquisition/power-up time is t2 + 2(1/fSCLK) =
55 ns + 1 µs = 1.05 µs, satisfying the maximum requirement of
640 ns for the power-up time. As in this example and with
other slower clock values, the part will be fully powered up
and the signal will already be acquired before the third SCLK
falling edge; however, the track-and-hold will not go into hold
mode until that point. In this example, the part may be pow-
ered up and the signal may be fully acquired at approximately
point B in Figure 3.
Timing Example 1
From Figure 3, having fSCLK = 3.4 MHz and a throughput of
100 kSPS gives a cycle time of tCONVERT + t8 + tQUIET = 10 µs.
Assuming VDD = 1.8 V, tCONVERT = t2 + 15(1/fSCLK) = 55 ns +
4.41 µs = 4.46 µs, and t8 = 60 ns max, then tQUIET = 5.48 µs,
which satisfies the requirement of 10 ns for tQUIET. The part is
fully powered up and the signal is fully acquired at Point A.
This means that the acquisition/power-up time is t2 + 2(1/fSCLK
= 55 ns + 588 ns = 643 ns, satisfying the maximum require-
ment of 640 ns for the power-up time.
)
t1
CS
tCONVERT
t2
t6
A
SCLK
1
2
3
4
5
13
14
t5
15
16
t8
t3
t4
t7
tQUIET
SDATA
Z
ZERO
ZERO
ZERO
DB11
DB10
DB2
DB1
DB0
THREE-
STATE
THREE-STATE
4 LEADING ZEROS
Figure 2. AD7466 Serial Interface Timing Diagram
CS
tCONVERT
t2
B
A
SCLK
1
2
3
4
5
13
14
15
16
t8
tQUIET
ACQUISITION TIME
AUTOMATIC
POWER-DOWN
TRACK-AND-HOLD
IN TRACK
TRACK-AND-HOLD IN HOLD
1/THROUGHPUT
POINT A: THE PART IF FULLY POWERED UP WITH V FULLY ACQUIRED.
IN
Figure 3. AD7466 Serial Interface Timing Example
REV. 0
–7–
AD7466/AD7467/AD7468
ABSOLUTE MAXIMUM RATINGS1
Lead Temperature, Soldering
(TA = 25°C, unless otherwise noted.)
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 kV
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V
Digital Input Voltage to GND . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Output Voltage to GND . . . . . –0.3 V to VDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . . . 10 mA
Operating Temperature Range
Commercial (B Version) . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . +150°C
SOT-23 Package
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional opera-
tion of the device at these or any other conditions above those listed in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . 229.6°C/W
θ
JC Thermal Impedance . . . . . . . . . . . . . . . . . . . 91.99°C/W
MSOP Package
θ
θ
JA Thermal Impedance . . . . . . . . . . . . . . . . . . . 205.9°C/W
JC Thermal Impedance . . . . . . . . . . . . . . . . . . . 43.74°C/W
ORDERING GUIDE
Temperature
Range
Linearity
Package
Option2
Model
Error (LSB)1
Branding
AD7466BRT-REEL
AD7466BRT-REEL7
AD7466BRT-RL2
AD7466BRM
AD7466BRM-REEL
AD7466BRM-REEL7
AD7467BRT-REEL
AD7467BRT-REEL7
AD7467BRT-RL2
AD7467BRM
AD7467BRM-REEL
AD7467BRM-REEL7
AD7468BRT-REEL
AD7468BRT-REEL7
AD7468BRT-RL2
AD7468BRM
AD7468BRM-REEL
AD7468BRM-REEL7
EVAL-AD7466CB3
EVAL-AD7467CB3
EVAL-CONTROL BRD24
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
1.5 max
1.5 max
1.5 max
1.5 max
1.5 max
1.5 max
0.5 max
0.5 max
0.5 max
0.5 max
0.5 max
0.5 max
0.2 max
0.2 max
0.2 max
0.2 max
0.2 max
0.2 max
RT-6
RT-6
RT-6
RM-8
RM-8
RM-8
RT-6
RT-6
RT-6
RM-8
RM-8
RM-8
RT-6
RT-6
RT-6
RM-8
CLB
CLB
CLB
CLB
CLB
CLB
CMB
CMB
CMB
CMB
CMB
CMB
CNB
CNB
CNB
CNB
CNB
CNB
RM-8
RM-8
Evaluation Board
Evaluation Board
NOTES
1Linearity error here refers to integral nonlinearity.
2RT = SOT-23, RM = MSOP.
3This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.
4This board is a complete unit that allows a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designator. To order a
complete evaluation kit, you will need to order a particular ADC evaluation board, e.g., EVAL-AD7466CB, the EVAL-CONTROL BRD2, and a 12 V ac trans-
former. See relevant evaluation board technical note for more information.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD7466/AD7467/AD7468 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
–8–
REV. 0
AD7466/AD7467/AD7468
PIN CONFIGURATION
6-Lead SOT-23 8-Lead MSOP
1
2
3
4
8
7
6
5
V
DD
1
6
CS
CS
V
DD
AD7466
AD7467
AD7468
AD7466
AD7467
AD7468
2
3
5
4
SDATA
SCLK
GND
SDATA
SCLK
NC
GND
V
V
IN
IN
TOP VIEW
TOP VIEW
(Not to Scale)
NC
(Not to Scale)
NC = NO CONNECT
PIN FUNCTION DESCRIPTION
Mnemonic Function
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7466/
AD7467/AD7468 and frames the serial data transfer.
VDD
Power Supply Input. The VDD range for the AD7466/AD7467/AD7468 is from 1.6 V to 3.6 V.
GND
Analog Ground. Ground reference point for all circuitry on the AD7466/AD7467/AD7468. All analog input signals
should be referred to this GND voltage.
VIN
Analog Input. Single-ended analog input channel. The input range is 0 V to VDD.
SDATA
Data Out. Logic output. The conversion result from the AD7466/AD7467/AD7468 is provided on this output as a
serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream from the AD7466
consists of four leading zeros followed by the 12 bits of conversion data, provided MSB first. The data stream from the
AD7467 consists of four leading zeros followed by the 10 bits of conversion data, provided MSB first. The data stream
from the AD7468 consists of four leading zeros followed by the eight bits of conversion data, provided MSB first.
SCLK
NC
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also
used as the clock source for the AD7466/AD7467/AD7468’s conversion process.
No Connect.
REV. 0
–9–
AD7466/AD7467/AD7468
TERMINOLOGY
Integral Nonlinearity (INL)
errors occur due to integral and differential nonlinearities, inter-
nal ac noise sources, and so on.
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. For the
AD7466/AD7467/AD7468 the endpoints of the transfer func-
tion are zero scale, a point 1 LSB below the first code transition,
and full scale, a point 1 LSB above the last code transition.
Signal-to-(Noise + Distortion) Ratio (SINAD)
This is the measured ratio of signal-to-(noise + distortion) at
the output of the A/D converter. The signal is the rms value of
the sine wave and noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), including
harmonics, but excluding dc.
Differential Nonlinearity (DNL)
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Total Unadjusted Error (TUE)
This is a comprehensive specification that includes gain error,
linearity error, and offset error.
Offset Error
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Total Harmonic Distortion (THD)
Total harmonic distortion is the ratio of the rms sum of harmonics
to the fundamental. For the AD7466/AD7467/AD7468, it is
defined as
Gain Error
This is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (i.e., VREF – 1 LSB) after the
offset error has been adjusted out.
V22 +V32 +V42 +V52 +V62
THD (dB) = 20log
Track-and-Hold Acquisition Time
V
1
The track-and-hold acquisition time is the time required for the
part to acquire a full-scale step input value within 1 LSB or a
30 kHz ac input value within 0.5 LSB. For the AD7466/
AD7467/AD7468, the part enters track mode on the CS falling
edge, and returns to hold mode on the third SCLK falling edge.
The part remains in hold mode until the following CS falling
edge. See Figure 3 and the Serial Interface section for more
details.
where V1 is the rms amplitude of the fundamental, and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through
sixth harmonics.
Peak Harmonic or Spurious Noise (SFDR)
Peak harmonic or spurious noise is the ratio of the rms value of
the next largest component in the ADC output spectrum (up to
fS/2 and excluding dc) to the rms value of the fundamental.
Normally, the value of this specification is determined by the
largest harmonic in the spectrum, but for ADCs where the
harmonics are buried in the noise floor, it will be a noise peak.
Signal-to-Noise Ratio (SNR)
This is the measured ratio of signal to noise at the output of the
A/D converter. The signal is the rms value of the sine wave
input. Noise is the rms quantization error within the Nyquist
bandwidth (fS/2). The rms value of the sine wave is one half its
peak-to-peak value divided by √2 and the rms value for the
quantization noise is q/√12. The ratio is dependent on the num-
ber of quantization levels in the digitization process; the more
levels, the smaller the quantization noise.
Intermodulation Distortion (IMD)
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa nfb where
m, n = 0, 1, 2, 3, and so on. Intermodulation distortion terms
are those for which neither m nor n are equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb), and
(fa – 2fb).
For an ideal N-bit converter, the SNR is defined as:
SNR = 6.02N + 1.76 dB
The AD7466/AD7467/AD7468 are tested using the CCIF
standard where two input frequencies are used. In this case, the
second order terms are usually distanced in frequency from the
original sine waves, while the third order terms are usually at a
frequency close to the input frequencies. As a result, the second
and third order terms are specified separately. The calculation
of the intermodulation distortion is as per the THD specification,
where it is the ratio of the rms sum of the individual distortion
products to the rms amplitude of the sum of the fundamentals,
expressed in dBs.
Thus, for a 12-bit converter, this is 74 dB; for a 10-bit converter,
it is 62 dB; and for an 8-bit converter, it is 50 dB.
Practically, though, various error sources in the ADC cause the
measured SNR to be less than the theoretical value. These
–10–
REV. 0
Typical Performance Characteristics–AD7466/AD7467/AD7468
PERFORMANCE CURVES
DC Accuracy Curves
Dynamic Performance Curves
TPC 8 and TPC 9 show typical INL and DNL performance for
the AD7466.
TPC 1, TPC 2, and TPC 3 show typical FFT plots for the
AD7466, AD7467, and AD7468, respectively, at 100 kSPS
sample rate and 30 kHz input tone.
Power Requirements Curves
TPC 10 shows the supply current versus supply voltage for the
AD7466 at –40°C, +25°C, and +85°C, with SCLK frequency
of 3.4 MHz and a sampling rate of 100 kSPS.
TPC 4 shows the Signal-to-(Noise + Distortion) Ratio per-
formance versus input frequency for various supply voltages
while sampling at 100 kSPS with a SCLK frequency of 3.4 MHz
for the AD7466.
TPC 11 shows the maximum current versus supply voltage for
the AD7466 with different SCLK frequencies.
TPC 5 shows the Signal-to-Noise Ratio (SNR) performance
versus input frequency for various supply voltages while sam-
pling at 100 kSPS with a SCLK frequency of 3.4 MHz for
the AD7466.
TPC 12 shows the shutdown current versus supply voltage.
TPC 13 shows the power consumption versus throughput
rate for the AD7466 with a SCLK of 3.4 MHz and differ-
ent supply voltages.
TPC 6 shows a graph of the Total Harmonic Distortion versus
analog input signal frequency for various supply voltages while
sampling at 100 kSPS with a SCLK frequency of 3.4 MHz for
the AD7466.
See the Power Consumption section for more details.
TPC 7 shows a graph of the Total Harmonic Distortion versus
analog input frequency for different source impedances when using
a supply voltage of 2.7 V, a SCLK frequency of 3.4 MHz, and
sampling at a rate of 100 kSPS for the AD7466. See the Analog
Input section.
15
25
8192 POINT FFT
8192 POINT FFT
V
f
= 1.8V
V
= 1.8V
DD
DD
= 100kSPS
f
= 100kSPS
SAMPLE
SAMPLE
5
–15
–35
–55
–75
–95
–115
–5
–25
f
= 30kHz
f
= 30kHz
IN
IN
SINAD = 70.82dB
THD = –84.18dB
SFDR = –85.48dB
SINAD = 61.51dB
THD = –80.61dB
SFDR = –82.10dB
–45
–65
–85
–105
0
5
10
15
20
25
30
35
40
45
50
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY (kHz)
FREQUENCY (kHz)
TPC 2. AD7467 Dynamic Performance at 100 kSPS
TPC 1. AD7466 Dynamic Performance at 100 kSPS
REV. 0
–11–
AD7466/AD7467/AD7468
–65
–67
–69
–71
–73
–75
–77
–79
–81
–83
–85
5
8192 POINT FFT
TEMP = 25؇C
V
f
= 1.8V
DD
–5
= 100kSPS
SAMPLE
f
= 30kHz
IN
–15
–25
–35
–45
–55
–65
–75
–85
–95
SINAD = 49.83dB
THD = –79.37dB
SFDR = –70.46dB
V
= 1.8V
DD
V
= 2.2V
DD
V
= 1.6V
DD
V
= 3V
DD
V
= 3.6V
V
= 2.7V
DD
DD
0
5
10
15
20
25
30
35
40
45
50
10
100
FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
TPC 3. AD7468 Dynamic Performance at 100 kSPS
TPC 6. THD vs. Analog Input Frequency at 100 kSPS for
Various Supply Voltages
–76
–65
TEMP = 25؇C
DD
TEMP = 25؇C
V
= 2.7V
–77
–78
–79
–80
–81
–82
–83
–84
–66
–67
–68
–69
R
= 1k⍀
IN
R
= 10⍀
IN
V
= 1.8V
V
= 1.6V
V
= 2.2V
DD
DD
DD
–70
–71
–72
–73
R
= 510⍀
R
= 100⍀
IN
IN
V
= 3.6V
V
= 3V
V
= 2.7V
DD
DD
DD
R
= 0⍀
IN
10
100
10
100
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
TPC 4. AD7466 SINAD vs. Analog Input Frequency
at 100 kSPS for Various Supply Voltages
TPC 7. THD vs. Analog Input Frequency for Various
Source Impedances
1.0
–68.0
V
= 1.8V
TEMP = 25؇C
DD
TEMP = 25؇C
fIN = 50Hz
0.8
0.6
–68.5
fSAMPLE = 100kSPS
–69.0
–69.5
–70.0
0.4
0.2
V
= 1.6V
DD
V
= 1.8V
DD
0
–70.5
–71.0
–71.5
–72.0
–72.5
–73.0
V
= 2.2V
DD
–0.2
–0.4
–0.6
–0.8
–1.0
V
= 3.6V
V
= 3V
V
= 2.7V
DD
DD
DD
0
512
1024 1536 2048 2560 3072 3584
CODE
4096
10
100
INPUT FREQUENCY (kHz)
TPC 5. AD7466 SNR vs. Analog Input Frequency
at 100 kSPS for Various Supply Voltages
TPC 8. AD7466 INL Performance
–12–
REV. 0
AD7466/AD7467/AD7468
1.0
0.8
2.5
2.0
1.5
1.0
0.5
0
V
= 1.8V
DD
TEMP = 25؇C
fIN = 50Hz
fSAMPLE = 100kSPS
0.6
0.4
TEMP = +85؇C
0.2
0
–0.2
–0.4
–0.6
–0.8
TEMP = +25؇C
TEMP = –40؇C
0
512
1024 1536 2048 2560 3072 3584
CODE
4096
1.5
2.0
2.5
3.0
3.5
4.0
SUPPLY VOLTAGE (V)
TPC 9. AD7466 DNL Performance
TPC 12. Shutdown Current vs. Supply Voltage
290
265
240
215
190
165
140
115
90
1.4
fSAMPLE = 100kSPS
TEMP = –40؇C
TEMP = 25؇C
1.2
V
V
= 3.0V
= 2.7V
DD
TEMP = +25؇C
1.0
0.8
0.6
0.4
0.2
0
DD
V
V
= 2.2V
= 1.8V
DD
DD
TEMP = +85؇C
65
1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
SUPPLY VOLTAGE (V)
0
50
100
150
200
250
THROUGHPUT (kSPS)
TPC 10. Supply Current vs. Supply Voltage, SCLK 3.4 MHz
TPC 13. Power Consumption vs. Throughput Rate,
SCLK 3.4 MHz
560
TEMP = 25؇C
500
fSCLK = 3.4MHz, fSAMPLE = 200kSPS
440
fSCLK = 2.4MHz, fSAMPLE = 140kSPS
380
320
260
200
fSCLK = 1.2MHz, fSAMPLE = 50kSPS
140
80
1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8
SUPPLY VOLTAGE (V)
TPC 11. Maximum Current vs. Supply Voltage,
for Different SCLK Frequencies
REV. 0
–13–
AD7466/AD7467/AD7468
CIRCUIT INFORMATION
When the ADC starts a conversion (see Figure 5), SW2 will
open and SW1 will move to Position B, causing the comparator
to become unbalanced. The control logic and the charge redis-
tribution DAC are used to add and subtract fixed amounts of
charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is rebal-
anced, the conversion is complete. The control logic generates
the ADC output code. Figure 6 shows the ADC transfer function.
The AD7466/AD7467/AD7468 are fast, micropower, 12-/10-/
8-bit, A/D converters respectively. The parts can be operated
from a 1.6 V to 3.6 V supply. When operated from any supply
voltage within this range, the AD7466/AD7467/AD7468 are
capable of throughput rates of 200 kSPS when provided with a
3.4 MHz clock.
The AD7466/AD7467/AD7468 provide the user with an on-
chip track-and-hold, an A/D converter, and a serial interface
housed in a tiny 6-lead SOT-23 or 8-lead MSOP package,
which offer the user considerable space savings advantages over
alternative solutions. The serial clock input accesses data from
the part but also provides the clock source for the successive
approximation A/D converter. The analog input range is 0 V to
VDD. An external reference is not required for the ADC and
there is no on-chip reference. The reference for the AD7466/
AD7467/AD7468 is derived from the power supply, thus giving
the widest possible dynamic input range.
CHARGE
REDISTRIBUTION
DAC
SAMPLING
CAPACITOR
A
V
IN
CONTROL
LOGIC
SW1
SW2
CONVERSION
PHASE
B
COMPARATOR
AGND
V
/2
DD
Figure 5. ADC Conversion Phase
ADC TRANSFER FUNCTION
The output coding of the AD7466/AD7467/AD7468 is straight
binary. The designed code transitions occur at successive inte-
ger LSB values (i.e., 1 LSB, 2 LSB, and so on). The LSB size is
VDD/4096 for the AD7466, VDD/1024 for the AD7467, and
VDD/256 for the AD7468. The ideal transfer characteristic for
the AD7466/AD7467/AD7468 is shown in Figure 6.
The AD7466/AD7467/AD7468 also features an Automatic
Power-Down mode option to allow power savings between
conversions. The power-down feature is implemented across
the standard serial interface, as described in the Mode of
Operation section.
CONVERTER OPERATION
The AD7466/AD7467/AD7468 is a successive approximation
analog-to-digital converter based around a charge redistribution
DAC. Figures 4 and 5 show simplified schematics of the ADC.
Figure 4 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in position A, the comparator is held in a
balanced condition, and the sampling capacitor acquires the
signal on VIN.
111...111
111...110
111...000
011...111
1LSB = V /4096 (AD7466)
DD
CHARGE
REDISTRIBUTION
DAC
1LSB = V /1024 (AD7467)
DD
1LSB = V /256 (AD7468)
DD
000...010
000...001
000...000
SAMPLING
CAPACITOR
A
V
IN
0V 1LSB
+V – 1LSB
DD
CONTROL
LOGIC
SW1
B
ANALOG INPUT
ACQUISITION
PHASE
SW2
COMPARATOR
Figure 6. AD7466/AD7467/AD7468 Transfer Characteristic
AGND
V
/2
DD
Figure 4. ADC Acquisition Phase
–14–
REV. 0
AD7466/AD7467/AD7468
TYPICAL CONNECTION DIAGRAM
reference. Its tiny footprint, low power consumption, and the
additional shutdown capability make the ADR318 ideal for
battery-powered applications.
Figure 7 shows a typical connection diagram for the AD7466/
AD7467/AD7468. VREF is taken internally from VDD and there-
fore VDD should be well decoupled. This provides an analog
input range of 0 V to VDD
.
Table I. AD7466 Performance for
Various Voltage Reference ICs
The conversion result consists of four leading zeros followed by
the MSB of the 12-bit, 10-bit, or 8-bit result from the AD7466,
AD7467, or AD7468, respectively. See the Serial Interface
section. Alternatively, because the supply current required by
the AD7466/AD7467/AD7468 is so low, a precision reference can
be used as the supply source to the AD7466/AD7467/AD7468.
Reference Tied
to VDD
AD7466 SNR Performance (dB)
ADR318 @ 1.8 V
ADR370 @ 2.048 V
ADR421 @ 2.5 V
ADR423 @ 3 V
70.73
70.72
71.13
71.44
The REF19x series devices are precision micropower, low dropout
voltage references. For the AD7466/AD7467/AD7468 voltage
range operation, the REF193, REF192 , and REF191 can be
used to supply the required voltage to the ADC delivering 3 V,
2.5 V, and 2.048 V, respectively (see Figure 7). This configura-
tion is especially useful if the power supply is quite noisy or if
the system supply voltages are at some value other than 3 V or
2.5 V (e.g., 5 V). The REF19x will output a steady voltage to
the AD7466/AD7467/AD7468. If the low dropout REF192 is
used, when the AD7466 is converting at a rate of 100 kSPS, the
REF192 will need to supply a maximum of 240 µA to the
AD7466. The load regulation of the REF192 is typically
10 ppm/mA (REF192, VS = 5 V), which results in an error of
2.4 ppm (6 µV) for the 240 µA drawn from it. This corresponds to
a 0.0098 LSB error for the AD7466 with VDD = 2.5 V from the
REF192. For applications where power consumption is impor-
tant, the automatic power-down mode of the ADC and the sleep
mode of the REF19x reference should be used to improve power
performance. See the Mode of Operation section.
Analog Input
Figure 8 shows an equivalent circuit of the AD7466/AD7467/
AD7468 analog input structure. The two diodes, D1 and D2,
provide ESD protection for the analog inputs. Care must be
taken to ensure that the analog input signal never exceeds the
supply rails by more than 300 mV. This will cause these diodes
to become forward biased and start conducting current into the
substrate. Capacitor C1 in Figure 8 is typically about 4 pF and
can primarily be attributed to pin capacitance. The resistor R1
is a lumped component made up of the on resistance of a
switch. This resistor is typically about 200 Ω. The capacitor
C2 is the ADC sampling capacitor and has a capacitance of
20 pF typically.
V
DD
C2
20pF
D1
R1
V
IN
2.5V
1F
TANT
5V
SUPPLY
REF192
C1
4pF
D2 CONVERSION PHASE—SWITCH OPEN
TRACK PHASE—SWITCH CLOSED
0.1F
10F
0.1F
240A
680nF
V
DD
Figure 8. Equivalent Analog Input Circuit
0VTOV
DD
SCLK
V
IN
INPUT
For ac applications, removing high frequency components from
the analog input signal by using band-pass filter on the rel-
evant analog input pin is recommended. In applications where
harmonic distortion and signal-to-noise ratio are critical, the
analog input should be driven from a low impedance source.
Large source impedances will significantly affect the ac per-
formance of the ADC. This may necessitate the use of an
input buffer amplifier. The choice of the op amp will be a
function of the particular application.
C/P
AD7466
SDATA
GND
CS
SERIAL
INTERFACE
Figure 7. REF192 as Power Supply to AD7466
Table I provides some typical performance data with various
references used as a VDD source under the same setup condi-
tions. The ADR318, for instance, is a 1.8 V band gap voltage
REV. 0
–15–
AD7466/AD7467/AD7468
Table II provides typical performance data for various op amps
used as the input buffer under constant setup conditions.
the part begins to power up and the track-and-hold, which was
in hold while the part was in power down, will go into track mode.
The conversion is also initiated at this point. On the third
SCLK falling edge after the CS falling edge, the track-and-
hold will return to hold mode.
Table II. AD7466 Performance for Various Input Buffers
Op Amp in the
Input Buffer
AD7466 SNR Performance (dB)
30 kHz Input, VDD = 1.8 V
For the AD7466, 16 serial clock cycles are required to complete
the conversion and access the complete conversion result. The
AD7466 will automatically enter power-down mode on the 16th
SCLK falling edge.
AD8510
AD8610
AD797
70.75
71.45
71.42
For the AD7467, 14 serial clock cycles are required to complete
the conversion and access the complete conversion result. The
AD7467 will automatically enter power-down mode on the 14th
SCLK falling edge.
When no amplifier is used to drive the analog input, the source
impedance should be limited to low values. The maximum
source impedance will depend on the amount of total harmonic
distortion (THD) that can be tolerated. The THD will increase
as the source impedance increases and performance will degrade.
TPC 7 shows a graph of the total harmonic distortion versus
analog input signal frequency for different source impedances
when using a supply voltage of 2.7 V and sampling at a rate of
100 kSPS.
For the AD7468, 12 serial clock cycles are required to complete
the conversion and access the complete conversion result. The
AD7468 will automatically enter power-down mode on the 12th
SCLK falling edge.
The AD7466 will also enter power-down mode if CS is brought
high any time before the 16th SCLK falling edge. The conver-
sion that was initiated by the CS falling edge will be terminated
and SDATA will go back into three-state. This also applies for
the AD7467 and AD7468; if CS is brought high before the
conversion is complete (the 14th SCLK falling edge for the
AD7467 and the 12th SCLK falling edge for the AD7468), the
part will enter power-down, the conversion will be terminated,
and SDATA will go back into three-state.
Digital Inputs
The digital inputs applied to the AD7466/AD7467/AD7468 are
not limited by the maximum ratings that limit the analog inputs.
Instead, the digital inputs applied can go to 7 V and are not
restricted by the VDD + 0.3 V limit as on the analog input. For
example, if the AD7466/AD7467/AD7468 were operated with a
VDD of 3 V, 5 V logic levels could be used on the digital inputs.
However, it is important to note that the data output on SDATA
will still have 3 V logic levels when VDD = 3 V. Another advan-
tage of SCLK and CS not being restricted by the VDD + 0.3 V
limit is the fact that power supply sequencing issues are avoided.
If CS or SCLK is applied before VDD, there is no risk of latch-
up as there would be on the analog inputs if a signal greater
Although CS may idle high or low between conversions, to save
power, bringing CS high once the conversion is complete is
recommended.
When supplies are first applied to the AD7466/AD7467/
AD7468, a dummy conversion should be performed to ensure
that the part is in power-down mode, the track-and-hold is in
hold mode, and SDATA is in three-state.
than 0.3 V were applied prior to VDD
.
MODE OF OPERATION
Once a data transfer is complete (SDATA has returned to
three-state), another conversion can be initiated after the quiet
time, tQUIET, has elapsed by bringing CS low again.
The AD7466/AD7467/AD7468 automatically enters power-down
at the end of each conversion. This mode of operation is designed
to provide flexible power management options and to optimize the
power dissipation/throughput rate ratio for low power application
requirements. Figure 9 shows the general diagram of the opera-
tion for the AD7466/AD7467/AD7468. On the CS falling edge,
AD7468 ENTERS POWER-DOWN
AD7467 ENTERS POWER-DOWN
THE PART BEGINS
TO POWER UP
THE PART IS POWERED UP
AND V FULLY ACQUIRED
IN
AD7466 ENTERS POWER-DOWN
CS
1
2
3
12
14
16
SCLK
SDATA
VALID DATA
Figure 9. Normal Mode Operation
–16–
REV. 0
AD7466/AD7467/AD7468
POWER CONSUMPTION
This can be seen in Figure 10, which shows the supply current
versus SCLK frequency for various supply voltages at a through-
put rate of 100 kSPS. For a fixed throughput rate, the supply
current (average current) will drop as the SCLK frequency
increases because the part will be in power-down mode most
of the time. It can also be seen that for a lower supply voltage
the supply current drops accordingly.
The AD7466/AD7467/AD7468 automatically enters power-
down mode at the end of each conversion or if CS is brought
high before the conversion is finished.
When the AD7466/AD7467/AD7468 is in power-down mode,
all the analog circuitry is powered down and the current con-
sumption is typically 8 nA.
To achieve the lowest power dissipation, there are some consid-
erations the user should keep in mind.
390
fSAMPLE = 100kSPS
TEMP = 25؇C
360
330
300
270
240
210
180
150
120
90
The conversion time is determined by the serial clock frequency;
the faster the SCLK frequency, the shorter the conversion time.
This implies that as the frequency increases, the part will be dissi-
pating power for a shorter period of time, when the conversion is
taking place, and it will remain in power-down mode for a longer
percentage of the cycle time or throughput rate.
V
= 3.6V
= 3.0V
DD
DD
V
V
V
= 2.7V
= 1.8V
DD
DD
Figure 11 shows two AD7466s running with two different
SCLK frequencies, SCLK A and SCLK B, with SCLK A
having the higher SCLK frequency. For the same throughput
rate, the AD7466 using SCLK A will have a shorter conver-
sion time than the AD7466 using SCLK B, and it will remain
in power-down mode longer. The current consumption in
power-down mode is very low; therefore, the average power
consumption will be greatly reduced.
V
= 2.2V
DD
V
= 1.6V
2.4
DD
60
2.2
2.6
2.8
3.0
3.2
3.4
3.6
SCLK FREQUENCY (MHz)
Figure 10. Supply Current vs. SCLK Frequency for a
Fixed Throughput Rate and Different Supply Voltages
1/THROUGHPUT
CONVERSION TIME B
CONVERSION TIME A
CS
1
1
16
SCLK A
SCLK B
16
Figure 11. Conversion Time Comparison for Different SCLK Frequencies and a Fixed Throughput Rate
1/THROUGHPUT B
1/THROUGHPUT A
POWER DOWN TIME A
CONVERSION TIME A
CS A
POWER DOWN TIME B
CONVERSION TIME B
CS B
1
16
SCLK
Figure 12. Conversion Time vs. Power-Down Time for a Fixed SCLK Frequency and Different Throughput Rates
REV. 0
–17–
AD7466/AD7467/AD7468
TPC 13 shows power consumption versus throughput rate for a
3.4 MHz SCLK frequency. In this case, the conversion time
will be the same for all cases because the SCLK frequency is a
fixed parameter. Low throughput rates will lead to lower current
consumptions, with a higher percentage of the time in power-
down mode. Figure 12 shows two AD7466s running with the
same SCLK frequency but at different throughput rates. The A
throughput rate is higher than the B throughput rate. The
slower the throughput rate, the longer the period of time the
part will be in power-down mode, and the average power con-
sumption will drop accordingly.
The average power consumption includes the power dissipated
when the part is converting and the power dissipated when the
part is in power-down mode. The average power dissipated
during conversion is calculated as the percentage of the cycle
time spent when converting multiplied by the maximum current
during conversion. The average power dissipated in power-
down mode is calculated as the percentage of cycle time spent
in power-down mode multiplied by the current figure for
power-down mode. In order to obtain the value for the average
power, these terms must be multiplied by the voltage.
Considering the maximum current for each SCLK frequency for
Figure 13 shows power versus throughput rate for different
supply voltages and SCLK frequencies. For this plot, all the
elements regarding power consumption that were explained
previously (the influence of the SCLK frequency, the influence
of the throughput rate, and the influence of the supply voltage)
are taken into consideration.
V
DD = 1.8 V:
Power Consumption A = ((4.7/20) × 186 µA + (15.3/20) ×
100 nA) × 1.8 V = (43.71 + 0.076) µA × 1.8 V = 78.8 µW =
0.07 mW
Power Consumption B = ((13/20) × 108 µA + (7/20) ×
100 nA) × 1.8 V = (70.2 + 0.035) µA × 1.8 V = 126.42 µW
= 0.126 mW
1.4
TEMP = 25؇C
It can be concluded that for a fixed throughput rate, the average
power consumption drops as the SCLK frequency increases.
1.2
V
= 3.0V, SCLK = 2.4MHz
DD
Power Consumption Example 2
1.0
0.8
0.6
0.4
0.2
0
This example shows that for a fixed SCLK frequency, as the
throughput rate decreases, the average power consumption
drops. From Figure 12, for SCLK = 3.4 MHz, Throughput A =
100 kSPS (which gives a cycle time of 10 µs) and Throughput B =
50 kSPS (which gives a cycle time of 20 µs) the following values
can be obtained:
V
= 3.0V, SCLK = 3.4MHz
DD
V
= 1.8V, SCLK = 2.4MHz
DD
Conversion Time A = 16
؋
(1/SCLK) = 4.7 µs (47% of the cycle time for a throughput of 100 kSPS)
V
= 1.8V, SCLK = 3.4MHz
DD
Power-Down Time A = (1/Throughput A) – Conversion
Time A = 10 µs – 4.7 µs = 5.3 µs (53% of the cycle time)
0
50
100
150
200
250
THROUGHPUT (kSPS)
Figure 13. Power vs. Throughput Rate for Different
SCLK and Supply Voltages
Conversion Time B = 16 × (1/SCLK) = 4.7 µs (23.5% of
the cycle time for a throughput of 50 kSPS)
The following two examples illustrate through calculations what
has been explained in this section.
Power-Down Time B = (1/Throughput B) – Conversion
Time B = 20 µs – 4.7 µs = 15.3 µs (76.5% of the cycle time)
Power Consumption Example 1
The average power consumption is calculated as explained
in Power Consumption Example 1, considering the maximum
current for a 3.4 MHz SCLK frequency for VDD = 1.8 V.
This example shows that for a fixed throughput rate, as the
SCLK frequency increases, the average power consumption
drops. From Figure 11, having SCLK A = 3.4 MHz, SCLK B =
1.2 MHz, and a throughput rate of 50 kSPS, which gives a cycle
time of 20 µs, the following values can be obtained:
Power Consumption A = ((4.7/10) × 186 µA + (5.3/10) ×
100 nA) × 1.8 V= (87.42 + 0.053) µA × 1.8 V = 157.4 µW
= 0.157 mW
Conversion Time A = 16 × (1/SCLK A) = 4.7 µs (23.5% of
the cycle time)
Power Consumption B = ((4.7/20) × 186 µA + (15.3/20) ×
100 nA) × 1.8 V = (43.7 + 0.076) µA × 1.8 V = 78.79 µW
= 0.078 mW
Power-Down Time A = (1/Throughput) – Conversion
Time A = 20 µs – 4.7 µs = 15.3 µs (76.5% of the cycle time)
It can be concluded that for a fixed SCLK frequency, the aver-
age power consumption drops as the throughput rate decreases.
Conversion Time B = 16 × (1/SCLK B) = 13 µs (65% of
the cycle time)
Power-Down Time B = (1/Throughput) – Conversion
Time B = 20 µs – 13 µs = 7 µs (35% of the cycle time)
–18–
REV. 0
AD7466/AD7467/AD7468
SERIAL INTERFACE
clock cycles are required to perform the conversion process and
to access data from the AD7467.
Figures 14, 15, and 16 show the detailed timing diagrams for
serial interfacing to the AD7466/AD7467/AD7468. The serial
clock provides the conversion clock and controls the transfer of
information from the ADC during a conversion.
For the AD7468, the 12th SCLK falling edge will cause the
SDATA line to go back into three-state, and the part will enter
power-down. If the rising edge of CS occurs before 12 SCLKs
have elapsed, the conversion will be terminated, the SDATA
line will go back into three-state, and the AD7468 will enter
power down; otherwise SDATA returns to three-state on the
12th SCLK falling edge, as shown in Figure 16. Twelve serial
clock cycles are required to perform the conversion process and
to access data from the AD7468.
The part begins to power up on the CS falling edge. The falling
edge of CS puts the track-and-hold into track mode and takes
the bus out of three-state. The conversion is also initiated at this
point. On the third SCLK falling edge after the CS falling edge,
the part should be fully powered up, as shown in Figure 14 at
point B, and the track-and-hold will return to hold.
For the AD7466, the SDATA line will go back into three-state
and the part will enter power-down on the 16th SCLK falling
edge. If the rising edge of CS occurs before 16 SCLKs have
elapsed, the conversion will be terminated, the SDATA line will
go back into three-state, and the part will enter power-down;
otherwise SDATA returns to three-state on the 16th SCLK
falling edge, as shown in Figure 14. Sixteen serial clock cycles
are required to perform the conversion process and to access
data from the AD7466.
CS going low provides the first leading zero to be read in by the
microcontroller or DSP. The remaining data is then clocked out
by subsequent SCLK falling edges, beginning with the second
leading zero; thus the first clock falling edge on the serial clock
has the first leading zero provided and also clocks out the second
leading zero. For the AD7466, the final bit in the data transfer
is valid on the 16th SCLK falling edge, having been clocked out
on the previous (15th) SCLK falling edge.
In applications with a slow SCLK, it is possible to read in data
on each SCLK rising edge. In such a case, the first falling edge
of SCLK after the CS falling edge will clock out the second
leading zero and could be read in the following rising edge. If
the first SCLK edge after the CS falling edge is a falling edge,
the first leading zero that was clocked out when CS went low
will be missed unless it is not read on the first SCLK falling
For the AD7467, the 14th SCLK falling edge will cause the
SDATA line to go back into three-state, and the part will enter
power-down. If the rising edge of CS occurs before 14 SCLKs
have elapsed, the conversion will be terminated, the SDATA
line will go back into three-state, and the AD7467 will enter
power-down; otherwise SDATA returns to three-state on the
14th SCLK falling edge, as shown in Figure 15. Fourteen serial
t1
CS
tCONVERT
t2
t6
B
SCLK
1
2
3
4
5
13
14
t5
15
16
t8
t3
ZERO
t4
t7
tQUIET
SDATA
Z
ZERO
ZERO
DB11
DB10
DB2
DB1
DB0
THREE-
STATE
THREE-STATE
4 LEADING ZEROS
12 BITS OF DATA
Figure 14. AD7466 Serial Interface Timing Diagram
t1
CS
tCONVERT
t2
t6
B
1
2
3
4
5
13
t5
14
SCLK
t8
t7
t3
tQUIET
t4
Z
ZERO
ZERO
ZERO
DB9
DB8
10 BITS OF DATA
DB0
SDATA
THREE-STATE
THREE-STATE
4 LEADING ZEROS
Figure 15. AD7467 Serial Interface Timing Diagram
t1
CS
tCONVERT
t2
t6
B
1
2
3
4
11
12
SCLK
t8
t5
t7
tQUIET
t3
t4
SDATA
Z
ZERO
ZERO
ZERO
DB7
DB0
8 BITS OF DATA
THREE-STATE
THREE-STATE
4 LEADING ZEROS
Figure 16. AD7468 Serial Interface Timing Diagram
–19–
REV. 0
AD7466/AD7467/AD7468
edge. The 15th falling edge of SCLK will clock out the last bit
and it could be read in the following rising SCLK edge.
AD7466/AD7467/AD7468 to ADSP-218x
The ADSP-218x family of DSPs is interfaced directly to the
AD7466/AD7467/AD7468 without any glue logic. The SPORT
control register should be set up as follows:
If the first SCLK edge after CS falling edge is a rising edge, CS
will clock out the first leading zero as before, and it may be read
on the SCLK rising edge. The next SCLK falling edge will
clock out the second leading zero, and it could be read on the
following rising edge.
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
ISCLK = 1, Internal Serial Clock
TFSR = RFSR= 1, Frame Every Word
IRFS = 0, Sets up RFS as an Input
ITFS = 1, Sets up TFS as an Output
SLEN = 1111, 16 Bits for the AD7466
SLEN = 1101, 14 Bits for the AD7467
SLEN = 1011, 12 Bits for the AD7468
MICROPROCESSOR INTERFACING
The serial interface on the AD7466/AD7467/AD7468 allows
the part to be connected directly to a range of many different
microprocessors. This section explains how to interface the
AD7466/AD7467/AD7468 with some of the more common
microcontroller and DSP serial interface protocols.
AD7466/AD7467/AD7468 to TMS320C541 Interface
The connection diagram is shown in Figure 18. The ADSP-218x
has the TFS and RFS of the SPORT tied together, with TFS
set as an output and RFS set as an input. The DSP operates in
alternate framing mode, and the SPORT control register is set
up as described. The frame synchronization signal generated on
the TFS is tied to CS, and as with all signal processing applica-
tions, equidistant sampling is necessary. However, in this example,
the timer interrupt is used to control the sampling rate of the
ADC and, under certain conditions, equidistant sampling may
not be achieved.
The serial interface on the TMS320C541 uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7466/AD7467/AD7468. The CS input allows easy interfac-
ing between the TMS320C541 and the AD7466/AD7467/
AD7468 without requiring any glue logic. The serial port of the
TMS320C541 is set up to operate in burst mode (FSM = 1 in the
serial port control register, SPC) with internal CLKX (MCM = 1
in the SPC register) and internal frame signal (TXM = 1 in the
SPC register), so both pins are configured as outputs. For the
AD7466, the word length should be set to 16 bits (FO = 0 in
the SPC register). The standard synchronous serial port inter-
face in this DSP only allows frames with a word length of 16 bits or
8 bits. Therefore, for the AD7467 and AD7468 where 14 and
12 bits are required, the FO bit also would be set up to 16 bits.
In these cases, the user should keep in mind that the last two
and four bits for the AD7467 and AD7468, respectively, will be
invalid data as the SDATA line goes back into three-state on the
14th and 12th SCLK falling edge.
The timer registers, for example, are loaded with a value that
will provide an interrupt at the required sample interval. When
an interrupt is received, a value is transmitted with TFS/DT
(ADC control word). The TFS is used to control the RFS and
therefore the reading of data. The frequency of the serial clock
is set in the SCLKDIV register. When the instruction to trans-
mit with TFS is given, i.e., AX0 = TX0, the state of the SCLK is
checked. The DSP will wait until the SCLK has gone high, low,
and high again before transmission will start. If the timer and
SCLK values are chosen such that the instruction to transmit
occurs on or near the rising edge of SCLK, the data may be
transmitted or it may wait until the next clock edge.
To summarize, the values in the SPC register are
FO = 0
FSM = 1
MCM = 1
TXM = 1
For example, the ADSP-2111 has a master clock frequency of
16 MHz. If the SCLKDIV register is loaded with the value 3,
an SCLK of 2 MHz is obtained, and eight master clock periods
will elapse for every SCLK period. If the timer registers are loaded
with the value 803, 100.5 SCLKs will occur between interrupts
and subsequently between transmit instructions. This situation
will result in nonequidistant sampling as the transmit instruction
is occurring on a SCLK edge. If the number of SCLKs between
interrupts is a whole integer figure of N, equidistant sampling
will be implemented by the DSP.
The connection diagram is shown in Figure 17. Note that for
signal processing applications, it is imperative that the frame
synchronization signal from the TMS320C541 provides equi-
distant sampling.
AD7466/
AD7467/
AD7468*
TMS320C541*
SCLK
CLKX
AD7466/
AD7467/
AD7468*
ADSP-218x*
CLKR
DR
SDATA
SCLK
SCLK
CS
FSX
FSR
DR
SDATA
CS
RFS
TFS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 17. Interfacing to the TMS320C541
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 18. Interfacing to the ADSP-218x
–20–
REV. 0
AD7466/AD7467/AD7468
AD7466/AD7467/AD7468 to DSP563xx Interface
APPLICATION HINTS
The connection diagram in Figure 19 shows how the AD7466/
AD7467/AD7468 can be connected to the SSI (synchronous
serial interface) of the DSP563xx family of DSPs from Motorola.
The SSI is operated in synchronous and normal mode (SYN = 1
and MOD = 0 in the Control Register B, CRB) with an inter-
nally generated word frame sync for both Tx and Rx (bits FSL1 = 0
and FSL0 = 0 in the CRB register). Set the word length in the
Grounding and Layout
The printed circuit board that houses the AD7466/AD7467/
AD7468 should be designed such that the analog and digital
sections are separated and confined to certain areas of the
board. This facilitates the use of ground planes that can be
separated easily. A minimum etch technique is generally best
for ground planes because it gives the best shielding. Digital
and analog ground planes should be joined at only one place.
If the AD7466/AD7467/AD7468 is in a system where mul-
tiple devices require an AGND to DGND connection, the
connection should still be made at one point only, a star
ground point that should be established as close as possible
to the AD7466/AD7467/AD7468.
Control Register A (CRA) to 16 by setting bits WL2 = 0, WL1 = 1
and WL0 = 0 for the AD7466. The word length for the AD7468
can be set to 12 bits (WL2 = 0, WL1 = 0, and WL0 = 1). This
DSP does not offer the option for a 14-bits word length, so the
AD7467 word length will be set up to 16 bits like the AD7466’s.
In this case, the user should keep in mind that the last two bits
will be invalid data as the SDATA goes back into three-state on
the 14th SCLK falling edge.
,
Avoid running digital lines under the device because these will
couple noise onto the die. The analog ground plane should be
allowed to run under the AD7466/AD7467/AD7468 to avoid
noise coupling. The power supply lines to the AD7466/AD7467/
AD7468 should use as large a trace as possible to provide low
impedance paths and to reduce the effects of glitches on the
power supply line. Fast switching signals like clocks should be
shielded with digital ground to avoid radiating noise to other
sections of the board, and clock signals should never be run
near the analog inputs. Avoid crossover of digital and analog
signals. Traces on opposite sides of the board should run at
right angles to each other, which will reduce the effects of
feedthrough through the board. A microstrip technique is by
far the best choice but is not always possible with a double-
sided board. With this technique, the component side of the
board is dedicated to ground planes while signals are placed on
the solder side.
The FSP (frame sync polarity) bit in the CRB register can be set
to 1, which means the frame goes low and a conversion starts.
Likewise, by means of bits SCD2, SCKD, and SHFD in the
CRB register, it will be established that pins SC2 (the frame
sync signal) and SCK in the serial port will be configured as
outputs and the MSB will be shifted first.
To summarize,
MOD = 0
SYN = 1
WL2, WL1, WL0 depend on the word length
FSL1 = 0, FSL0 = 0
FSP = 1, Negative Frame Sync
SCD2 = 1
SCKD = 1
SHFD = 0
Good decoupling is also very important. All analog supplies
should be decoupled with 10 µF tantalum in parallel with 0.1 µF
capacitors to AGND. All digital supplies should have a 0.1 µF
ceramic disc capacitor to DGND. To achieve the best perfor-
mance from these decoupling components, the user should
attempt to keep the distance between the decoupling capacitor
and the VDD and GND pins to a minimum, with short track
lengths connecting the respective pins.
Note that for signal processing applications, it is imperative that
the frame synchronization signal from the DSP563xx provides
equidistant sampling.
AD7466/
AD7467/
AD7468*
DSP563xx*
SCLK
SCK
Evaluating the AD7466/AD7467 Performance
SRD
SC2
SDATA
The evaluation board package includes a fully assembled and
tested evaluation board, documentation, and software for
controlling the board from the PC via the eval-board control-
ler. To demonstrate/evaluate the ac and dc performance of the
AD7466/AD7467, the eval-board controller can be used in
conjunction with the AD7466/AD7467CB evaluation board, as
well as many other Analog Devices evaluation boards ending in
the CB designator.
CS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 19. Interfacing to the DSP563xx
The software allows the user to perform ac (fast Fourier
transform) and dc (histogram of codes) tests on the AD7466/
AD7467. See the evaluation board application note for more
information.
REV. 0
–21–
AD7466/AD7467/AD7468
OUTLINE DIMENSIONS
6-Lead Small Outline Transistor Package [SOT-23]
(RT-6)
Dimensions shown in millimeters
2.90 BSC
6
1
5
2
4
3
2.80 BSC
1.60 BSC
PIN 1
0.95 BSC
1.90
BSC
1.30
1.15
0.90
1.45 MAX
0.22
0.08
0.60
0.45
0.30
10؇
4؇
0؇
0.50
0.30
0.15 MAX
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-178AB
8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
3.00
BSC
8
5
4
4.90
BSC
3.00
BSC
1
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
0.80
0.40
8؇
0؇
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187AA
–22–
REV. 0
–23–
–24–
相关型号：
AD7467BRTZ-R2
1-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO6, MO-178-AB, SOT-23, 6 PIN
ADI
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