AD7467BRT [ADI]
1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23; 1.8 V ，微功耗，8 /10/ 12位ADC的6引脚SOT -23
| 型号： | AD7467BRT |
| 厂家： | 
ADI |
| 描述： | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| 文件： | 总15页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
pecifications
1.8V, Micro-Power,
a
Preliminary Technical Data
8/10/12-BitADCsin6LeadSOT-23
AD7466/AD7467/AD7468
FEATURES
F U NC T IO NAL B LO C K D IAG RAM
Specified for VDD of 1.8 V to 3.6 V
Low Pow er:
V
DD
0.9 m W m ax at 60 kSPS w ith 3.6 V Supplies
0.4 m W m ax at 100 kSPS w ith 1.8 V Supplies
Fast Throughput Rate: 100 kSPS
12/10/8-BIT
Wide Input Bandw idth:
V
T/H
SUCCESSIVE
APPROXIMATION
ADC
IN
70dB SNR at 30 kHz Input Frequency
Flexible Pow er/ Serial Clock Speed Managem ent
No Pipeline Delays
High Speed Serial Interface
SPI/ QSPI/ µWire/ DSP Com patible
SCLK
Standby Mode: 0.5 µA m ax
6-Lead SOT-23 Package and 8 lead µSOIC
CONTROL LOGIC
SDATA
CS
AD7466/67/68
APPLICATIONS
Battery Pow ered System s
Medical Instrum ents
Ram ote Data Acquisition
Isolated Data Acquisition
GND
P R O D U C T H IG H LIG H T S
1. Specified for Supply voltages of 1.8 V to 3.6 V
G E NE R AL D E S C R IP T IO N
T he AD 7466/AD 7467/AD 7468 are 12/10/8-bit, high
speed, low power, successive-approximation ADCs re-
spectively. T he parts operate from a single 1.8 V to 3.6 V
power supply and feature throughput rates up to 100
kSPS. T he parts contain a low-noise, wide bandwidth
track/hold amplifier which can handle input frequencies in
excess of 100 kHz.
2. 8/10/12-Bit ADCs in a SOT -23 package.
3. H igh T hroughput with Low Power Consumption
4 . Flexible Power/Serial Clock Speed Management
The conversion rate is determined by the serial clock
allowing the conversion time to be reduced through the
serial clock speed increase. Automatic power down after
conversion, which allows the average power cunsumption
to be reduced when in powerdown. Power consumption
is 0.5 µA max when in powerdown.
T he conversion process and data acquisition are controlled
using CS and the serial clock, allowing the devices to
interface with microprocessors or DSPs. T he input signal
is sampled on the falling edge of CS and the conversion is
also initiated at this point. T here are no pipelined delays
associated with the part.
5. Reference derived from the power supply.
6. N o Pipeline D elay
T he part features a standard successive-approximation
ADC with accurate control of the conversions via a CS
input.
T he AD7466/AD7467/AD7468 use advanced design tech-
niques to achieve very low power dissipation at high
throughput rates.
T he reference for the part is taken internally from VDD.
T his allows the widest dynamic input range to the ADC.
T hus the analog input range for the part is 0 to VDD. T he
conversion rate is determined by the SCLK.
REV. PrC 07/01
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 781/ 329-4700
Fax: 781/ 326-8703
World Wide Web Site: http:/ / w w w.analog.com
Analog Devices, Inc., 2001
pecifications
1
(V = 1.8 V to 3.6 V, fSCLK = 2.4 MHz, fSAMPLE = 100 kSPS unless otherwise noted; T =
DD
A
AD7466–SPECIFICATIONS
T to T , unless otherwise noted.)
MIN
MAX
P a r a m et er
B Version1, 2
U n it
T est C on d it ion s/C om m en t s
D YN AM IC P ERF O RM AN C E
Signal-to-N oise + D istortion (SIN AD )2
Signal-to-N oise Ratio (SN R) 2
T otal H armonic Distortion (T H D)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation D istortion (IM D )2
Second Order T erms
fIN = 30 kHz Sine Wave
7 0
7 1
–7 8
–8 0
dB min
dB min
dB typ
dB typ
fa = 29.1 kHz, fb = 29.9 kHz
–7 8
–7 8
1 0
dB typ
dB typ
ns typ
T hird Order T erms
Aperture D elay
Aperture Jitter
3 0
ps typ
Full Power Bandwidth
Full Power Bandwidth
T BD
T BD
M H z typ
M H z typ
@ 3 dB
@ 0.1 dB
D C AC C U RAC Y
Resolution
1 2
± 1.5
± 0.6
–0.9/+ 1.5
± 0.75
± 1.5
Bits
LSB m ax
LSB typ
Integral N onlinearity2
D ifferential N onlinearity2
LSB max Guaranteed No Missed Codes to 12 Bits
LSB typ
LSB m ax
LSB m ax
Offset Error3
Gain Error3
± 1.5
AN ALOG IN PU T
Input Voltage Ranges
D C Leakage Current
Input C apacitance
0 to VD D
± 1
3 0
V
µA m ax
pF typ
LOG IC IN PU T S
Input High Voltage, VIN H
Input Low Voltage, VIN L
Input Current, IIN, SCLK Pin
Input Current, IIN, CS Pin
0.7(VD D
0.4
± 1
± 1
1 0
)
V min
VD D = 1.8 V to 3.6 V
V max
µA m ax
µA typ
pF max
T ypically 10 nA, VIN = 0 V or VD D
2,3
Input Capacitance, C IN
LO G IC O U T PU T S
Output High Voltage, VO H
Output Low Voltage, VOL
Floating-State Leakage C urrent
Floating-State Output C apacitance2,3
Output C oding
VD D – 0.2
0.2
± 10
V min
ISOURCE = 200 µA; VDD = 1.8 V to 3.6 V
ISINK = 200 µA
V max
µA m ax
pF max
1 0
Straight (N atural) Binary
C O N VERSIO N RAT E
C onversion T ime
T rack/H old Acquisition T ime
6.66
T BD
T BD
100
µs max
ns max
ns max
Sixteen SC LK C ycles
Full-Scale Step Input
Sine Wave Input
T hroughput Rate
kSP S m ax See Serial Interface Section
PO WER REQ U IREM EN T S
VDD
1.8/3.6
V min/max
IDD
Digital I/Ps = 0 V or VD D
N ormal M ode (Operational)
350
200
µA max
µA max
VDD = 3 V. SCLK On or Off
VDD = 1.8 V. SCLK On or Off
Power-D own
0.5
8 0
µA m ax
µA max
SC LK Off
SC LK O n
Power D issipation4
N ormal M ode (Operational)
T BD
m W m ax VD D = 3 V. fSAMPLE = T BD
m W m ax VD D = 1.8 V. fSAMPLE = T BD
Power-D own
1.5
0.9
µW m ax
µW m ax
VD D = 3 V. SCLK Off
VD D = 1.8 V. SCLK Off
NOTES
1Temperaturerangesasfollows:BVersions:–40°Cto+85°C.
2SeeTerminology.
3Sampletestedat25°Ctoensurecompliance.
4SeePowerVersusThroughputRatesection.
Specificationssubjecttochangewithoutnotice.
–2–
REV. PrC
pecifications
1
(V = 1.8 V to 3.6 V, fSCLK = 2.4 MHz, fSAMPLE = 100 kSPS unless otherwise noted; T =
DD
A
AD7467–SPECIFICATIONS
T to T , unless otherwise noted.)
MIN
MAX
2
P ar am eter
B Version1,
Un it
Test C onditions/C om m ents
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)2
T otal Harmonic Distortion (T HD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second Order T erms
fIN = 30 kHz Sine Wave,
61
–73
–74
dB min
dB max
dB max
fa = 29.1 kHz, fb = 29.9 kHz
–78
–78
10
dB typ
dB typ
ns typ
T hird Order T erms
Aperture Delay
Aperture Jitter
30
ps typ
Full Power Bandwidth
Full Power Bandwidth
T BD
T BD
MHz typ
M H z typ
@ 3 dB
@ 0.1 dB
D C ACCURACY
Resolution
10
Bits
Integral Nonlinearity
Differential Nonlinearity
Offset Error
±1
±0.9
±1
LSB max
LSB max
LSB max
LSB max
Guaranteed No Missed Codes to 10 Bits
Gain Error
±1
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to VDD
±1
30
V
µA max
pF typ
LOGIC INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN, SCLK Pin
Input Current, IIN, CS Pin
0.7(VD D )
V min
VDD = 1.8 to 3.6 V
0.4
±1
±1
10
V max
µA max
µA typ
pF max
T ypically 10 nA, VIN = 0 V or VDD
2,3
Input Capacitance, CIN
LOGIC OUT PUT S
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance2,3
Output Coding
VDD – 0.2
0.2
±10
V min
ISOURCE = 200 µA;
ISINK = 200 µA
V max
µA max
pF max
10
Straight (Natural) Binary
CONVERSION RAT E
Conversion T ime
T rack/Hold Acquisition T ime
T hroughput Rate
5
µs max
ns max
kSPS max
12 SCLK Cycles with SCLK at 20 MHz
See Serial Interface Section
T BD
100
POWER REQUIREMENT S
VD D
1.8/3.6
V min/max
I D D
Digital I/Ps = 0 V or VDD
VDD = 3 V . SCLK On or Off
VDD = 1.8 V . SCLK On or Off
SCLK Off
Normal Mode (Operational)
350
200
0.5
80
µA max
µA max
µA max
µA max
Power-Down Mode
SCLK On
Power Dissipation4
Normal Mode (Operational)
T BD
T BD
1.5
mW max
mW max
µW max
µW max
VDD = 3 V. fSAMPLE = 100 kSPS
VDD = 1.8 V. fSAMPLE = T BD
VDD = 3 V. SCLK Off
Power-D own
0.9
VDD = 1.8 V. SCLK Off
NOTES
1Temperaturerangesasfollows:BVersions:–40°Cto+85°C.
2SeeTerminology.
3Sampletestedat25°Ctoensurecompliance.
4SeePowerVersusThroughputRatesection.
Specificationssubjecttochangewithoutnotice.
REV. PrC
–3–
pecifications
1
(V = 1.8 V to 3.6 V, fSCLK = 2.4 MHz, fSAMPLE = 100 kSPS unless otherwise noted; T =
DD
A
AD7468–SPECIFICATIONS
T to T , unless otherwise noted.)
MIN
MAX
2
P ar am eter
B Version1,
Un it
Test C onditions/C om m ents
DYNAMIC PERFORMANCE
Signal-to-Noise + Distortion (SINAD)2
T otal Harmonic Distortion (T HD)2
Peak Harmonic or Spurious Noise (SFDR)2
Intermodulation Distortion (IMD)2
Second Order T erms
fIN =30 kHz Sine Wave, fSAMPLE=100kSPS
fa = 29.1 kHz, fb = 29.9 kHz
49
–65
–65
dB min
dB max
dB max
–68
–68
10
dB typ
dB typ
ns typ
T hird Order T erms
Aperture Delay
Aperture Jitter
30
ps typ
Full Power Bandwidth
Full Power Bandwidth
T BD
T BD
MHz typ
M H z typ
@ 3 dB
@ 0.1 dB
D C ACCURACY2
Resolution
8
Bits
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
T otal Unadjusted Error (T UE)
±0.5
±0.5
±0.5
±0.5
±0.5
LSB max
LSB max
LSB max
LSB max
LSB max
Guaranteed No Missed Codes to 8 Bits
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to VDD
±1
30
V
µA max
pF typ
LOGIC INPUT S
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN, SCLK Pin
Input Current, IIN, CS Pin
0.7(VD D )
V min
VDD = 1.8 to 3.6 V
0.4
±1
±1
10
V max
µA max
µA typ
pF max
T ypically 10 nA, VIN = 0 V or VDD
2,3
Input Capacitance, CIN
LOGIC OUT PUT S
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance3,
VDD – 0.2
0.2
±10
V min
ISOURCE = 200 µA; VDD = 1.8 V to 3.6 V
ISINK = 200 µA
V max
µA max
pF max
4
10
Output Coding
Straight (Natural) Binary
CONVERSION RAT E
Conversion T ime
T rack/Hold Acquisition T ime
T hroughput Rate
4.166
T BD
100
µs max
ns max
kSPS max
10 SCLK Cycles with SCLK at 2.4 MHz
See Serial Interface Section
POWER REQUIREMENT S
VD D
1.8/3.6
V min/max
I D D
Digital I/Ps = 0 V or VDD
VDD = 3V. SCLK On or Off
VDD = 1.8 V . SCLK On or Off
SCLK Off
Normal Mode (Static)
350
200
0.5
80
µA max
µA max
µA max
µA max
Power-Down Mode
SCLK On
Power Dissipation5
Normal Mode (Operational)
T BD
T BD
1.5
mW max
mW max
µW max
µW max
VDD = 3 V. fSAMPLE = T BD
VDD = 1.8 V. fSAMPLE = T BD
VDD = 3 V. SCLK Off
Power-D own
0.9
VDD = 1.8 V. SCLK Off
NOTES
1Temperaturerangesasfollows:BVersions:–40°Cto+85°C.
2SeeTerminology.
3Sampletestedat25°Ctoensurecompliance.
4SeePowerVersusThroughputRatesection.
Specificationssubjecttochangewithoutnotice.
–4–
REV. PrC
pecifications
AD7466/AD7467/AD7468
(V = +1.8 V to +3.6 V; T = TMIN to T , unless otherwise noted.)
1
DD
A
MAX
TIMINGSPECIFICATIONS
P ar am eter
AD7466
Units
D escription
2
fSCLK
10
kH z min
T BD
16* tSCLK
T BD
M H z max
tCONVERT
tquiet
ns min
Minimum Quiet T ime required between Bus Relinquish
and start of next conversion
t1
T BD
10
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns max
µs typ
Minimum CS Pulse Width
CS to SCLK Setup T ime
Delay from CS Until SDAT A 3-State Disabled
Data Access T ime After SCLK Falling Edge
SCLK Low Pulse Width
SCLK High Pulse Width
SCLK to Data Valid Hold T ime
SCLK falling Edge to SDAT A High Impedance
Power up time from Full Power-down.
t23
t3
T BD
T BD
0.4tSCLK
0.4tSCLK
T BD
T BD
T BD
3
t4
t5
t6
t74
t8
5
tpower-up
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 Volts.
2Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4t8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to
remove the effects of charging or discharging the 50 pF capacitor. T his means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the
part and is independent of the bus loading.
5See Power-up T ime section.
Specifications subject to change without notice.
AB SO LUT E M AXIM UM RAT ING S 1
(T A = +25°C unless otherwise noted)
VDD to GND
–0.3 V to T BD V
–0.3 V to VDD + 0.3 V
–0.3 V to T BDV
I
200µA
OL
Analog Input Voltage to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
–0.3 V to VDD + 0.3 V
Input Current to Any Pin Except Supplies2
Operating T emperature Range
Commercial (A, B Version)
± 10 mA
TO
OUTPUT
PIN
+1.6V
–40°C to +85°C
–65°C to +150°C
+ 150°C
C
L
Storage T emperature Range
Junction T emperature
50pF
SOT -23 Package, Power D issipation
θJA Thermal Impedance
450 mW
200µA
I
OH
229.6°C/W (SOT23)
205.9°C/W (µSOIC)
91.99°C/W (SOT23)
43.74°C/W (µSOIC)
θJC Thermal Impedance
Figure 1. Load Circuit for Digital Output Tim ing
Specifications
Lead T emperature, Soldering
Vapor Phase (60 secs)
Infared (15 secs)
+ 215°C
+ 220°C
T BD
E S D
NOTES
1Stressesabove those listed under “Absolute Maximum Ratings” maycause permanent
damage to the device. Thisisa stressratingonlyand functionaloperation ofthe device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods mayaffect device reliability.
2T ransient currents of up to 100 mA will not cause SCR latch up.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7466/AD7467/AD7468 feature proprietary ESD protection circuitry, per-
manent damage may occur on devices subjected to high energy electrostatic discharges. There-
fore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
REV. PrC
–5–
pecifications
AD7466/AD7467/AD7468
P IN F U NC T IO N D E SC R IP T IO N
P in P in
No. Mnem onic
Function
6
CS
Chip Select. Active low logic input. T his input provides the dual function of initiating con-
versions on the AD7466/AD7467/AD7468 and also frames the serial data transfer.
1
2
VDD
Power Supply Input. T he VDD range for the AD7466/67/68 is from +1.8 V to +3.6 V.
G N D
Analog Ground. Ground reference point for all circuitry on the AD7466/AD7467/AD7468.
All analog input signals should be referred to this GND voltage.
3
5
VIN
Analog Input. Single-ended analog input channel. T he input range is 0 to VDD.
SD AT A
Data Out. Logic Output. T he conversion result from the AD7466/AD7467/AD7468 is pro-
vided on this output as a serial data stream. T he bits are clocked out on the falling edge of
the SCLK input. T he data stream from the AD7466 consists of four leading zeros followed
by the 12 bits of conversion data which is provided MSB first. T he data stream for the
AD7467 consists of four leading zeros followed by 10 bits of data. T he datastream for the
AD7468 consists of four leading zeros followed by 8 bits of data.
4
SC L K
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part.
T his clock input is also used as the clock source for the AD7466/AD7467/AD7468 conver-
sion process.
O R D E R ING G U ID E
Tem perature
Range
Linearity
P ackage
O ption2
Branding
Inform ation
Model
Error (LSB)1
AD 7466BRT
AD 7467BRT
AD 7468BRT
AD 7466BRM
AD 7467BRM
AD 7468BRM
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
± 1 max
± 1 max
± 0.5 max
± 1 max
± 1 max
± 0.5 max
RT -6
RT -6
RT -6
RM -8
RM -8
RM -8
C L B
C M B
C N B
C Q B
C RB
C S B
EVAL-AD 7466C B3
EVAL-AD 7467C B3
EVAL-C O N T RO L BRD 24
NOTES
1LinearityError here refers to integrallinearityerror.
2RT = SOT -23, RM = µSOIC.
3T his can be used as a stand-alone evaluation board or in conjunction with the EVAL-CONT ROL BOARD for evaluation/demonstration purposes.
4T his board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
AD 7466/67/68 P INC O NF IG URAT IO N
AD 7466/67/68 SO T-23
V
DD
1
2
3
6
5
4
CS
AD7466/7/8
TOP VIEW
(Not to Scale)
SDATA
GND
V
SCLK
IN
AD 7466/67/68 µSO IC
CS
V
1
2
3
4
8
7
6
5
DD
GND
SDATA
SCLK
NC
AD7466/7/8
TOP VIEW
(Not to Scale)
V
IN
NC
–6–
REV. PrC
pecifications
AD7466/AD7467/AD7468
T ota l H a r m on ic D istor tion
T E R M I N O L O G Y
In t egr a l Non lin ea r it y
T otal harmonic distortion (T HD) is the ratio of the rms
sum of harmonics to the fundamental. For the AD7466/
AD7467/AD7468, it is defined as:
T his is the maximum deviation from a straight line pass-
ing through the endpoints of the ADC transfer function.
For the AD7466/67/68 the endpoints of the transfer
function are zero scale, a point 1 LSB below the first
code transition, and full scale, a point 1 LSB above the
last code transition.
2
2
2
4
2
2
V2
V
V
V
V
+
6
+
+
+
3
5
THD (d B ) 20 lo g
=
V1
D iffer en t ia l Non lin ea r it y
This is the difference between the measured and the ideal 1
LSB change between any two adjacent codes in the ADC.
where V1 is the rms amplitude of the fundamental and V2,
V3, V4, V5 and V6 are the rms amplitudes of the second
through the sixth harmonics.
P eak H ar m onic or Spur ious Noise
O ffset E r r or
Peak harmonic or spurious noise is defined as the ratio of
the rms value of the next largest component in the ADC
output spectrum (up to fS/2 and excluding dc) to the rms
value of the fundamental. Normally, the value of this
specification is determined by the largest harmonic in the
spectrum, but for ADCs where the harmonics are buried
in the noise floor, it will be a noise peak.
T his is the deviation of the first code transition (00 . . .
000) to (00 . . . 001) from the ideal, i.e AGND + 1
L SB.
G a in E r r or
T his is the deviation of the last code transition (111 . . .
110) to (111 . . . 111) from the ideal (i.e., VREF – 1LSB)
after the offset error has been adjusted out.
In t er m od u la t ion D ist or t ion
With inputs consisting of sine waves at two frequencies, fa
and fb, any active device with nonlinearities will create
distortion products at sum and difference frequencies of
mfa ± nfb where m, n = 0, 1, 2, 3, etc. Intermodulation
distortion terms are those for which neither m nor n are
equal to zero. For example, the second order terms in-
clude (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
T r a ck/H old Acqu isition T im e
T he track/hold amplifier returns into track mode at the
end of conversion. T rack/Hold acquisition time is the
time required for the output of the track/hold amplifier
to reach its final value, within ±0.5 LSB, after the end
of conversion. See serial interface timing section for
more details.
T he AD7466/AD7467/AD7468 are tested using the CCIF
standard where two input frequencies are used. In this
case, the second order terms are usually distanced in fre-
quency from the original sine waves while the third order
terms are usually at a frequency close to the input frequen-
cies. As a result, the second and third order terms are
specified separately. T he calculation of the
intermodulation distortion is as per the T H D specification
where it is the ratio of the rms sum of the individual dis-
tortion products to the rms amplitude of the sum of the
fundamentals expressed in dBs.
Signal to (Noise + D istor tion) Ratio
T his is the measured ratio of signal to (noise + distor-
tion) at the output of the A/D converter. T he signal is
the rms amplitude of the fundamental. Noise is the sum
of all nonfundamental signals up to half the sampling
frequency (fS/2), excluding dc. T he ratio is dependent on
the number of quantization levels in the digitization
process; the more levels, the smaller the quantization
noise. T he theoretical signal to (noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is
given by:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
T hus for a 12-bit converter, this is 74 dB and for a 10-
bit converter this is 62dB.
REV. PrC
–7–
pecifications
AD7466/AD7467/AD7468
AD 7466/AD 7467/AD 7468 T YP IC AL P E RF O RMANC E
C U R VE S
Figure 2 shows a typical FFT plot for the AD7466 at 100
kHz sample rate and 30 kHz input frequency.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TITLE
TITLE
Figure 4. PSRR vs Supply Ripple Frequency
Figure 2. AD7466 Dynam ic Perform ance at 100 kSPS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
TITLE
TITLE
Figure 5. AD7466 THD vs Analog Input Frequency at 100
kSPS
Figure 3. AD7466 SINAD vs Analog Input Frequency at 100
kSPS
–8–
REV. PrC
pecifications
AD7466/AD7467/AD7468
C IR C U IT INF O R M AT IO N
T he AD 7466/AD 7467/AD 7468 are fast, micro-power, 12/
10/8-bit, A/D converters respectively. T he parts can be
operated from a +1.8 V to +3.6 V supply. When operated
from any supply voltage within this range, the AD7466/
AD7467/AD7468 is capable of throughput rates of 100
kSPS when provided with a 2 MHz clock.
CHARGE
REDISTRIBUTION
DAC
SAMPLING
CAPACITOR
A
V
IN
CONTROL
LOGIC
SW1
SW2
B
T he AD7466/AD7467/AD7468 provides the user with an
on-chip track/hold, A/D converter, and a serial interface
housed in a tiny 6-pin SOT -23 package, which offers the
user considerable space saving advantages over alternative
solutions. T he serial clock input accesses data from the
part but also provides the clock source for the successive-
approximation A/D converter. T he analog input range is 0
to VDD. An external reference is not required for the ADC
and neither is there a reference on-chip. T he reference for
the AD7466/AD7467/AD7468 is derived from the power
supply and thus gives the widest dynamic input range.
CONVERSION
PHASE
COMPARATOR
V
/ 2
DD
AGND
Figure 9. ADC Conversion Phase
AD C T RANSF E R F U NC T IO N
T he output coding of the AD7466/AD7467/AD7468 is
straight binary. T he designed code transitions occur at
successive integer LSB values (i.e., 1LSB, 2LSBs, etc.).
T he LSB size is = VDD/4096 for the AD7466,the LSB size
T he AD7466/AD7467/AD7468 also features an automatic
power-down mode option to allow power saving between
conversions. T he power-down feature is implemented
across the standard serial interface as described in the
“Modes of Operation” section.
is =
VDD/1024 for the AD7467, and the LSB size is =
VDD/256 for the AD7468 . T he ideal transfer characteristic
for the AD7466/AD7467/AD7468 is shown in figure 10
below.
111...111
111...110
C O NVE R T E R O P E R AT IO N
T he AD 7466/AD 7467/AD 7468 is a successive approxi-
mation analog-to-digital converter based around a charge
redistribution DAC. Figures 8 and 9 show simplified
schematics of the ADC. Figure 8 shows the ADC during
its acquisition phase. SW2 is closed and SW1 is in posi-
tion A, the comparator is held in a balanced condition and
111...000
1LSB = V
1LSB = V
1LSB = V
/4096 (AD7466)
/1024 (AD7467)
/256 (AD7468)
DD
DD
DD
011...111
000...010
000...001
000...000
1LSB
+V
-1LSB
DD
0V
the sampling capacitor acquires the signal on VIN
.
ANALOG INPUT
Figure 10. AD7466/67/68 Transfer Characteristic
C H A R G E
R E D I S T R I B U T I O N
D A C
S A M P L I N G
C A P A C I T O R
A
V
I N
C O N T R O L
L O G I C
S W 1
B
S W 2
A C Q U I S I T I O N
P H A S E
C O M P A R A T O R
A G N D
V
/ 2
D D
Figure 8. ADC Acquisition Phase
When the ADC starts a conversion, see figure 9, SW2 will
open and SW1 will move to position B causing the com-
parator to become unbalanced. T he Control Logic and
the Charge Redistribution DAC are used to add and sub-
tract fixed amounts of charge from the sampling capacitor
to bring the comparator back into a balanced condition.
When the comparator is rebalanced the conversion is com-
plete. T he Control Logic generates the ADC output code.
Figure 10 shows the ADC transfer function.
REV. PrC
–9–
pecifications
AD7466/AD7467/AD7468
T YP IC AL C O NNE C T IO N D IAG R AM
An a log In p u t
Figure 11 shows a typical connection diagram for the
AD7466/AD7467/AD7468. VREF is taken internally from
VDD and as such VDD should be well decoupled. T his pro-
vides an analog input range of 0V to VDD. For the
AD7466 the conversion result is output in a 16-bit word
with four leading zeroes followed by the MSB of the 12-
bit result. T he AD7467 conversion result consists of four
leading zeros followed by the MSB of the 10-bit result.
T he AD7468 conversion result consists of four leading
zeros followed by the MSB of the 8-bit result.
Alternatively, because the supply current required by the
AD7466/AD7467/AD7468 is so low, a presision reference
can be used as the supply source to the AD7466/AD7467/
AD7468. A REF19x voltage reference (REF193 for 3V,
REF192 for 2.5 V ) can be used to supply the required
voltage to the ADC - see figure 11. T his configuration is
especially useful if your power supply is quite noisy or if
the system supply voltages are at some value other than 3V
(e.g. 2.5V). T he REF19x will output a steady voltage to
the AD 7466/AD 7467/AD 7468. In applications where
power consumption is important, the automatic power
down mode of the ADC and the sleep mode of the
REF19x reference should be used to improve power per-
formance. See Modes of Operation section of the
datasheet.
Figure 12 shows an equivalent circuit of the analog input
sturcture of the AD7466/AD7467/7468. T he two diodes
D1 and D2 provide ESD protection for the analog inputs.
Care must be taken to ensure that the analog input signal
never exceeds the supply rails by more than 200mV. T his
will cause these diodes to become forward biased and start
conducting current into the substrate. T he capacitor C1 in
figure 12 is typically about 4pF and can primarily be at-
tributed to pin capacitance. T he resistor R1 is a lumped
component made up of the on resistance of a switch. T his
resistor is typically about 100Ω. T he capacitor C2 is the
ADC sampling capacitor and has a capacitance of 16pF
typically. For ac applications, removing high frequency
components from the analog input signal is recommended
by use of a band-pass filter on the relevant analog input
pin. In applications where harmonic distortion and signal
to noise ratio are critical the analog input should be driven
V
DD
D1
D2
C2
16PF
R1
V
IN
C1
4pF
CONVERSION PHASE - SWITCH OPEN
TRACK PHASE - SWITCH CLOSED
+3V
+5V
REF193
SUPPLY
1µF
TANT
0.1µF
1mA
10µF
0.1µF
680nF
0V toV
V
AD7466/67/68
DD
SCLK
DD
V
µC/µP
IN
Figure 12. Equivalent Analog Input Circuit
INPUT
SDATA
GND
CS
from a low impedance source. Large source impedances
will significantly affect the ac performance of the ADC.
T his may necessitate the use of an input buffer amplifier.
T he choice of the op amp will be a function of the par-
ticular application.
SERIAL
INTERFACE
When no amplifier is used to drive the analog input the
source impedance should be limited to low values. T he
maximum source impedance will depend on the amount of
total harmonic distortion (T HD) that can be tolerated.
T he T HD will increase as the source impedance increases
and performance will degrade. Figure 13 shows a graph of
the T otal Harmonic Distortion vs. analog input signal
frequency for different source impedances when using a
supply voltage of 2.7V and sampling at a rate of 100
kSP S.
Figure 11. REF193 as Power Supply to AD7466/AD7467/
AD7468
–10–
REV. PrC
pecifications
AD7466/AD7467/AD7468
0
0
0
M O D E O F O P E R AT IO N
T he AD 7466/AD 7467/AD 7468 automatically enters
powerdown at the end of each conversion. T his mode of
operation is designed to provide flexible power manage-
ment options and to optimize the power dissipation/
throughput rate ratio for differing application require-
ments. Figure 14 shows the general diagram of the
operaion of the AD7466/AD7467/AD7468. On the falling
CS edge the part begins to power up and the T rack and
Hold, which was in Hold while the part was in power
down, will go into track mode. When operating the part
with a 2.4 MHz clock it will take 2 clock cycles to fully
power up the part and acquire the input signal. On the
third SCLK falling edge after the CS falling edge the
T rack and Hold will return to hold mode. For the
AD7466 sixteen serial clock cycles are required to com-
plete the conversion and access the complete conversion
result.On the 16th SCLK falling edge the part will auto-
matically enter power down . T he AD7467 will automati-
cally enter powerdown on the fourteenth SCLK falling
edge. T he AD7468 will automatically enter powerdown
on the twelveth SCLK falling edge. When supplies are
first applied to the AD7466/AD7467/AD7468 a dummy
conversion should be performed to ensure that the part is
in powerdown mode.
0
0
0
0
0
0
0
TITLE
Figure 13. THD vs. Analog Input Frequency for Various
Source Im pedance
D igita l In p u ts
T he digital inputs applied to the AD7466/AD7467/
AD7468 are not limited by the maximum ratings which
limit the analog inputs. One advantage of SCLK and CS
not being restricted by the VDD + 0.3V limit is the fact that
power supply sequencing issues are avoided. If CS or
SCLK are applied before VDD then there is no risk of
latch-up as there would be on the analog inputs if a signal
T he conversion is iniated on the falling edge of CS as
described in the Serial Interface section. For the AD7466
if CS is brought high any time before the 16th SCLK
falling edge the part will enter power down and the con-
version that was initiated by the falling edge of CS will be
terminated and SDAT A will go back into tri-state. T his
also applies for the AD7467/AD7468, if CS is brought
high before the conversion is complete (the 14th SCLK
falling edge for the AD7467, and the 12th SCLK falling
edge for the AD7468) the part will enter powerdown and
the conversion will be terminated.
greater than 0.3V was applied prior to VDD
.
Once a data transfer is complete (SDAT A has returned to
tri-state), another conversion can be initiated after the
quiet time, tquiet, has elapsed by bringing CS low again.
THE PART BEGINS
TO POWER UP
AD7467 ENTERS
POWERDOWN
AD7468 ENTERS
POWERDOWN
AD7466 ENTERS
POWERDOWN
12
14
16
2
3
1
VALID DATA
Figure 14. Norm al Mode Operation
REV. PrC
–11–
pecifications
AD7466/AD7467/AD7468
SE R IAL INT E R F AC E
terminated and the SDAT A line will go back into tri-state
and the AD7467 will enter powerdown, otherwise SDAT A
returns to tri-state on the 14th SCLK falling edge as
ahown in figure 16. Fourteen serial clock cycles are re-
quired to perform the conversion process and to access
data from the AD7467.
Figure 15, 16, 17 show the detailed timing diagram for
serial interfacing to the AD 7466/AD 7467/AD 7468.T he
serial clock provides the conversion clock and also con-
trols the transfer of information from the ADC during a
conversion.
For the AD7468, the 12th SCLK falling edge will cause
the SDAT A line to go back into tri-state and the part will
enter powerdown. If the rising edge of CS occurs before
12 SCLKs have elapsed then the conversion will be termi-
nated and the SDAT A line will go back into tri-state and
the AD7468 will enter powerdown, otherwise SDAT A
returns to tri-state on the 12th SCLK falling edge as
ahown in figure 17. T welve serial clock cycles are re-
quired to perform the conversion process and to access
data from the AD7468.
On the CS falling edge the part begins to power up. T he
falling edge of CS puts the track and hold into track mode
and takes the bus out of tristate. T he conversion is also
initiated at this point and will require 16 SCLK cycles to
complete. On the third SCLK falling edge the part should
be fully powered up, as shown in figure 15 at point B. On
the third SCLK falling edge after the CS falling edge the
track and hold will return to hold. On the 16th SCLK
falling edge the SDAT A line will go back into tristate and
the AD7466 will enter power down. If the rising edge of
CS occurs before 16 SCLKs have elapsed then the conver-
sion will be terminated and the SDAT A line will go back
into tri-state and the part will enter power down, otherwise
SDAT A returns to tri-state on the 16th SCLK falling
edge as shown in Figure 15. Sixteen serial clock cycles
are required to perform the conversion process and to
access data from the AD7466.
CS going low provides the first leading zero to be read in
by the microcontroller or DSP. T he remaining data is
then clocked out by subsequent SCLK falling edges be-
ginning with the 2nd leading zero, thus the first falling
clock edge on the serial clock has the first leading zero
provided and also clocks out the second leading zero. For
the Ad7466 the final bit in the data transfer is valid on the
sixteenth falling edge, having being clocked out on the
previous (15th) falling edge.
For the AD7467, the fourteenth SCLK falling edge will
cause the SDAT A line to go back into tri-state and the
part will enter powerdown. If the rising edge of CS occurs
before 14 SCLKs have elapsed then the conversion will be
CS
tconvert
t2
B
t6
SCLK
3
4
5
1
2
13
15
14
t5
16
tquie
t
t8
DB0
t7
t4
t3
ZERO
4 LEADING ZERO'S
DB2
ZERO
ZERO
DB10
DB1
Z
DB11
SDATA
3-STATE
3-STATE
Figure 15. AD7466 Serial Interface Tim ing Diagram
CS
SCLK
SDATA
tconvert
t2
B
3
t6
4
5
1
2
13
t5
14
tquiet
t8
DB0
t3
t7
t4
ZERO
ZERO
ZERO
DB9
Z
DB8
3-STATE
3-STATE
4 LEADING ZERO'S
Figure 16. AD7467 Serial Interface Tim ing Diagram
CS
tconvert
t2
B
t6
SCLK
3
4
1
2
12
t8
11
t7
tquiet
t5
t3
t4
ZERO
4 LEADING ZERO'S
ZERO
ZERO
DB7
SDATA
Z
DB0
8 BITS OF DATA
3-STATE
3-STATE
Figure 17. AD7468 Serial Interface Tim ing Diagram
–12–
REV. PrC
pecifications
AD7466/AD7467/AD7468
equidistant sampling is necessary. However, in this ex-
ample, the timer interrupt is used to control the sampling
rate of the ADC and under certain conditions, equidistant
sampling may not be acheived.
M IC R O P R O C E S S O R INT E R F AC ING
T he serial interface on the AD7466/AD7467/AD7468
allows the part to be directly connected to a range of many
different microprocessors. T his section explains how to
interface the AD7466/AD7467/AD7468 with some of the
more common microcontroller and DSP serial interface
protocols.
T he T imer registers etc. are loaded with a value
which will provide an interrupt at the required sample
interval. When an interrupt is received, a value is trans-
mitted with T FS/DT (ADC control word). T he T FS is
used to control the RFS and hence the reading of data.
T he frequency of the serial clock is set in the SCLKDIV
register. When the instrustion to transmit with T FS is
given, (i.e. AX0=T X0), the state of the SCLK is checked.
T he DSP will wait until the SCLK has gone High, Low
and High before transmission will start. If the timer and
SCLK values are chosen such that the instruction to trans-
mit occurs on or near the rising edge of SCLK, then the
data may be transmitted or it may wait until the next clock
edge.
AD 7466/7/8 to T MS320C 5xC 54x
T he serial interface on the T MS320C5x uses a continuous
serial clock and frame synchronization signals to synchro-
nize the data transfer operations with peripheral devices
like the AD7466/67/68. T he CS input allows easy inter-
facing between the T MS320C5x and the AD7466/67/68
without any glue logic required. T he serial port of the
T MS320C5x/C54x is set up to operate in burst mode
with internal CLKX (T X serial clock) and FSX (T X
frame sync). T he serial port control register (SPC) must
have the following setup: FO = 0, FSM = 1, MCM = 1
and T XM = 1. T he format bit, FO, may be set to 1 to set
the word length to 8-bits, in order to implement the
power-down mode on the AD7466/67/68.
For example, the ADSP2111 has a master clock frequency
of 16MHz. If the SCLKDIV register is loaded with the
value 3 then a SCLK of 2MHz is obtained, and 8 master
clock periods will elapse for every 1 SCLK period. If the
timer registers are loaded with the value 803, then 100.5
SCLKs will occur between interrupts and subsequently
between transmit instructions. T his situation will result in
non-equidistant sampling as the transmit instruction is
occuring on a SCLK edge. If the number of SCLKs be-
tween interrupts is a whole integer figure of N then equi-
distant sampling will be implemented by the DSP.
T he connection diagram is shown in Figure 18. It should
be noted that for signal processing applications, it is im-
perative that the frame synchronisation signal from the
T M S320C 5x/C 54x will provide equidistant sampling.
TMS320C5x/C54x*
AD7466/7/8*
CLKX
SCLK
CLKR
DR
ADSP21xx*
AD7466/7/8*
SDATA
SCLK
SCLK
FSX
FSR
CS
DR
SDATA
RFS
CS
*Additional Pins omitted for clarity
TFS
Figure 18. Interfacing to the TMS320C5x
AD 7466/7/8 to AD SP 21xx
*Additional Pins omitted for clarity
T he ADSP21xx family of DSPs are interfaced directly to
the AD7466/67/68 without any glue logic required. T he
SPORT control register should be set up as follows:
T FSW = RFSW = 1, Alternate Framing
INVRFS = INVT FS = 1, Active Low Frame Signal
DT YPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data words
ISCLK = 1, Internal serial clock
T FSR = RFSR = 1, Frame every word
IRFS = 0,
IT FS = 1.
Figure 19. Interfacing to the ADSP-21xx
AD 7466/67/68 to D SP 56xxx
T he connection diagram in figure 20 shows how the
AD7466/67/68 can be connected to the SSI (Synchronous
Serial Interface) of the DSP56xxx family of DSPs from
Motorola. T he SSI is operated in Synchronous Mode
(SYN bit in CRB =1) with internally generated 1-bit
clock period frame sync for both T X and RX (bits FSL1
=1 and FSL0 =0 in CRB). Set the word length to 16 by
setting bits WL1 =1 and WL0 = 0 in CRA. It should be
noted that for signal processing applications, it is impera-
tive that the frame synchronisation signal from the
D SP56xxx will provide equidistant sampling.
T he connection diagram is shown in Figure 19. T he
ADSP21xx has the T FS and RFS of the SPORT tied
together, with T FS set as an output and RFS set as an
input. T he DSP operates in Alternate Framing Mode and
the SPORT control register is set up as described. T he
Frame synchronisation signal generated on the T FS is
tied to CS and as with all signal processing applications
REV. PrC
–13–
pecifications
AD7466/AD7467/AD7468
DSP56xxx*
AD7466/7/8*
SCK
SCLK
SDATA
SRD
SC2
CS
*Additional Pins omitted for clarity
Figure 20. Interfacing to the DSP56xx
AD 7466/67/68 to MC 68H C 16
T he Serial Peripheral Interface (SPI) on the MC68H C16
is configured for Master Mode (MST R = 1), Clock Po-
larity Bit (CPOL) = 1 and the Clock Phase Bit (CPHA)
= 0. T he SPI is configured by writing to the SPI Control
Register (SPCR) - see 68HC16 user manual. T he serial
transfer will take place as a 16-bit operation when the
SIZE bit in the SPCR register is set to SIZE = 1. A con-
nection diagram is shown in figure 21.
MC68HC16*
AD7466/7/8*
SCLK/PMC2
SCLK
SDATA
MISO/PMC0
SS/PMC3
CS
*Additional Pins omitted for clarity
Figure 21. Interfacing to the MC68HC16
–14–
REV. PrC
pecifications
AD7466/AD7467/AD7468
O U T LINE D IM E NS IO NS
D imensions shown in inches and (mm).
6-lead SO T23 (RT-6)
0.122 (3.10)
0.106 (2.70)
6
1
5
2
4
3
0.071 (1.80)
0.059 (1.50)
0.118 (3.00)
0.098 (2.50)
PIN
1
0.037 (0.95) BSC
0.075 (1.90)
BSC
0.051 (1.30)
0.035 (0.90)
0.057 (1.45)
0.035 (0.90)
10
°
0.020 (0.50)
0.010 (0.25)
0.022 (0.55)
0.014 (0.35)
0.006 (0.15)
0.000 (0.00)
SEATING
PLANE
0
°
0.009 (0.23)
0.003 (0.08)
8-lead m icr oSO IC (RM-8)
0.122 (3.10)
0.114 (2.90)
5
4
8
1
0.199 (5.05)
0.187 (4.75)
0.122 (3.10)
0.114 (2.90)
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.120 (3.05)
0.112 (2.84)
0.043 (1.09)
0.006 (0.15)
0.002 (0.05)
0.037 (0.94)
33°
27°
0.018 (0.46)
0.028 (0.71)
0.016 (0.41)
SEATING
PLANE
0.011 (0.28)
0.003 (0.08)
0.008 (0.20)
REV. PrC
–15–
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