AD7490BRU-EP-RL7 [ADI]
IC 16-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO28, PLASTIC, MO-153AE, TSSOP-28, Analog to Digital Converter;
| 型号： | AD7490BRU-EP-RL7 |
| 厂家： | 
ADI |
| 描述： | IC 16-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO28, PLASTIC, MO-153AE, TSSOP-28, Analog to Digital Converter 光电二极管 转换器 |
| 文件： | 总12页 (文件大小：368K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-Channel, 1 MSPS, 12-Bit ADC
with Sequencer in 28-Lead TSSOP
AD7490-EP
FUNCTIONAL BLOCK DIAGRAM
FEATURES
V
DD
Fast throughput rate: 1 MSPS
Specified for VDD of 4.75 V to 5.25 V
Low power at maximum throughput rates
12.5 mW maximum at 1 MSPS with 5 V supplies
16 (single-ended) inputs with sequencer
Wide input bandwidth
AD7490-EP
REF
V
IN
0
12-BIT
SUCCESSIVE
T/H
IN
APPROXIMATION
ADC
INPUT
MUX
69.5 dB SNR at 50 kHz input frequency
Flexible power/serial clock speed management
No pipeline delays
V
15
IN
High speed serial interface, SPI/QSPI™/MICROWIRE™/
DSP compatible
Full shutdown mode: 0.5 µA maximum
28-lead TSSOP package
SCLK
DOUT
DIN
CONTROL
LOGIC
SEQUENCER
CS
V
DRIVE
Support defense and aerospace applications (AQEC)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
One assembly/test site
AGND
Figure 1.
One fabrication site
Enhanced product change notification
Qualification data available on request
GENERAL DESCRIPTION
The AD7490-EP is a 12-bit high speed, low power, 16-channel,
successive approximation ADC. The part operates from a single
4.75 V to 5.25 V power supply and features throughput rates up
to 1 MSPS. The part contains a low noise, wide bandwidth
track-and-hold amplifier that can handle input frequencies in
excess of 1 MHz.
The AD7490-EP is available in a 28-lead TSSOP package.
Full details about this enhanced product are available in the
AD7490 data sheet, which should be consulted in conjunction
with this data sheet.
PRODUCT HIGHLIGHTS
1. The AD7490-EP offers up to 1 MSPS throughput rates.
2. A sequence of channels can be selected, through which the
AD7490-EP cycles and converts.
3. The AD7490-EP operates from a single 4.75 V to 5.25 V
supply. The VDRIVE function allows the serial interface to
connect directly to either 3 V or 5 V processor systems
The conversion process and data acquisition are controlled using
CS
and the serial clock signal, allowing the device to easily inter-
face with microprocessors or DSPs. The input signal is sampled
CS
on the falling edge of , and conversion is also initiated at this
point. There are no pipeline delays associated with the part.
The AD7490-EP uses advanced design techniques to achieve
very low power dissipation at high throughput rates. For
maximum throughput rates, the AD7490-EP consumes just
2.5 mA with 5 V supplies.
independent of VDD
.
4. The conversion rate is determined by the serial clock,
allowing the conversion time to be reduced through the
serial clock speed increase. The part also features various
shutdown modes to maximize power efficiency at lower
throughput rates. Power consumption is 0.5 µA, maximum,
when in full shutdown.
By setting the relevant bits in the control register, the analog input
range for the part can be selected to be a 0 V to REFIN input or a
0 V to 2 × REFIN input, with either straight binary or twos comple-
ment output coding. The AD7490-EP features 16 single-ended
analog inputs with a channel sequencer to allow a preprogrammed
selection of channels to be converted sequentially. The conver-
sion time is determined by the SCLK frequency because this is
also used as the master clock to control the conversion.
5. The part features a standard successive approximation
CS
ADC with accurate control of the sampling instant via a
input and once off conversion control.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2010 Analog Devices, Inc. All rights reserved.
AD7490-EP
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................6
ESD Caution...................................................................................6
Pin Configuration and Function Descriptions..............................7
Typical Performance Characteristics ..............................................8
Outline Dimensions..........................................................................9
Ordering Guide .............................................................................9
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
REVISION HISTORY
4/10—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
AD7490-EP
SPECIFICATIONS
VDD = 4.75 V to 5.25 V, VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK1 = 20 MHz, TA = TMIN to TMAX, unless otherwise noted.
Temperature range (EP version): −55°C to +125°C.
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DYNAMIC PERFORMANCE
Signal-to-(Noise + Distortion) (SINAD)
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
Second-Order Terms
fIN = 50 kHz sine wave, fSCLK = 20 MHz
69
69.5
70.5
dB
dB
dB
dB
−84
−86
−74
−75
fa = 40.1 kHz, fb = 41.5 kHz
−85
−85
10
dB
dB
ns
Third-Order Terms
Aperture Delay
Aperture Jitter
50
ps
Channel-to-Channel Isolation
Full Power Bandwidth
fIN = 400 kHz
3 dB
0.1 dB
−82
8.2
1.6
dB
MHz
MHz
DC ACCURACY
Resolution
12
Bits
LSB
Integral Nonlinearity
Differential Nonlinearity
0 V to REFIN Input Range
Offset Error
Offset Error Match
Gain Error
1
Guaranteed no missed codes to 12 bits
Straight binary output coding
−0.95/+1.5 LSB
0.6
8
0.5
2
LSB
LSB
LSB
LSB
Gain Error Match
0 V to 2 × REFIN Input Range
0.6
−REFIN to +REFIN biased about REFIN with
twos complement output coding offset
Positive Gain Error
Positive Gain Error Match
Zero Code Error
2
0.5
8
0.5
1
0.5
LSB
LSB
LSB
LSB
LSB
LSB
0.6
Zero Code Error Match
Negative Gain Error
Negative Gain Error Match
ANALOG INPUT
Input Voltage Range
RANGE bit set to 1
RANGE bit set to 0
0
0
REFIN
2 × REFIN
1
V
V
µA
pF
DC Leakage Current
Input Capacitance
20
2.5
36
REFERENCE INPUT
REFIN Input Voltage
DC Leakage Current
REFIN Input Impedance
LOGIC INPUTS
1% specified performance
fSAMPLE = 1 MSPS
V
µA
kΩ
1
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
0.7 × VDRIVE
V
V
µA
pF
0.3 × VDRIVE
1
10
VIN = 0 V or VDRIVE
0.01
Input Capacitance, CIN+2
Rev. 0 | Page 3 of 12
AD7490-EP
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating State Leakage Current
Floating State Output Capacitance2
Output Coding
ISOURCE = 200 µA
ISINK = 200 µA
WEAK/TRI bit set to 0
WEAK/TRI bit set to 0
Coding bit set to 1
Coding bit set to 0
VDRIVE − 0.2
V
V
µA
pF
0.4
10
10
Straight (natural) binary
Twos complement
CONVERSION RATE
Conversion Time
Track-and-Hold Acquisition Time
16 SCLK cycles, SCLK = 20 MHz
Sine wave input
Full-scale step input
800
300
300
1
ns
ns
ns
MSPS
Throughput Rate
POWER REQUIREMENTS
VDD
4.75
2.7
5.25
5.25
V
V
VDRIVE
IDD
Digital inputs = 0 V or VDRIVE
SCLK on or off
fSCLK = 20 MHz
Normal Mode (Static)
Normal Mode (Operational)
(fS = Maximum Throughput)
Auto Standby Mode
600
µA
2.5
mA
fSAMPLE = 500 kSPS
Static
1.55
960
0.02
mA
µA
µA
µA
µA
100
Auto Shutdown Mode
fSAMPLE = 250 kSPS
Static
SCLK on or off
0.5
0.5
Full Shutdown Mode
Power Dissipation
Normal Mode (Operational)
Auto Standby Mode (Static)
Auto Shutdown Mode (Static)
Full Shutdown Mode
fSCLK = 20 MHz
12.5
460
2.5
mW
µW
µW
µW
2.5
1 Specifications apply for fSCLK up to 20 MHz. However, for serial interfacing requirements, see the Timing Specifications section.
2 Guaranteed by characterization.
Rev. 0 | Page 4 of 12
AD7490-EP
TIMING SPECIFICATIONS
VDD = 4.75 V to 5.25 V, VDRIVE ≤ VDD, REFIN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.
Table 2. Timing Specifications1
Parameter Limit at TMIN, TMAX
Unit
Description
2
fSCLK
10
kHz min
MHz max
20
tCONVERT
tQUIET
t2
16 × tSCLK
50
10
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
Minimum quiet time required between bus relinquish and start of next conversion
CS to SCLK setup time
3
t3
t3b4
14
Delay from CS until DOUT three-state disabled
Delay from CS to DOUT valid
20
3
t4
40
0.4 × tSCLK
0.4 × tSCLK
15
15/50
20
5
20
1
Data access time after SCLK falling edge
SCLK low pulse width
SCLK high pulse width
t5
t6
t7
SCLK to DOUT valid hold time
5
t8
ns min/max SCLK falling edge to DOUT high impedance
t9
ns min
ns min
ns min
µs max
DIN setup time prior to SCLK falling edge
DIN hold time after SCLK falling edge
16th SCLK falling edge to CS high
t10
t11
t12
Power-up time from full power-down/auto shutdown/auto standby modes
1 Guaranteed by characterization. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V (see Figure 2).
2 The mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.4 V or 0.7 VDRIVE
.
4 t3b represents a worst-case figure for having ADD3 available on the DOUT line, that is, if the AD7490-EP goes back into three-state at the end of a conversion and some
other device takes control of the bus between conversions, the user has to wait a maximum time of t3b before having ADD3 valid on the DOUT line. If the DOUT line is
CS
weakly driven to ADD3 between conversions, the user typically has to wait 12 ns at 5 V after the falling edge before seeing ADD3 valid on DOUT.
5 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish
time of the part and is independent of the bus loading.
200µA
I
OL
TO OUTPUT
PIN
1.6V
C
L
25pF
200µA
I
OH
Figure 2. Load Circuit for Digital Output Timing Specifications
Rev. 0 | Page 5 of 12
AD7490-EP
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 3.
Parameter
Rating
VDD to GND
−0.3 V to +7 V
VDRIVE to GND
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
10 mA
Analog Input Voltage to GND
Digital Input Voltage to GND
Digital Output Voltage to GND
REFIN to GND
Input Current to Any Pin Except Supplies1
Operating Temperature Ranges
Enhanced Plastic (EP Version)
Storage Temperature Range
Junction Temperature
ESD CAUTION
−55°C to +125°C
−65°C to +150°C
150°C
TSSOP Package, Power Dissipation
θJA Thermal Impedance
450 mW
97.9°C/W (TSSOP)
14°C/W (TSSOP)
θJC Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
ESD
215°C
220°C
1 kV
1 Transient currents of up to 100 mA do not cause SCR latch-up.
Rev. 0 | Page 6 of 12
AD7490-EP
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
11
1
2
28
27
26
25
V
V
V
V
12
13
14
15
IN
IN
IN
IN
IN
V
10
IN
V
9
3
IN
NC
4
V
V
V
V
V
V
V
V
V
8
7
6
5
4
3
2
1
0
5
AGND
AD7490-EP 24
IN
IN
IN
IN
IN
IN
IN
IN
IN
6
23 REF
IN
TOP VIEW
7
22 V
DD
(Not to Scale)
8
21 AGND
20 CS
9
10
11
12
13
19 DIN
18 NC
17
V
DRIVE
16 SCLK
15 DOUT
AGND 14
NC = NO CONNECT
ALL NC PINS SHOULD BE
CONNECTED STRAIGHT TO AGND
Figure 3. 28-Lead TSSOP Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
20
23
22
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the
AD7490-EP and also frames the serial data transfer.
Reference Input for the AD7490-EP. An external reference must be applied to this input. The voltage range for the
external reference is 2.5 V 1% for specified performance.
Power Supply Input. The VDD range for the AD7490-EP is from 2.7 V to 5.25 V. For the 0 V to 2 × REFIN range, VDD
should be from 4.75 V to 5.25 V.
REFIN
VDD
14, 21,
24
AGND
Analog Ground. Ground reference point for all circuitry on the AD7490-EP. All analog/digital input signals and any
external reference signal should be referred to this AGND voltage. All AGND pins should be connected together.
13 to 5,
3 to 1,
28 to 25
VIN0 to
VIN15
Analog Input 0 through Analog Input 15. Sixteen single-ended analog input channels that are multiplexed into
the on chip track-and-hold. The analog input channel to be converted is selected by using the address bits ADD3
through ADD0 of the control register. The address bits, in conjunction with the SEQ and SHADOW bits, allow the
sequence register to be programmed. The input range for all input channels can extend from 0 V to REFIN or 0 V to
2 × REFIN as selected via the RANGE bit in the control register. Any unused input channels should be connected to
AGND to avoid noise pickup.
19
15
DIN
Data In. Logic input. Data to be written to the control register of the AD7490-EP is provided on this input and is
clocked into the register on the falling edge of SCLK (see the AD7490 data sheet).
DOUT
Data Out. Logic output. The conversion result from the AD7490-EP is provided on this output as a serial data
stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four address bits
indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data, which is
provided by MSB first. The output coding can be selected as straight binary or twos complement via the CODING
bit in the control register.
16
17
SCLK
VDRIVE
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also
used as the clock source for the conversion process of the AD7490-EP.
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface of the
AD7490-EP operates.
Rev. 0 | Page 7 of 12
AD7490-EP
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.8
5
8192 POINT FFT
V
= V
= 5V
DD
DRIVE
fSAMPLE = 1MSPS
TEMPERATURE = 25°C
fIN = 50kHZ
SINAD = 70.697dB
THD = –79.171dB
–15
0.6
0.4
SFDR = –79.93dB
–35
0.2
0
–55
–75
–95
–0.2
–0.4
–0.6
–0.8
–1.0
0
512
1024
1536
2048
2560
3072
3584
4096
0
50
100 150 200 250 300 350 400 450 500
FREQUENCY (kHz)
CODE
Figure 6. Typical INL
Figure 4. Dynamic Performance at 1 MSPS
1.0
0.8
–50
–55
–60
–65
–70
–75
–80
–85
V
= V
= 5V
fS = 1MSPS
= 25°C
DD
DRIVE
TEMPERATURE = 25°C
T
A
V
= 5.25V
DD
RANGE = 0V TO REF
0.6
IN
R
= 1000Ω
IN
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
R
= 100Ω
IN
R
= 5Ω
IN
R
= 10Ω
IN
0
512
1024
1536
2048
2560
3072
3584
4096
10
100
INPUT FREQUENCY (Hz)
1000
CODE
Figure 5. THD vs. Analog Input Frequency
for Various Analog Source Impedances
Figure 7. Typical DNL
Rev. 0 | Page 8 of 12
AD7490-EP
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
8°
0°
0.75
0.60
0.45
0.30
0.19
0.20
0.09
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AE
Figure 8. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in millimeters
ORDERING GUIDE
Integral Linearity
Model
Temperature Range Error (LSB)
Package Description
Package Option
AD7490BRU-EP-RL7 −55°C to +125°C
1
28-Lead Thin Shrink Small Outline Package [TSSOP] RU-28
Rev. 0 | Page 9 of 12
AD7490-EP
NOTES
Rev. 0 | Page 10 of 12
AD7490-EP
NOTES
Rev. 0 | Page 11 of 12
AD7490-EP
NOTES
©2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08936-0-4/10(0)
Rev. 0 | Page 12 of 12
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