AD7492AR [ADI]
1.25 MSPS, 16 mW Internal REF and CLK, 12-Bit Parallel ADC; 1.25 MSPS ， 16毫瓦内部REF和CLK ， 12位并行ADC
| 型号： | AD7492AR |
| 厂家： | 
ADI |
| 描述： | 1.25 MSPS, 16 mW Internal REF and CLK, 12-Bit Parallel ADC |
| 文件： | 总16页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1.25 MSPS, 16 mW Internal REF and CLK,
12-Bit Parallel ADC
a
AD7492
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Specified for VDD of 2.7 V to 5.25 V
Throughput Rate of 1 MSPS—AD7492
Throughput Rate of 1.25 MSPS—AD7492-5
Low Power
4 mW Typ at 1 MSPS with 3 V Supplies
11 mW Typ at 1 MSPS with 5 V Supplies
Wide Input Bandwidth
AVDD
VDRIVE
DVDD
REF OUT
2.5V
REF
CLOCK
OSCILLATOR
BUF
DB11
DB0
70 dB Typ SNR at 100 kHz Input Frequency
2.5 V Internal Reference
OUTPUT
DRIVERS
T/H
12-BIT SAR
ADC
VIN
On-Chip CLK Oscillator
Flexible Power/Throughput Rate Management
No Pipeline Delays
High-Speed Parallel Interface
Sleep Mode: 50 nA Typ
24-Lead SOIC and TSSOP Packages
PS/FS
CONTROL
LOGIC
CONVST
CS
RD
AD7492
BUSY
GENERAL DESCRIPTION
The AD7492 and AD7492-5 are 12-bit high-speed, low power,
successive-approximation ADCs. The parts operate from a
single 2.7 V to 5.25 V power supply and feature throughput rates
up to 1.25 MSPS. They contain a low-noise, wide bandwidth
track/hold amplifier that can handle bandwidths up to 10 MHz.
AGND
DGND
PRODUCT HIGHLIGHTS
1. High Throughput with Low Power Consumption
The AD7492-5 offers 1.25 MSPS throughput with 16 mW
power consumption.
The conversion process and data acquisition are controlled using
standard control inputs allowing easy interface to microproces-
sors or DSPs. The input signal is sampled on the falling edge of
CONVST and conversion is also initiated at this point. The
BUSY goes high at the start of conversion and goes low 880 ns
(AD7492) or 680 ns (AD7492-5) later to indicate that the con-
version is complete. There are no pipeline delays associated with
the part. The conversion result is accessed via standard CS and
RD signals over a high-speed parallel interface.
2. Flexible Power/Throughput Rate Management
The conversion time is determined by an internal clock. The
part also features two sleep modes, partial and full, to maxi-
mize power efficiency at lower throughput rates.
3. No Pipeline Delay
The part features a standard successive-approximation ADC
with accurate control of the sampling instant via a CONVST
input and once-off conversion control.
The AD7492 uses advanced design techniques to achieve very
low power dissipation at high throughput rates. With 5 V
supplies and 1.25 MSPS, the average current consumption
AD7492-5 is typically 2.75 mA. The part also offers flexible
power/throughput rate management.
4. Flexible Digital Interface
The VDRIVE feature controls the voltage levels on the I/O
digital pins.
5. Fewer Peripheral Components
It is also possible to operate the part in a full sleep mode and a
partial sleep mode, where the part wakes up to do a conversion
and automatically enters a sleep mode at the end of conversion.
The type of sleep mode is hardware selected by the PS/FS pin.
Using these sleep modes allows very low power dissipation num-
bers at lower throughput rates.
The AD7492 optimizes PCB space by using an internal
Reference and internal CLK.
The analog input range for the part is 0 to REF IN. The 2.5 V
reference is supplied internally and is available for external refer-
encing. The conversion rate is determined by the internal clock.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2001
AD7492
1
(VDD = 4.75 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.)
AD7492-5–SPECIFICATIONS
Parameter
A Version1
B Version1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
fS = 1.25 MSPS
Signal to Noise + Distortion (SINAD)
69
68
70
68
–83
–87
–75
–83
–90
–76
69
68
70
68
–83
–87
–75
–83
–90
–76
dB typ
dB min
dB typ
dB min
dB typ
dB typ
dB max
dB typ
dB typ
dB max
fIN = 500 kHz Sine Wave
fIN = 100 kHz Sine Wave
Signal-to-Noise Ratio (SNR)
fIN = 500 kHz Sine Wave
fIN = 100 kHz Sine Wave
fIN = 500 kHz Sine Wave
fIN = 100 kHz Sine Wave
fIN = 100 kHz Sine Wave
fIN = 500 kHz Sine Wave
fIN = 100 kHz Sine Wave
fIN = 100 kHz Sine Wave
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise (SFDR)
Intermodulation Distortion (IMD)
Second Order Terms
–82
–90
–71
–88
5
–82
–90
–71
–88
5
dB typ
dB typ
dB typ
dB typ
ns typ
fIN = 500 kHz Sine Wave
fIN = 100 kHz Sine Wave
fIN = 500 kHz Sine Wave
fIN = 100 kHz Sine Wave
Third Order Terms
Aperture Delay
Aperture Jitter
15
15
ps typ
Full Power Bandwidth
10
10
MHz typ
DC ACCURACY
Resolution
fS = 1.25 MSPS
12
12
Bits
Integral Nonlinearity
Differential Nonlinearity
1.5
+1.5/–0.9
1.25
+1.5/–0.9
LSB max
LSB max
Guaranteed No Missed Codes to
12 Bits (A and B Version)
Offset Error
Gain Error
9
2.5
9
2.5
LSB max
LSB max
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to 2.5
1
33
0 to 2.5
1
33
V
µA max
pF typ
REFERENCE OUTPUT
REF OUT Output Voltage Range
2.5
2.5
V
1.5% for Specified Performance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
2
VDRIVE × 0.7
VDRIVE × 0.3
1
VDRIVE × 0.7
VDRIVE × 0.3
1
V min
VDD = 5 V 5%
VDD = 5 V 5%
Typically 10 nA, VIN = 0 V or VDD
2
V max
µA max
pF max
Input Current, IIN
Input Capacitance, CIN
3
10
10
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
VDRIVE – 0.2
0.4
10
10
VDRIVE – 0.2
0.4
10
10
V min
ISOURCE = 200 µA
ISINK = 200 µA
V max
µA max
pF max
Straight (Natural) Binary
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
Throughput Rate
680
120
1.25
680
120
1.25
ns max
ns min
MSPS max Conversion Time + Acquisition Time
POWER REQUIREMENTS
VDD
4.75/5.25
4.75/5.25
V min/max
IDD
Digital I/Ps = 0 V or DVDD.
Normal Mode
3.3
1.8
250
1
3.3
1.8
250
1
mA max
mA max
µA max
µA max
fS = 1.25 MSPS, Typ 2.75 mA
Quiescent Current
Partial Sleep Mode
Full Sleep Mode
Power Dissipation4
Normal Mode
Static. Typ 190 µA
Static. Typ 200 nA
Digital I/Ps = 0 V or DVDD
16.5
1.25
5
16.5
1.25
5
mW max
mW max
µW max
Partial Sleep Mode
Full Sleep Mode
NOTES
1Temperature ranges as follows: A and B Versions: –40°C to +85°C.
2VINH and VINL trigger levels are set by the VDRIVE voltage. The logic interface circuitry is powered by VDRIVE
3Sample tested @ 25°C to ensure compliance.
.
4See Power vs. Throughput Rate section.
Specifications subject to change without notice.
–2–
REV. 0
AD7492
AD7492–SPECIFICATIONS1
(VDD = 2.7 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.)
Parameter
A Version1
B Version1
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
fS = 1 MSPS
Signal to Noise + Distortion (SINAD)
69
68
70
68
–85
–87
–75
–86
–90
–76
69
68
70
68
–85
–87
–75
–86
–90
–76
dB typ
dB min
dB typ
dB min
dB typ
dB typ
dB max
dB typ
dB typ
dB max
fIN = 500 kHz Sine Wave
fIN = 100 kHz Sine Wave
fIN = 500 kHz Sine Wave
Signal-to-Noise Ratio (SNR)
f
IN = 100 kHz Sine Wave
Total Harmonic Distortion (THD)
fIN = 500 kHz Sine Wave
f
f
IN = 100 kHz Sine Wave
IN = 100 kHz Sine Wave
Peak Harmonic or Spurious Noise (SFDR)
fIN = 500 kHz Sine Wave
IN = 100 kHz Sine Wave
f
fIN = 100 kHz Sine Wave
Intermodulation Distortion (IMD)
Second Order Terms
–77
–90
–69
–88
5
–77
–90
–69
–88
5
dB typ
dB typ
dB typ
dB typ
ns typ
fIN = 500 kHz Sine Wave
f
IN = 100 kHz Sine Wave
Third Order Terms
fIN = 500 kHz Sine Wave
fIN = 100 kHz Sine Wave
Aperture Delay
Aperture Jitter
15
15
ps typ
Full Power Bandwidth
10
10
MHz typ
DC ACCURACY
Resolution
fS = 1 MSPS
12
12
Bits
Integral Nonlinearity
1.5
LSB max
LSB typ
LSB max
LSB max
0.6
1
+1.5/–0.9
VDD = 5 V
VDD = 3 V
Guaranteed No Missed Codes to
12 Bits (A and B Version)
Differential Nonlinearity
+1.5/–0.9
Offset Error
Gain Error
9
2.5
9
2.5
LSB max
LSB max
ANALOG INPUT
Input Voltage Ranges
DC Leakage Current
Input Capacitance
0 to 2.5
1
33
0 to 2.5
1
33
V
µA max
pF typ
REFERENCE OUTPUT
REF OUT Output Voltage Range
2.5
2.5
V
1.5% for Specified Performance
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
2
VDRIVE × 0.7
VDRIVE × 0.7
V min
VDD = 5 V 5%
VDD = 5 V 5%
Typically 10 nA, VIN = 0 V or VDD
2
VDRIVE × 0.3
VDRIVE × 0.3
V max
µA max
pF max
Input Current, IIN
Input Capacitance, CIN
1
10
1
10
3
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage Current
Floating-State Output Capacitance
Output Coding
VDRIVE – 0.2
0.4
10
10
VDRIVE – 0.2
0.4
10
10
V min
ISOURCE = 200 µA
ISINK = 200 µA
V max
µA max
pF max
Straight (Natural) Binary
Straight (Natural) Binary
CONVERSION RATE
Conversion Time
Track/Hold Acquisition Time
Throughput Rate
880
120
1
880
120
1
ns max
ns min
MSPS max Conversion Time + Acquisition Time
POWER REQUIREMENTS
VDD
2.7/5.25
2.7/5.25
V min/max
IDD
Digital I/Ps = 0 V or DVDD.
Normal Mode
3
3
mA max
mA max
µA max
µA max
fS = 1 MSPS, Typ 2.2 mA
Quiescent Current
Partial Sleep Mode
Full Sleep Mode
Power Dissipation4
Normal Mode
1.8
250
1
1.8
250
1
Static. Typ 190 µA
Static. Typ 200 nA
Digital I/Ps = 0 V or DVDD
VDD = 5 V
VDD = 5 V
VDD = 5 V
15
1.25
5
15
1.25
5
mW max
mW max
µW max
Partial Sleep Mode
Full Sleep Mode
NOTES
1Temperature ranges as follows: A and B Versions: –40°C to +85°C.
2VINH and VINL trigger levels are set by the VDRIVE voltage. The logic interface circuitry is powered by VDRIVE
3Sample tested @ 25°C to ensure compliance.
.
4See Power vs. Throughput Rate section.
Specifications subject to change without notice.
–3–
REV. 0
AD7492
TIMING SPECIFICATIONS1
(VDD = 2.7 V to 5.25 V, TA = TMIN to TMAX, unless otherwise noted.)
Limit at TMIN, TMAX
AD7492
AD7492-52
Parameter
Unit
Description
tCONVERT
tWAKEUP
880
203
500
10
10
40
0
680
203
500
10
10
N/A
0
ns max
µs max
µs max
ns min
ns max
ns max
ns max
ns max
ns min
ns min
ns max
ns max
ns min
ns min
Partial Sleep Wake-Up Time
Full Sleep Wake-Up Time
CONVST Pulsewidth
CONVST to BUSY Delay, VDD = 5 V
CONVST to BUSY Delay, VDD = 3 V
BUSY to CS Setup Time
CS to RD Setup Time
t1
t2
t34
t4
t54
t65
t7
t8
t9
t10
0
0
20
15
8
0
120
100
20
15
8
0
120
100
RD Pulsewidth
Data Access Time after Falling Edge of RD
Bus Relinquish Time after Rising Edge of RD
CS to RD Hold Time
Acquisition Time
Quiet Time
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. See
Figure 1.
2The AD7492-5 is specified with VDD = 4.75 V to 5.25 V.
3This is the time needed for the part to settle within 0.5 LSB of its stable value. Conversion can be initiated earlier than 20 µs, but we cannot guarantee that the part
will sample within 0.5 LSB of the true analog input value. Therefore we recommend that the user does not start conversion until after the specified time.
4Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
5t7 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t7, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
Specifications subject to change without notice.
200A
I
OL
TO OUTPUT
PIN
1.6V
C
L
50pF
200A
I
OH
Figure 1. Load Circuit for Digital Output Timing Specifications
–4–
REV. 0
AD7492
ABSOLUTE MAXIMUM RATINGS 1
(TA = 25°C unless otherwise noted)
PIN CONFIGURATION
AVDD to AGND/DGND . . . . . . . . . . . . . . . . . –0.3 V to +7 V
DVDD to AGND/DGND . . . . . . . . . . . . . . . . . –0.3 V to +7 V
1
2
24 DB8
23
DB9
DB10
DB7
22 DB6
21
20 DV
V
DRIVE to AGND/DGND . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
DRIVE to DVDD . . . . . . . . . . . . . . . . –0.3 V to DVDD + 0.3 V
(MSB) DB11
3
AV
4
V
DD
DRIVE
V
REF OUT
5
DD
AGND TO DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Analog Input Voltage to AGND . . . –0.3 V to AVDD + 0.3 V
Digital Input Voltage to DGND . . . –0.3 V to DVDD + 0.3 V
Input Current to Any Pin Except Supplies2 . . . . . . . 10 mA
Operating Temperature Range
Commercial (A and B Versions) . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
SOIC, TSSOP Package Dissipation . . . . . . . . . . . . . . 450 mW
AD7492
TOP VIEW
(Not to Scale)
6
19 DGND
18 DB5
17 DB4
16 DB3
V
IN
AGND
CS
7
8
9
RD
10
11
15
14
DB2
DB1
CONVST
PS/FS
BUSY 12
13 DB0 (LSB)
θ
JA Thermal Impedance . . . . . . . . . . . . . . . 75°C/W (SOIC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C/W (TSSOP)
JC Thermal Impedance . . . . . . . . . . . . . . . 25°C/W (SOIC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35°C/W (TSSOP)
θ
Lead Temperature, Soldering
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi-
tions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7492 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Temperature
Range
Resolution
(Bits)
Throughput Rate
(MSPS)
Package
Description
Package
Option1
Model
AD7492AR
AD7492ARU
AD7492BR
AD7492BRU
AD7492AR-5
AD7492ARU-5
AD7492BR-5
AD7492BRU-5
EVAL-AD7492CB2
EVAL-CONTROL BRD23
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
12
12
12
12
12
12
12
12
1
1
1
1
1.25
1.25
1.25
1.25
SOIC
TSSOP
SOIC
TSSOP
SOIC
TSSOP
SOIC
TSSOP
R-24
RU-24
R-24
RU-24
R-24
RU-24
R-24
RU-24
Evaluation Board
Controller Board
NOTES
1R = SOIC; RU = TSSOP.
2This can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD2 for evaluation/demonstration purposes.
3This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in the CB designators.
REV. 0
–5–
AD7492
PIN FUNCTION DESCRIPTION
Pin
Mnemonic
Function
1–3,
13–18,
22–24
DB9–DB11,
DB0–DB5,
DB6–DB8
Data Bit 0 to DB11. Parallel digital outputs that provide the conversion result for the part. These
are three-state outputs that are controlled by CS and RD. The output high voltage level for these
outputs is determined by the VDRIVE input.
4
AVDD
Analog Supply Voltage, 2.7 V to 5.25 V. This is the only supply voltage for all analog circuitry on
the AD7492. The AVDD and DVDD voltages should ideally be at the same potential and must not
be more than 0.3 V apart, even on a transient basis. This supply should be decoupled to AGND.
5
6
REF OUT
VIN
Reference Out. The output voltage from this pin is 2.5 V 1%.
Analog Input. Single-ended analog input channel. The input range is 0 V to REFIN. The analog
input presents a high dc input impedance.
7
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7492. All analog input
signals should be referred to this AGND voltage. The AGND and DGND voltages should
ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
8
CS
Chip Select. Active low logic input used in conjunction with RD to access the conversion result.
The conversion result is placed on the data bus following the falling edge of both CS and RD.
CS and RD are both connected to the same AND gate on the input so the signals are inter-
changeable. CS can be hardwired permanently low.
9
RD
Read Input. Logic input used in conjunction with CS to access the conversion result. The con-
version result is placed on the data bus following the falling edge of both CS and RD. CS and
RD are both connected to the same AND gate on the input so the signals are interchangeable.
CS and RD can be hardwired permanently low, in which case the data bus is always active and
the result of the new conversion is clocked out slightly before to the BUSY line going low.
10
CONVST
Conversion Start Input. Logic input used to initiate conversion. The input track/hold amplifier
goes from track mode to hold mode on the falling edge of CONVST and the conversion process
is initiated at this point. The conversion input can be as narrow as 10 ns. If the CONVST input
is kept low for the duration of conversion and is still low at the end of conversion, the part will
automatically enter a sleep mode. The type of sleep mode is determined by the PS/FS pin. If the
part enters a sleep mode, the next rising edge of CONVST wakes up the part. Wake-up time
depends on the type of sleep mode.
11
12
PS/FS
Partial Sleep/Full Sleep Mode. This pin determines the type of sleep mode the part will enter if
the CONVST pin is kept low for the duration of the conversion and is still low at the end of
conversion. In partial sleep mode the internal reference circuit and oscillator circuit is not pow-
ered down and draws 250 µA maximum. In full sleep mode all of the analog circuitry is
powered down and the current drawn is negligible. This pin is hardwired either high (DVDD) or
low (GND).
BUSY
BUSY Output. Logic output indicating the status of the conversion process. The BUSY signal
goes high after the falling edge of CONVST and stays high for the duration of conversion. Once
conversion is complete and the conversion result is in the output register, the BUSY line returns
low. The track/hold returns to track mode just prior to the falling edge of BUSY and the acquisi-
tion time for the part begins when BUSY goes low. If the CONVST input is still low when BUSY
goes low, the part automatically enters its sleep mode on the falling edge of BUSY.
19
20
DGND
DVDD
Digital Ground. This is the ground reference point for all digital circuitry on the AD7492. The
DGND and AGND voltages should ideally be at the same potential and must not be more than
0.3 V apart, even on a transient basis.
Digital Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for all digital circuitry on the
AD7492 apart from the output drivers and input circuitry. The DVDD and AVDD voltages
should ideally be at the same potential and must not be more than 0.3 V apart even on a tran-
sient basis. This supply should be decoupled to DGND.
21
VDRIVE
Supply Voltage for the Output Drivers and Digital Input circuitry, 2.7 V to 5.25 V. This voltage
determines the output high voltage for the data output pins and the trigger levels for the digital
inputs. It allows the AVDD and DVDD to operate at 5 V (and maximize the dynamic performance
of the ADC) while the digital input and output pins can interface to 3 V logic.
–6–
REV. 0
AD7492
Peak Harmonic or Spurious Noise
TERMINOLOGY
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is deter-
mined by the largest harmonic in the spectrum, but for ADCs
where the harmonics are buried in the noise floor, it will be a
noise peak.
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1/2 LSB
below the first code transition, and full scale, a point 1/2 LSB
above the last code transition.
Differential Nonlinearity
Intermodulation Distortion
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation distortion terms are
those for which neither m nor n is equal to zero. For example,
the second order terms include (fa + fb) and (fa – fb), while the
third order terms include (2fa + fb), (2fa – fb), (fa + 2fb) and
(fa – 2fb).
Offset Error
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Gain Error
The last transition should occur at the analog value 1 1/2 LSB
below the nominal full scale. The first transition is a 1/2 LSB
above the low end of the scale (zero in the case of AD7492).
The gain error is the deviation of the actual difference between
the first and last code transitions from the ideal difference between
the first and last code transitions with offset errors removed.
The AD7492 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second order terms are usually distanced
in frequency from the original sine waves while the third order
terms are usually at a frequency close to the input frequencies.
As a result, the second and third order terms are specified sepa-
rately. The calculation of the intermodulation distortion is as
per the THD specification where it is the ratio of the rms sum of
the individual distortion products to the rms amplitude of the
sum of the fundamentals expressed in dBs.
Track/Hold Acquisition Time
The track/hold amplifier returns into track mode after the end of
conversion. Track/Hold acquisition time is the time required for
the output of the track/hold amplifier to reach its final value,
within 0.5 LSB, after the end of conversion.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the sum of all nonfundamental signals
up to half the sampling frequency (fS/2), excluding dc. The ratio
is dependent on the number of quantization levels in the digiti-
zation process; the more levels, the smaller the quantization noise.
The theoretical signal to (noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by:
Aperture Delay
In a sample/hold, the time required after the hold command for
the switch to open fully is the aperture delay. The sample is, in
effect, delayed by this interval, and the hold command would
have to be advanced by this amount for precise timing.
Aperture Jitter
Aperture jitter is the range of variation in the aperture delay. In
other words, it is the uncertainty about when the sample is
taken. Jitter is the result of noise which modulates the phase of
the hold command. This specification establishes the ultimate
timing error, hence the maximum sampling frequency for a
given resolution. This error will increase as the input dV/dt
increases.
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB and for a 10-bit con-
verter is 62 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7492 it is defined as:
(V22 +V32 +V42 +V52 +V62)
THD (dB) = 20 log
V
1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
REV. 0
–7–
–Typical Performance Characteristics
AD7492
71
70
69
0
–20
5V
68
67
66
65
–40
–60
3V
64
–80
63
62
61
–100
–120
60
0
500
1000
1500
2000
2500
0
100000
200000
300000
400000
500000
600000
INPUT FREQUENCY – kHz
FREQUENCY – Hz
TPC 1. Typical SNR+D vs. Input Tone
TPC 4. Typical SNR @ 500 kHz Input Tone
95
90
85
80
75
70
65
60
55
50
0
–0.5
5V
5V
–1.0
–1.5
–2.0
–2.5
–3.0
–3.5
3V
100
200
350
500
1000
2000
1
10
100
1000
100000
10000
INPUT FREQUENCY – kHz
FREQUENCY – Hz
TPC 2. Typical THD vs. Input Tone
TPC 5. Typical Bandwidth
70.60
70.40
0
V
= 5V
CC
–40؇C
100mV p-p SINEWAVE ON V
CC
–20
–40
–60
–80
f
= 1MHz, f = 100kHz
SAMPLE
IN
70.20
70.00
69.80
69.60
+25؇C
+125؇C
–55؇C
+85؇C
69.40
69.20
–100
–120
69.00
2.50
4.00
SUPPLY – Volts
4.50
3.50
5.00
5.50
3.00
92
0
5
10 16 20 26 31 36 41 46 51 57 61 67 72 77 82 88
97
49
59
74
3
8 13 18 23 28 34 39
54
64 69
80 84 89 94 100
44
V
RIPPLE FREQUENCY – kHz
CC
TPC 3. Typical SNR vs. Supply
TPC 6. Typical Power Supply Rejection Ratio (PSRR)
–8–
REV. 0
AD7492
1
0.8
0.6
0.4
0.2
0
Figure 3 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in Position A. The comparator is held in a
balanced condition and the sampling capacitor acquires the
signal on VIN
.
CAPACITIVE
DAC
–0.2
2k⍀
A
V
IN
–0.4
–0.6
B
CONTROL LOGIC
SW1
SW2
COMPARATOR
AGND
–0.8
–1
Figure 3. ADC Acquisition Phase
1023
1534
2045
2556
3067
3578
4089
0
512
CODE
Figure 4 shows the ADC during conversion. When conversion
starts, SW2 will open and SW1 will move to Position B, causing
the comparator to become unbalanced. The ADC then runs
through its successive approximation routine and brings the com-
parator back into a balanced condition. When the comparator is
rebalanced, the conversion result is available in the SAR register.
TPC 7. Typical INL for 2.75 V @ 25°C
1
0.8
0.6
0.4
0.2
0
CAPACITIVE
DAC
2k⍀
A
V
IN
SW1
B
CONTROL LOGIC
SW2
–0.2
COMPARATOR
AGND
–0.4
–0.6
Figure 4. ADC Conversion Phase
–0.8
–1
TYPICAL CONNECTION DIAGRAM
Figure 5 shows a typical connection diagram for the AD7492.
Conversion is initiated by a falling edge on CONVST. Once
CONVST goes low the BUSY signal goes high, and at the end
of conversion the falling edge of BUSY is used to activate an
Interrupt Service Routine. The CS and RD lines are then activated
in parallel to read the 12 data bits. The internal bandgap reference
voltage is 2.5 V, providing an analog input range of 0 V to 2.5 V,
making the AD7492 a unipolar A/D. A capacitor with a mini-
mum capacitance of 100 nF is needed at the output of the REF
OUT pin as it stabilizes the internal reference value. It is recom-
mended to perform a dummy conversion after power-up as the
first conversion result could be incorrect. This also ensures that
the part is in the correct mode of operation. The CONVST pin
should not be floating when power is applied as a rising edge on
CONVST might not wake up the part.
1023
1534
2045
CODE
2556
3067
3578
4089
0
512
TPC 8. Typical DNL for 2.75 V @ 25°C
CIRCUIT DESCRIPTION
CONVERTER OPERATION
The AD7492 is a 12-bit successive approximation analog-to-
digital converter based around a capacitive DAC. The AD7492
can convert analog input signals in the range 0 V to VREF. Figure 2
shows a very simplified schematic of the ADC. The Control
Logic, SAR, and the Capacitive DAC are used to add and sub-
tract fixed amounts of charge from the sampling capacitor to
bring the comparator back into a balanced condition.
COMPARATOR
In Figure 5 the VDRIVE pin is tied to DVDD, which results in logic
output voltage values being either 0 V or DVDD. The voltage
applied to VDRIVE controls the voltage value of the output logic
signals and the input logic signals. For example, if DVDD is
supplied by a 5 V supply and VDRIVE by a 3 V supply, the logic
output voltage levels would be either 0 V or 3 V. This feature
allows the AD7492 to interface to 3 V parts while still enabling
the A/D to process signals at 5 V supply.
CAPACITIVE
DAC
V
IN
SWITCHES
SAR
V
REF
CONTROL
INPUTS
CONTROL LOGIC
OUTPUT DATA
12-BIT PARALLEL
Figure 2. Simplified Block Diagram of AD7492
REV. 0
–9–
AD7492
Figure 7 shows the equivalent charging circuit for the sampling
capacitor when the ADC is in its acquisition phase. R3 represents
the source impedance of a buffer amplifier or resistive network,
R1 is an internal switch resistance, R2 is for bandwidth control,
and C1 is the sampling capacitor. C2 is back-plate capacitance
and switch parasitic capacitance.
ANALOG
SUPPLY
2.7V–5.25V
+
+
10F
0.1F
47F
AV
DD
V
DRIVE
DV
DD
1nF
AD7492
C/P
During the acquisition phase the sampling capacitor must be
charged to within 0.5 LSB of its final value.
REF OUT
2.5V
100nF
0V TO 2.5V
V
IN
PARALLELED
INTERFACE
DB0–
DB9 (DB11)
C1
R1
22pF
V
IN
125⍀
R3
PS/FS
CS
R2
636⍀
C2
8pF
CONVST
RD
BUSY
Figure 7. Equivalent Analog Input Circuit
ANALOG INPUT
Figure 8 shows the equivalent circuit of the analog input struc-
ture of the AD7492. The two diodes, D1 and D2, provide ESD
protection for the analog inputs. The capacitor C3 is typically
about 4 pF and can be primarily attributed to pin capacitance.
The resistor R1 is an internal switch resistance. This resistor is
typically about 125 Ω. The capacitor C1 is the sampling capaci-
tor while R2 is used for bandwidth control.
Figure 5. Typical Connection Diagram
ADC TRANSFER FUNCTION
The output coding of the AD7492 is straight binary. The designed
code transitions occur at successive integer LSB values (i.e.,
1 LSB, 2 LSB, etc.). The LSB size is = 2.5/4096 for the AD7492.
The ideal transfer characteristic for the AD7492 is shown in
Figure 6.
111...111
111...110
V
DD
C1
22pF
R1
R2
636⍀
D1
125⍀
V
IN
111...000
C3
4pF
C2
8pF
1LSB = V
/4096
REF
D2
011...111
000...010
000...001
000...000
Figure 8. Equivalent Analog Input Circuit
PARALLEL INTERFACE
The parallel interface of the AD7492 is 12 bits wide. The output
data buffers are activated when both CS and RD are logic low.
At this point the contents of the data register are placed onto the
data bus. Figure 9 shows the timing diagram for the parallel port.
0V 1/2LSB
+V
–1LSB
REF
ANALOG INPUT
Figure 6. Transfer Characteristic for 12 Bits
AC ACQUISITION TIME
In ac applications it is recommended to always buffer analog
input signals. The source impedance of the drive circuitry must
be kept as low as possible to minimize the acquisition time of
the ADC. Large values of impedance at the VIN pin of the
ADC will cause the THD to degrade at high input frequencies.
Figure 10 shows the timing diagram for the parallel port when
CS and RD are tied permanently low. In this setup, once the
BUSY line goes from high to low, the conversion process is
completed. The data is available on the output bus slightly
before the falling edge of BUSY.
It is important to point out that the data bus cannot change
state while the A/D is doing a conversion as this would have a
detrimental effect on the conversion in progress. The data out
lines will go three-state again when either the RD or CS line
goes high. Thus the CS can be tied low permanently, leaving the
RD line to control conversion result access. Please reference the
Table I. Dynamic Performance Specifications
Typical Amplifier
Input
Buffers
SNR
500 kHz
THD
500 kHz
Current
Consumption
AD9631
AD797
69.5
69.6
80
81.6
17 mA
8.2 mA
VDRIVE section for output voltage levels.
OPERATING MODES
The AD7492 has two possible modes of operation depending on
the state of the CONVST pulse at the end of a conversion, Mode 1
and Mode 2.
DC Acquisition Time
The ADC starts a new acquisition phase at the end of a conver-
sion and ends it on the falling edge of the CONVST signal. At
the end of conversion there is a settling time associated with the
sampling circuit. This settling time lasts 120 ns. The analog
signal on VIN is also being acquired during this settling time;
therefore, the minimum acquisition time needed is 120 ns.
Mode 1 (High-Speed Sampling)
In this mode of operation the CONVST pulse is brought high
before the end of conversion, i.e., before the BUSY goes low (see
Figure 10). If the CONVST pin is brought from high to low while
BUSY is high, the conversion is restarted. When operating in
–10–
REV. 0
AD7492
tCONVERT
CONVST
t9
t2
t10
BUSY
t3
CS
RD
t4
t8
t5
t7
t6
DBx
Figure 9. Parallel Port Timing
tCONVERT
CONVST
BUSY
DBx
t9
t2
DATA N
DATA N+1
Figure 10. Parallel Port Timing with CS and RD Tied Low
this mode a new conversion should not be initiated until 140 ns
after BUSY goes low. This acquisition time allows the track/hold
circuit to accurately acquire the input signal. As mentioned
earlier, a read should not be done during a conversion. This
mode facilitates the fastest throughput times for the AD7492.
conversions typically 1 µs after the rising edge of CONVST. The
CONVST line can go from a high to a low during the wake-up
time, but the conversion will still not be initiated until after 1 µs.
We recommend that conversion should not be initiated until at
least 20 µs of the wake-up time has elapsed. This will ensure that
the AD7492 has stabilized to within 0.5 LSB of the analog input
value. After 1 µs, the AD7492 will have only stabilized to within
approximately 3 LSB of the input value. From full sleep this wake-
up time is typically 500 µs. In all cases the BUSY line will only go
high once CONVST goes low. Superior power performance can
be achieved in these modes of operation by waking up the
AD7492 only to carry out a conversion. The optimum power
performance is obtained when using full sleep mode as the ADC
comparator, Reference buffer and Reference circuit is powered
down. While in partial sleep mode, only the ADC comparator is
powered down and the reference buffer is put into a low power
mode. The 100 nF capacitor on the REF OUT pin is kept charged
up by the reference buffer in partial sleep mode while in full
sleep mode this capacitor slowly discharges. This explains why
the wake-up time is shorter in partial sleep mode. In both sleep
modes the clock oscillator circuit is powered down.
Mode 2 (Partial or Full Sleep Mode)
Figure 11 shows AD7492 in Mode 2 operation where the ADC
goes into either partial or full sleep mode after conversion. The
CONVST line is brought low to initiate a conversion and remains
low until after the end of conversion. If CONVST goes high and
low again while BUSY is high, the conversion is restarted. Once
the BUSY line goes from a high to a low, the CONVST line has its
status checked and, if low, the part enters a sleep mode. The
type of sleep mode the AD7492 enters depends on what ever
way the PS/FS pin is hardwired. If the PS/FS pin is tied high,
the AD7492 will enter partial sleep mode. If the PS/FS pin is
tied low, the AD7492 will enter full sleep mode.
The device wakes up again on the rising edge of the CONVST
signal. From partial sleep the AD7492 is capable of starting
tCONVERT
CONVST
tWAKEUP
BUSY
CS
RD
DBx
Figure 11. Mode 2 Operation
–11–
REV. 0
AD7492
VDRIVE
CONVST
The VDRIVE pin is used as the voltage supply to the digital output
drivers and the digital input circuitry. It is a separate supply
from AVDD and DVDD. The purpose of using a separate supply
for the digital input/output interface is that the user can vary the
output high voltage, VOH, and the logic input levels, VINH and
VINL, from the VDD supply to the AD7492. For example, if
AVDD and DVDD are using a 5 V supply, the VDRIVE pin can be
powered from a 3 V supply. The ADC has better dynamic per-
formance at 5 V than at 3 V, so operating the part at 5 V, while
still being able to interface to 3 V parts, pushes the AD7492 to
the top bracket of high performance 12-bit A/Ds. Of course, the
ADC can have its VDRIVE and DVDD pins connected together
and be powered from a 3 V or 5 V supply. The trigger levels are
VDRIVE × 0.7 and VDRIVE × 0.3 for the digital inputs.
tCONVERT
tQUIESCENT
BUSY
1.12s
880ns
2s
Figure 12. Mode 1 Power Dissipation
Mode 2 (Full Sleep Mode)
Figure 13 shows the AD7492 conversion sequence in Mode 2,
Full Sleep mode, using a throughput rate of approximately
100 SPS. At 5 V supply the current consumption for the part
when converting is 3 mA, while the full sleep current is 1 µA
max. The power dissipated during this power-down is negligible
and thus not worth considering in the total power figure. During
the wake-up phase, the AD7492 will draw typically 1.8 mA. Over-
all power dissipated is:
The pins that are powered from VDRIVE are DB0–DB11, CS,
RD, CONVST, and BUSY.
PS/FS PIN
As previously mentioned, the PS/FS pin is used to control the
type of power-down mode that the AD7492 can enter into if
operated in Mode 2. This pin can be hardwired either high or
low, or even controlled by another device. It is important to
note that toggling the PS/FS pin while in power-down mode will
not switch the part between partial sleep and full sleep modes.
To switch from one sleep mode to another, the AD7492 will have
to be powered up and the polarity of the PS/FS pin changed. It
can then be powered down to the required sleep mode.
(880 ns/10 ms) × (5 × 3 mA) + (500 µs/10 ms) × (5 × 1.8 mA)
= 451.32 µW
tCONVERT
tWAKEUP
CONVST
500s
tQUIESCENT
BUSY
POWER-UP
It is recommended that the user performs a dummy conversion
after power-up, as the first conversion result could be incorrect.
This also ensures that the parts is in the correct mode of opera-
tion. The recommended power-up sequence is as follows:
9.5ms
880ns
10ms
Figure 13. Full Sleep Power Dissipation
Mode 2 (Partial Sleep Mode)
1 > GND
2 > VDD
4 > Digital Inputs
5 > VIN
Figure 14 shows the AD7492 conversion sequence in Mode 2,
Partial Sleep mode, using a throughput rate of 1 kSPS. At 5 V
supply the current consumption for the part when converting is
3 mA, while the partial sleep current is 250 µA max. During the
wake-up phase, the AD7492 will draw typically 1.8 mA. Power
dissipated during wake-up and conversion is :
3 > VDRIVE
Power vs. Throughput
The two modes of operation for the AD7492 will produce dif-
ferent power versus throughput performances, Mode 1 and
Mode 2; see Operating Modes section of the data sheet for more
detailed descriptions of these modes. Mode 2 is the Sleep Mode
(Partial/Full) of the part and it achieves the optimum power
performance.
(880 ns/1 ms) × (5 × 3 mA) + (20 µs/1 ms) × (5 × 1.8 mA) =
193.2 µW
Power dissipated during power-down is:
Mode 1
(979 µs/1 ms) × (5 × 250 µA) = 1.22 mW
Figure 12 shows the AD7492 conversion sequence in Mode 1
using a throughput rate of 500 kSPS. At 5 V supply the current
consumption for the part when converting is 3 mA and the quies-
cent current is 1.8 mA. The conversion time of 880 ns contributes
6.6 mW to the overall power dissipation in the following way:
Overall power dissipated is:
193.2 µW + 1.22 mW = 1.41 mW
tCONVERT
tWAKEUP
(880 ns/2 µs) × (5 × 3 mA) = 6.6 mW
CONVST
20s
The contribution to the total power dissipated by the remaining
1.12 µs of the cycle is 5.04 mW.
tQUIESCENT
BUSY
(1.12 µs/2 µs) × (5 × 1.8 mA) = 5.04 mW
Thus the power dissipated during each cycle is:
6.6 mW + 5.04 mW = 11.64 mW
880ns
1ms
979s
Figure 14. Partial Sleep Power Dissipation
–12–
REV. 0
AD7492
Figure 15 to Figure 17 show a typical graphical representation
of Power versus Throughput for the AD7492 when in (a) Mode
1 @ 5 V and 3 V, (b) Mode 2 in full sleep mode @ 5 V and 3 V
and (c) Mode 2 in partial sleep mode @ 5 V and 3 V.
GROUNDING AND LAYOUT
The analog and digital power supplies are independent and
separately pinned out to minimize coupling between analog and
digital sections within the device. To complement the excellent
noise performance of the AD7492 it is imperative that care be
given to the PCB layout. Figure 18 shows a recommended
connection diagram for the AD7492.
12
10
All of the AD7492 ground pins should be soldered directly to a
5V
ground plane to minimize series inductance. The AVDD, DVDD
and VDRIVE pins should be decoupled to both the analog and
,
8
6
4
digital ground planes. The REF OUT pin should be decoupled
to the analog ground plane with a minimum capacitor value of
100 nF. This capacitor helps to stabilize the internal reference
circuit. The large value capacitors will decouple low frequency
noise to analog ground, the small value capacitors will decouple
high frequency noise to digital ground. All digital circuitry power
pins should be decoupled to the digital ground plane. The use
of ground planes can physically separate sensitive analog com-
ponents from the noisy digital system. The two ground planes
should be joined in only one place and should not overlap so as
to minimize capacitive coupling between them. If the AD7492
is in a system where multiple devices require AGND to DGND
connections, the connection should still be made at one point
only, a star ground point, that should be established as close as
possible to the AD7492.
3V
2
0
0
100 200
400 500 600
800 900 1000
300
700
THROUGHPUT – kHz
Figure 15. Power vs. Throughput (Mode 1 @ 5 V and 3 V)
3.5
3.0
ANALOG
SUPPLY
5V
2.5
+
+
10F
0.1F
47F
2.0
5V
AV
DD
1.5
DV
DD
1nF
AGND
DGND
3V
1.0
AD7492
0.5
0
V
DRIVE
+
1nF
10F
0
10
20
40
50
60
80
90
100
30
70
THROUGHPUT – kHz
REF OUT
2.5V
+
100nF
Figure 16. Power vs. Throughput (Mode 2 in Full Sleep
Mode @ 5 V and 3 V)
Figure 18. Typical Decoupling Circuit
2.5
Noise can be minimized by applying some simple rules to the
PCB layout: analog signals should be kept away from digital
signals; fast switching signals like clocks should be shielded with
digital ground to avoid radiating noise to other sections of the
board and clock signals should never be run near the analog
inputs; avoid running digital lines under the device as these will
couple noise onto the die; the power supply lines to the AD7492
should use as large a trace as possible to provide a low imped-
ance path and reduce the effects of glitches on the power supply
line; avoid crossover of digital and analog signals and place
traces that are on opposite sides of the board at right angles
to each other.
5V
2.0
1.5
1.0
0.5
0
3V
Noise to the analog power line can be further reduced by use of
multiple decoupling capacitors as shown in Figure 18. Decou-
pling capacitors should be placed directly at the power inlet to
the PCB and also as close as possible to the power pins of the
AD7492. The same decoupling method should be used on other
ICs on the PCB, with the capacitor leads as short as possible to
minimize lead inductance.
0
10
20
40
50
60
80
90
100
30
70
THROUGHPUT – kHz
Figure 17. Power vs. Throughput (Mode 2 in Partial
Sleep Mode @ 5 V and 3 V)
REV. 0
–13–
AD7492
POWER SUPPLIES
AD7492 to TMS320C25 Interface
Separate power supplies for AVDD and DVDD are desirable, but
Figure 21 shows an interface between the AD7492 and the
TMS320C25. The CONVST signal can be applied from the
TMS320C25 or from an external source. The BUSY line inter-
rupts the digital signal processor when conversion is completed.
The TMS320C25 does not have a separate RD output to drive
the AD7492 RD input directly. This has to be generated from
the processor STRB and R/W outputs with the addition of some
glue logic. The RD signal is OR-gated with the MSC signal to
provide the WAIT state required in the read cycle for correct
interface timing. The following instruction is used to read the
conversion from the AD7492:
if necessary, DVDD may share its power connection to AVDD
The digital supply (DVDD) must not exceed the analog supply
(AVDD) by more than 0.3 V in normal operation.
.
MICROPROCESSOR INTERFACING
AD7492 to ADSP-2185 Interface
Figure 19 shows a typical interface between the AD7492 and the
ADSP-2185. The ADSP-2185 processor can be used in one of two
memory modes, Full Memory Mode and Host Mode. The Mode
C pin determines in which mode the processor works. The inter-
face in Figure 19 is set up to have the processor working in Full
Memory Mode, which allows full external addressing capabilities.
IN D,ADC
where D is Data Memory address and the ADC is the AD7492
address. The read operation must not be attempted during
conversion.
When the AD7492 has finished converting, the BUSY line
requests an interrupt through the IRQ2 pin. The IRQ2 interrupt
has to be set up in the interrupt control register as edge-sensitive.
The DMS (Data Memory Select) pin latches in the address of the
A/D into the address decoder. The read operation is thus started.
OPTIONAL
CONVST
A0–A15
OPTIONAL
ADDRESS BUS
AD7492
TMS320C25*
CONVST
A0–A15
ADDRESS BUS
ADDRESS
DECODER
CS
IS
AD7492
ADSP-2185*
ADDRESS
DECODER
BUSY
CS
DMS
STRB
IRQ2
RD
BUSY
RD
R/W
RD
100k⍀
READY
MODE C
DB0–DB9
(DB11)
MSC
DB0–DB9
(DB11)
D0–D23
DATA BUS
DMD0–DMD15
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 19. Interfacing to the ADSP-2185
*ADDITIONAL PINS OMITTED FOR CLARITY
AD7492 to ADSP-21065L Interface
Figure 21. Interfacing to the TMS320C25
AD7492 to PIC17C4x Interface
Figure 20 shows a typical interface between the AD7492 and the
ADSP-21065L SHARC® processor. This interface is an example
of one of three DMA handshake modes. The MSX control line
is actually three memory select lines. Internal ADDR25–24 are
decoded into MS3-0, these lines are then asserted as chip selects.
The DMAR1 (DMA Request 1) is used in this setup as the
interrupt to signal end of conversion. The rest of the interface is
standard handshaking operation.
Figure 22 shows a typical parallel interface between the AD7492
and PIC17C42/43/44. The microcontroller sees the A/D as
another memory device with its own specific memory address on
the memory map. The CONVST signal can either be controlled
by the microcontroller or an external source. The BUSY signal
provides an interrupt request to the microcontroller when a con-
version ends. The INT pin on the PIC17C42/43/44 must be
configured to be active on the negative edge. PORTC and PORTD
of the microcontroller are bidirectional and used to address the
AD7492 and also to read in the 12-bit data. The OE pin on the
PIC can be used to enable the output buffers on the AD7492 and
preform a read operation.
OPTIONAL
CONVST
ADDR –ADDR
23
ADDRESS BUS
0
AD7492
ADDRESS
LATCH
MS
X
OPTIONAL
ADDRESS
BUS
ADSP-21065L*
CONVST
PIC17C4x*
ADDRESS
DECODER
CS
DB0–DB9
(DB11)
DMAR
BUSY
1
AD0–AD15
AD74792
RD
RD
DB0–DB9
(DB11)
ADDRESS
LATCH
ADDRESS
DECODER
CS
ALE
D0–D31
DATA BUS
OE
RD
INT
BUSY
*ADDITIONAL PINS OMITTED FOR CLARITY
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 20. Interfacing to ADSP-21065L
Figure 22. Interfacing to the PIC17C4x
SHARC is a registered trademark of Analog Devices, Inc.
–14–
REV. 0
AD7492
AD7492 to 80C186 Interface
OPTIONAL
Figure 23 shows the AD7492 interfaced to the 80C186 micropro-
cessor. The 80C186 DMA controller provides two independent
high-speed DMA channels where data transfer can occur between
memory and I/O spaces. (The AD7492 occupies one of these I/O
spaces.) Each data transfer consumes two bus cycles, one cycle
to fetch data and the other to store data.
AD0–AD15
A16–A19
ADDRESS/DATA BUS
CONVST
ADDRESS
LATCH
ALE
AD7492
ADDRESS
BUS
80C186*
ADDRESS
DECODER
CS
After the AD7492 has finished conversion, the BUSY line gen-
erates a DMA request to Channel 1 (DRQ1). As a result of the
interrupt, the processor performs a DMA READ operation
which also resets the interrupt latch. Sufficient priority must
be assigned to the DMA channel to ensure that the DMA
request will be serviced before the completion of the next con-
version. This configuration can be used with 6 MHz and 8 MHz
80C186 processors.
DRQ1
Q
R
S
BUSY
RD
RD
DB0–DB9
(DB11)
DATA BUS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 23. Interfacing to 80C186
REV. 0
–15–
AD7492
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead SOIC
(R-24)
0.6141 (15.60)
0.5985 (15.20)
24
1
13
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
12
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
0.0098 (0.25)
؋
45؇ 8؇
0؇
0.0500
(1.27)
BSC
SEATING
PLANE
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
0.0500 (1.27)
0.0157 (0.40)
0.0125 (0.32)
0.0091 (0.23)
24-Lead TSSOP
(RU-24)
0.311 (7.90)
0.303 (7.70)
24
13
0.177 (4.50)
0.169 (4.30)
0.256 (6.50)
0.246 (6.25)
1
12
PIN 1
0.006 (0.15)
0.002 (0.05)
0.0433 (1.10)
MAX
8؇
0؇
0.0256 (0.65) 0.0118 (0.30)
0.028 (0.70)
0.020 (0.50)
SEATING
PLANE
0.0079 (0.20)
0.0035 (0.090)
BSC
0.0075 (0.19)
–16–
REV. 0
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