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AD7490 [ADI]

16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP; 16通道， 1 MSPS ， 12位ADC，定序器采用28引脚TSSOP
AD7490
型号： AD7490
厂家： ADI    ADI
描述：

16-Channel, 1 MSPS, 12-Bit ADC with Sequencer in 28-Lead TSSOP
16通道， 1 MSPS ， 12位ADC，定序器采用28引脚TSSOP
文件： 总24页 (文件大小：904K)
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16-Channel, 1 MSPS, 12-Bit ADC  
with Sequencer in 28-Lead TSSOP  
a
AD7490  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
Fast Throughput Rate: 1 MSPS  
V
DD  
Specified for VDD of 2.7 V to 5.25 V  
Low Power at Max Throughput Rates:  
5.4 mW Max at 870 kSPS with 3 V Supplies  
12.5 mW Max at 1 MSPS with 5 V Supplies  
16 (Single-Ended) Inputs with Sequencer  
Wide Input Bandwidth:  
69.5 dB SNR at 50 kHz Input Frequency  
Flexible Power/Serial Clock Speed Management  
No Pipeline Delays  
High Speed Serial Interface SPI™/QSPI™/  
MICROWIRE™/DSP Compatible  
Full Shutdown Mode: 0.5 ꢀA Max  
28-Lead TSSOP and 32-Lead LFCSP Packages  
REF  
IN  
V
0
IN  
T/H  
•
•
•
•
•
•
•
•
•
•
•
•
•
12-BIT  
SUCCESSIVE  
APPROXIMATION  
ADC  
I/P  
MUX  
V
15  
IN  
SCLK  
DOUT  
DIN  
CONTROL LOGIC  
SEQUENCER  
GENERAL DESCRIPTION  
The AD7490 is a 12-bit high speed, low power, 16-channel,  
successive-approximation ADC. The part operates from a single  
2.7 V to 5.25 V power supply and features throughput rates up  
to 1 MSPS. The part contains a low noise, wide bandwidth  
track-and-hold amplifier that can handle input frequencies in  
excess of 1 MHz.  
CS  
AD7490  
V
DRIVE  
GND  
The conversion process and data acquisition are controlled  
using CS and the serial clock signal, allowing the device to  
easily interface with microprocessors or DSPs. The input signal  
is sampled on the falling edge of CS and conversion is also  
initiated at this point. There are no pipeline delays associated  
with the part.  
PRODUCT HIGHLIGHTS  
1. High Throughput with Low Power Consumption  
The AD7490 offers up to 1 MSPS throughput rates. At  
maximum throughput with 3 V supplies, the AD7490  
dissipates just 5.4 mW of power.  
The AD7490 uses advanced design techniques to achieve very  
low power dissipation at high throughput rates. For maximum  
throughput rates, the AD7490 consumes just 1.8 mA with 3 V  
supplies, and 2.5 mA with 5 V supplies.  
2. Sixteen Single-Ended Inputs with Channel Sequencer  
A Sequence of channels can be selected, through which the  
AD7490 will cycle and convert.  
3. Single-Supply Operation with VDRIVE Function  
By setting the relevant bits in the Control Register, the analog  
input range for the part can be selected to be a 0 to REFIN input or  
a 0 to 2 ꢀ REFIN with either straight binary or twos complement  
output coding. The AD7490 features 16 single-ended analog  
inputs with a channel sequencer to allow a preprogrammed  
selection of channels to be converted sequentially.  
The AD7490 operates from a single 2.7 V to 5.25 V supply.  
The VDRIVE function allows the serial interface to connect  
directly to either 3 V or 5 V processor systems independent  
of VDD  
.
4. Flexible Power/Serial Clock Speed Management  
The conversion rate is determined by the serial clock, allowing  
the conversion time to be reduced through the serial clock  
speed increase. The part also features various shutdown  
modes to maximize power efficiency at lower throughput  
rates. Power consumption is 0.5 µA max when in full shutdown.  
The conversion time is determined by the SCLK frequency as  
this is also used as the master clock to control the conversion.  
The AD7490 is available in a 28-lead thin shrink small outline  
(TSSOP) package, and a 32-lead chip scale package.  
5. No Pipeline Delay  
The part features a standard successive-approximation ADC  
with accurate control of the sampling instant via a CS input  
and once off conversion control.  
SPI and QSPI are trademarks of Motorola Inc.  
MICROWIRE is a trademark of National Semiconductor Corporation  
REV. A  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat  
may result from its use. No license is granted by implication or otherwise  
under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
www.analog.com  
© Analog Devices, Inc., 2002  
(VDD = VDRIVE = 2.7 V to 5.25 V, REFIN = 2.5 V, fSCLK1 = 20 MHz, TA = TMIN to TMAX, unless  
AD7490–SPECIFICATIONS otherwise noted.)  
Parameter  
B Version2  
Unit  
Test Conditions/Comments  
IN = 50 kHz Sine Wave, fSCLK = 20 MHz  
@ 5 V, 70.5 dB typ  
@ 3 V, 69.5 dB typ  
DYNAMIC PERFORMANCE  
f
Signal to Noise +1 Distortion (SINAD)3  
69  
68  
69.5  
–74  
–71  
–75  
–73  
dB min  
dB min  
dB min  
dB max  
dB max  
dB max  
dB max  
Signal to Noise Ratio (SNR)3  
Total Harmonic Distortion (THD)3  
@ 5 V, –84 dB typ  
@ 3 V, –77 dB typ  
@ 5 V, –86 dB typ  
@ 3 V, –80 dB typ  
Peak Harmonic or Spurious Noise (SFDR)3  
Intermodulation Distortion (IMD)3  
Second Order Terms  
Third Order Terms  
fa = 40.1 kHz, fb = 41.5 kHz  
–85  
–85  
10  
dB typ  
dB typ  
ns typ  
Aperture Delay  
Aperture Jitter  
50  
ps typ  
Channel-to-Channel Isolation3  
Full Power Bandwidth  
–82  
8.2  
1.6  
dB typ  
MHz typ  
MHz typ  
fIN = 400 kHz  
@ 3 dB  
@ 0.1 dB  
DC ACCURACY3  
Resolution  
Integral Nonlinearity  
Differential Nonlinearity  
0 V to VREF IN Input Range  
Offset Error  
Offset Error Match  
Gain Error  
Gain Error Match  
0 V to 2 ꢀ VREF IN Input Range  
12  
1
–0.95/+1.5  
Bits  
LSB max  
LSB max  
Guaranteed No Missed Codes to 12 Bits  
Straight Binary Output Coding  
0.6 LSB typ  
8
0.5  
2
LSB max  
LSB max  
LSB max  
LSB max  
0.6  
–VREF IN to +VREF IN Biased about VREF with  
Twos Complement Output Coding Offset  
Positive Gain Error  
Positive Gain Error Match  
Zero Code Error  
Zero Code Error Match  
Negative Gain Error  
Negative Gain Error Match  
2
0.5  
8
0.5  
1
0.5  
LSB max  
LSB max  
LSB max  
LSB max  
LSB max  
LSB max  
0.6 LSB typ  
ANALOG INPUT  
Input Voltage Ranges  
0 to REFIN  
0 to 2 ꢀ REFIN  
V
V
RANGE Bit Set to 1  
RANGE Bit Set to 0,  
VDD/VDRIVE = 4.75 V to 5.25 V for 0 to 2 ꢀ REFIN  
DC Leakage Current  
Input Capacitance  
1
20  
µA max  
pF typ  
REFERENCE INPUT  
REFIN Input Voltage  
DC Leakage Current  
REFIN Input Impedance  
2.5  
1
36  
V
1% Specified Performance  
fSAMPLE = 1 MSPS  
µA max  
kΩ typ  
LOGIC INPUTS  
Input High Voltage, VINH  
Input Low Voltage, VINL  
Input Current, IIN  
0.7 ꢀ VDRIVE V min  
0.3 ꢀ VDRIVE V max  
1
µA max  
pF max  
Typically 10 nA, VIN 5 0 V or VDRIVE  
4
Input Capacitance, CIN  
10  
LOGIC OUTPUTS  
Output High Voltage, VOH  
Output Low Voltage, VOL  
Floating-State Leakage Current  
Floating-State Output Capacitance4  
Output Coding  
VDRIVE – 0.2  
V min  
ISOURCE = 200 µA; VDD = 2.7 V to 5.25 V  
ISINK = 200 µA  
Weak/Tri Bit Set to 0  
Weak/Tri Bit Set to 0  
Coding Bit Set to 1  
0.4  
10  
10  
V max  
µA max  
pF max  
Straight (Natural) Binary  
Twos Complement  
Coding Bit Set to 0  
–2–  
REV. A  
AD7490  
Parameter  
B Version2  
Unit  
Test Conditions/Comments  
CONVERSION RATE  
Conversion Time  
800  
300  
300  
1
ns max  
ns max  
ns max  
MSPS max  
16 SCLK Cycles, SCLK = 20 MHz  
Sine Wave Input  
Full-Scale Step Input  
Track-and-Hold Acquisition Time3  
Throughput Rate  
@ 5 V (See Serial Interface section.)  
POWER REQUIREMENTS  
VDD  
2.7/5.25  
2.7/5.25  
V min/max  
V min/max  
VDRIVE  
5
IDD  
Digital I/Ps = 0 V or VDRIVE  
Normal Mode (Static)  
Normal Mode (Operational)  
(fS = Max Throughput)  
Auto Standby Mode  
600  
2.5  
1.8  
1.55  
92  
960  
0.5  
0.5  
µA typ  
VDD = 2.7 V to 5.25 V, SCLK On or Off  
VDD = 4.75 V to 5.25 V, fSCLK = 20 MHz  
VDD = 2.7 V to 3.6 V, fSCLK = 20 MHz  
fSAMPLE = 500 kSPS  
Static  
fSAMPLE = 250 kSPS  
mA max  
mA max  
mA typ  
µA max  
µA typ  
Auto Shutdown Mode  
µA max  
µA max  
Static  
Full Shutdown Mode  
Power Dissipation5  
SCLK On or Off (20 nA typ)  
Normal Mode (Operational)  
12.5  
5.4  
460  
276  
2.5  
1.5  
2.5  
1.5  
mW max  
mW max  
µW max  
µW max  
µW max  
µW max  
µW max  
µW max  
VDD = 5 V, fSCLK = 20 MHz  
VDD = 3 V, fSCLK = 20 MHz  
VDD = 5 V  
VDD = 3 V  
VDD = 5 V  
Auto Standby Mode (Static)  
Auto Shutdown Mode (Static)  
Full Shutdown Mode  
V
DD = 3 V  
VDD = 5 V  
VDD = 3 V  
NOTES  
1Specifications apply for fSCLK up to 20 MHz. However, for serial interfacing requirements, see Timing Specifications.  
2Temperature Ranges (B Version): –40°C to +85°C.  
3See Terminology section.  
4Sample tested at 25°C to ensure compliance.  
5See Power Versus Throughput Rate section.  
Specifications subject to change without notice.  
REV. A  
–3–  
AD7490  
TIMING SPECIFICATIONS1 (VDD = 2.7 V to 5.25 V, VDRIVE ≤ VDD, REFIN = 2.5 V; TA = TMIN to TMAX, unless otherwise noted.)  
Limit at TMIN, TMAX  
Parameter  
VDD = 3 V  
VDD = 5 V  
Unit  
Description  
2
fSCLK  
10  
10  
kHz min  
16  
20  
MHz max  
tCONVERT  
tQUIET  
16 ꢀ tSCLK  
50  
16 ꢀ tSCLK  
50  
ns min  
Minimum Quiet Time Required between Bus  
Relinquish and Start of Next Conversion  
CS to SCLK Setup Time  
Delay from CS until DOUT Three-State Disabled  
Delay from CS to DOUT Valid  
Data Access Time after SCLK Falling Edge  
SCLK Low Pulsewidth  
SCLK High Pulsewidth  
SCLK to DOUT Valid Hold Time  
SCLK Falling Edge to DOUT High Impedance  
DIN Setup Time prior to SCLK Falling Edge  
DIN Hold Time after SCLK Falling Edge  
Sixteenth SCLK Falling Edge to CS High  
Power-Up Time from Full Power-Down/  
Auto Shutdown/Auto Standby Modes  
t23  
t3  
12  
20  
30  
60  
0.4 tSCLK  
0.4 tSCLK  
15  
15/50  
20  
5
20  
1
10  
14  
20  
40  
0.4 tSCLK  
0.4 tSCLK  
15  
15/50  
20  
5
20  
1
ns min  
ns max  
ns max  
ns max  
ns min  
ns min  
ns min  
ns min/max  
ns min  
ns min  
ns min  
µs max  
t3b3 4  
t4  
t5  
t6  
t75  
t8  
t9  
t10  
t11  
t12  
NOTES  
1Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.  
(See Figure 1.) The 3 V operating range spans from 2.7 V to 3.6 V. The 5 V operating range spans from 4.75 V to 5.25 V.  
2Mark/Space ratio for the SCLK input is 40/60 to 60/40. The maximum SCLK frequency is 16 MHz with VDD = 3 V to give a throughput of 870 kSPS. Care must be  
taken when interfacing to account for data access time t4, and the setup time required for the user’s processor. These two times will determine the maximum SCLK  
frequency with which the user’s system can operate. (See Serial Interface section.)  
3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.4 V or 0.7 VDRIVE V.  
4t3b represents a worst-case figure for having ADD3 available on the DOUT line, i.e., if the AD7490 went back into three-state at the end of a conversion and some  
other device took control of the bus between conversions, the user would have to wait a maximum time of t3b before having ADD3 valid on DOUT line. If the DOUT  
line is weakly driven to ADD3 between conversions, then the user would typically have to wait 17 ns at 3 V and 12 ns at 5 V after the CS falling edge before seeing  
ADD3 valid on DOUT.  
5t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated  
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics, is the true bus relinquish  
time of the part and is independent of the bus loading.  
Specifications subject to change without notice.  
–4–  
REV. A  
AD7490  
ABSOLUTE MAXIMUM RATINGS1  
LFCSP, TSSOP Package, Power Dissipation . . . . . . 450 mW  
(TA = 25°C, unless otherwise noted.)  
θ
JA Thermal Impedance . . . . . . . . . . . 108.2°C/W (LFCSP)  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 97.9°C/W (TSSOP)  
JC Thermal Impedance . . . . . . . . . . . 32.71°C/W (LFCSP)  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14°C/W (TSSOP)  
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V  
VDRIVE to GND . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V  
Analog Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V  
Digital Input Voltage to GND . . . . . . . . . . . . . –0.3 V to +7 V  
Digital Output Voltage to GND . . . . . –0.3 V to VDD + 0.3 V  
REFIN to GND . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V  
Input Current to Any Pin Except Supplies2 . . . . . . . . 10 mA  
Operating Temperature Ranges  
θ
Lead Temperature, Soldering  
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . 215°C  
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 220°C  
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV  
NOTES  
1 Stresses above those listed under Absolute Maximum Ratings may cause perma-  
nent damage to the device. This is a stress rating only; functional operation of the  
device at these or any other conditions above those listed in the operational  
sections of this specification is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect device reliability.  
Commercial (B Version) . . . . . . . . . . . . . . –40°C to +85°C  
Storage Temperature Range . . . . . . . . . . . –65°C to +150°C  
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C  
2 Transient currents of up to 100 mA will not cause SCR latch up.  
200ꢀA  
I
OL  
TO  
OUTPUT  
PIN  
1.6V  
C
L
25pF  
200ꢀA  
I
OH  
Figure 1. Load Circuit for Digital Output Timing Specifications  
ORDERING GUIDE  
Temperature  
Range  
Linearity  
Package  
Option  
Package  
Description  
Model  
Error (LSB)1  
AD7490BCP  
–40°C to +85°C  
–40°C to +85°C  
Evaluation Board  
1
1
CP-32  
RU-28  
LFCSP  
TSSOP  
AD7490BRU  
EVAL-AD7490CB2  
EVAL-CONTROL BRD23 Controller Board  
NOTES  
1Linearity error refers to integral linearity error.  
2This can be used as a stand-alone evaluation board or in conjunction with the Evaluation Controller Board for evaluation/  
demonstration purposes.  
3This board is a complete unit allowing a PC to control and communicate with all Analog Devices evaluation boards ending in  
the CB designators. To order a complete evaluation kit, you will need to order the particular ADC evaluation board, e.g.,  
EVAL-AD7490CB, the EVAL-CONTROL-BRD2, and a 12 V ac transformer. See relevant evaluation board technical note for  
more information.  
CAUTION  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily  
accumulate on the human body and test equipment and can discharge without detection. Although  
the AD7490 features proprietary ESD protection circuitry, permanent damage may occur on  
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are  
recommended to avoid performance degradation or loss of functionality.  
WARNING!  
ESD SENSITIVE DEVICE  
REV. A  
–5–  
AD7490  
PIN CONFIGURATIONS*  
28-Lead TSSOP  
32-Lead LFCSP  
V
11  
10  
9
V
12  
13  
14  
15  
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
IN  
IN  
V
IN  
V
IN  
32 31 30 29 28 27 26 25  
V
V
IN  
3
IN  
1
2
3
4
5
6
7
8
NC  
24  
23  
22  
21  
20  
19  
18  
17  
V
15  
IN  
NC  
V
IN  
4
V
8
NC  
IN  
V
8
IN  
AGND  
5
V
7
6
AGND  
IN  
V
7
6
REF  
IN  
6
IN  
V
V
AD7490  
REF  
IN  
IN  
AD7490  
V
V
V
7
IN  
DD  
TOP VIEW  
TOP VIEW  
5
4
V
IN  
DD  
(Not to Scale)  
(Not to Scale)  
5
4
AGND  
8
IN  
V
V
AGND  
IN  
V
V
9
IN  
CS  
3
CS  
IN  
3
2
DIN  
10  
11  
12  
13  
14  
NC  
DIN  
IN  
V
V
NC  
IN  
9
10 11 12 13 14 15 16  
NC = NO CONNECT  
1
0
V
DRIVE  
IN  
V
SCLK  
DOUT  
IN  
AGND  
NC = NO CONNECT  
EXPOSED PAD SHOULD BETIEDTO AGND  
*ALL NC PINS SHOULD BE CONNECTED STRAIGHT TO AGND  
PIN FUNCTION DESCRIPTIONS  
Mnemonic  
Function  
CS  
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the  
AD7490 and also frames the serial data transfer.  
REFIN  
VDD  
Reference Input for the AD7490. An external reference must be applied to this input. The voltage range  
for the external reference is 2.5 V 1% for specified performance.  
Power Supply Input. The VDD range for the AD7490 is from 2.7 V to 5.25 V. For the 0 to 2 ꢀ REFIN  
range, VDD should be from 4.75 V to 5.25 V.  
AGND  
Analog Ground. Ground reference point for all circuitry on the AD7490. All analog/digital input signals  
and any external reference signal should be referred to this AGND voltage. All AGND pins should be  
connected together.  
VIN0–VIN15  
Analog Input 0 through Analog Input 15. Sixteen single-ended analog input channels that are multiplexed  
into the on-chip track-and-hold. The analog input channel to be converted is selected by using the address  
bits ADD3 through ADD0 of the control register. The address bits in conjunction with the SEQ and  
SHADOW bits allow the Sequence Register to be programmed. The input range for all input channels can  
extend from 0 V to REFIN or 0 V to 2 ꢀ REFIN as selected via the RANGE bit in the Control Register.  
Any unused input channels should be connected to AGND to avoid noise pickup.  
DIN  
Data In. Logic input. Data to be written to the AD7490’s Control Register is provided on this input and  
is clocked into the register on the falling edge of SCLK (see Control Register section).  
DOUT  
Data Out. Logic output. The conversion result from the AD7490 is provided on this output as a serial  
data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists  
of four address bits indicating which channel the conversion result corresponds to, followed by the 12 bits  
of conversion data, which is provided MSB first. The output coding may be selected as straight binary or  
twos complement via the CODING Bit in the Control Register.  
SCLK  
VDRIVE  
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock  
input is also used as the clock source for the AD7490’s conversion process.  
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface  
of the AD7490 will operate.  
–6–  
REV. A  
AD7490  
TERMINOLOGY  
PSR (Power Supply Rejection)  
Integral Nonlinearity  
Variations in power supply will affect the full scale transition, but not  
the converter’s linearity. Power supply rejection is the maximum  
change in full-scale transition point due to a change in power-  
supply voltage from the nominal value. (See Typical Performance  
Characteristics.)  
This is the maximum deviation from a straight line passing through  
the endpoints of the ADC transfer function. The endpoints of  
the transfer function are zero scale, a point 1 LSB below the first  
code transition, and full scale, a point 1 LSB above the last code  
transition.  
Track/Hold Acquisition Time  
Differential Nonlinearity  
This is the difference between the measured and the ideal 1 LSB  
change between any two adjacent codes in the ADC.  
The track/hold amplifier returns into track on the 14th SCLK  
falling edge. Track/hold acquisition time is the minimum time  
required for the track and hold amplifier to remain in track  
mode for its output to reach and settle to within 1 LSB of the  
applied input signal, given a step change to the input signal.  
Offset Error  
This is the deviation of the first code transition (00…000) to  
(00…001) from the ideal, i.e., AGND ꢁ 1 LSB.  
Signal to (Noise + Distortion) Ratio  
This is the measured ratio of signal to (noise + distortion) at the  
output of the A/D converter. The signal is the rms amplitude of  
the fundamental. Noise is the sum of all nonfundamental signals  
up to half the sampling frequency (fS/2), excluding dc. The ratio  
is dependent on the number of quantization levels in the digitiza-  
tion process; the more levels, the smaller the quantization noise.  
The theoretical signal to (noise + distortion) ratio for an ideal  
N-bit converter with a sine wave input is given by:  
Offset Error Match  
This is the difference in offset error between any two channels.  
Gain Error  
This is the deviation of the last code transition (111…110) to  
(111…111) from the ideal (i.e., REFIN ꢂ 1 LSB) after the offset  
error has been adjusted out.  
Gain Error Match  
This is the difference in gain error between any two channels.  
Signal to (Noise +Distortion) =(6.02 N +1.76) dB  
Zero Code Error  
Thus for a 12-bit converter, this is 74 dB.  
This applies when using the twos complement output coding  
option, in particular to the 2 ꢀ REFIN input range with –REFIN  
to +REFIN biased about the REFIN point. It is the deviation of the  
midscale transition (all 0s to all 1s) from the ideal VIN voltage,  
i.e., REFIN – 1 LSB.  
Total Harmonic Distortion  
Total harmonic distortion (THD) is the ratio of the rms sum of  
harmonics to the fundamental. For the AD7490, it is defined as:  
2
2
2
V2 +V3 +V4 +V52 +V62  
THD(dB) = 20 × log  
Zero Code Error Match  
This is the difference in zero code error between any two channels.  
V1  
where V1 is the rms amplitude of the fundamental and V2, V3,  
V4, V5, and V6 are the rms amplitudes of the second through the  
sixth harmonics.  
Positive Gain Error  
This applies when using the twos complement output coding  
option, in particular to the 2 ꢀ REFIN input range with –REFIN  
to +REFIN biased about the REFIN point. It is the deviation of  
the last code transition (011…110) to (011…111) from the ideal  
(i.e., +REFIN ꢂ 1 LSB) after the Zero Code Error has been  
adjusted out.  
Peak Harmonic or Spurious Noise  
Peak harmonic or spurious noise is defined as the ratio of the rms  
value of the next largest component in the ADC output spectrum  
(up to fS/2 and excluding dc) to the rms value of the fundamental.  
Normally, the value of this specification is determined by the  
largest harmonic in the spectrum, but for ADCs where the har-  
monics are buried in the noise floor, it will be a noise peak.  
Positive Gain Error Match  
This is the difference in Positive Gain Error between any two  
channels.  
Intermodulation Distortion  
Negative Gain Error  
With inputs consisting of sine waves at two frequencies, fa and fb,  
any active device with nonlinearities will create distortion products  
at sum and difference frequencies of mfa nfb, where m, n = 0,  
1, 2, 3, and so on. Intermodulation distortion terms are those for  
which neither m nor n are equal to zero. For example, the second  
order terms include (fa + fb) and (fa – fb), while the third order  
terms include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).  
This applies when using the twos complement output coding  
option, in particular to the 2 ꢀ REFIN input range with –REFIN  
to +REFIN biased about the REFIN point. It is the deviation of  
the first code transition (100…000) to (100…001) from the  
ideal (i.e., –REFIN + 1 LSB) after the Zero Code Error has been  
adjusted out.  
Negative Gain Error Match  
This is the difference in negative gain error between any two  
channels.  
The AD7490 is tested using the CCIF standard where two input  
frequencies near the top end of the input bandwidth are used.  
In this case, the second order terms are usually distanced in  
frequency from the original sine waves while the third order terms  
are usually at a frequency close to the input frequencies. As a  
result, the second and third order terms are specified separately.  
The calculation of the intermodulation distortion is as per the  
THD specification, where it is the ratio of the rms sum of the  
individual distortion products to the rms amplitude of the sum  
of the fundamentals expressed in dBs.  
Channel-to-Channel Isolation  
Channel-to-channel isolation is a measure of the level of cross-  
talk between channels. It is measured by applying a full-scale  
400 kHz sine wave signal to all 15 nonselected input channels and  
determining how much that signal is attenuated in the selected  
channel with a 50 kHz signal. The figure is given worst case  
across all 16 channels for the AD7490.  
REV. A  
–7–  
AD7490–Typical Performance Characteristics  
TPC 1 shows a typical FFT plot for the AD7490 at 1 MSPS  
sample rate and 50 kHz input frequency.  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
V
ꢁ 3V/5V, 10nF CAP  
DD  
200mV p-p SINEWAVE ONV  
DD  
REF ꢁ 2.5V, 1ꢀF CAP  
IN  
TPC 3 shows the power supply rejection ratio versus supply  
ripple frequency for the AD7490. The power supply rejection  
ratio is defined as the ratio of the power in the ADC output at  
full-scale frequency f, to the power of a 200 mV p-p sine wave  
applied to the ADC VDD supply of frequency fS.  
T
ꢁ 25 C  
A
Pf   
PSRR (dB) = 10 × log  
Pf  
S   
V
ꢁ 5V  
ꢁ 3V  
DD  
Pf is equal to the power at frequency f in ADC output; PfS is equal  
to power at frequency fS coupled onto the ADC VDD supply input.  
Here, a 200 mV p-p sine wave is coupled onto the VDD supply.  
10 nF decoupling was used on the supply and a 1 µF decoupling  
cap on the REFIN pin.  
V
DD  
0
100k 200k 300k 400k 500k 600k 700k 800k 900k 1M  
INPUT FREQUENCY – Hz  
TPC 3. PSRR vs. Supply Ripple Frequency  
–50  
5
8192 POINT FFT  
fS ꢁ MAXTHROUGHPUT  
ꢁ 25 C  
fSAMPLEꢁ 1MSPS  
fIN ꢁ 50kHz  
SINAD ꢁ 70.697dB  
THD ꢁ –79.171dB  
SFDR ꢁ –79.93dB  
T
A
–55  
–60  
–65  
–70  
–75  
–80  
–85  
–90  
RANGE ꢁ 0TO REF  
–15  
–35  
IN  
V
ꢁ V  
ꢁ V  
ꢁ 2.7V  
ꢁ 3.6V  
DD  
DRIVE  
DRIVE  
V
–55  
DD  
–75  
V
ꢁ V  
ꢁ V  
ꢁ 4.75V  
ꢁ 5.25V  
DD  
DRIVE  
DRIVE  
V
–95  
DD  
–115  
10  
100  
INPUT FREQUENCY – kHz  
1000  
0
50  
100 150 200 250 300 350 400  
FREQUENCY – kHz  
500  
450  
TPC 4. THD vs. Analog Input Frequency for Various  
Supply Voltages at 1 MSPS  
TPC 1. Dynamic Performance at 1 MSPS  
–50  
75  
70  
65  
60  
55  
fS ꢁ 1 MSPS  
T
ꢁ 25 C  
A
V
ꢁ V  
ꢁ V  
ꢁ 5.25V  
ꢁ 4.75V  
DD  
DRIVE  
DRIVE  
–55  
V
ꢁ 5.25V  
DD  
V
DD  
RANGE ꢁ 0TO REF  
IN  
R
ꢁ 1000  
IN  
–60  
–65  
–70  
–75  
V
ꢁ V  
ꢁ 3.6V  
DRIVE  
DD  
R
ꢁ 100  
IN  
R
ꢁ 50  
IN  
V
ꢁ V  
ꢁ 2.7V  
DRIVE  
DD  
fS ꢁ MAXTHROUGHPUT  
ꢁ 25 C  
–80  
–85  
T
R ꢁ10
A
IN  
RANGE ꢁ 0TO REF  
IN  
10  
100  
INPUT FREQUENCY – kHz  
1000  
10  
100  
INPUT FREQUENCY – kHz  
1000  
TPC 2. SINAD vs. Analog Input Frequency for  
Various Supply Voltages at 1 MSPS  
TPC 5. THD vs. Analog Input Frequency for Various  
Analog Source Impedances  
–8–  
REV. A  
AD7490  
1.0  
0.8  
1.0  
0.8  
V
ꢁ V  
ꢁ 5V  
DRIVE  
V
ꢁ V  
ꢁ 5V  
DD  
DRIVE  
TEMP ꢁ 25 C  
DD  
TEMP ꢁ 25 C  
0.6  
0.6  
0.4  
0.4  
0.2  
0.2  
0
0
–0.2  
–0.4  
–0.6  
–0.8  
–1.0  
–0.2  
–0.4  
–0.6  
–0.8  
–1.0  
0
512  
1024  
1536  
2048 2560  
CODE  
3072 3584  
4096  
0
512  
1024  
1536  
2048 2560  
CODE  
3072 3584  
4096  
TPC 7. Typical DNL  
TPC 6. Typical INL  
CONTROL REGISTER  
The Control Register on the AD7490 is a 12-bit, write-only register. Data is loaded from the DIN pin of the AD7490 on the falling  
edge of SCLK. The data is transferred on the DIN line at the same time as the conversion result is read from the part. The data transferred  
on the DIN line corresponds to the AD7490 configuration for the next conversion. This requires 16 serial clocks for every data transfer.  
Only the information provided on the first 12 falling clock edges (after CS falling edge) is loaded to the Control Register. MSB denotes  
the first bit in the data stream. The bit functions are outlined in Table I.  
Table I. Control Register Bit Functions  
MSB  
LSB  
WRITE  
SEQ  
ADD3  
ADD2  
ADD1  
ADD0  
PM1  
PM0  
SHADOW WEAK/TRI RANGE CODING  
Bit  
Name  
Description  
11  
WRITE  
The value written to this bit of the Control Register determines whether the following 11 bits will be loaded  
to the Control Register or not. If this bit is a 1, the following 11 bits will be written to the Control Register;  
if it is a 0, the remaining 11 bits are not loaded to the Control Register and so it remains unchanged.  
10  
SEQ  
The SEQ Bit in the Control Register is used in conjunction with the Shadow Bit to control the use of the  
sequencer function and access the Shadow Register. (See Table IV.)  
9–6  
ADD3–ADD0  
These four address bits are loaded at the end of the present conversion sequence, and select which analog  
input channel is to be converted on in the next serial transfer, or may select the final channel in a con-  
secutive sequence as described in Table IV. The selected input channel is decoded as shown in Table II.  
The address bits corresponding to the conversion result are also output on DOUT prior to the 12 bits of  
data (see Serial Interface section). The next channel to be converted on will be selected by the mux on  
the 14th SCLK falling edge.  
5, 4  
3
PM1, PM0  
SHADOW  
Power Management Bits. These two bits decode the mode of operation of the AD7490 as shown in Table III.  
The Shadow Bit in the Control Register is used in conjunction with the SEQ Bit to control the use of the  
sequencer function and access the Shadow Register. (See Table IV.)  
2
WEAK/TRI  
This bit selects the state of the DOUT line at the end of the current serial transfer. If it is set to 1, the  
DOUT line will be weakly driven to the channel address bit ADD3 of the ensuing conversion. If this bit is  
set to 0, then DOUT will return to three-state at the end of the serial transfer. See the Serial Interface  
section for more details.  
1
0
RANGE  
This bit selects the analog input range to be used on the AD7490. If it is set to 0, then the analog input range  
will extend from 0 V to 2 ꢀ REFIN. If it is set to 1, then the analog input range will extend from 0 V to  
REFIN (for the next conversion). For 0 V to 2 ꢀ REFIN, VDD = 4.75 V to 5.25 V.  
CODING  
This bit selects the type of output coding the AD7490 will use for the conversion result. If this bit is set to 0,  
the output coding for the part will be twos complement. If this bit is set to 1, the output coding from the  
part will be straight binary (for the next conversion).  
REV. A  
–9–  
AD7490  
Table II. Channel Selection  
SEQUENCER OPERATION  
The configuration of the SEQ and Shadow Bits in the Control  
Register allows the user to select a particular mode of operation  
of the sequencer function. Table IV outlines the four modes of  
operation of the Sequencer.  
Analog Input  
Channel  
ADD3  
ADD2  
ADD1  
ADD0  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
VIN  
0
1
2
3
4
5
6
7
8
9
Table IV. Sequence Selection  
SEQ SHADOW  
0 0  
Sequence Type  
This configuration means the sequence  
function is not used. The analog input  
channel selected for each individual  
conversion is determined by the contents  
of the channel address bits ADD0  
through ADD3 in each prior write  
operation. This mode of operation reflects  
the normal operation of a multichannel  
ADC, without sequencer function being  
used, where each write to the AD7490  
selects the next channel for conversion.  
(See Figure 2.)  
VIN10  
VIN11  
VIN12  
VIN13  
VIN14  
VIN15  
0
1
This configuration selects the Shadow  
Register for programming. After the write  
to the Control Register, the following  
write operation will load the contents  
of the Shadow Register. This will program  
the sequence of channels to be converted  
on continuously with each successive  
valid CS falling edge. (See Shadow Regis-  
ter, Table V, and Figure 3.) The channels  
selected need not be consecutive.  
Table III. Power Mode Selection  
Mode  
PM1  
PM0  
1
1
Normal Operation  
In this mode, the AD7490 remains in full  
power mode regardless of the status of any of  
the logic inputs. This mode allows the fastest  
possible throughput rate from the AD7490.  
1
0
0
1
Full Shutdown  
In this mode, the AD7490 is in full shut-down  
mode, with all circuitry on the AD7490 powering  
down. The AD7490 retains the information  
in the Control Register while in full shutdown.  
The part remains in full shutdown until these  
bits are changed in the Control Register.  
1
1
0
1
If the SEQ and SHADOW Bits are set  
in this way, then the sequence function  
will not be interrupted upon completion  
of the WRITE operation. This allows  
other bits in the Control Register to be  
altered while in a sequence without  
terminating the cycle.  
Auto Shutdown  
In this mode, the AD7490 automatically enters  
shutdown mode at the end of each conversion  
when the Control Register is updated. Wake-up  
time from shutdown is 1 µs and the user should  
ensure that 1 µs has elapsed before attempting  
to perform a valid conversion on the part in  
this mode.  
This configuration is used in conjunction  
with the channel address bits ADD3 to  
ADD0 to program continuous conver-  
sions on a consecutive sequence of  
channels from Channel 0 through to a  
selected final channel as determined by  
the channel address bits in the Control  
Register. (See Figure 4.)  
0
0
Auto Standby  
In this standby mode, portions of the AD7490  
are powered down, but the on-chip bias gen-  
erator remains powered-up. This mode is  
similar to Auto Shutdown and allows the part  
to power-up within one dummy cycle, i.e.,  
1 µs with a 20 MHz SCLK.  
For more information, see the Modes of Operation section.  
–10–  
REV. A  
AD7490  
SHADOW REGISTER  
The Shadow Register on the AD7490 is a 16-bit, write-only register. Data is loaded from the DIN Pin of the AD7490 on the falling  
edge of SCLK. The data is transferred on the DIN line at the same time as a conversion result is read from the part. This requires 16 serial  
falling edges for the data transfer. The information is clocked into the Shadow Register provided the SEQ and Shadow Bits were set to  
0, 1 respectively in the previous write to the Control Register. MSB denotes the first bit in the data stream. Each bit represents an  
analog input from channel 0 through to channel 15. A sequence of channels may be selected through which the AD7490 will cycle with  
each consecutive CS falling edge after the write to the Shadow Register. To select a sequence of channels, the associated channel bit  
must be set for each analog input. The AD7490 will continuously cycle through the selected channels in ascending order, beginning  
with the lowest channel, until a write operation occurs (i.e., the WRITE Bit is set to 1) with the SEQ and Shadow Bits configured in  
any way except 1, 0 (see Table IV). The bit functions are outlined in Table V.  
Table V. Shadow Register Bit Functions  
MSB  
VIN0  
LSB  
VIN1  
VIN2  
VIN3  
VIN4  
VIN5  
VIN6  
VIN7  
VIN8  
VIN9 VIN10 VIN11 VIN12 VIN13 VIN14 VIN15  
POWER ON  
POWER ON  
DUMMY CONVERSIONS  
DIN = ALL 1s  
DUMMY CONVERSIONS  
DIN = ALL 1s  
DIN: WRITE TO CONTROL REGISTER,  
WRITE BIT = 1,  
SELECT CODING, RANGE, AND POWER MODE  
SELECT CHANNEL A3–A0 FOR CONVERSION,  
SEQ = SHADOW = 0  
DIN: WRITE TO CONTROL REGISTER,  
WRITE BIT = 1,  
SELECT CODING, RANGE, AND POWER MODE  
SELECT CHANNEL A3–A0 FOR CONVERSION,  
SEQ = 0 SHADOW = 1  
CS  
CS  
DOUT: CONVERSION RESULT FROM PREVIOUSLY  
SELECTED CHANNEL A3–A0  
CS  
DIN: WRITE TO SHADOW REGISTER, SELECTING  
WHICH CHANNELS TO CONVERT ON; CHANNELS  
SELECTED NEED NOT BE CONSECUTIVE  
DOUT: CONVERSION RESULT FROM PREVIOUSLY  
SELECTED CHANNEL A3–A0  
DIN: WRITE TO CONTROL REGISTER,  
WRITE BIT = 1,  
SELECT CODING, RANGE, AND POWER MODE  
SELECT A3–A0 FOR CONVERSION,  
SEQ = SHADOW = 0  
CS  
WRITE BIT = 1,  
SEQ = SHADOW = 0  
WRITE BIT = 1,  
WRITE BIT = 0  
SEQ = 1, SHADOW = 0  
CONTINUOUSLY  
CONTINUOUSLY  
CONVERTS ON THE  
SELECTED  
SEQUENCE OF  
CHANNELS  
CONVERTS ON THE  
SELECTED SEQUENCE  
OF CHANNELS BUT  
WILL ALLOW RANGE,  
CODING, AND SO ON,  
TO CHANGE IN THE  
CONTROL REGISTER  
WITHOUT INTERRUPT-  
ING THE SEQUENCE  
PROVIDED,  
CS  
Figure 2. SEQ Bit = 0, SHADOW Bit = 0 Flowchart  
Figure 2 reflects the normal operation of a multichannel ADC,  
where each serial transfer selects the next channel for conversion.  
In this mode of operation, the sequencer function is not used.  
WRITE  
BIT = 0  
WRITE BIT = 0  
Figure 3 shows how to program the AD7490 to continuously con-  
vert on a particular sequence of channels. To exit this mode of  
operation and revert back to the normal mode of operation of a  
multichannel ADC (as outlined in Figure 2), ensure the WRITE  
Bit = 1 and the SEQ = SHADOW = 0 on the next serial transfer.  
SEQ = 1 SHADOW = 0  
WRITE BIT = 1,  
SEQ = 1,  
SHADOW = 0  
Figure 3. SEQ Bit = 0, SHADOW Bit = 1 Flowchart  
REV. A  
–11–  
AD7490  
Figure 4 shows how a sequence of consecutive channels can be  
converted on without having to program the Shadow Register or  
write to the part on each serial transfer. Again, to exit this mode of  
operation and revert back to the normal mode of operation of a  
multichannel ADC (as outlined in Figure 2), ensure the WRITE  
Bit = 1 and the SEQ = SHADOW = 0 on the next serial transfer.  
Figures 5 and 6 show simplified schematics of the ADC. The ADC  
comprises Control Logic, SAR, and a Capacitive DAC, which are  
used to add and subtract fixed amounts of charge from the sampling  
capacitor to bring the comparator back into a balanced condition.  
Figure 5 shows the ADC during its acquisition phase. SW2 is closed  
and SW1 is in position A. The comparator is held in a balanced  
condition and the sampling capacitor acquires the signal on the  
selected VIN channel.  
POWER ON  
DUMMY CONVERSIONS  
DIN = ALL 1s  
CAPACITIVE  
DAC  
A
4kꢂ  
DIN: WRITE TO CONTROL REGISTER,  
WRITE BIT = 1,  
SELECT CODING, RANGE, AND POWER MODE  
SELECT CHANNEL A3–A0 FOR CONVERSION,  
SEQ = 1 SHADOW = 1  
V
0
.
.
IN  
CONTROL  
LOGIC  
CS  
SW1  
B
SW2  
V
15  
IN  
COMPARATOR  
AGND  
Figure 5. ADC Acquisition Phase  
DOUT: CONVERSION RESULT FROM CHANNEL 0  
When the ADC starts a conversion (see Figure 6), SW2 will  
open and SW1 will move to position B causing the comparator  
to become unbalanced. The Control Logic and the Capacitive  
DAC are used to add and subtract fixed amounts of charge from  
the sampling capacitor to bring the comparator back into a balanced  
condition. When the comparator is rebalanced, the conversion is  
complete. The Control Logic generates the ADC output code.  
Figure 8 shows the ADC transfer function.  
CONTINUOUSLY CONVERTS ON A CONSECUTIVE  
SEQUENCE OF CHANNELS FROM CHANNEL 0 UP  
TO AND INCLUDING THE PREVIOUSLY SELECTED  
A3–A0 IN THE CONTROL REGISTER  
CS  
WRITE BIT = 0  
WRITE BIT = 1,  
SEQ = 1,  
SHADOW = 0  
CONTINUOUSLY CONVERTS ON THE SELECTED  
SEQUENCE OF CHANNELS BUT WILL ALLOW  
RANGE, CODING, AND SO ON, TO CHANGE IN THE  
CONTROL REGISTER WITHOUT INTERRUPTING  
THE SEQUENCE PROVIDED, SEQ = 1, SHADOW = 0  
CS  
WRITE BIT = 1,  
SEQ = 1,  
SHADOW = 0  
CAPACITIVE  
DAC  
A
4kꢂ  
V
0
.
.
IN  
Figure 4. SEQ Bit = 1, SHADOW Bit = 1 Flowchart  
CONTROL  
LOGIC  
SW1  
B
SW2  
CIRCUIT INFORMATION  
V
15  
IN  
COMPARATOR  
The AD7490 is a fast, 16-channel, 12-bit, single-supply, A/D conver-  
ter. The parts can be operated from a 2.7 V to 5.25 V supply. When  
operated from a 5 V supply, the AD7490 is capable of throughput  
rates of up to 1 MSPS when provided with a 20 MHz clock.  
AGND  
Figure 6. ADC Conversion Phase  
Analog Input  
Figure 7 shows an equivalent circuit of the analog input structure  
of the AD7490. The two diodes, D1 and D2, provide ESD pro-  
tection for the analog inputs. Care must be taken to ensure that  
the analog input signal never exceeds the supply rails by more  
than 200 mV. This will cause these diodes to become forward  
biased and start conducting current into the substrate. 10 mA is the  
maximum current these diodes can conduct without causing  
irreversible damage to the part. The capacitor C1 in Figure 7 is  
typically about 4 pF and can primarily be attributed to pin  
capacitance. The resistor R1 is a lumped component made up of  
The AD7490 provides the user with an on-chip track/hold, A/D  
converter, and a serial interface housed in either 28-lead TSSOP or  
32-lead LFCSP package. The AD7490 has 16 single-ended  
input channels with a channel sequencer, allowing the user to select  
a sequence of channels through which the ADC can cycle with  
each consecutive CS falling edge. The serial clock input accesses  
data from the part, controls the transfer of data written to the ADC,  
and provides the clock source for the successive-approximation  
A/D converter. The analog input range for the AD74790 is 0 to  
REFIN or 0 to 2 ꢀ REFIN depending on the status of Bit 1 in the  
Control Register. For the 0 to 2 ꢀ REFIN range, the part must  
be operated from a 4.75 V to 5.25 V supply.  
V
DD  
The AD7490 provides flexible power management options to  
allow the user to achieve the best power performance for a given  
throughput rate. These options are selected by programming the  
Power Management bits in the Control Register.  
C2  
D1  
30pF  
R1  
V
IN  
C1  
4pF  
D2  
CONVERSION PHASE—SWITCH OPEN  
TRACK PHASE—SWITCH CLOSED  
CONVERTER OPERATION  
The AD7490 is a 12-bit successive approximation analog-to-digital  
converter based around a capacitive DAC. The AD7490 can convert  
Figure 7. Equivalent Analog Input Circuit  
analog input signals in the range 0 V to VREF IN or 0 V to 2 ꢀ VREF IN  
.
–12–  
REV. A  
AD7490  
the on resistance of a switch (track and hold switch) and also includes  
the on resistance of the input multiplexer. The total resistance is  
typically about 400 Ω. The capacitor C2 is the ADC sampling  
capacitor and typically has a capacitance of 30 pF. For ac appli-  
cations, removing high frequency components from the analog  
input signal is recommended by use of an RC low-pass filter on  
the relevant analog input pin. In applications where harmonic distor-  
tion and signal-to-noise ratio are critical, the analog input should  
be driven from a low impedance source. Large source impedances  
will significantly affect the ac performance of the ADC. This  
may necessitate the use of an input buffer amplifier. The choice  
of the op amp will be a function of the particular application.  
011…111  
011…110  
•
•
000…001  
000…000  
111…111  
•
•
1 LSB ꢁ 2 ꢄ V  
ꢆ4096  
REF  
100…010  
100…001  
100…000  
–V  
REF  
ꢅ 1 LSB  
+V ꢃ 1 LSB  
REF  
ꢃ 1 LSB  
REF  
ANALOG INPUT  
V
When no amplifier is used to drive the analog input, the source  
impedance should be limited to low values. The maximum  
source impedance will depend on the amount of total harmonic  
distortion (THD) that can be tolerated. The THD will increase as  
the source impedance increases, and performance will degrade  
(see TPC 5).  
Figure 9. Twos Complement Transfer Characteristic  
with REFIN REFIN Input Range  
Handling Bipolar Input Signals  
Figure 10 shows how useful the combination of the 2 ꢀ REFIN  
input range and the twos complement output coding scheme is for  
handling bipolar input signals. If the bipolar input signal is biased  
about REFIN and twos complement output coding is selected,  
then REFIN becomes the zero code point, –REFIN is negative  
fullscale and +REFIN becomes positive full scale, with a dynamic  
range of 2 ꢀ REFIN.  
ADC TRANSFER FUNCTION  
The output coding of the AD7490 is either straight binary or twos  
complement depending on the status of the LSB (RANGE Bit) in  
the Control Register. The designed code transitions occur midway  
between successive LSB values (i.e., 1 LSB, 2 LSBs, and so on).  
The LSB size is equal to REFIN/4096. The ideal transfer charac-  
teristic for the AD7490 when straight binary coding is selected  
is shown in Figure 8.  
TYPICAL CONNECTION DIAGRAM  
Figure 11 shows a typical connection diagram for the AD7490. In  
this setup, the AGND pin is connected to the analog ground plane  
of the system. In Figure 11, REFIN is connected to a decoupled  
2.5 V supply from a reference source, the AD780, to provide an  
analog input range of 0 V to 2.5 V (if RANGE Bit is 1) or 0 V to  
5 V (if RANGE Bit is 0). Although the AD7490 is connected to a  
VDD of 5 V, the serial interface is connected to a 3 V micropro-  
cessor. The VDRIVE pin of the AD7490 is connected to the same  
3 V supply of the microprocessor to allow a 3 V logic interface  
(see Digital Inputs section.) The conversion result is output in a  
16-bit word. This 16-bit data stream consists of four address bits  
indicating which channel the conversion result corresponds to,  
followed by the 12 bits of conversion data. For applications where  
111…111  
111…110  
•
•
111…000  
•
1 LSB ꢁ V  
/4096  
011…111  
REF  
•
•
000…010  
000…001  
000…000  
1 LSB  
+V  
IN  
ꢃ 1 LSB  
REF  
0V  
ANALOG INPUT  
V
REF  
IS EITHER REF OR 2 ꢄ REF  
IN  
Figure 8. Straight Binary Transfer Characteristic  
V
DD  
V
DD  
V
REF  
REF  
IN  
+REF  
IN  
011…111  
000…000  
100…000  
(ꢁ 2 ꢄ REF  
)
IN  
V
DRIVE  
0.1ꢀF  
R4  
R1  
REF  
IN  
V
TWOS  
COMPLEMENT  
AD7490  
R3  
R2  
–REF  
DSP/ꢀP  
IN  
V
•
•
0
DOUT  
IN  
(ꢁ 0V)  
V
0V  
V
15  
IN  
R1 ꢁ R2 ꢁ R3 ꢁ R4  
Figure 10. Handling Bipolar Signals  
REV. A  
–13–  
AD7490  
power consumption is of concern, the power-down modes should  
be used between conversions or bursts of several conversions to  
improve power performance. (See Modes of Operation section.)  
through ADD0 will then determine the final channel in the consecu-  
tive sequence. The next conversion will be on Channel 0, then  
Channel 1 and so on until the channel selected via the address  
bits ADD3 through ADD0 is reached. The cycle will begin  
again on the next serial transfer provided the WRITE Bit is set  
to low or, if high, that the SEQ and Shadow Bits are set to 1, 0;  
then the ADC will continue its preprogrammed automatic se-  
quence uninterrupted. Regardless of which channel selection  
method is used, the 16-bit word output from the AD7490 during  
each conversion will always contain the channel address that the  
conversion result corresponds to followed by the 12-bit conver-  
sion result (see Serial Interface section).  
0.1ꢀF  
10ꢀF  
5V  
SUPPLY  
SERIAL  
INTERFACE  
V
DD  
V
•
•
0
SCLK  
DOUT  
CS  
IN  
0VTO REF  
IN  
ꢀC/ꢀP  
AD7490  
V
15  
IN  
AGND  
DIN  
REF  
V
DRIVE  
IN  
Digital Inputs  
The digital inputs applied to the AD7490 are not limited by the  
maximum ratings that limit the analog inputs. Instead, the digi-  
tal inputs applied can go to 7 V and are not restricted by the  
VDD + 0.3 V limit as on the analog inputs.  
0.1ꢀF  
10ꢀF  
0.1ꢀF  
2.5V  
AD780  
3V  
SUPPLY  
ALL UNUSED INPUT CHANNELS SHOULD BE CONNECTEDTO GND  
Another advantage of SCLK, DIN, and CS not being restricted  
by the VDD + 0.3 V limit is the fact that power supply sequencing  
Figure 11. Typical Connection Diagram  
issues are avoided. If CS, DIN, or SCLK are applied before VDD  
then there is no risk of latch-up as there would be on the analog  
,
Analog Input  
Any one of 16 analog input channels may be selected for conversion  
by programming the multiplexer with the address bits ADD3–ADD0  
in the Control Register. The channel configurations are shown in  
Table II. The AD7490 may also be configured to automatically  
cycle through a number of channels as selected. The sequencer  
feature is accessed via the SEQ and SHADOW Bits in the Control  
Register (see Table IV). The AD7490 can be programmed to  
continuously convert on a selection of channels in ascending order.  
The analog input channels to be converted on are selected through  
programming the relevant bits in the Shadow Register (see Table V).  
The next serial transfer will then act on the sequence programmed  
by executing a conversion on the lowest channel in the selection.  
inputs if a signal greater than 0.3 V was applied prior to VDD  
.
VDRIVE  
The AD7490 also has the VDRIVE feature. VDRIVE controls the voltage  
at which the serial interface operates. VDRIVE allows the ADC to  
easily interface to both 3 V and 5 V processors. For example, if  
the AD7490 were operated with a VDD of 5 V, the VDRIVE Pin  
could be powered from a 3 V supply. The AD7490 has better  
dynamic performance with a VDD of 5 V while still being able to  
interface to 3 V processors. Care should be taken to ensure VDRIVE  
does not exceed VDD by more than 0.3 V. (See Absolute Maximum  
Ratings section.)  
The next serial transfer will result in a conversion on the next  
highest channel in the sequence and so on. It is not necessary to  
write to the Control Register once a sequencer operation has  
been initiated. The WRITE Bit must be set to zero or the DIN  
line tied low to ensure the Control Register is not accidently  
overwritten, or the sequence operation interrupted. If the  
Control Register is written to at any time during the sequence, then  
it must be ensured that the SEQ and Shadow Bits are set to 1, 0  
to avoid interrupting the automatic conversion sequence. This  
pattern will continue until such time as the AD7490 is written to  
and the SEQ and Shadow Bits are configured with any bit combi-  
nation except 1, 0. On completion of the sequence, the AD7490  
sequencer will return to the first selected channel in the Shadow  
Register and commence the sequence again if uninterrupted.  
Reference Section  
An external reference source should be used to supply the 2.5 V  
reference to the AD7490. Errors in the reference source will result  
in gain errors in the AD7490 transfer function and will add to the  
specified full scale errors of the part. A capacitor of at least 0.1 µF  
should be placed on the REFIN Pin. Suitable reference sources  
for the AD7490 include the AD780, REF193, and the AD1852.  
If 2.5 V is applied to the REFIN Pin, the analog input range can  
either be 0 V to 2.5 V or 0 V to 5 V, depending on the RANGE  
Bit in the Control Register.  
MODES OF OPERATION  
The AD7490 has a number of different modes of operation. These  
modes are designed to provide flexible power management options.  
These options can be chosen to optimize the power dissipation/  
throughput rate ratio for differing application requirements. The  
mode of operation of the AD7490 is controlled by the power  
management bits, PM1 and PM0, in the Control Register, as  
detailed in Table III. When power supplies are first applied to the  
AD7490, care should be taken to ensure the part is placed in the  
required mode of operation (see Powering Up the AD7490 section.)  
Rather than selecting a particular sequence of channels, a number  
of consecutive channels beginning with channel 0 may also be  
programmed via the Control Register alone without needing to  
write to the Shadow Register. This is possible if the SEQ and  
Shadow Bits are set to 1, 1. The channel address bits ADD3  
–14–  
REV. A  
AD7490  
Normal Mode (PM1 = PM0 = 1)  
both loaded with 1 on every data transfer. Sixteen serial clock  
cycles are required to complete the conversion and access the  
conversion result. The track and hold will go back into track on  
the 14th SCLK falling edge. CS may then idle high until the next  
conversion or may idle low until sometime prior to the next  
conversion, (effectively idling CS low).  
This mode is intended for the fastest throughput rate performance  
as the user does not have to worry about any power-up times with  
the AD7490 remaining fully powered at all times. Figure 12 shows  
the general diagram of the operation of the AD7490 in this mode.  
CS  
Once a data transfer is complete (DOUT has returned to three-  
state WEAK/TRI Bit ꢃ 0), another conversion can be initiated  
after the quiet time, tQUIET, has elapsed by bringing CS low again.  
1
16  
12  
SCLK  
DOUT  
Full Shutdown (PM1 = 1, PM0 = 0)  
CHANNEL IDENTIFIER BITS + CONVERSION RESULT  
DATA INTO CONTROL/SHADOW REGISTER  
In this mode, all internal circuitry on the AD7490 is powered  
down. The part retains information in the Control Register during  
full shutdown. The AD7490 remains in full shutdown until  
the power management bits in the Control Register, PM1 and  
PM0, are changed.  
DIN  
NOTES  
1. CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES  
2. SHADOW REGISTER DATA IS LOADED ON FIRST 16 SCLK CYCLES  
If a write to the Control Register occurs while the part is in Full  
Shutdown, with the power management bits changed to PM0 =  
PM1 = 1, Normal Mode, the part will begin to power up on the CS  
rising edge. The track and hold that was in hold while the part was  
in Full Shutdown will return to track on the 14th SCLK falling edge.  
Figure 12. Normal Mode Operation  
The conversion is initiated on the falling edge of CS and the track  
and hold will enter hold mode as described in the Serial Interface  
section. The data presented to the AD7490 on the DIN line during  
the first 12 clock cycles of the data transfer is loaded to the  
Control Register (provided WRITE Bit is 1). If data is to be written to  
the Shadow Register (SEQ ꢃ 0, SHADOW ꢃ1 on previous write),  
data presented on the DIN line during the first 16 SCLK cycles is  
loaded into the Shadow Register. The part will remain fully powered  
up in Normal Mode at the end of the conversion as long as PM1  
and PM0 are set to 1 in the write transfer during that conversion.  
To ensure continued operation in Normal Mode, PM1 and PM0 are  
To ensure that the part is fully powered up, tPOWER UP (t12)  
should have elapsed before the next CS falling edge. Figure 13  
shows the general diagram for this sequence.  
Auto Shutdown (PM1 = 0, PM0 = 1)  
In this mode, the AD7490 automatically enters shutdown at the  
end of each conversion when the Control Register is updated.  
When the part is in shutdown, the track and hold is in hold mode.  
Figure 14 shows the general diagram of the operation of the  
PART IS IN FULL  
SHUTDOWN  
PART BEGINSTO POWER UP ON CS  
RISING EDGE AS PM1 ꢁ 1, PM0 ꢁ 1  
PART IS FULLY POWERED UP  
ONCE T  
HAS ELAPSED  
POWER UP  
t12  
CS  
1
16  
1
16  
14  
14  
SCLK  
DOUT  
DIN  
CHANNEL IDENTIFIER BITS + CONVERSION RESULT  
DATA INTO CONTROL/SHADOW REGISTER  
DATA IN TO CONTROL REGISTER  
CONTROL REGISTER IS LOADED ONTHE  
FIRST 12 CLOCKS, PM1 ꢁ 1, PM0 ꢁ 1  
TO KEEP PART IN NORMAL MODE, LOAD  
PM1 ꢁ 1, PM0 ꢁ 1 IN CONTROL REGISTER  
Figure 13. Full Shutdown Mode Operation  
PART ENTERS  
SHUTDOWN ON CS  
RISING EDGE AS  
PM1 ꢁ 0, PM0 ꢁ 1  
PART ENTERS  
PART BEGINS  
TO POWER  
UP ON CS  
SHUTDOWN ON CS  
RISING EDGE AS  
PM1 ꢁ 0, PM0 ꢁ 1  
PART IS FULLY  
POWERED UP  
FALLING EDGE  
CS  
SCLK  
DOUT  
DUMMY CONVERSION  
1
16  
1
16  
1
16  
CHANNEL IDENTIFIER BITS + CONVERSION RESULT  
DATA INTO CONTROL/SHADOW REGISTER  
INVALID DATA  
CHANNEL IDENTIFIER BITS + CONVERSION RESULT  
DATA INTO CONTROL/SHADOW REGISTER  
DIN  
CONTROL REGISTER IS LOADED ONTHE  
FIRST 12 CLOCKS, PM1 ꢁ 0, PM0 ꢁ 1  
CONTROL REGISTER CONTENTS SHOULD  
NOT CHANGE,WRITE BIT ꢁ 0  
TO KEEP PART INTHIS MODE, LOAD PM1 ꢁ 0, PM0 ꢁ 1  
IN CONTROL REGISTER OR SETWRITE BIT = 0  
Figure 14. Auto Shutdown Mode Operation  
–15–  
REV. A  
AD7490  
AD7490 in this mode. In Shutdown Mode, all internal circuitry on  
the AD7490 is powered down. The part retains information in  
the Control Register during shutdown. The AD7490 remains in  
shutdown until the next CS falling edge it receives. On this CS  
falling edge, the track and hold that was in hold while the part was  
in shutdown will return to track. Wake-up time from auto shut-  
down is 1 µs, and the user should ensure that 1 µs has elapsed  
before attempting a valid conversion. When running the AD7490  
with a 20 MHz clock, one dummy cycle of 16 ꢀ SCLKs should  
be sufficient to ensure the part is fully powered up. During this  
dummy cycle, the contents of the Control Register should remain  
unchanged; therefore the WRITE Bit should be 0 on the DIN line.  
This dummy cycle effectively halves the throughput rate of the part,  
with every other conversion result being valid. In this mode, the  
power consumption of the part is greatly reduced with the part  
entering shutdown at the end of each conversion. When the Control  
Register is programmed to move into auto shutdown, it does so  
at the end of the conversion. The user can move the ADC in and  
out of the low power state by controlling the CS signal.  
hold that was in hold while the part was in standby will return to  
track. Wake-up time from standby is 1 µs; the user should ensure  
that 1 µs has elapsed before attempting a valid conversion on the  
part in this mode. When running the AD7490 with a 20 MHz  
clock, one dummy cycle of 16 ꢀ SCLKs should be sufficient to  
ensure the part is fully powered up. During this dummy cycle, the  
contents of the Control Register should remain unchanged,  
therefore the WRITE Bit should be set to 0 on the DIN line. This  
dummy cycle effectively halves the throughput rate of the part  
with every other conversion result being valid. In this mode, the  
power consumption of the part is greatly reduced with the part  
entering standby at the end of each conversion. When the Control  
Register is programmed to move into Auto Standby, it does so at  
the end of the conversion. The user can move the ADC in and out  
of the low power state by controlling the CS signal.  
Powering Up the AD7490  
When supplies are first applied to the AD7490, the ADC may  
power up in any of the operating modes of the part. To ensure the  
part is placed into the required operating mode, the user should  
perform a dummy cycle operation as outlined in Figure 16.  
Auto Standby (PM1 = PM0 = 0)  
In this mode, the AD7490 automatically enters Standby Mode at  
the end of each conversion when the Control Register is updated.  
Figure 15 shows the general diagram of the operation of the  
AD7490 in this mode. When the part is in standby, portions of the  
AD7490 are power-down but the on-chip bias generator remains  
powered up. The part retains information in the Control Register  
during standby. The AD7490 remains in standby until it receives  
the next CS falling edge. On this CS falling edge, the track and  
The three dummy conversion operations outlined in Figure 16 must  
be performed to place the part into either of the auto modes. The  
first two conversions of this dummy cycle operation are performed  
with the DIN line tied HIGH, and for the third conversion of the  
dummy cycle operation, the user should write the desired control  
register configuration to the AD7490 in order to place the part  
into the required Auto Mode. On the third CS rising edge after the  
PART ENTERS  
STANDBY ON CS  
RISING EDGE AS  
PM1 ꢁ 0, PM0 ꢁ 0  
PART ENTERS  
STANDBY ON CS  
RISING EDGE AS  
PM1 ꢁ 0, PM0 ꢁ 0  
PART BEGINS  
TO POWER  
UP ON CS  
PART IS FULLY  
POWERED UP  
FALLING EDGE  
CS  
SCLK  
DOUT  
DUMMY CONVERSION  
12  
1
16  
1
16  
1
16  
12  
12  
INVALID DATA  
CHANNEL IDENTIFIER BITS + CONVERSION RESULT  
DATA IN TO CONTROL/SHADOW REGISTER  
CHANNEL IDENTIFIER BITS + CONVERSION RESULT  
DATA IN TO CONTROL/SHADOW REGISTER  
DIN  
CONTROL REGISTER IS LOADED ONTHE  
FIRST 12 CLOCKS, PM1 ꢁ 0, PM0 ꢁ 0  
CONTROL REGISTER SHOULD REMAIN  
UNCHANGED,WRITE BIT ꢁ 0  
TO KEEP PART INTHIS MODE, LOAD PM1 ꢁ 0,  
PM0 ꢁ 0 IN CONTROL REGISTER  
Figure 15. Auto Standby Mode Operation  
CORRECTVALUE IN CONTROL  
REGISTERVALID DATA FROM  
NEXT CONVERSION USER CAN  
WRITETO SHADOW REGISTER  
IN NEXT CONVERSION  
CS  
SCLK  
DOUT  
DUMMY CONVERSION  
DUMMY CONVERSION  
1
16  
1
16  
1
16  
12  
12  
12  
INVALID DATA  
INVALID DATA  
INVALID DATA  
DATA IN TO CONTROL  
DIN  
KEEP DIN LINETIED HIGH FOR FIRSTTWO DUMMY CONVERSIONS  
CONTROL REGISTER IS LOADED ONTHE  
FIRST 12 CLOCK EDGES  
Figure 16. Placing into the Required Operating Mode after Supplies are Applied  
–16–  
REV. A  
AD7490  
supplies are applied, the Control Register will contain the correct  
information and valid data will result from the next conversion.  
preceded by the four channel address bits ADD3 to ADD0,  
identifying which channel the conversion result corresponds to.  
CS going low provides address bit ADD3 to be read in by the  
microprocessor or DSP. The remaining address bits and data bits  
are then clocked out by subsequent SCLK falling edges beginning  
with the second address bit ADD2; thus the first SCLK falling  
edge on the serial clock has address bit ADD3 provided and also  
clocks out address bit ADD2. The final bit in the data transfer is  
valid on the 16th falling edge, having being clocked out on the  
previous (15th) falling edge.  
Therefore, to ensure the part is placed into the correct operating  
mode when supplies are first applied to the AD7490, the user must  
first issue two serial write operations with the DIN line tied  
high. On the third conversion cycle, the user can then write to the  
Control Register to place the part into any of the operating modes.  
The user should not write to the Shadow Register until the fourth  
conversion cycle after the supplies are applied to the ADC in  
order to guarantee the Control Register contains the correct data.  
Writing of information to the Control Register takes place on  
the first 12 falling edges of SCLK in a data transfer, assuming the  
MSB, i.e., the WRITE Bit, has been set to 1. If the Control Register  
is programmed to use the Shadow Register, writing of information  
to the Shadow Register will take place on all 16 SCLK falling  
edges in the next serial transfer (see Figure 18). The Shadow Reg-  
ister will be updated upon the rising edge of CS and the track and  
hold will begin to track the first channel selected in the sequence.  
If the user wishes to place the part into either Normal Mode or  
Full Shutdown Mode, the second dummy cycle with DIN tied  
high can be omitted from the three dummy conversion operation  
outlined in Figure 16.  
SERIAL INTERFACE  
Figure 17 shows the detailed timing diagram for serial interfacing  
to the AD7490. The serial clock provides the conversion clock  
and also controls the transfer of information to and from the  
AD7490 during each conversion.  
If the WEAK/TRI Bit in the Control Register is set to 1, rather than  
returning to true three-state upon the 16th SCLK falling edge,  
the DOUT line will instead be pulled weakly to the logic level  
corresponding to ADD3 of the next serial transfer. This is done  
to ensure that the MSB of the next serial transfer is set up in time  
for the first SCLK falling edge after the CS falling edge. If the  
WEAK/TRI Bit is set to 0 and the DOUT line has been in true  
three-state between conversions, then depending on the particular  
DSP or microcontroller interfacing to the AD7490, address bit  
ADD3 may not be set up in time for the DSP/micro to clock it in  
successfully. In this case, ADD3 would only be driven from the  
falling edge of CS and must then be clocked in by the DSP on the  
following falling edge of SCLK. However, if the WEAK/TRI Bit  
had been set to 1, then although DOUT is driven with address bit  
ADD3 since the last conversion, it is nevertheless so weakly driven  
The CS signal initiates the data transfer and conversion process.  
The falling edge of CS puts the track and hold into hold mode,  
takes the bus out of three-state, and the analog input is sampled  
at this point. The conversion is also initiated at this point and  
will require 16 SCLK cycles to complete. The track and hold  
will go back into track on the 14th SCLK falling edge as shown in  
Figure 17 at point B, except when the write is to the Shadow  
Register, in which case the track and hold will not return to  
track until the rising edge of CS, i.e., point C in Figure 18. On  
the 16th SCLK falling edge, the DOUT line will go back into  
three-state (assuming the WEAK/TRI Bit is set to 0). Sixteen  
serial clock cycles are required to perform the conversion process  
and to access data from the AD7490. The 12 bits of data are  
CS  
B
t2  
tCONVERT  
t6  
SCLK  
1
2
3
4
5
6
13  
14  
t5  
15  
16  
t4  
t7  
t11  
DB0  
t8  
t3  
b
t3  
tQUIET  
DOUT  
DIN  
ADD2  
t9  
ADD1  
ADD0  
DB11  
DB10  
DB2  
DB1  
THREE-  
STATE  
THREE-  
STATE  
FOUR IDENTIFICATION BITS  
t10  
ADD3  
WRITE  
SEQ  
ADD3  
ADD2  
ADD1  
ADD0  
DONTC  
DONTC  
DONTC  
Figure 17. Serial Interface Timing Diagram  
C
CS  
t2  
tCONVERT  
t6  
SCLK  
1
2
3
4
5
6
13  
14  
15  
16  
t4  
t7  
t5  
t11  
DB0  
t8  
t3  
ADD2  
ADD1  
ADD0  
DB11  
DB10  
DB2  
DB1  
DOUT  
DIN  
THREE-  
STATE  
THREE-  
STATE  
t9  
V
FOUR IDENTIFICATION BITS t10  
ADD3  
V
0
1
V
2
V
3
V
4
V
5
V
13  
V
14  
V 15  
IN  
IN  
IN  
IN  
IN  
IN  
IN  
IN  
IN  
Figure 18. Writing to Shadow Register Timing Diagram  
–17–  
REV. A  
AD7490  
that another device may still take control of the bus. It will not  
lead to a bus contention (e.g., a 10 kΩ pull-up or pull-down  
resistor would be sufficient to overdrive the logic level of ADD3  
between conversions) and all 16 channels may be identified.  
However, if this does happen and another device takes control of  
the bus, it is not guaranteed that DOUT will be fully driven to  
ADD3 again in time for the read operation when control of the  
bus is taken back.  
compared to Standby. However as the throughput rate is increased,  
the part spends less time in power-down states, hence difference  
in power dissipated is negligible between modes. For 3 V supplies,  
the power consumption of the AD7490 decreases. Similar power  
calculations can be done at 3 V.  
10  
V
ꢁ 5V  
DD  
AUTO STANDBY  
AUTO SHUTDOWN  
This is especially useful if using an automatic sequence mode to  
identify to which channel each result corresponds. Obviously, if  
only the first eight channels are in use, then address bit ADD3  
does not need to be decoded, and whether it is successfully clocked  
in as a 1 or 0 will not matter as long as it is still counted by the  
DSP/micro as the MSB of the 16-bit serial transfer.  
1
0.1  
POWER VERSUS THROUGHPUT RATE  
By operating the AD7490 in Auto Shutdown or Auto Standby  
Mode, the average power consumption of the ADC decreases at  
lower throughput rates. Figure 19 shows how as the throughput  
rate is reduced, the part remains in its shutdown state longer and  
the average power consumption over time drops accordingly.  
0.01  
0
50  
100  
150  
200  
250  
300  
350  
THROUGHPUT – kSPS  
Figure 19. Power vs. Throughput Rate  
in Auto Shutdown and Auto Standby Mode  
For example if the AD7490 is operated in a continuous sampling  
mode with a throughput rate of 100 kSPS and an SCLK of 20 MHz  
(VDD = 5 V), with PM1 = 0 and PM0 = 1, i.e., the device is in  
Auto Shutdown Mode, then the power consumption is calcu-  
lated as follows:  
MICROPROCESSOR INTERFACING  
The serial interface on the AD7490 allows the part to be directly  
connected to a range of many different microprocessors. This  
section explains how to interface the AD7490 with some of the  
more common microcontroller and DSP serial interface protocols.  
The maximum power dissipation during normal operation is  
12.5 mW (VDD = 5 V). If the power-up time from Auto Shutdown  
is one dummy cycle, i.e., 1 µs, and the remaining conversion time is  
another cycle, i.e., 1 µs, then the AD7490 can be said to dissipate  
12.5 mW for 2 µs during each conversion cycle. For the remainder  
of the conversion cycle, 8 µs, the part remains in Shutdown Mode.  
The AD7490 can be said to dissipate 2.5 µW for the remaining  
8 µs of the conversion cycle. If the throughput rate is 100 kSPS,  
the cycle time is 10 µs and the average power dissipated during  
each cycle is  
AD7490 to TMS320C541  
The serial interface on the TMS320C541 uses a continuous serial  
clock and frame synchronization signals to synchronize the data  
transfer operations with peripheral devices like the AD7490.  
The CS input allows easy interfacing between the TMS320C541  
and the AD7490 without any glue logic required. The serial port  
of the TMS320C541 is set up to operate in burst mode with inter-  
nal CLKX0 (TX serial clock on serial port 0) and FSX0 (TX frame  
sync from serial port 0). The Serial Port Control Register (SPC)  
must have the following setup: FO = 0, FSM = 1, MCM = 1, and  
TXM = 1. The connection diagram is shown in Figure 20. It should  
be noted that for signal processing applications, it is imperative  
that the frame synchronization signal from the TMS320C541  
will provide equidistant sampling. The VDRIVE pin of the AD7490  
takes the same supply voltage as that of the TMS320C541. This  
allows the ADC to operate at a higher voltage than the serial  
interface, i.e., TMS320C541, if necessary.  
2
10  
8
10  
× 12.5 mW +  
× 2.5 µW = 2.502 mW  
When operating the AD7490 in Auto Standby Mode, PM1 =  
PM0 = 0 at 5 V, 100 kSPS, the AD7490 power dissipation is calcu-  
lated as follows:  
The maximum power dissipation is 12.5 mW at 5 V during normal  
operation. Again the power-up time from Auto Standby is one  
dummy cycle, 1 µs, and the remaining conversion time is another  
dummy cycle, 1 µs. The AD7490 dissipates 12.5 mW for 2 µs during  
each conversion cycle. For the remainder of the conversion cycle,  
8 µs, the part remains in Standby Mode, dissipating 460 µW for  
8 µs. If the throughput rate is 100 kSPS, the cycle time is 10 µs  
and the average power dissipated during each conversion cycle is  
TMS320C541*  
AD7490  
CLKX  
CLKR  
DR  
SCLK  
DOUT  
DIN  
2
10  
8
10  
× 12.5 mW +  
× 460 µW = 2.868 mW  
DT  
FSX  
FSR  
CS  
Figure 19 shows the power versus throughput rate when using both  
the Auto Shutdown Mode and Auto Standby Mode with 5 V  
supplies. At the lower throughput rates, power consumption for the  
Auto Shutdown Mode is lower than that for the Auto Standby  
Mode, with the AD7490 dissipating less power when in Shutdown  
V
DRIVE  
*ADDITIONAL PINS REMOVED FOR CLARITY  
V
DD  
Figure 20. Interfacing to the TMS320C541  
–18–  
REV. A  
AD7490  
AD7490 to ADSP-21xx  
ADSP-218x*  
AD7490  
The ADSP-21xx family of DSPs are interfaced directly to the  
AD7490 without any glue logic required. The VDRIVE Pin of the  
AD7490 takes the same supply voltage as that of the ADSP-218x.  
This allows the ADC to operate at a higher voltage than the  
serial interface, i.e., ADSP-218x, if necessary.  
SCLK  
SCLK  
DR  
DOUT  
CS  
RFS  
TFS  
DT  
DIN  
The SPORT0 Control Register should be set up as follows:  
V
DRIVE  
TFSW ꢃ  
RFSW ꢃ 1, Alternate Framing  
INVRFS ꢃ INVTFS ꢃ 1, Active Low Frame Signal  
DTYPE ꢃ 00, Right Justify Data  
*ADDITIONAL PINS REMOVED FOR CLARITY  
V
DD  
SLEN ꢃ  
ISCLK ꢃ  
TFSR ꢃ  
IRFS ꢃ  
ITFS ꢃ  
1111, 16-Bit Datawords  
1, Internal Serial Clock  
RFSR ꢃ 1, Frame Every Word  
0
1
Figure 21. Interfacing to the ADSP-218x  
AD7490 to DSP563xx  
The connection diagram in Figure 22 shows how the AD7490 can  
be connected to the ESSI (Synchronous Serial Interface) of the  
DSP563xx family of DSPs from Motorola. Each ESSI (2 on board)  
is operated in Synchronous Mode (SYN bit in CRB ꢃ 1) with  
internally generated 1-bit clock period frame sync for both Tx  
and Rx (bits FSL1 ꢃ 0 and FSL0 ꢃ 0 in CRB). Normal operation  
of the ESSI is selected by making MOD ꢃ 0 in the CRB. Set  
the word length to 16 by setting bits WL1 ꢃ 1 and WL0 ꢃ 0 in  
CRA. The FSP Bit in the CRB should be set to 1 so the frame  
sync is negative. It should be noted that for signal processing  
applications, it is imperative that the frame synchronization  
signal from the DSP563xx will provide equidistant sampling.  
The connection diagram is shown in Figure 21. The ADSP-218x  
has the TFS and RFS of the SPORT tied together, with TFS set  
as an output and RFS set as an input. The DSP operates in  
Alternate Framing Mode and the SPORT Control Register is set  
up as described. The frame synchronization signal generated on the  
TFS is tied to CS, and as with all signal processing applications,  
equidistant sampling is necessary. However in this example, the  
timer interrupt is used to control the sampling rate of the ADC and  
under certain conditions, equidistant sampling may not be achieved.  
The Timer Register for example is loaded with a value that will  
provide an interrupt at the required sample interval. When an  
interrupt is received, a value is transmitted with TFS/DT (ADC  
control word). The TFS is used to control the RFS and thus the  
reading of data. The frequency of the serial clock is set in the  
SCLKDIV Register. When the instruction to transmit with TFS is  
given, (i.e., AX0 ꢃ TX0), the state of the SCLK is checked.  
The DSP will wait until the SCLK has gone high, low and high  
before transmission will start. If the timer and SCLK values are  
chosen such that the instruction to transmit occurs on or near  
the rising edge of SCLK, then the data may be transmitted or it  
may wait until the next clock edge.  
DSP563xx*  
AD7490  
SCLK  
SCK  
SRD  
DOUT  
CS  
STD  
SC2  
DIN  
V
DRIVE  
*ADDITIONAL PINS REMOVED FOR CLARITY  
V
DD  
Figure 22. Interfacing to the DSP563xx  
For example, if the ADSP-2189 with a 20 MHz crystal has an  
overall master clock frequency of 40 MHz, then the master cycle  
time would be 25 ns. If the SCLKDIV Register is loaded with the  
value 3, a SCLK of 5 MHz is obtained, and eight master clock  
periods will elapse for every 1 SCLK period. Depending on the  
throughput rate selected, if the timer registers are loaded with  
the value 803, 100.5 SCLKs will occur between interrupts and  
subsequently between transmit instructions. This situation will  
result in nonequidistant sampling as the transmit instruction is  
occurring on a SCLK edge. If the number of SCLKs between  
interrupts is a figure of N, then equidistant sampling will be  
implemented by the DSP.  
In the example shown in Figure 22, the serial clock is taken from  
the ESSI so the SCK0 Pin must be set as an output, SCKD ꢃ 1.  
The VDRIVE Pin of the AD7490 takes the same supply voltage as  
that of the DSP563xx. This allows the ADC to operate at a higher  
voltage than the serial interface, i.e., DSP563xx, if necessary.  
REV. A  
–19–  
AD7490  
APPLICATION HINTS  
Grounding and Layout  
The AD7490 has very good immunity to noise on the power  
supplies as can be seen by the PSRR vs. Supply Ripple Frequency  
plot, TPC 3. However, care should still be taken with regard to  
grounding and layout.  
they must be placed as close as possible to the device, ideally right  
up against the device. The 0.1 µF capacitors should have low  
Effective Series Resistance (ESR) and Effective Series Induc-  
tance (ESI), such as the common ceramic types or surface mount  
types, which provide a low impedance path to ground at high  
frequencies to handle transient currents due to internal logic  
switching.  
The printed circuit board that houses the AD7490 should be  
designed such that the analog and digital sections are separated  
and confined to certain areas of the board. This facilitates the  
use of ground planes that can be separated easily. A minimum  
etch technique is generally best for ground planes as it gives the  
best shielding. All three AGND pins of the AD7490 should be  
sunk in the AGND plane. Digital and analog ground planes  
should be joined at only one place. If the AD7490 is in a system  
where multiple devices require an AGND to DGND connection,  
the connection should still be made at one point only, a star  
ground point which should be established as close as possible to  
the AD7490.  
PCB Design Guidelines For Chip Scale Package  
The lands on the chip scale package (CP-32), are rectangular. The  
printed circuit board pad for these should be 0.1 mm longer than  
the package land length and 0.05 mm wider than the package  
land width. The land should be centered on the pad. This will  
ensure that the solder joint size is maximized. The bottom of the  
chip scale package has a central thermal pad. The thermal pad  
on the printed circuit board should be at least as large as this  
exposed pad. On the printed circuit board, there should be a  
clearance of at least 0.25 mm between the thermal pad and the  
inner edges of the pad pattern. This will ensure that shorting is  
avoided. Thermal vias may be used on the printed circuit board  
thermal pad to improve thermal performance of the package. If vias  
are used, they should be incorporated in the thermal pad at  
1.2 mm pitch grid. The via diameter should be between 0.3 mm  
and 0.33 mm and the via barrel should be plated with 1 oz. copper  
to plug the via. The user should connect the printed circuit  
board thermal pad to AGND.  
Avoid running digital lines under the device as these will couple  
noise onto the die. The analog ground plane should be allowed to  
run under the AD7490 to avoid noise coupling. The power supply  
lines to the AD7490 should use as large a trace as possible to  
provide low impedance paths and reduce the effects of glitches on  
the power supply line. Fast switching signals like clocks should  
be shielded with digital ground to avoid radiating noise to other  
sections of the board, and clock signals should never be run near  
the analog inputs. Avoid crossover of digital and analog signals.  
Traces on opposite sides of the board should run at right angles to  
each other. This will reduce the effects of feedthrough through  
the board. A microstrip technique is by far the best but is not  
always possible with a double-sided board. In this technique, the  
component side of the board is dedicated to ground planes  
while signals are placed on the solder side.  
Evaluating the AD7490 Performance  
The recommended layout for the AD7490 is outlined in the  
evaluation board for the AD7490. The evaluation board package  
includes a fully assembled and tested evaluation board, docu-  
mentation, and software for controlling the board from the PC  
via the EVAL-BOARD CONTROLLER. The EVAL-BOARD  
CONTROLLER can be used in conjunction with the AD7490  
Evaluation board, as well as many other Analog Devices  
evaluation boards ending in the CB designator, to demonstrate/  
evaluate the ac and dc performance of the AD7490.  
Good decoupling is also important. All analog supplies should be  
decoupled with 10 µF tantalum in parallel with 0.1 µF capacitors  
to AGND. To achieve the best from these decoupling components,  
The software allows the user to perform ac (fast Fourier transform)  
and dc (histogram of codes) tests on the AD7490. The software and  
documentation are on a CD shipped with the evaluation board.  
–20–  
REV. A  
AD7490  
OUTLINE DIMENSIONS  
28-Lead Thin Shrink Small Outline Package [TSSOP]  
(RU-28)  
Dimensions shown in millimeters  
9.80  
9.70  
9.60  
28  
15  
14  
4.50  
4.40  
4.30  
6.40 BSC  
1
PIN 1  
0.65  
BSC  
1.20  
MAX  
0.15  
0.05  
0.75  
0.60  
0.45  
8ꢇ  
0ꢇ  
0.30  
0.19  
0.20  
0.09  
COPLANARITY  
0.10  
SEATING  
PLANE  
COMPLIANT TO JEDEC STANDARDS MO-153AE  
32-Lead Frame Chip Scale Package [LFCSP]  
(CP-32)  
Dimensions shown in millimeters  
5.00  
BSC SQ  
0.60 MAX  
PIN 1  
0.60 MAX  
INDICATOR  
25  
24  
32  
1
PIN 1  
INDICATOR  
0.50  
BSC  
4.75  
BSC SQ  
3.25  
3.10  
2.95  
TOP  
VIEW  
BOTTOM  
VIEW  
SQ  
0.50  
0.40  
0.30  
17  
16  
8
9
3.50  
REF  
0.70 MAX  
0.65 NOM  
12ꢇ MAX  
0.05 MAX  
0.02 NOM  
1.00  
0.30  
0.23  
0.18  
0.90  
0.80  
COPLANARITY  
0.08  
0.25 REF  
SEATING  
PLANE  
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2  
REV. A  
–21–  
AD7490  
Revision History  
Location  
Page  
10/02—Data Sheet changed from REV. 0 to REV. A.  
Addition to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Changes to TIMING SPECIFICATIONS Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Change A Grade to B Grade in ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Addition to ORDERING GUIDE Note 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5  
Changes to TYPICAL PERFORMANCE CHARACTERISTICS text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Added new TPC 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Text Changes to Figures 2–4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Changes to Figure 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
Text Changes to Figures 11–16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Addition to Analog Input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14  
Change to Figure 19 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Change to Figures 20–22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18  
Added APPLICATION HINTS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20  
–22–  
REV. A  
–23–  
–24–  

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